A solar cell and a method of manufacturing the same

Abstract

The present application relates to a solar cell and a preparation method thereof, comprising the following steps: providing a semiconductor substrate and forming a doped structure on the lower surface of the semiconductor substrate, the doped structure comprising a tunneling layer, an intrinsic layer, and a first doped structure and a second doped structure with opposite conductive types in the intrinsic layer, and a separation structure separating the first doped structure and the second doped structure; forming a passivation and anti-reflection material layer on the upper surface of the semiconductor substrate and the lower surface of the doped structure, respectively; removing the passivation and anti-reflection material layer on the lower surface of the first doped structure and the second doped structure to form a passivation and anti-reflection layer comprising a first passivation and anti-reflection layer on the lower surface of the separation structure and a second passivation and anti-reflection layer on the upper surface of the semiconductor substrate, respectively; and forming a first conductive part and a second conductive part covering at least the lower surface of the first doped structure and the lower surface of the second doped structure, and the first conductive part and the second conductive part are spaced apart from each other at the end close to the separation structure. The solar cell and the preparation method thereof greatly improve the parasitic absorption of the solar cell.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of solar cells, in particular to a solar cell and a preparation method thereof. BACKGROUND

[0002] Back contact solar cells are an advanced solar cell design, whose core concept is to place all metal electrodes on the back of the cell, thus ensuring that the front of the cell is not blocked by any metal grid lines. This design maximizes the area of the cell that absorbs sunlight, reduces optical loss, and improves photoelectric conversion efficiency. The advantage of the back contact (BC) cell structure is that the front can be completely used for light absorption, while the back is used for current collection, thereby improving the overall performance of the cell.

[0003] In recent years, research institutions and enterprises at home and abroad have been actively exploring interdigitated back contact (IBC) solar cell technology. IBC cells place all electrodes on the back of the cell, eliminating the shading of the front grid lines, thereby improving the photoelectric conversion efficiency of the cell. However, the conventional structure of IBC solar cells is limited by metal recombination and passivation film layers, and cannot further improve the conversion efficiency. In order to break through this limitation, the cell structure needs to be improved.

[0004] Tunnel oxide passivated contact (TOPCon) technology is a technology that forms a tunnel oxide layer and a doped polysilicon layer on the surface of the cell to achieve high-efficiency solar cells. This technology suppresses the recombination rate of minority carriers at the interface through the tunnel oxide passivation contact structure, greatly improving the open-circuit voltage and fill factor of the cell.

[0005] In order to further improve the performance of solar cells, combined with the tunnel oxide passivation contact technology of TOPCon cells, a new generation of tunnel oxide passivated back contact (TBC) solar cells has been developed. The electrodes of this cell are all located on the back of the cell, without considering the front optical problem. By making a tunnel oxide passivation contact structure, the recombination rate of minority carriers at the interface is effectively suppressed, thereby greatly improving the open-circuit voltage and fill factor of the cell. TBC solar cells achieve tunnel oxide and intrinsic polysilicon passivation layers through low-pressure chemical vapor deposition (LPCVD) process. These layers of selective carrier transport and doped polysilicon passivation contact are of great significance for achieving high-efficiency solar cells.

[0006] Although the TBC solar cell performs well in electrical performance, the problem of optical loss still exists, mainly due to the parasitic absorption of the polycrystalline silicon. In order to further improve the photoelectric conversion efficiency of the solar cell, this problem needs to be solved, and the structure and process selection of the cell need to be optimized. SUMMARY

[0007] Therefore, it is necessary to provide a solar cell and a preparation method thereof in view of the problem that the parasitic absorption in the prior art solar cell greatly affects the photoelectric conversion efficiency of the solar cell.

[0008] In order to achieve the above-mentioned purpose, in one aspect, the present application provides a preparation method of a solar cell, comprising the following steps:

[0009] providing a semiconductor substrate;

[0010] forming a doped structure on the lower surface of the semiconductor substrate, the doped structure comprising a tunneling layer, an intrinsic layer, a first doped structure, a second doped structure and an isolation structure in the intrinsic layer, the isolation structure isolating the first doped structure and the second doped structure, and the first doped structure and the second doped structure being opposite in conductivity type;

[0011] forming a passivation and anti-reflection material layer on the upper surface of the semiconductor substrate and the lower surface of the doped structure, respectively;

[0012] removing the passivation and anti-reflection material layer on the lower surface of the first doped structure and the second doped structure to form a passivation and anti-reflection layer, the passivation and anti-reflection layer comprising a first passivation and anti-reflection layer on the lower surface of the isolation structure and a second passivation and anti-reflection layer on the upper surface of the semiconductor substrate;

[0013] forming a first conductive part covering at least the lower surface of the first doped structure, and forming a second conductive part covering at least the lower surface of the second doped structure, the first conductive part and the second conductive part being spaced apart between one end close to the isolation structure.

[0014] In one embodiment, forming the doped structure on the lower surface of the semiconductor substrate comprises the following steps:

[0015] forming the tunneling layer and the intrinsic layer in sequence on the lower surface of the semiconductor substrate;

[0016] forming a first doped initial structure and a second doped initial structure on the lower surface of the intrinsic layer, the first doped initial structure and the second doped initial structure being spaced apart and opposite in conductivity type;

[0017] forming the first doped initial structure and the second doped initial structure on the lower surface of the intrinsic layer, and annealing the intrinsic layer after forming the first doped initial structure and the second doped initial structure on the lower surface of the intrinsic layer, wherein the first doped initial structure forms the first doped structure in the intrinsic layer, the second doped initial structure forms the second doped structure in the intrinsic layer, and the intrinsic layer between the first doped structure and the second doped structure forms the isolation structure.

[0018] In one embodiment, before forming the passivation anti-reflective material layer on the upper surface of the semiconductor substrate, further comprising:

[0019] forming a textured structure on the upper surface of the semiconductor substrate.

[0020] In one embodiment, forming the textured structure on the upper surface of the semiconductor substrate comprises:

[0021] forming a protection layer on the lower surface of the doped structure;

[0022] wet etching the upper surface of the semiconductor substrate to form the textured structure;

[0023] removing the protection layer.

[0024] In one embodiment, after forming the passivation anti-reflective material layer on the upper surface of the semiconductor substrate and the lower surface of the doped structure, before removing the passivation anti-reflective material layer on the lower surface of the first doped structure and the second doped structure, further comprising:

[0025] annealing the passivation anti-reflective material layer.

[0026] In one embodiment, the passivation anti-reflective material layer comprises a first passivation material and a second passivation material stacked in sequence, the first passivation material comprises Al x O y , and the second passivation material comprises at least one of silicon nitride, silicon oxide, and silicon oxynitride.

[0027] In one embodiment, the first conductive part and / or the second conductive part extends to the lower surface of the first passivation anti-reflective layer.

[0028] In one embodiment, forming the first conductive part covering at least the lower surface of the first doped structure and forming the second conductive part covering at least the lower surface of the second doped structure comprises:

[0029] forming a conductive material layer covering the lower surface of the first doped structure, the lower surface of the second doped structure, and the exposed surface of the first passivation anti-reflective layer;

[0030] forming an isolation groove in the conductive material layer, the isolation groove penetrating through the conductive material layer and an opening width of the isolation groove being not greater than a width of the isolation structure, to form the first conductive part covering at least a lower surface of the first doped structure and the second conductive part covering at least a lower surface of the second doped structure.

[0031] In one of the embodiments, after forming the first conductive part covering at least the lower surface of the first doped structure and forming the second conductive part covering at least the lower surface of the second doped structure, further comprising:

[0032] forming a first lead electrode on a lower surface of the first conductive part and forming a second lead electrode on a lower surface of the second conductive part.

[0033] The present application also provides a solar cell prepared by the preparation method of the solar cell as described in any one of the above embodiments.

[0034] The solar cell and the preparation method thereof as described above have the following beneficial effects: by forming the passivation and anti-reflection material layer on the lower surface of the doped structure, free hydrogen in the passivation and anti-reflection material layer repairs defect centers and dangling bonds of the first doped structure, the second doped structure and the tunneling layer in the annealing process, improving the quality of the first doped structure, the second doped structure and the tunneling layer, improving the performance of the solar cell, and removing the passivation and anti-reflection material layer on the lower surface of the first doped structure and the second doped structure to form the first passivation and anti-reflection layer on the lower surface of the isolation structure, ensuring good interface passivation effect and isolation effect of the first doped structure and the second doped structure, and also helping to achieve good electrical contact subsequently; by directly forming the first conductive part covering at least the lower surface of the first doped structure and the second conductive part covering at least the lower surface of the second doped structure, the first conductive part and the second conductive part have good conductivity, realizing high transmittance, low resistivity and efficient carrier collection, greatly improving the loss of battery conversion efficiency caused by parasitic absorption, and the first conductive part and the second conductive part are spaced apart between one end of the first conductive part close to the isolation structure and one end of the second conductive part close to the isolation structure, realizing isolation of the first doped structure and the second doped structure while ensuring the conduction of the horizontal current; in addition, in some embodiments, the first doped structure, the second doped structure and the isolation structure are directly formed in the intrinsic layer by annealing, avoiding the formation of "leakage current" channels while greatly simplifying the process flow. BRIEF DESCRIPTION OF DRAWINGS

[0035] In order to make the technical solutions in the embodiments of the present application or the prior art clearer, the accompanying drawings that need to be used in the embodiments or the prior art description will be briefly introduced. Obviously, the accompanying drawings in the following description only need to be some embodiments of the present application, and other drawings can be obtained by those skilled in the art without any creative effort.

[0036] Figure 1 A flow chart of a preparation method of a solar cell provided in an embodiment;

[0037] Figure 2 A cross-sectional structure schematic diagram after forming a tunnel layer and an intrinsic layer in the preparation method of the solar cell provided in an embodiment;

[0038] Figure 3 A cross-sectional structure schematic diagram after forming a first doped initial structure and a second doped initial structure in the preparation method of the solar cell provided in an embodiment;

[0039] Figure 4 A cross-sectional structure schematic diagram after forming a first doped structure, a second doped structure and an isolation structure in the preparation method of the solar cell provided in an embodiment;

[0040] Figure 5 A cross-sectional structure schematic diagram after forming a protection layer in the preparation method of the semiconductor structure provided in an embodiment;

[0041] Figure 6 A cross-sectional structure schematic diagram after forming a texturing structure in the preparation method of the solar cell provided in an embodiment;

[0042] Figure 7 A cross-sectional structure schematic diagram after forming a passivation and anti-reflection material layer in the preparation method of the solar cell provided in an embodiment;

[0043] Figure 8 A cross-sectional structure schematic diagram after forming a passivation and anti-reflection layer in the preparation method of the solar cell provided in an embodiment;

[0044] Figure 9 A cross-sectional structure schematic diagram after forming a conductive material layer in the preparation method of the solar cell provided in an embodiment;

[0045] Figure 10 A cross-sectional structure schematic diagram after forming a first conductive part and a second conductive part in the preparation method of the solar cell provided in an embodiment.

[0046] Figure 11 A cross-sectional structure schematic diagram after forming a first lead-out electrode and a second lead-out electrode in the preparation method of the solar cell provided in an embodiment.

[0047] Reference Signs List:

[0048] 1 - semiconductor substrate, 2 - doped structure, 21 - tunneling layer, 22 - intrinsic layer, 23 - first doped structure, 24 - second doped structure, 25 - isolation structure, 26 - first doped initial structure, 27 - second doped initial structure, 3 - passivation anti-reflective layer, 31 - passivation anti-reflective material layer, 32 - first passivation anti-reflective layer, 33 - second passivation anti-reflective layer, 4 - first conductive part, 5 - second conductive part, 6 - protective layer, 7 - conductive material layer, 8 - isolation groove, 9 - first lead electrode, 10 - second lead electrode. DETAILED DESCRIPTION

[0049] For the purpose of promoting an understanding of the application, the application will now be described in greater detail with reference to the figures. The embodiments shown in the figures are intended to explain the present application and are not intended to limit the present application in any way. Rather, the present application can be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

[0050] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description of the application herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0051] It will be understood that when an element or layer is referred to as being "on", "adjacent", "connected" or "coupled" to another element or layer, it can be directly on, adjacent, connected or coupled to the other element or layer or intervening elements or layers can be present. In contrast, when an element is referred to as being "directly on", "directly adjacent", "directly connected" or "directly coupled" to another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section; for example, a first doped type could be termed a second doped type; and similarly, a second doped type could be termed a first doped type; a first doped type and a second doped type are different doped types, e.g., a first doped type can be P-type and a second doped type can be N-type, or a first doped type can be N-type and a second doped type can be P-type.

[0052] Spatially relative terms, such as "beneath", "below", "lower", "under", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and / or operation in addition to the orientations depicted in the figures. For example, if a device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. The device can also be oriented in the other direction (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0053] The singular forms "a", "an", and "the" include plural referents unless the context clearly dictates otherwise. It will be further understood that the terms "comprises", "comprising", "includes" and / or "including", or the like, when used in this specification, specify the presence of stated features, integers, steps, operations, elements, components, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or combinations thereof.

[0054] Embodiments of the application are described herein with reference to the drawings, which show ideal embodiments (and intermediate structures) of the application. Variations can be made to the shapes of the elements shown because of such factors as manufacturing techniques and / or tolerances, and therefore other embodiments of the application should not be construed as limited to the particular shapes of elements shown. For example, an implanted region shown as a rectangle will typically have rounded or curved features at its edges and / or an implanted concentration gradient rather than a binary change from the implanted region to the non-implanted region. Similarly, a buried region formed by implantation can result in some implantation in the region between the buried region and the surface through which the implant was performed. Therefore, the regions shown in the drawings are schematic only and their shapes are not intended to represent the actual shape of a region of a device, and are not intended to limit the scope of the application.

[0055] Referring to the flowchart of a method for manufacturing a solar cell, the present application provides a method for manufacturing a solar cell, comprising the following steps: Figure 1

[0056] S1: providing a semiconductor substrate 1;

[0057] S2: forming a doped structure 2 on the lower surface of the semiconductor substrate 1, the doped structure 2 comprising a tunneling layer 21, an intrinsic layer 22, a first doped structure 23, a second doped structure 24 and an isolation structure 25 in the intrinsic layer 22 in sequence, the isolation structure 25 separating the first doped structure 23 and the second doped structure 24, and the first doped structure 23 and the second doped structure 24 having opposite conductivity types;

[0058] S3: forming a passivation and anti-reflection material layer 31 on the upper surface of the semiconductor substrate 1 and the lower surface of the doped structure 2 respectively;

[0059] S4: removing the passivation and anti-reflection material layer 31 on the lower surface of the first doped structure 21 and the second doped structure 22 to form a passivation and anti-reflection layer 3, the passivation and anti-reflection layer 3 comprising a first passivation and anti-reflection layer 32 on the lower surface of the isolation structure 25 and a second passivation and anti-reflection layer 33 on the upper surface of the semiconductor substrate 1;

[0060] S5: forming a first conductive part 4 covering at least the lower surface of the first doped structure 23, and forming a second conductive part 5 covering at least the lower surface of the second doped structure 24, the first conductive part 4 and the second conductive part 5 being spaced apart between the end of the first conductive part 4 close to the isolation structure 25 and the end of the second conductive part 5 close to the isolation structure 25.

[0061] ​The preparation method of the solar cell forms the passivation and anti-reflection material layer 31 on the lower surface of the doping structure 2, so that the free hydrogen in the passivation and anti-reflection material layer 31 repairs the defect centers and dangling bonds of the first doping structure 23, the second doping structure 24 and the tunneling layer 21 during the annealing process, improves the quality of the first doping structure 23, the second doping structure 24 and the tunneling layer 21, and improves the performance of the solar cell. The passivation and anti-reflection material layer 31 located on the lower surface of the first doping structure 23 and the second doping structure 24 is removed to form the first passivation and anti-reflection layer 32 located on the lower surface of the isolation structure 25, which ensures good interface passivation effect and isolation effect of the first doping structure 23 and the second doping structure 24, and also helps to achieve good electrical contact subsequently. By directly forming the first conductive part 4 covering at least the lower surface of the first doping structure 23 and the second conductive part 5 covering at least the lower surface of the second doping structure 24, the first conductive part 4 and the second conductive part 5 have good conductivity, achieving high transmittance, low resistivity and efficient carrier collection. The loss of battery conversion efficiency caused by parasitic absorption is greatly improved. The end of the first conductive part 4 close to the isolation structure 25 and the end of the second conductive part 5 close to the isolation structure 25 are spaced apart, which realizes the isolation of the first doping structure 23 and the second doping structure 24 while ensuring the conduction of the horizontal current. In addition, in some embodiments, the first doping structure 23, the second doping structure 24 and the isolation structure 25 are directly formed in the intrinsic layer 22 by annealing treatment, which avoids the formation of "leakage current" channels and greatly simplifies the process flow.

[0062] Step S1 is performed to provide a semiconductor substrate 1. The material of the semiconductor substrate 1 includes single crystal silicon, polycrystalline silicon, compound semiconductor (for example, gallium nitride, gallium arsenide, etc.), but can also include one or more other semiconductor materials. In this embodiment, the material of the semiconductor substrate 1 is single crystal silicon, and the semiconductor substrate 1 is also doped with N-type or P-type doping elements.

[0063] In some embodiments, step S1 further includes a step S11 of performing cleaning treatment on the semiconductor substrate 1, wherein the cleaning treatment on the semiconductor substrate 1 includes the following steps S111-S114:

[0064] S111: performing pre-polishing treatment on the surface of the semiconductor substrate 1; the pre-polishing treatment on the surface of the semiconductor substrate 1 is to clean and pre-polish the mechanical cutting damage layer, metal ions, dirt and impurities of the substrate 1 by using chemical reagents, so as to modify the semiconductor substrate 1 into a relatively flat interface; wherein the reagent used for the pre-polishing treatment on the surface of the semiconductor substrate 1 includes at least one of NH4OH, NaOH, KOH, H2O or other suitable reagents, and the pre-polishing temperature ranges from 65°C to 80°C, and the pre-polishing treatment time ranges from 180s to 300s.

[0065] S112: pre-cleaning the surface of the semiconductor substrate 1 after the pre-polishing treatment; the pre-cleaning of the surface of the semiconductor substrate 1 after the pre-polishing treatment can effectively remove impurities on the surface of the semiconductor substrate 1 after the pre-polishing treatment; wherein the reagent used for the pre-cleaning of the surface of the semiconductor substrate 1 after the pre-polishing treatment includes one of NaOH, KOH, H2O2, H2O or other suitable reagents, and when NaOH is used for pre-cleaning, the concentration of NaOH is in the range of 45wt% to 55wt%, the concentration of KOH is in the range of 45wt% to 55wt%, the concentration of H2O2 is in the range of 25wt% to 35wt%, the pre-cleaning temperature is in the range of about 55°C to 65°C, and the pre-cleaning time is in the range of 120s to 180s.

[0066] S113: hydrophobic treatment of the surface of the semiconductor substrate 1 after the pre-cleaning treatment; the hydrophobic treatment of the surface of the semiconductor substrate 1 can ensure the cleanliness of the surface of the semiconductor substrate 1 and improve the anti-pollution ability of the surface of the semiconductor substrate 1, wherein the reagent used for the hydrophobic treatment of the surface of the semiconductor substrate 1 includes at least one of HF, HCL, H2O, and when HF is used for hydrophobic treatment, the concentration of HF is in the range of 45wt% to 55wt%, and when HCL is used for hydrophobic treatment, the concentration of HCL is in the range of 30wt% to 40wt%, the hydrophobic treatment is carried out at room temperature, and the hydrophobic treatment time is in the range of 120s to 360s.

[0067] S114: drying treatment of the surface of the semiconductor substrate 1 after the hydrophobic treatment; the drying treatment of the semiconductor substrate 1 can fully remove the water vapor impurities on the surface of the semiconductor substrate 1, which is helpful for the subsequent process. The drying treatment of the semiconductor substrate 1 is carried out in an inert gas atmosphere, and the inert gas includes nitrogen or other suitable inert gas, and the drying treatment time is in the range of 480s to 800s.

[0068] Referring to Figures 2 to 4 , step S2 is performed to form a doped structure 2 on the lower surface of the semiconductor substrate 1, the doped structure 2 includes a tunneling layer 21, an intrinsic layer 22, a first doped structure 23, a second doped structure 24 and an isolation structure 25 in the intrinsic layer 22, the isolation structure 25 isolates the first doped structure 23 and the second doped structure 24, and the conductive types of the first doped structure 23 and the second doped structure 24 are opposite.

[0069] In some embodiments, step S2 further includes steps S21-S23 of forming the doped structure 2, including:

[0070] S21: Forming a tunnel layer 21 and an intrinsic layer 22 which are sequentially stacked on the lower surface of the semiconductor substrate 1; the tunnel layer 21 and the intrinsic layer 22 are used to realize high-efficiency passivation of the back surface and selective collection of carriers, wherein the material of the tunnel layer 21 includes SiO x The method for forming the tunnel layer 21 includes thermal oxidation, nitric acid oxidation, ozone oxidation or other suitable methods, and the thickness of the tunnel layer 21 ranges from 1 nm to 3 nm; the material of the intrinsic layer 22 includes amorphous silicon or other suitable materials, and the amorphous silicon material of the intrinsic layer 22 is formed by silane decomposition, the method for forming the intrinsic layer 22 includes low-pressure chemical vapor deposition, plasma-enhanced chemical vapor deposition, catalytic chemical vapor deposition, atomic layer deposition, physical vapor deposition or other suitable methods, and the thickness of the intrinsic layer 22 ranges from 40 nm to 80 nm.

[0071] S22: Forming a first doped initial structure 26 and a second doped initial structure 27 on the lower surface of the intrinsic layer 22, respectively, and the first doped initial structure 26 and the second doped initial structure 27 are arranged with an interval and have opposite conductivity types; wherein the first doped initial structure 26 includes boron elements, and the second doped initial structure 27 includes phosphorus elements, the method for forming the first doped initial structure 26 is slurry brushing, and when the first doped initial structure 26 is formed by slurry brushing, the solid content of the first doped initial structure 26 ranges from 20% to 55%, and the viscosity ranges from 20 Pa to 50 Pa, the method for forming the second doped initial structure 27 is slurry brushing, and when the second doped initial structure 27 is formed by slurry brushing, the solid content of the second doped initial structure 27 ranges from 15% to 35%, and the viscosity ranges from 20 Pa to 50 Pa, the width of the first doped initial structure 26 ranges from 600 nm to 800 nm, the width of the second doped initial structure 27 ranges from 400 nm to 600 nm, and the width ratio of the first doped initial structure 26 to the second doped initial structure 27 ranges from 3:2 to 4:3.

[0072] S23: annealing the intrinsic layer 22 after the first and second doping initial structures 26 and 27 are formed on the lower surface, after the annealing, the first doping initial structure 26 forms the first doping structure 23 in the intrinsic layer 27, the second doping initial structure 27 forms the second doping structure 24 in the intrinsic layer 22, and the intrinsic layer 22 between the first and second doping structures 23 and 24 is the isolation structure 25. The annealing of the intrinsic layer 22 after the first and second doping initial structures 26 and 27 are formed on the lower surface realizes the transformation of the intrinsic layer 25 to the doping structure, and the existence of the tunneling layer 21 and the low surface concentration ensure that there is no large amount of "dead layer" at the interface, which provides more space for the passivation of the existing thin intrinsic layer 22; during the process, part of the intrinsic layer 22 without any element doping is reserved as the isolation structure 25 to prevent the formation of a back "leakage current" channel, and the first doping structure 23, the second doping structure 24 and the isolation structure 25 are directly formed by annealing, which greatly simplifies the process flow. The annealing is performed in a nitrogen or oxygen atmosphere, the temperature range of the annealing is 850°C-1050°C, and the time range of the annealing is 10-30 minutes. Exemplarily, the width of the first doping structure 23 is greater than the width of the second doping structure 24. The width of the first doping structure 23 can also be less than or equal to the width of the second doping structure 24, which can be selected according to actual conditions.

[0073] Please refer to Figures 5 to 7 , execute step S3, respectively form a passivation and anti-reflection material layer 31 on the upper surface of the semiconductor substrate 1 and the lower surface of the doping structure 2.

[0074] In some embodiments, step S3 further includes step S31, i.e., before forming the passivation and anti-reflection material layer 31 on the upper surface of the semiconductor substrate 1, it further includes: forming a textured structure 11 on the upper surface of the semiconductor substrate 1. The textured structure 11 is a small pyramid-shaped structure or other microstructure formed on the upper surface of the semiconductor substrate 1, which increases the surface area above the semiconductor substrate 1, thereby improving the absorption of sunlight.

[0075] In some embodiments, forming the textured structure 11 on the upper surface of the semiconductor substrate 1 includes the following steps S311-S313:

[0076] S311: Form a protective layer 6 on the lower surface of the doped structure 2; the protective layer 6 is used to protect the lower surface of the doped structure 2 when forming the rough structure 11 on the upper surface of the semiconductor substrate 1, the material of the protective layer 6 includes at least one of silicon oxide, silicon oxynitride, borosilicate glass or other suitable material, the method for forming the protective layer 6 includes low pressure chemical vapor deposition, plasma enhanced chemical vapor deposition, physical vapor deposition, catalytic chemical vapor deposition, atomic layer deposition or other suitable method, and the thickness of the formed protective layer 6 ranges from 2 nm to 50 nm.

[0077] S312: Perform wet etching on the upper surface of the semiconductor substrate 1 to form the rough structure 11; the reagent used for wet etching on the upper surface of the semiconductor substrate 1 includes at least one of NaOH, KOH and H2O, and exemplarily, when the reagent used is a mixed solution of NaOH or KOH and H2O, the volume ratio of NaOH or KOH to H2O is 1:15, the processing temperature ranges from 75°C to 83°C, and the processing time ranges from 360s to 420s, in addition, the reflectivity of the upper surface of the semiconductor substrate 1 after forming the rough structure 11 ranges from 8% to 11%.

[0078] S313: Remove the protective layer 6. The subsequent process can be ensured to proceed smoothly, and the reagent used for removing the protective layer 6 includes at least one of HF and H2O, and exemplarily, when the reagent used is a mixed solution of HF and H2O, the volume ratio of HF to H2O is 1:20, and the time range for removing the protective layer 6 ranges from 100s to 400s.

[0079] In some embodiments, the passivation anti-reflection material layer 31 includes a first passivation material and a second passivation material stacked in sequence, the first passivation material includes Al x O y , and the second passivation material includes at least one of silicon nitride, silicon oxide and silicon oxynitride. Al x O y is used as the first passivation material, the negative charge of Al x O y can ensure efficient passivation effect and better saturation of dangling bonds on the silicon surface, and the second passivation material can effectively protect the first passivation material and achieve efficient defect center repair through chemical passivation. Exemplarily, the first passivation material is Al x O yThe first passivation material is formed by reaction of trimethylaluminum and H2O or trimethylaluminum and O3, the thickness of the first passivation material is 3 nm to 10 nm, and the method for forming the first passivation material includes plasma-enhanced atomic layer deposition, atomic layer deposition, physical vapor deposition, or other suitable methods; the thickness of the second passivation material is 70 nm to 110 nm, and the refractive index of the second passivation material is 2.0% to 2.4%.

[0080] The step S3 further includes a step S32, that is, after the passivation anti-reflection material layer 31 is formed on the upper surface of the semiconductor substrate 1 and the lower surface of the doped structure 2, before the passivation anti-reflection material layer 31 on the lower surfaces of the first doped structure 23 and the second doped structure 24 is removed, the passivation anti-reflection material layer 31 is subjected to annealing treatment. The annealing treatment of the passivation anti-reflection material layer 31 is performed at a medium-high temperature, and the annealing treatment of the passivation anti-reflection material layer 31 can diffuse free hydrogen in the passivation anti-reflection material layer 31 into the first doped structure 23, the second doped structure 24, and the tunneling layer 21, repair defect centers, neutralize dangling bonds, and finally improve the quality of the first doped structure 23, the second doped structure 24, and the tunneling layer 21.

[0081] Referring to Figure 8 The step S4 is performed to remove the passivation anti-reflection material layer 31 on the lower surfaces of the first doped structure 23 and the second doped structure 24 to form a passivation anti-reflection layer 3, which includes a first passivation anti-reflection layer 32 on the lower surface of the isolation structure 25 and a second passivation anti-reflection layer 33 on the upper surface of the semiconductor substrate 1.

[0082] In some embodiments, the width of the first passivation anti-reflection layer 32 is less than the difference between the width of the first doped structure 23 and the width of the second doped structure 24, that is, the second passivation anti-reflection layer 32 is arranged on the upper surface of the isolation structure 25, which ensures good interface passivation effect and isolation effect of the first doped structure 23 and the second doped structure 24, and also realizes good electrical contact. By forming the second passivation anti-reflection layer 33 on the upper surface of the textured structure 11, light absorption can be improved and the recombination loss of carriers on the front surface can be reduced, thereby improving the open-circuit voltage and short-circuit current of the battery and obtaining higher conversion efficiency.

[0083] In some embodiments, the method for removing the passivation anti-reflection material layer 31 on the lower surface of the first doped structure 23 and the second doped structure 24 includes laser etching or other suitable methods. The method for removing the passivation anti-reflection material layer 31 on the lower surface of the first doped structure 23 and the second doped structure 24 by laser etching achieves high precision and high efficiency processing, reduces errors and losses in the production process, avoids affecting the first doped structure 23 and the second doped structure 24, improves the yield of the solar cell, and when laser etching is used to remove the passivation anti-reflection material layer 31 on the lower surface of the first doped structure 23 and the second doped structure 24, the laser wavelength used is 355 nm, and the power range is 50 W to 120 W.

[0084] Referring to Figures 9 to 10 , step S5 is performed to form the first conductive part 4 covering at least the lower surface of the first doped structure 23, and the second conductive part 5 covering at least the lower surface of the second doped structure 24, and the first conductive part 4 is arranged apart from the second conductive part 5 near one end of the isolation structure 25.

[0085] In some embodiments, step S5 further includes S51-S52, i.e., forming the first conductive part 4 covering at least the lower surface of the first doped structure 23, and the second conductive part 5 covering at least the lower surface of the second doped structure 24, includes the following steps:

[0086] S51: forming a conductive material layer 7 covering the lower surface of the first doped structure 23, the lower surface of the second doped structure 24, and the exposed surface of the first passivation anti-reflection layer 32;

[0087] S52: forming an isolation groove 8 in the conductive material layer 7, the isolation groove 8 penetrating the conductive material layer 7, and the opening width of the isolation groove 8 being not greater than the width of the isolation structure 25, to form the first conductive part 4 covering at least the lower surface of the first doped structure 23, and the second conductive part 5 covering at least the lower surface of the second doped structure 24. By forming the first conductive part 4 covering the lower surface of the first doped structure 23, and the second conductive part 5 covering the lower surface of the second doped structure 24, the first conductive part 4 and the second conductive part 5 have good conductivity, which can achieve higher transmittance, lower resistivity, and high-efficiency carrier collection, and improve the performance of the solar cell. Moreover, the first conductive part 4 covers the lower surface of the first doped structure 23, and the second conductive part 5 covers the lower surface of the second doped structure 24, i.e., the first conductive part 4 and the second conductive part 5 are not in contact, which ensures the conduction of the lateral current while achieving the isolation of the first doped structure 23 and the second doped structure 24. The method for forming the conductive material layer 7 includes magnetron sputtering or other suitable methods, and when magnetron sputtering is used to form the conductive material layer 7, the working atmosphere gas used includes argon, the working gas pressure range is 0.2 Pa to 10 Pa, and the power density range is 60 W to 500 W.

[0088] In some embodiments, the method of forming the isolation groove 8 includes laser etching or other suitable methods; the isolation groove 8 is formed in the conductive material layer 7, and the opening width of the isolation groove 8 is not greater than the width of the isolation structure 25, which avoids the exposure of the first doped structure 23 and the second doped structure 24 while realizing the lateral current conduction of the solar cell. Exemplarily, the opening width of the isolation groove 8 is 60 μm to 300 μm. The laser etching technology can realize high-precision and high-efficiency processing, reduce errors and losses in the production process, avoid affecting the isolation structure 25 and the first passivation and anti-reflection layer 32, and improve the yield of the solar cell. When the laser etching is used to form the isolation groove 8, the laser wavelength includes 355 nm and 532 nm, which can be selected according to the actual situation, and the laser power ranges from 40 W to 80 W.

[0089] In some embodiments, the conductive material layer 7 includes a transparent conductive oxide. The transparent conductive oxide is used as the conductive material layer 7 to prepare the first conductive part 4 and the second conductive part 5, which can realize higher light transmittance and electrical conductivity, thereby greatly improving the photoelectric conversion efficiency of the solar cell.

[0090] In some embodiments, the first conductive part 4 and / or the second conductive part 5 extends to the lower surface of the first passivation and anti-reflection layer 32. That is, the first conductive part 4 and / or the second conductive part 5 also covers part of the lower surface of the first passivation and anti-reflection layer 32, and the first conductive part 4 and the second conductive part 5 do not contact each other, which ensures the lateral current conduction while improving the isolation effect of the first doped structure 23 and the second doped structure 24.

[0091] Please refer to Figure 11 In some embodiments, the method of preparing the solar cell further includes step S6 of forming the first conductive part 4 covering the lower surface of the first doped structure 23, and forming the second conductive part 5 covering the lower surface of the second doped structure 24, and further includes forming the first lead electrode 9 on the lower surface of the first conductive part 4 and forming the second lead electrode 10 on the lower surface of the second conductive part 5. The first lead electrode 9 and the second lead electrode 10 are used as positive and negative electrodes, respectively, to lead out the current.

[0092] The formation of the first lead electrode 9 and the second lead electrode 10 includes the following steps S61-S62:

[0093] S61: Forming a first electrode material (not shown) on the lower surface of the first conductive part 4 and a second electrode material (not shown) on the lower surface of the second conductive part 5, wherein the method for forming the first electrode material includes paste brushing, and the material of the first electrode material includes silver, aluminum, copper or other suitable conductive material; the method for forming the second electrode material includes paste brushing, and the material of the second electrode material includes silver, aluminum, copper or other suitable conductive material.

[0094] S62: Performing solidification treatment on the first electrode material and the second electrode material to form the first lead electrode 9 and the second lead electrode 10. The method for performing solidification treatment on the first electrode material and the second electrode material includes sintering, and when the sintering method is used to perform solidification treatment on the first electrode material and the second electrode material, the sintering temperature ranges from 150°C to 1000°C, and the processing time is about 60s to 600s.

[0095] It should be understood that, although Figure 1 the steps in the flowchart of the method are shown in sequence according to the arrows, these steps are not necessarily executed in sequence according to the arrows. Unless otherwise specified herein, the execution of these steps is not strictly limited in sequence, and these steps can be executed in other sequences. Moreover, Figure 1 at least part of the steps in the method can include multiple steps or multiple stages, which are not necessarily executed at the same time, but can be executed at different times, and the execution sequence of these steps or stages is not necessarily sequential, but can be executed alternately or alternately with at least part of other steps or steps or stages in other steps.

[0096] Please continue to refer to Figure 11 , the present application also provides a solar cell, and the solar cell is prepared by the above-mentioned method for preparing a solar cell, comprising: a semiconductor substrate 1, a doped structure 2, a passivation anti-reflection layer 3, a first conductive part 4 and a second conductive part 5, wherein the doped structure 2 is located on the lower surface of the semiconductor substrate 1, the doped structure 2 includes a tunneling layer 21, an intrinsic layer 22, a first doped structure 23, a second doped structure 24 and a separation structure 25 separating the first doped structure 23 and the second doped structure 24 which are sequentially stacked in the intrinsic layer 22, and the conductive types of the first doped structure 23 and the second doped structure 24 are opposite; the passivation anti-reflection layer 3 includes a first passivation anti-reflection layer 32 located on the lower surface of the separation structure 25 and a second passivation anti-reflection layer 33 located on the upper surface of the semiconductor substrate 1; the first conductive part 4 covers at least the lower surface of the first doped structure 23, the second conductive part 5 covers at least the lower surface of the second doped structure 24, and the one end of the first conductive part 4 close to the separation structure 25 and the one end of the second conductive part 5 close to the separation structure 25 are arranged with a spacing.

[0097] In some embodiments, the semiconductor substrate 1 has a textured structure 11 on the upper surface, and the second passivation anti-reflection layer 33 covers the upper surface of the textured structure 11.

[0098] In some embodiments, the first conductive part 4 and / or the second conductive part 5 extends to the lower surface of the first passivation anti-reflection layer 32. That is, the first conductive part 4 and / or the second conductive part 5 also covers part of the lower surface of the first passivation anti-reflection layer 32.

[0099] In some embodiments, the solar cell further comprises a first lead electrode 9 and a second lead electrode 10, the first lead electrode 9 is located on the lower surface of the first conductive part 4, and the second lead electrode 10 is located on the lower surface of the second conductive part 5.

[0100] In the description of the present specification, the description of the terms "some embodiments", "other embodiments", "ideal embodiments", and the like means that the specific features, structures, materials, or characteristics described in connection with the embodiments or examples are included in at least one embodiment or example of the present application. In the present specification, the illustrative description of the above terms does not necessarily refer to the same embodiment or example.

[0101] The technical features of the above-described embodiments can be combined in any manner. In order to make the description concise, all possible combinations of the technical features of the above-described embodiments are not described, however, as long as the combinations of the technical features do not contradict each other, they should be considered within the scope of the present specification.

[0102] The above-described embodiments only express several implementation manners of the present application, and the description is relatively specific and detailed, but it should not be understood as a limitation on the patent scope of the application. It should be noted that for ordinary skilled persons in the art, several modifications and improvements can be made without departing from the concept of the present application, and these are within the protection scope of the present application. Therefore, the patent protection scope of the present application should be subject to the appended claims.

Claims

1. A method for preparing a solar cell, characterized in that: The steps include: providing a semiconductor substrate; forming a doping structure on the lower surface of the semiconductor substrate, the doping structure comprising a tunneling layer, an intrinsic layer, and a first doping structure, a second doping structure, and an isolation structure located in the intrinsic layer, wherein the isolation structure isolates the first doping structure from the second doping structure, and the first doping structure and the second doping structure have opposite conductivity types; forming a passivation anti-reflection material layer on the upper surface of the semiconductor substrate and the lower surface of the doped structure respectively; removing the passivation anti-reflection material layer located on the lower surfaces of the first doping structure and the second doping structure to form a passivation anti-reflection layer, wherein the passivation anti-reflection layer includes a first passivation anti-reflection layer located on the lower surface of the isolation structure and a second passivation anti-reflection layer located on the upper surface of the semiconductor substrate; A first conductive portion is formed to at least cover the lower surface of the first doped structure, and a second conductive portion is formed to at least cover the lower surface of the second doped structure, wherein the first conductive portion is spaced apart from an end of the isolation structure and an end of the second conductive portion is spaced apart from an end of the isolation structure. After the passivation anti-reflection material layer is formed on the upper surface of the semiconductor substrate and the lower surface of the doped structure, and before the passivation anti-reflection material layer located on the lower surfaces of the first doped structure and the second doped structure is removed, the method further includes: annealing the passivation anti-reflection material layer.

2. The method for preparing a solar cell according to claim 1, wherein: Forming the doping structure on the lower surface of the semiconductor substrate includes the following steps: forming the tunneling layer and the intrinsic layer stacked in sequence on the lower surface of the semiconductor substrate; forming a first doped initial structure and a second doped initial structure on the lower surface of the intrinsic layer, wherein the first doped initial structure and the second doped initial structure are spaced apart and have opposite conductivity types; The intrinsic layer after the first doping initial structure and the second doping initial structure are formed on the lower surface is annealed. After the annealing, the first doping initial structure forms the first doping structure in the intrinsic layer, and the first doping initial structure forms the second doping structure in the intrinsic layer. The undoped intrinsic layer between the first doping structure and the second doping structure serves as the isolation structure.

3. The method for preparing a solar cell according to claim 1, wherein: Before forming the passivation anti-reflection material layer on the upper surface of the semiconductor substrate, the method further includes: A textured structure is formed on the upper surface of the semiconductor substrate.

4. The method for preparing a solar cell according to claim 3, wherein: Forming the textured structure on the upper surface of the semiconductor substrate comprises the following steps: forming a protective layer on the lower surface of the doped structure; Wet etching the upper surface of the semiconductor substrate to form the textured structure; The protective layer is removed.

5. The method for preparing a solar cell according to claim 1, wherein: The passivation anti-reflection material layer includes a first passivation material and a second passivation material stacked in sequence, wherein the first passivation material includes Al x O y The second passivation material includes at least one of silicon nitride, silicon oxide, and silicon oxynitride.

6. The method for preparing a solar cell according to claim 1, wherein: The first conductive portion and / or the second conductive portion extends to the lower surface of the first passivation anti-reflection layer.

7. The method for preparing a solar cell according to claim 1, wherein: Forming the first conductive portion covering at least the lower surface of the first doped structure and forming the second conductive portion covering at least the lower surface of the second doped structure comprises the following steps: forming a conductive material layer covering the lower surface of the first doped structure, the lower surface of the second doped structure, and the exposed surface of the first passivation anti-reflection layer; An isolation trench is formed in the conductive material layer, wherein the isolation trench penetrates the conductive material layer and the opening width of the isolation trench is no greater than the width of the isolation structure, so as to form the first conductive portion that at least covers the lower surface of the first doping structure and the second conductive portion that at least covers the lower surface of the second doping structure.

8. The method for preparing a solar cell according to claim 1, wherein: After forming the first conductive portion covering at least the lower surface of the first doped structure and forming the second conductive portion covering at least the lower surface of the second doped structure, the method further includes: A first extraction electrode is formed on the lower surface of the first conductive portion, and a second extraction electrode is formed on the lower surface of the second conductive portion.

9. A solar cell, characterized in that: The solar cell is prepared by the method for preparing a solar cell according to any one of claims 1 to 8.

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