Reordering workloads to improve cross-thread concurrency in processor-based devices

Abstract

The invention discloses reordering workloads to improve cross-thread concurrency in a processor-based device. In this regard, in some exemplary aspects, a processor-based device receives a plurality of workloads from a requester and constructs a weighted dependency graph based on the plurality of workloads. The weighted dependency graph includes: a plurality of vertices, each vertex corresponding to a workload of a plurality of workloads; and further comprising one or more directed edges, each directed edge connecting two vertices of the plurality of vertices and indicating dependencies between corresponding two workloads of the plurality of workloads. After generating the weighted dependency graph, the processor-based device performs topological ordering of the weighted dependency graph; and generating a workload execution order based on the topological ranking. By scheduling workload execution according to a workload execution order, concurrency between threads may be maximized, and processor resources may be utilized more efficiently.

Description

[0001] Priority application

[0002] This application claims priority to U.S. patent application No. 17 / 816,833, filed on August 2, 2022, entitled “REORDERING WORKLOADS TO IMPROVE CONCURRENCY ACROSSTHREADS IN PROCESSOR-BASED DEVICES,” the entire contents of which are incorporated herein by reference. Technical Field

[0003] The technology of this disclosure generally relates to multithreading in processor-based devices. Background Art

[0004] Modern processor-based devices include a dedicated processing unit called a graphics processing unit (GPU) to accelerate the rendering of graphics and video data for display. The GPU can be implemented as an integrated component of a general-purpose central processing unit (CPU), or as a discrete hardware component separated from the CPU. Due to its highly parallel architecture and structure (including, for example, multiple cores, each core having its own graphics hardware pipeline), the GPU performs algorithms for parallel processing of large blocks of data more efficiently than a general-purpose CPU. For example, a GPU can render a three-dimensional (3D) graphic image using a mode called "tile rendering" or "bin-based rendering". The GPU subdivides an image that can be decomposed into triangles into multiple smaller tiles. The GPU then determines which triangles that make up the image are visible in each tile, and renders each tile continuously using the fast on-chip memory in the GPU to keep a portion of the image in the tile. Once the tile has been rendered, the on-chip memory is copied to its appropriate location in the system memory for output to the display, and the next tile is rendered.

[0005] The process of rendering tiles by the GPU can be further broken down into multiple operations that can be executed concurrently in separate processor cores or graphics hardware pipelines. For example, tile rendering can involve a tile visibility thread executed on a first processor core, a rendering thread executed on a second processor core, and a parsing thread executed on a third processor core. The purpose of the tile visibility thread is to determine which triangles contribute fragments to each tile, and the result is a visibility stream that contains a bit for each triangle checked, and the bit indicates whether the triangle is visible in a given tile. The visibility stream is compressed and written to system memory. The GPU also executes a rendering thread to draw the portion of the image located within each tile, and performs pixel rasterization and shading. Triangles that are not eliminated by the visibility stream check are rendered by this thread. Finally, the GPU can also execute a parsing thread to copy portions of the image contained in each tile to the system memory. After the rendering of the tile is completed, the color content of the rendered tile is parsed into the system memory before continuing to the next tile.

[0006] As described above, using separate processor cores or graphics hardware pipelines to, for example, execute a tile visibility thread and a rendering thread in parallel can result in improved GPU performance. However, cross-thread resource dependencies between workloads executed by separate cores may limit the GPU's ability to execute workloads concurrently. For example, one GPU core may need to suspend execution of a workload that depends on the results of a workload still executing in another GPU core. This may result in underutilization of the GPU's processing resources and increased execution time. Note that while this article discusses issues of concurrency affected by cross-thread dependencies in the context of multi-core GPUs, similar issues may arise in devices based on multi-core processors where cross-thread dependencies may arise. Summary of the invention

[0007] Various aspects disclosed in the detailed description include reordering workloads to improve cross-thread concurrency in a processor-based device. Related apparatus, methods, and computer-readable media are also disclosed. In this regard, in some exemplary aspects disclosed herein, a processor-based device (e.g., using a workload execution reordering circuit of a graphics processing unit (GPU), or by executing a driver or other software including a workload execution reordering process) receives multiple workloads from a requester (e.g., an application or an application programming interface (API)). The processor-based device constructs a weighted dependency graph based on the multiple workloads, wherein the weighted dependency graph includes: multiple vertices, each vertex corresponding to a workload in the multiple workloads; and also includes one or more directed edges, each directed edge connecting two vertices and indicating a dependency between the corresponding two workloads. In some aspects, a directed edge representing a cross-thread dependency can be associated with an edge weight derived based on a distance between the two vertices. Some aspects can generate a vertex weight for each vertex corresponding to a workload independent of the cross-thread dependency. After generating the weighted dependency graph, the processor-based device performs a topological sort of the weighted dependency graph (e.g., based on edge weights and / or vertex weights, if applicable). Some aspects may provide that the processor-based device may assign a vertex priority to each of a plurality of vertices, and process the plurality of vertices in an order indicated by the vertex priority of each vertex. Finally, the processor-based device generates a workload execution order based on the topological sort. According to some aspects, the processor-based device may use the generated workload execution order to schedule independent workloads of the plurality of workloads to execute during idle time (i.e., time during which the processor would otherwise be paused due to dependencies between the workloads) between two dependent workloads of the plurality of workloads. In this way, concurrency between threads may be maximized by more efficiently using processor resources.

[0008] In another aspect, a processor-based device is provided. The processor-based device includes a workload execution reordering circuit configured to receive a plurality of workloads from a requester. The workload execution reordering circuit is further configured to construct a weighted dependency graph based on the plurality of workloads, wherein the weighted dependency graph includes: a plurality of vertices, each vertex corresponding to a workload in the plurality of workloads; and one or more directed edges, each directed edge connecting two vertices in the plurality of vertices and indicating a dependency between corresponding two workloads in the plurality of workloads. The workload execution reordering circuit is further configured to perform a topological sort on the weighted dependency graph. The workload execution reordering circuit is additionally configured to generate a workload execution order based on the topological sort.

[0009] On the other hand, a processor-based device is provided. The processor-based device includes a unit for receiving a plurality of workloads from a requester. The processor-based device further includes a unit for constructing a weighted dependency graph based on the plurality of workloads, wherein the weighted dependency graph includes: a plurality of vertices, each vertex corresponding to a workload in the plurality of workloads; and one or more directed edges, each directed edge connecting two vertices in the plurality of vertices and indicating a dependency between corresponding two workloads in the plurality of workloads. The processor-based device also includes a unit for performing a topological sort on the weighted dependency graph. The processor-based device further includes a unit for generating an execution order of the workloads based on the topological sort.

[0010] In another aspect, a method for reordering workloads to improve cross-thread concurrency is provided. The method includes receiving a plurality of workloads from a requester by executing a workload reordering process on a processor-based device. The method further includes constructing a weighted dependency graph based on the plurality of workloads, wherein the weighted dependency graph includes: a plurality of vertices, each vertex corresponding to a workload in the plurality of workloads; and one or more directed edges, each directed edge connecting two vertices in the plurality of vertices and indicating a dependency between corresponding two workloads in the plurality of workloads. The method also includes performing a topological sort on the weighted dependency graph. The method further includes generating a workload execution order based on the topological sort.

[0011] On the other hand, a non-transitory computer-readable medium is provided. The non-transitory computer-readable medium has computer-executable instructions stored thereon, which, when executed by a processor of a processor-based device, cause the processor to receive a plurality of workloads from a requester. The computer-executable instructions further cause the processor to construct a weighted dependency graph based on the plurality of workloads, wherein the weighted dependency graph includes: a plurality of vertices, each vertex corresponding to a workload in the plurality of workloads; and one or more directed edges, each directed edge connecting two vertices in the plurality of vertices and indicating a dependency between corresponding two workloads in the plurality of workloads. The computer-executable instructions also cause the processor to perform a topological sort of the weighted dependency graph. The computer-executable instructions further cause the processor to generate a workload execution order based on the topological sort. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 is a block diagram of an exemplary processor-based device configured to reorder workloads to improve cross-thread concurrency according to some aspects;

[0013] Figure 2A and Figure 2Bis a block diagram illustrating how reordering workloads according to some aspects disclosed herein can improve concurrency by reducing the occurrence of pauses during execution of threads;

[0014] Figure 3A and Figure 3B is a flow chart illustrating exemplary operations for constructing a weighted dependency graph to represent dependencies between multiple workloads according to some aspects;

[0015] Figures 4A-4G It shows that according to Figure 3A and Figure 3B A block diagram of a weighted dependency graph constructed by the exemplary operations described in;

[0016] Figures 5A-5C is a method for performing a topological sort to linearize Figures 4A-4G A flowchart of an exemplary operation of a weighted dependency graph shown in;

[0017] Figures 6A-6H It is shown in Figures 4A-4G The weighted dependency graph shown in Figures 5A-5C A block diagram of exemplary operations of to generate a result of a workflow execution sequence;

[0018] Fig. 7A and Figure 7B It is shown Figure 1 A flowchart of exemplary operations of software and / or hardware elements of a processor-based device for reordering workloads to improve cross-thread concurrency; and

[0019] Figure 8 Yes, it can include Figure 1 A block diagram of an exemplary processor-based device of a processor-based device. DETAILED DESCRIPTION

[0020] Referring now to the drawings, several exemplary aspects of the present disclosure are described. The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any aspect described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects.

[0021] Various aspects disclosed in the detailed description include reordering workloads to improve cross-thread concurrency in a processor-based device. Related apparatus, methods, and computer-readable media are also disclosed. In this regard, in some exemplary aspects disclosed herein, a processor-based device (e.g., using a workload execution reordering circuit of a graphics processing unit (GPU), or by executing a driver or other software including a workload execution reordering process) receives multiple workloads from a requester (e.g., an application or an application programming interface (API)). The processor-based device constructs a weighted dependency graph based on the multiple workloads, wherein the weighted dependency graph includes: multiple vertices, each vertex corresponding to a workload in the multiple workloads; and also includes one or more directed edges, each directed edge connecting two vertices in the vertices and indicating a dependency between the corresponding two workloads. In some aspects, a directed edge representing a cross-thread dependency can be associated with an edge weight derived based on a distance between the two vertices. Some aspects can generate a vertex weight for each vertex corresponding to a workload that is independent of the cross-thread dependency. After generating the weighted dependency graph, the processor-based device performs a topological sort of the weighted dependency graph (e.g., based on edge weights and / or vertex weights, if applicable). Some aspects may provide that the processor-based device may assign a vertex priority to each of a plurality of vertices, and process the plurality of vertices in an order indicated by the vertex priority of each vertex. Finally, the processor-based device generates a workload execution order based on the topological sort. According to some aspects, the processor-based device may use the generated workload execution order to schedule independent workloads of the plurality of workloads to be executed during an idle time between two dependent workloads of the plurality of workloads. In this way, concurrency between threads may be maximized by more efficiently using processor resources.

[0022] In this regard, Figure 1 1 is a block diagram of an exemplary processor-based device 100 including a processor 102. The processor 102 (which may also be referred to as a "processor core" or a "central processing unit (CPU) core") may be an in-order processor or an out-of-order processor (OoP), and / or may be one of a plurality of processors 102 provided by the processor-based device 100. Figure 1 In the example of FIG. 1 , processor 102 includes a graphics processing unit (in Figure 1 1 , and includes dedicated processing circuitry for handling rendering of graphics and / or video data for display. Figure 1 Processor 102 also executes a requester 106 , which may include a software application or API that submits a workload representing graphics and / or video data for processing by GPU 104 .

[0023] Figure 1 The processor-based device 100 may include any of known digital logic elements, semiconductor circuits, processing cores, and / or memory structures, as well as other elements or combinations thereof. The aspects described herein are not limited to any particular arrangement of elements, and the disclosed techniques may be readily extended to various structures and layouts on a semiconductor die or package. It should be understood that some aspects of the processor-based device 100 may include, in addition to Figure 1 Elements other than those shown, and / or may include Figure 1 For example, the processor-based device 100 may also include one or more CPUs, processor cores, caches, controllers, communication buses, and / or persistent storage devices, which are not described in detail for clarity. Figure 1 Omitted in .

[0024] like Figure 1 As shown, requester 106 has generated a plurality of workloads 108(0)-108(W) to send to GPU 104, each workload comprising, for example, a sequence of graphics instructions and / or operations for generating an image or video. A conventional GPU would receive workloads 108(0)-108(W) and would process each of workloads 108(0)-108(W) in sequence using a visualization thread and a rendering thread, with work being performed concurrently in each thread when possible. However, cross-thread dependencies (i.e., dependencies between workloads in different threads) that may exist between workloads 108(0)-108(W) may result in a pause in one thread while a workload waits for completion of another workload in another thread. For example, if a visualization operation of workload 108(1) depends on the results of a rendering operation of workload 108(0), but the rendering thread does not complete its processing of workload 108(0) quickly enough, the visualization thread will have to pause processing of workload 108(0). This results in wasted GPU processor resources and negatively impacts the performance of GPU 104 .

[0025] Thus, in this regard, the processor-based device 100 is configured to provide reordering of workloads to improve cross-thread concurrency. In some aspects, the processor 102 can be configured to execute a driver 110 that includes a workload execution reordering process 112 that performs the operations described herein for reordering workloads. Some aspects can provide that the processor 102 includes a workload execution reordering circuit 114 that embodies logic for performing the operations described herein for reordering workloads. In these aspects, the workload execution reordering circuit 114 can be implemented as Figure 1 The workload execution reordering circuit 114 may be a separate element as shown, or may be integrated into the GPU 104. For example, the workload execution reordering circuit 114 may be an element of a command processor (CP) (not shown) of the GPU 104, and may receive information required for the operation as a preamble to a command buffer (not shown).

[0026] In exemplary operation, processor 102 receives workloads 108(0)-108(W) from requestor 106 (e.g., by executing workload execution reordering process 112 or by using workload execution reordering circuit 114) and constructs weighted dependency graph 116 based on multiple workloads 108(0)-108(W). Figures 4A-4G In more detail, the weighted dependency graph 116 includes a plurality of vertices (not shown), each vertex being a point corresponding to a workload in the plurality of workloads 108(0)-108(W), and also includes one or more directed edges, each directed edge connecting two vertices in the vertices and indicating a dependency between the corresponding two workloads. In some aspects, the weighted dependency graph 116 may include a directed acyclic graph (DAG) (i.e., a directed graph without directed cycles).

[0027] After generating the weighted dependency graph 116, the processor 102 performs a topological sort of the weighted dependency graph 116, as indicated by arrow 118, to linearize the weighted dependency graph 116. As used herein, "topological sort" refers to a linear ordering of the vertices of the weighted dependency graph 116 such that for each directed edge uv from vertex u to vertex v, u precedes v in the ordering. As a non-limiting example, the topological sorting may be based on, for example, Kahn's sorting algorithm. Finally, the processor 102 generates a workload execution order 120 based on the topological sorting. The GPU 104 of the processor 102 then uses the workload execution order 120 to schedule the workloads 108(0)-108(W) in an order that may improve cross-thread concurrency. Figure 1 As shown, workload execution order 120 reorders workloads 108(0)-108(W) such that workload 108(W) (which in this example has no dependencies on other workloads and is therefore considered "independent") is executed before workload 108(1).

[0028] To illustrate how reordering workloads 108(0)-108(W) can improve concurrency by reducing the occurrence of pauses during execution of threads, Figure 2A and Figure 2BGPU execution timelines 200 and 202 are provided, respectively. GPU execution timeline 200 represents the regular execution of workloads 108(0)-108(W) in their original sequence, while GPU execution timeline 202 represents the execution of workloads 108(0)-108(W) according to Figure 1 The execution of workload execution order 120. GPU execution timeline 200 shows columns representing visualization thread 204 and rendering thread 206, while GPU execution timeline 202 shows columns representing visualization thread 208 and rendering thread 210.

[0029] for Figure 2A and Figure 2B , assuming that there is a cross-thread dependency between the visualization phase of workload 108(1) and the rendering phase of workload 108(0), while workload 108(W) does not depend on any other workload and is therefore independent. Figure 2A As shown in GPU execution timeline 200, after visualization thread 204 completes visualization of workload 108(0) and rendering thread 206 begins rendering of workload 108(0), visualization thread 204 cannot begin visualization of workload 108(1) until rendering thread 206 completes rendering of workload 108(0) (due to the dependency between visualization of workload 108(1) and rendering of workload 108(0). Therefore, visualization thread 204 must be paused. Similarly, once rendering thread 206 completes rendering of workload 108(0), rendering thread 206 cannot begin rendering of workload 108(1) until visualization thread 204 completes visualization of workload 108(1). Therefore, rendering thread 206 must be paused.

[0030] On the contrary, Figure 2B In the GPU execution timeline 202 in FIG. 1 , the order in which the workloads are executed has changed so that the independent workload 108(w) is executed between workloads 108(0) and 108(1). This is because Figure 2A As shown in the original order of workloads 108(0)-108(w) in FIG, due to the cross-thread dependency between workloads 108(0) and 108(1), workload 108(1) cannot be visualized until workload 108(0) is rendered. Thus, the reordering of the sequence of workload execution results in greater concurrency and shorter overall execution time because visualization thread 208 and rendering thread 210 can perform workload 108(w) visualization and workload 108(w) rendering, respectively, during times when the threads would otherwise be paused.

[0031] For the sake of Figure 2BThe sequence of workloads shown is reordered so that workload 108(W) is executed before workload 108(1), and cross-thread dependencies between workload 108(0) and workload 108(1) are determined and processed. In one example discussed below, in accordance with some aspects, such cross-thread dependencies are determined and tracked by constructing a weighted dependency graph to represent dependencies between multiple workloads. In this regard, to illustrate example operations for constructing a weighted dependency graph including a DAG to represent dependencies between multiple workloads in accordance with some aspects, a method is provided. Figure 3A and Figure 3B . Figure 3A and Figure 3B A flow chart illustrating an exemplary process 300 for constructing a weighted dependency graph is provided. Figure 3A and Figure 3B In the example process 300 of , it is assumed that according to the requester (e.g., Figure 1 The following describes the order in which the workload is processed. Figures 4A-4G The exemplary multiple workload execution is shown and discussed in more detail. Figure 3A and Figure 3B The result of the operation of process 300.

[0032] exist Figure 3A , the operations of process 300 begin at a processor (e.g., Figure 1 The processor 102 receives a plurality of workloads (e.g., Figure 1 The processor 102 determines whether there are more workloads to process (block 304). If there are no more workloads to process, then the operation ends. However, if the processor 102 determines at decision block 304 that there are more workloads to process, then the processor 102 adds the vertex corresponding to the current workload to the weighted dependency graph (block 306). The processor 102 then determines whether there are any dependencies between the current workload and the previous workload (block 308). If not, then at Figure 3B Operation continues at block 312 of . If the processor 102 determines at decision block 308 that a dependency exists, the processor 102 adds a directed edge corresponding to the dependency to the weighted dependency graph (block 310). Then Figure 3B Continue at block 312 in FIG.

[0033] Now turn to Figure 3B, the process 300 continues, and the processor 102 next determines whether there is a last tracked cross-thread dependency (i.e., whether the cross-thread dependency has been previously encountered and tracked by, for example, setting a last tracked cross-thread dependency indicator) (block 312). If there is no last tracked cross-thread dependency, then Figure 3B Operation resumes at block 314 of the . However, if the processor 102 determines at decision block 312 that the last tracked cross-thread dependency does exist, the processor 102 determines whether the current workload is independent of the last tracked cross-thread dependency (block 316). If not, then at Figure 3B Operation resumes at block 314. If the processor 102 determines at decision block 316 that the current workload is independent of the last tracked cross-thread dependency, the processor 102 adds vertex weights to the vertices based on the distance from the last tracked cross-thread dependency (block 318).

[0034] Processor 102 next determines whether the current workload has cross-thread dependencies (block 314). If not, then Figure 3A Operation resumes at block 304 of the process. However, if the processor 102 determines at decision block 314 that the current workload has a cross-thread dependency, the processor 102 adds an edge weight to the directed edge representing the cross-thread dependency (block 320). The processor 102 also updates the last tracked cross-thread dependency (i.e., indicates the current workload as the last encountered cross-thread dependency) (block 322). Then, Figure 3A Operation is resumed at box 304.

[0035] Figures 4A-4G Shown according to Figure 3A and Figure 3B 4. Construction of the weighted dependency graph 400 of the exemplary process 300 described in FIG. For illustration, assume that a requester (e.g., Figure 1 The requester 106) receives a plurality of workloads 108(0)-108(6) (i.e., Figure 1 108(0)-108(W), where W=6). Figure 4A As shown, vertex 402(0) is added to weighted dependency graph 400 to represent workload 108(0), the first workload processed from requester 106. Because workload 108(0) is first, there are no other workloads on which it depends. Vertex 402(0) is assigned a vertex weight 404(0) of zero (0).

[0036] exist Figure 4B, processing workload 108(1) causes vertex 402(1) to be added to weighted dependency graph 400. Processor 102 determines, based on the dependency information, that workload 108(1) has a cross-thread dependency on workload 108(0), and therefore adds directed edge 406(0) associated with edge weight 408(0) between vertex 402(0) and vertex 402(1). Edge weight 408(0) is set to a value of seven (7), which in this example is determined by dividing the total number of workloads (i.e., 7) by the logical distance between vertex 402(0) and vertex 402(1) (i.e., 1). Vertex 402(1) is assigned a vertex weight 404(1) of zero (0). In addition, the last tracked cross-thread dependency (not shown) is set to indicate vertex 402(0).

[0037] exist Figure 4C , processing of workload 108(2) results in vertex 402(2) being added to weighted dependency graph 400. Processor 102 determines, based on the dependency information, that workload 108(2) is not dependent on any other workload. Because workload 108(2) is independent of the last tracked cross-thread dependency, vertex 402(2) is assigned a vertex weight 404(2) of two (2), which is determined based on the logical distance between vertex 402(2) and the last tracked cross-thread dependency (i.e., vertex 402(0)).

[0038] exist Figure 4D , vertex 402(3) is added to weighted dependency graph 400 to represent workload 108(3). Processor 102 determines that workload 108(3) has an intra-thread dependency on workload 108(0), and therefore adds directed edge 406(1). Because the dependency is not a cross-thread dependency, directed edge 406(1) is unweighted (i.e., assigned an edge weight 408(1) of zero (0)). Vertex 402(3) depends on the last tracked cross-thread dependency (i.e., vertex 402(0)), and therefore vertex weight 404(3) of vertex 402(3) is set to zero (0).

[0039] exist Figure 4E, workload 108(4) is processed, resulting in vertex 402(4) being added to weighted dependency graph 400. Processor 102 determines that workload 108(4) has a cross-thread dependency on workload 108(2), and therefore adds directed edge 406(2) with edge weight 408(2) being 3.5 (i.e., the total number of workloads (7) divided by the logical distance between vertex 402(4) and vertex 402(2), which is 2). Because vertex 402(4) is also independent of the last tracked cross-thread dependency (i.e., vertex 402(0)), vertex 402(4) is assigned a vertex weight 404(4) having a value of four (4) (i.e., the logical distance between vertex 402(4) and vertex 402(0)). Finally, because vertex 402(4) has a cross-thread dependency on vertex 402(2), the last tracked cross-thread dependency is updated to indicate vertex 402(2).

[0040] exist Figure 4F , processing of workload 108(5) results in vertex 402(5) being added to weighted dependency graph 400. Processor 102 determines that vertex 402(5) has an intra-thread dependency on vertex 402(3). Therefore, directed edge 406(3) is added from vertex 402(3) to vertex 402(5) with edge weight 408(3) being zero (0). Because vertex 402(5) is independent of the last tracked cross-thread dependency (i.e., vertex 402(2)), vertex 402(5) is assigned a vertex weight 404(5) having a value of three (3), i.e., the logical distance between vertex 402(5) and vertex 402(2).

[0041] Finally, in Figure 4G , vertex 402(6) is added to represent workload 108(6). Processor 102 determines that workload 108(6) depends on both workload 108(2) and workload 108(4). The dependency on workload 108(2) is an intra-thread dependency, so an edge weight 408(4) of zero (0) is added to directed edge 406(4). Workload 108(6) has a cross-thread dependency on workload 108(4), so an edge weight 408(5) of 3.5 (i.e., the total number of workloads (7) divided by the logical distance between vertex 402(6) and vertex 402(4), which is 2) is added to directed edge 406(5). Note that because vertex 402(6) is independent of the last tracked cross-thread dependency (i.e., vertex 402(2)), vertex 402(6) is assigned a vertex weight 404(6) of zero (0).

[0042] To illustrate the use of topological sorting to linearize Figures 4A-4G 400 according to some aspects, Figures 5A-5C 4 is a flow chart illustrating an exemplary process 500 for sorting the weighted dependency graph 400. The operations of the process 500 are as follows: Figure 5A In the processor (for example, Figure 1 The execution of the workload execution reordering process 112 or by the processor 102 using the workload execution reordering circuit 114 begins (block 502) by setting the execution sequence number to zero (0). When the execution sequence is determined, a current value of the execution sequence is assigned to each workload to indicate its position in the generated workload execution sequence.

[0043] Processor 102 next obtains a list of all vertices 402(0)-402(6) in weighted dependency graph 400 (block 504). Processor 102 determines whether there are more vertices to check (block 506). If not, then Figure 5A Operation resumes at block 508 of the decision block. However, if processor 102 determines at decision block 506 that there are more vertices, processor 102 determines whether the current vertex is independent (block 510). If not, then Figure 5A Operation resumes at block 506 of . If processor 102 determines that the current vertex is independent, processor 102 adds the vertex to the priority queue (block 512). Processor 102 then determines whether the priority queue is empty (block 508). If so, processing ends. If not, Figure 5B The process continues at block 514.

[0044] Now turn to Figure 5B , process 500 continues with processor 102 dequeuing the next vertex in the priority queue (block 514). Processor 102 assigns the current value of the execution sequence number to the vertex (block 516). Processor 102 then increments the current value of the execution sequence number by one (1) (block 518). Next, processor 102 determines whether the vertex has an adjacent vertex (block 520). If not, operation returns to Figure 5A 508. However, if the processor 102 determines at decision block 520 that the vertex has an adjacent vertex, the processor 102 removes the directed edge connecting the vertex and the adjacent vertex (block 522). The processor 102 determines whether the adjacent vertex is now independent (block 524). If not, the operation returns to Figure 5A If the processor 102 determines that the adjacent vertices are now independent, the operation is performed at block 508. Figure 5C Continue at box 526.

[0045] Reference now Figure 5C , process 500 continues with processor 102 determining whether the adjacent vertices have weighted edges (block 526). If not, then Figure 5COperation continues at block 528 of the priority queue. If it is determined at decision block 528 that the adjacent vertex has a weighted edge, the processor 102 propagates the vertex weight of the adjacent vertex and the maximum edge weight of the adjacent vertex to the existing vertices in the priority queue (block 530). The processor 102 then adds the adjacent vertex to the priority queue (block 528). Operation then returns to Figure 5A Frame 508 in .

[0046] Figures 5A-5C is used to execute Figures 4A-4G The result of the exemplary operation of topologically sorting the weighted dependency graph 400 shown in FIG. 4 and generating a workflow execution order is shown in FIG. Figures 6A-6H When processing the weighted dependency graph 400, Figures 6A-6H The effect on the priority queue 600 and the workload execution order 120 is shown. To determine the priority with which vertices 402(0)-402(6) of the weighted dependency graph 400 are to be processed, the vertex priority P may be generated using the following equation, where V is the set of numeric vertex identifiers V1, vertex weights V2, and edge weights V3, and N is the total number of vertices in the graph G:

[0047] P(V)=(N-V1)+V2+V3

[0048] exist Fig. 6A , a breadth-first search is performed on all independent vertices in vertices 402(0)-402(6). Vertex 402(0) and vertex 402(2) have no dependencies, so they are added to priority queue 600. The vertex priority of vertex 402(0) is calculated as P(V0)=7-0+0+7=14, while the vertex priority of vertex 402(2) is calculated as P(V2)=(7-2)+2+3.5=10.5. Therefore, the highest priority vertex is determined to be vertex 402(0).

[0049] exist Figure 6B , vertex 402(0) (the highest priority vertex) is dequeued from priority queue 600 and the corresponding workload 108(0) is assigned execution sequence number zero (0) in workload execution order 120. Vertex 402(1) and vertex 402(3), i.e., the vertices adjacent to vertex 402(0), are then processed. Fig. 6A Directed edges 406(0) and 406(1) are removed, and because vertex 402(1) and vertex 402(3) each have no other edges and now have no dependencies, they are added to priority queue 600. The vertex priority of vertex 402(1) is calculated as P(V1)=7-1+0+0=6, and the vertex priority of vertex 402(3) is calculated as P(V3)=7-3+0+0=4.

[0050] exist Figure 6C , vertex 402(2) (the current highest priority vertex) is dequeued from priority queue 600 and the corresponding workload 108(2) is assigned execution sequence number one (1) in workload execution order 120. Adjacent vertex 402(4) and adjacent vertex 402(6) are processed and removed from weighted dependency graph 400. Figure 6A-6B 4. As shown in FIG. 1 , vertex 402(4) has corresponding directed edges 406(2) and 406(4) of vertex 402(6). Because vertex 402(4) is now independent, processor 102 determines whether vertex 402(4) has a directed edge with an assigned edge weight. In this case, vertex 402(4) has directed edge 406(5) to vertex 402(6) with an edge weight 408(5) of 3.5, and therefore the vertex weights and vertex priorities of all vertices in priority queue 600 (i.e., vertex 402(1) and vertex 402(3)) are updated.

[0051] The updated vertex weight 404(1) of vertex 402(1) is calculated as follows:

[0052] W(V1,G)=W(V1)'+W(V4)+E(V4)=0+4+3.5=7.5

[0053] The updated vertex priority of vertex 402(1) is calculated as follows:

[0054] P(V1)=P(V1)'+V2+V3=6+4+3.5=13.5

[0055] The updated vertex weight 404(3) of vertex 402(3) is calculated as follows:

[0056] W(V3,G)=W(V3)'+W(V4)+E(V4)=0+4+3.5=7.5

[0057] The updated vertex priority of vertex 402(3) is calculated as follows:

[0058] P(V3)=P(V3)'+V2+V3=4+4+3.5=11.5

[0059] Once the vertex priorities of vertex 402(1) and vertex 402(3) are updated, vertex 402(4) is enqueued in priority queue 600 because it is now independent. The vertex priority of vertex 402(4) is calculated as P(V4) = (7 - 4) + 4 + 3.5 = 10.5.

[0060] exist Fig.6D, vertex 402(1) (the current highest priority vertex) is dequeued from priority queue 600 and the corresponding workload 108(1) is assigned execution sequence number two (2) in workload execution order 120. Because there are no directed edges from vertex 402(1), processing continues to the next vertex in priority queue 600.

[0061] exist Fig. 6E , vertex 402(3) (the current highest priority vertex) is dequeued from priority queue 600, and the corresponding workload 108(3) is assigned execution sequence number three(3) in workload execution order 120. The adjacent vertex 402(5) is processed, and removed. Figures 6A-6D Directed edge 406(3) from vertex 402(3) to vertex 402(5) is added to priority queue 600. Because vertex 402(5) does not have any outgoing directed edges assigned edge weights, the priority of the vertices in priority queue 600 is not adjusted. In addition, since vertex 402(5) has no incoming directed edges, vertex 402(5) is added to priority queue 600 and its vertex priority is calculated as P(V5)=(7-5)+3=5.

[0062] exist Fig. 6F , vertex 402(4) (the current highest priority vertex) is dequeued from priority queue 600, and the corresponding workload 108(4) is assigned execution sequence number four(4) in workload execution order 120. The adjacent vertex 402(6) is processed, and the Figures 6A-6E Directed edge 406(5) from vertex 402(4) to vertex 402(6) is added to priority queue 600. Because vertex 402(6) does not have any outgoing directed edges assigned edge weights, the priority of the vertices in priority queue 600 is not adjusted. In addition, since vertex 402(6) has no incoming directed edges, vertex 402(6) is added to priority queue 600 and its vertex priority is calculated as P(V6)=(7-6)+0=1.

[0063] exist Figure 6G , vertex 402(5) (the current highest priority vertex) is dequeued from priority queue 600 and the corresponding workload 108(5) is assigned execution sequence number five(5) in workload execution order 120. Because there are no directed edges from vertex 402(5), processing continues to the next vertex in priority queue 600.

[0064] Finally, in Figure 6H, vertex 402(6) (the current highest priority vertex) is dequeued from priority queue 600 and the corresponding workload 108(6) is assigned execution sequence number six(6) in workload execution order 120. Because vertex 402(6) has no outgoing directed edges and priority queue 600 is now empty, generation of workload execution order 120 is complete.

[0065] To illustrate Figure 1 Exemplary operations of software and / or hardware elements of the processor-based device 100 for reordering workloads to improve cross-thread concurrency, Fig. 7A and Figure 7B A flow chart 700 is provided. For clarity, in describing Fig. 7A and Figure 7B Reference Figure 1 , Figures 4A-4G and Figures 6A-6H The operations in FIG. 7 are performed by a processor (e.g., Figure 1 of the workload execution reordering process 112 or by using the workload execution reordering circuit 114 of the processor 102) from the requestor (e.g., Figure 1 Requestor 106) receives multiple workloads (e.g., Figure 1 The processor 102 constructs a weighted dependency graph (e.g., Figures 4A-4G ), wherein the weighted dependency graph 400 includes: a plurality of vertices (eg, Figures 4A-4G 402(0)-402(6)), each vertex corresponding to a workload in the plurality of workloads 108(0)-108(W); and one or more directed edges (e.g., Figures 4A-4G Directed edges 406(0)-406(5)), each directed edge connecting two vertices among the plurality of vertices 402(0)-402(6) and indicating a dependency between corresponding two workloads among the plurality of workloads 108(0)-108(W) (block 704).

[0066] It should be appreciated that, according to some aspects, the operations of block 704 for constructing the weighted dependency graph 400 may be performed by performing the above-described Figure 3A and Figure 3B as well as Figures 4A-4G Thus, in some aspects, the operations of block 704 for constructing the weighted dependency graph 400 may include placing directed edges (e.g., Figures 4A-4G directed edge 406(0)) and edge weight (e.g., Figures 4A-4G408(0)) is associated (block 706), the edge weight being derived from the distance between the two vertices 402(0), 402(1) corresponding to the two corresponding workloads 108(0), 108(1). Some aspects may provide that the operations of block 704 for constructing the weighted dependency graph 400 may include for one or more workloads (e.g., Figures 4A-4G workloads 108(1)), generating one or more vertices corresponding to one or more workloads 108(1) (e.g., Figures 4A-4G The corresponding one or more vertex weights (e.g., Figures 4A-4G Vertex weight 404(1)) (block 708). Figure 7B Continue at box 710.

[0067] Reference now Figure 7B , the processor 102 then performs a topological sort of the weighted dependency graph 400 (block 710). It should be appreciated that, according to some aspects, the operations of block 710 for performing a topological sort of the weighted dependency graph 400 may be performed by performing the above-described Figures 5A-5C and Figures 6A-6H The operations described and illustrated are completed. Thus, in some aspects, the operations of box 710 for performing a topological sort of the weighted dependency graph 400 can be based on edge weights 408(0) (box 712). Some aspects can provide that the operations of box 710 for performing a topological sort of the weighted dependency graph 400 are based on one or more vertex weights 404(1) (box 714). According to some aspects, the operations of box 710 for performing a topological sort of the weighted dependency graph 400 can include assigning a vertex priority to each vertex in the plurality of vertices 402(0)-402(6) (box 716). The processor 102 then processes the plurality of vertices 402(0)-402(6) in an order indicated by the vertex priority of each vertex (box 718).

[0068] The processor 102 then generates a workload execution order based on the topological sort (e.g., Figure 1 and Figures 6A-6H In some aspects, the processor 102 may schedule independent workloads (e.g., Figure 1 and Figures 6A-6H workload 108(1)) in the plurality of workloads 108(0)-108(W)) in two dependent workloads (e.g., Figure 1 and Figures 6A-6HExecute during idle time between workloads 108(0), 108(2)) in (block 722).

[0069] Reordering workloads to improve cross-thread concurrency according to various aspects disclosed herein can be provided in or integrated into any processor-based device. Examples include, but are not limited to, set-top boxes, entertainment units, navigation devices, communication devices, fixed location data units, mobile location data units, global positioning system (GPS) devices, mobile phones, cellular phones, smart phones, session initiation protocol (SIP) phones, tablet computers, tablet phones, servers, computers, portable computers, mobile computing devices, laptop computers, wearable computing devices (e.g., smart watches, health or fitness trackers, glasses, etc.), desktop computers, personal digital assistants (PDAs), monitors, computer monitors, televisions, tuners, radios, satellite radios, music players, digital music players, portable music players, digital video players, video players, digital video disk (DVD) players, portable digital video players, automobiles, vehicle components, avionics systems, drones, and multicopters.

[0070] in this regard, Figure 8 It shows that it can include Figure 1 1. An example of a processor-based device 800 of the processor-based device 100 is shown. In this example, the processor-based device 800 includes a processor 802, which includes one or more central processing units (CPUs). Figure 8 804, which may also be referred to as a CPU core or processor core. The processor 802 may have a cache memory 806 coupled to the processor 802 for quickly accessing temporarily stored data. The processor 802 is coupled to a system bus 808 and may mutually couple master devices and slave devices included in the processor-based device 800. As is well known, the processor 802 communicates with these other devices by exchanging address, control, and data information on the system bus 808. For example, the processor 802 may transmit a bus transaction request to a memory controller 810 (as an example of a slave device). Although not shown in FIG. Figure 8 Although not shown in FIG. 8 , multiple system buses 808 may be provided, each of which may constitute a different structure.

[0071] Other master devices and slave devices may be connected to the system bus 808. Figure 8As shown, as an example, these devices may include a memory system 812, which includes a memory controller 810 and (multiple) memory arrays 814, one or more input devices 816, one or more output devices 818, one or more network interface devices 820, and one or more display controllers 822. The (multiple) input device 816 may include any type of input device, including but not limited to input keys, switches, voice processors, etc. The (multiple) output device 818 may include any type of output device, including but not limited to audio, video, other visual indicators, etc. The (multiple) network interface device 820 may be any device configured to allow data to be exchanged to and from the network 824. The network 824 may be any type of network, including but not limited to a wired or wireless network, a private or public network, a local area network (LAN), a wireless local area network (WLAN), a wide area network (WAN), a BLUETOOTH TM Networks and the Internet. The network interface device(s) 820 may be configured to support any type of communication protocol desired.

[0072] The processor 802 may also be configured to access display controller(s) 822 via the system bus 808 to control information sent to one or more displays 826. The display controller(s) 822 sends information to be displayed to the display(s) 826 via one or more video processors 828, which process the information to be displayed into a format suitable for the display(s) 826. The display(s) 826 may include any type of display, including but not limited to a cathode ray tube (CRT), a liquid crystal display (LCD), a plasma display, etc.

[0073] Those skilled in the art will further appreciate that the various illustrative logic blocks, modules, circuits and algorithms described in conjunction with the various aspects disclosed herein can be implemented as electronic hardware, stored in a memory or another computer-readable medium and executed by a processor or other processing device, or a combination of the two. The memory disclosed herein can be a memory of any type and size, and can be configured to store any type of information required. In order to clearly illustrate this interchangeability, they have been generally described above according to the functions of various illustrative components, blocks, modules, circuits and steps. How to implement such functions depends on specific applications, design choices and / or design constraints imposed on the entire system. The technician can implement the described functions in different ways for each specific application, but this implementation decision should not be interpreted as causing a deviation from the scope of the present disclosure.

[0074] The various illustrative logic blocks, modules, and circuits described in conjunction with the various aspects disclosed herein may be implemented or executed using a processor, digital signal processor (DSP), application specific integrated circuit (ASIC), field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. The processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, a combination of one or more microprocessors and a DSP core, or any other such configuration).

[0075] The various aspects disclosed herein may be embodied in hardware and in instructions stored in hardware, and may reside in, for example, random access memory (RAM), flash memory, read-only memory (ROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), registers, hard disks, removable disks, CD-ROMs, or any other form of computer-readable medium known in the art. An exemplary storage medium is coupled to a processor so that the processor can read information from the storage medium and write information to the storage medium. In an alternative, the storage medium may be an integral part of the processor. The processor and storage medium may reside in an ASIC. The ASIC may reside in a remote station. In an alternative, the processor and storage medium may reside in a remote station, a base station, or a server as discrete components.

[0076] It is also noted that the operational steps described in any exemplary aspects of this article are described to provide examples and discussions. The described operations can be performed in many different sequences other than the sequence shown. In addition, the operations described in a single operational step can actually be performed in multiple different steps. In addition, one or more operational steps discussed in the exemplary aspects can be combined. It should be understood that the operational steps shown in the flow chart can be modified in many different ways, which is obvious to those skilled in the art. Those skilled in the art will also understand that information and signals can be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols and chips that can be cited throughout the above description can be represented by voltage, current, electromagnetic waves, magnetic fields or particles, light fields or particles, or any combination thereof.

[0077] The foregoing description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations. Therefore, the disclosure is not intended to be limited to the examples and designs described herein, but to conform to the broadest scope consistent with the principles and novel features disclosed herein.

[0078] Examples of implementations are described in the following numbered clauses:

[0079] 1. A processor-based device comprising a workload execution reordering circuit, wherein the workload execution reordering circuit is configured to:

[0080] receiving a plurality of workloads from a requester;

[0081] A weighted dependency graph is constructed based on the plurality of workloads, wherein the weighted dependency graph comprises:

[0082] a plurality of vertices, each vertex corresponding to a workload in the plurality of workloads; and

[0083] one or more directed edges, each directed edge connecting two vertices of the plurality of vertices and indicating a dependency between corresponding two workloads of the plurality of workloads;

[0084] performing a topological sort of the weighted dependency graph; and

[0085] A workload execution order is generated based on the topological sort.

[0086] 2. A processor-based device according to claim 1, wherein the workload execution reordering circuit is further configured to: schedule an independent workload among the multiple workloads to be executed during an idle time between two dependent workloads among the multiple workloads based on the workload execution order.

[0087] 3. A processor-based apparatus as described in any of clauses 1-2, wherein the weighted dependency graph comprises a directed acyclic graph (DAG).

[0088] 4. A processor-based apparatus according to any of clauses 1-3, wherein the workload execution reordering circuit is configured to: perform the topological sorting based on Kahn's topological sorting algorithm.

[0089] 5. A processor-based device according to any of clauses 1 to 4, wherein:

[0090] A directed edge of the one or more directed edges represents a cross-thread dependency between the corresponding two workloads;

[0091] The workload execution reordering circuit is configured to: construct the weighted dependency graph by being configured to associate the directed edges with edge weights, the edge weights being derived from distances between the two vertices corresponding to the corresponding two workloads; and

[0092] The workload execution reordering circuit is configured to perform the topological sort based on the edge weights.

[0093] 6. The processor-based device of clause 5, wherein the edge weight is negatively correlated with a distance between two vertices corresponding to the two workloads.

[0094] 7. A processor-based device according to any of clauses 1 to 6, wherein:

[0095] The workload execution reordering circuitry is configured to: construct the weighted dependency graph by further being configured to, for one or more workloads independent of the cross-thread dependencies, generate corresponding one or more vertex weights for one or more vertices corresponding to the one or more workloads; and

[0096] The workload execution reordering circuitry is configured to perform the topological sorting further based on the one or more vertex weights.

[0097] 8. A processor-based device as described in clause 7, wherein each vertex weight of the one or more vertex weights is based on a logical distance from a vertex corresponding to the vertex weight to a vertex corresponding to a workload that causes the cross-thread dependency.

[0098] 9. The processor-based device of clause 7, wherein the workload execution reordering circuitry is configured to perform the topological sort by being further configured to:

[0099] assigning a vertex priority to each vertex of the plurality of vertices; and

[0100] The plurality of vertices are processed in an order indicated by the vertex priority of each vertex.

[0101] 10. The processor-based device of clause 9, wherein the vertex priority is determined based on the identity of each vertex, a vertex weight of the vertex, and an edge weight of the edge of the vertex.

[0102] 11. A processor-based device as described in any of clauses 1-10, which is integrated into a device selected from the group consisting of: a set-top box; an entertainment unit; a navigation device; a communication device; a fixed location data unit; a mobile location data unit; a global positioning system (GPS) device; a mobile phone; a cellular phone; a smart phone; a Session Initiation Protocol (SIP) phone; a tablet computer; a tablet phone; a server; a computer; a portable computer; a mobile computing device; a wearable computing device; a desktop computer; a personal digital assistant (PDA); a monitor; a computer monitor; a television; a tuner; a radio; a satellite radio; a music player; a digital music player; a portable music player; a digital video player; a video player; a digital video disk (DVD) player; a portable digital video player; an automobile; a vehicle component; an avionics system; an unmanned aerial vehicle; and a multi-rotor helicopter.

[0103] 12. A processor-based device comprising:

[0104] a unit for receiving a plurality of workloads from a requester;

[0105] Means for constructing a weighted dependency graph based on the plurality of workloads, wherein the weighted dependency graph comprises:

[0106] a plurality of vertices, each vertex corresponding to a workload in the plurality of workloads; and

[0107] one or more directed edges, each directed edge connecting two vertices of the plurality of vertices and indicating a dependency between corresponding two workloads of the plurality of workloads;

[0108] means for performing a topological sort of the weighted dependency graph; and

[0109] Means for generating a workload execution order based on the topological sort.

[0110] 13. A method for reordering workloads to improve cross-thread concurrency, comprising:

[0111] receiving a plurality of workloads from a requestor via a workload execution reordering process executed on a processor-based device;

[0112] A weighted dependency graph is constructed based on the plurality of workloads, wherein the weighted dependency graph comprises:

[0113] a plurality of vertices, each vertex corresponding to a workload in the plurality of workloads; and

[0114] one or more directed edges, each directed edge connecting two vertices of the plurality of vertices and indicating a dependency between corresponding two workloads of the plurality of workloads; performing a topological sort of the weighted dependency graph; and

[0115] A workload execution order is generated based on the topological sort.

[0116] 14. The method according to clause 13 further comprises: scheduling, by the processor-based device, an independent workload among the multiple workloads to be executed during an idle time between two dependent workloads among the multiple workloads based on the workload execution order.

[0117] 15. A method according to any of clauses 13-14, wherein the weighted dependency graph comprises a directed acyclic graph (DAG).

[0118] 16. The method according to any of clauses 13-15, wherein the topological sorting is performed based on Kahn's topological sorting algorithm.

[0119] 17. A method according to any one of clauses 13 to 16, wherein:

[0120] A directed edge of the one or more directed edges represents a cross-thread dependency between the corresponding two workloads;

[0121] Constructing the weighted dependency graph includes associating the directed edges with edge weights, the edge weights being derived from distances between the two vertices corresponding to the corresponding two workloads; and

[0122] The topological sorting is performed based on the edge weights.

[0123] 18. The method of clause 17, wherein the edge weight is negatively correlated with the distance between two vertices corresponding to the two workloads.

[0124] 19. A method according to clause 17, wherein:

[0125] Constructing the weighted dependency graph further includes: for one or more workloads independent of the cross-thread dependencies, generating corresponding one or more vertex weights for one or more vertices corresponding to the one or more workloads; and

[0126] Performing the topological sort is further based on the one or more vertex weights.

[0127] 20. The method of clause 19, wherein each of the one or more vertex weights is based on a logical distance from a vertex corresponding to the vertex weight to a vertex corresponding to a workload causing the cross-thread dependency.

[0128] 21. The method of clause 19, wherein performing the topological sort further comprises:

[0129] assigning a vertex priority to each vertex of the plurality of vertices; and

[0130] The plurality of vertices are processed in an order indicated by the vertex priority of each vertex.

[0131] 22. The method of clause 21, wherein the vertex priority is determined based on the identity of each vertex, the vertex weight of the vertex, and the edge weights of the edges of the vertex.

[0132] 23. A non-transitory computer-readable medium having stored thereon computer-executable instructions which, when executed by a processor of a processor-based device, cause the processor to:

[0133] receiving a plurality of workloads from a requester;

[0134] A weighted dependency graph is constructed based on the plurality of workloads, wherein the weighted dependency graph comprises:

[0135] a plurality of vertices, each vertex corresponding to a workload in the plurality of workloads; and

[0136] one or more directed edges, each directed edge connecting two vertices of the plurality of vertices and indicating a dependency between corresponding two workloads of the plurality of workloads;

[0137] performing a topological sort of the weighted dependency graph; and

[0138] A workload execution order is generated based on the topological sort.

Claims

1. A processor-based device comprising a workload execution reordering circuit, the workload execution reordering circuit being configured to: receiving a plurality of workloads from a requester; A weighted dependency graph is constructed based on the plurality of workloads, wherein: The weighted dependency graph includes: a plurality of vertices, each vertex corresponding to a workload in the plurality of workloads; and one or more directed edges, each directed edge connecting two vertices of the plurality of vertices and indicating a dependency between corresponding two workloads of the plurality of workloads; performing a topological sort of the weighted dependency graph; and A workload execution order is generated based on the topological sort.

2. The processor-based device of claim 1, wherein: The workload execution reordering circuit is further configured to schedule an independent workload of the plurality of workloads to be executed during an idle time between two dependent workloads of the plurality of workloads based on the workload execution order.

3. The processor-based device of claim 1 , wherein: The weighted dependency graph comprises a directed acyclic graph (DAG).

4. The processor-based device of claim 1 , wherein: The workload execution reordering circuit is configured to perform the topological sorting based on Kahn's topological sorting algorithm.

5. The processor-based device of claim 1 , wherein: A directed edge of the one or more directed edges represents a cross-thread dependency between the corresponding two workloads; The workload execution reordering circuit is configured to: construct the weighted dependency graph by being configured to associate the directed edges with edge weights, the edge weights being derived from distances between the two vertices corresponding to the corresponding two workloads; and The workload execution reordering circuit is configured to perform the topological sort based on the edge weights.

6. The processor-based device of claim 5, wherein: The edge weight is negatively correlated with the distance between the two vertices corresponding to the two workloads.

7. The processor-based device of claim 5, wherein: The workload execution reordering circuitry is configured to: construct the weighted dependency graph by further being configured to, for one or more workloads independent of the cross-thread dependencies, generate corresponding one or more vertex weights for one or more vertices corresponding to the one or more workloads; and The workload execution reordering circuitry is configured to perform the topological sorting further based on the one or more vertex weights.

8. The processor-based device of claim 7, wherein: Each vertex weight of the one or more vertex weights is based on a logical distance from a vertex corresponding to the vertex weight to a vertex corresponding to a workload causing the cross-thread dependency.

9. The processor-based device of claim 7, wherein: The workload execution reordering circuit is configured to perform the topological sort by being further configured to: assigning a vertex priority to each vertex of the plurality of vertices; as well as The plurality of vertices are processed in an order indicated by the vertex priority of each vertex.

10. The processor-based device of claim 9, wherein: The vertex priority is determined based on the identity of each vertex, the vertex weight of the vertex, and the edge weight of the edge of the vertex.

11. The processor-based device of claim 1 , integrated into a device selected from the group consisting of: a set-top box; an entertainment unit; a navigation device; a communication device; a fixed location data unit; a mobile location data unit; a global positioning system (GPS) device; a mobile phone; a cellular phone; a smart phone; a session initiation protocol (SIP) phone; a tablet computer; a tablet phone; a server; a computer; a portable computer; a mobile computing device; a wearable computing device; a desktop computer; a personal digital assistant (PDA); a monitor; a computer monitor; a television; a tuner; a radio; a satellite radio; a music player; a digital music player; a portable music player; a digital video player; a video player; a digital video disk (DVD) player; a portable digital video player; an automobile; a vehicle component; an avionics system; an unmanned aerial vehicle; and a multicopter.

12. A processor-based device comprising: a unit for receiving a plurality of workloads from a requester; Means for constructing a weighted dependency graph based on the plurality of workloads, wherein the weighted dependency graph comprises: a plurality of vertices, each vertex corresponding to a workload in the plurality of workloads; and one or more directed edges, each directed edge connecting two vertices of the plurality of vertices and indicating a dependency between corresponding two workloads of the plurality of workloads; means for performing a topological sort of the weighted dependency graph; and Means for generating a workload execution order based on the topological sort.

13. A method for reordering workloads to improve cross-thread concurrency, comprising: receiving a plurality of workloads from a requestor via a workload execution reordering process executed on a processor-based device; A weighted dependency graph is constructed based on the plurality of workloads, wherein the weighted dependency graph comprises: a plurality of vertices, each vertex corresponding to a workload in the plurality of workloads; and one or more directed edges, each directed edge connecting two vertices of the plurality of vertices and indicating a dependency between corresponding two workloads of the plurality of workloads; performing a topological sort of the weighted dependency graph; and A workload execution order is generated based on the topological sort.

14. The method according to claim 13, further comprising: An independent workload among the plurality of workloads is scheduled, by the processor-based device, to be executed during an idle time between two dependent workloads among the plurality of workloads based on the workload execution order.

15. The method according to claim 13, wherein: The weighted dependency graph comprises a directed acyclic graph (DAG).

16. The method according to claim 13, wherein: The topological sorting is performed based on Kahn's topological sorting algorithm.

17. The method of claim 13, wherein: A directed edge of the one or more directed edges represents a cross-thread dependency between the corresponding two workloads; Constructing the weighted dependency graph includes associating the directed edges with edge weights, the edge weights being derived from distances between the two vertices corresponding to the corresponding two workloads; and The topological sorting is performed based on the edge weights.

18. The method according to claim 17, wherein: The edge weight is negatively correlated with the distance between the two vertices corresponding to the two workloads.

19. The method of claim 17, wherein: Constructing the weighted dependency graph further includes: for one or more workloads independent of the cross-thread dependencies, generating corresponding one or more vertex weights for one or more vertices corresponding to the one or more workloads; and Performing the topological sort is further based on the one or more vertex weights.

20. The method according to claim 19, wherein: Each vertex weight of the one or more vertex weights is based on a logical distance from a vertex corresponding to the vertex weight to a vertex corresponding to a workload causing the cross-thread dependency.

21. The method according to claim 19, wherein: Performing the topological sort further includes: assigning a vertex priority to each vertex of the plurality of vertices; and The plurality of vertices are processed in an order indicated by the vertex priority of each vertex.

22. The method according to claim 21, wherein: The vertex priority is determined based on the identity of each vertex, the vertex weight of the vertex, and the edge weight of the edge of the vertex.

23. A non-transitory computer-readable medium having stored thereon computer-executable instructions which, when executed by a processor of a processor-based device, cause the processor to: receiving a plurality of workloads from a requester; A weighted dependency graph is constructed based on the plurality of workloads, wherein: The weighted dependency graph includes: a plurality of vertices, each vertex corresponding to a workload in the plurality of workloads; and one or more directed edges, each directed edge connecting two vertices of the plurality of vertices and indicating a dependency between corresponding two workloads of the plurality of workloads; performing a topological sort of the weighted dependency graph; and A workload execution order is generated based on the topological sort.

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