Fan-out package for semiconductor power module

Abstract

A fan-out package (102) (202) (302-1) (302-2) (402-1) (402-2) (502-1) (502-2) (602) (702) (802-1) (802-2) (902-1) (902-2) (1002-1) (1002-2) may include a plurality of semiconductor dies (104) (204) (304) (404) (504) (604) (704) (804) (904) (904) (1004), each of the semiconductor dies including a first surface and a second surface opposite the first surface. The fan-out package includes a redistribution layer (108) (208) (308) (408) (508) (608) (708) (808) (908) (1008) coupled to a first surface of each of the plurality of semiconductor dies, a die backside conductive member (106) (206) (306) (406) (506) (606) (706) (806) (906) (1006) coupled to a second surface of each of the plurality of semiconductor dies, and a package material (114) (214) (314) (414) (514) (614) (814) (914) (1014) coupled to the plurality of semiconductor dies and the die backside conductive member.

Description

Background Art

[0001] Some conventional fan-out packages may include an encapsulation material applied to the backside of the semiconductor die. Summary of the invention

[0002] In some aspects, the technology described herein relates to a fan-out package comprising: a plurality of semiconductor dies, each of the semiconductor dies comprising a first surface and a second surface opposite the first surface; a redistribution layer coupled to the first surface of each of the plurality of semiconductor dies; a die back side conductive member coupled to the second surface of each of the plurality of semiconductor dies; and a packaging material coupled to the plurality of semiconductor dies and the die back side conductive member.

[0003] In some aspects, the technology described herein relates to a power module comprising: a substrate; a first fan-out package coupled to the substrate; and a second fan-out package coupled to the substrate, each of the first fan-out package and the second fan-out package comprising: a plurality of semiconductor dies, each of the semiconductor dies comprising a first surface and a second surface opposite to the first surface; a redistribution layer coupled to the first surface of each of the plurality of semiconductor dies; a die back conductive member coupled to the second surface of each of the plurality of semiconductor dies; and a packaging material coupled to the plurality of semiconductor dies and the die back conductive member.

[0004] In some aspects, the technology described herein relates to a method for manufacturing a fan-out package, the method comprising: coupling a die back conductive member to a first surface of each semiconductor die in a plurality of semiconductor dies; applying a packaging material to the die back conductive member and the plurality of semiconductor dies; forming a redistribution layer on a second surface of each semiconductor die in the plurality of semiconductor dies; and removing a portion of the packaging material to expose a surface of the die back conductive member.

[0005] The details of one or more implementations are set forth in the accompanying drawings and the description that follows. Other features will be apparent from the description and drawings, and from the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1A A fan-out package according to one aspect is shown.

[0007] Figure 1B A semiconductor power die according to one aspect is shown.

[0008] Figure 2AA fan-out package with conductive spacers according to another aspect is shown.

[0009] Figure 2B A fan-out package assembly having a plurality of fan-out packages is shown according to one aspect.

[0010] Figure 2C A package configuration diagram of a fan-out package assembly according to one aspect is shown.

[0011] Figure 2D A top view of a fan-out package assembly is shown according to one aspect.

[0012] Figure 2E A bottom view of a fan-out package assembly according to one aspect is shown.

[0013] Figure 3 A double-sided cooled power module with multiple fan-out packages according to one aspect is shown.

[0014] Figure 4 A single-sided cooled power module with multiple fan-out packages according to one aspect is shown.

[0015] FIG. 5A to FIG. 5D A manufacturing process for creating various fan-out packages according to one aspect is shown.

[0016] Fig. 6A A fan-out package with a conductive plate according to one aspect is shown.

[0017] Figure 6B A fan-out package assembly having a plurality of fan-out packages is shown according to one aspect.

[0018] Figure 6C A package configuration diagram of a fan-out package assembly according to one aspect is shown.

[0019] Fig.6D A top view of a fan-out package assembly is shown according to one aspect.

[0020] Fig. 6E A bottom view of a fan-out package assembly according to one aspect is shown.

[0021] Fig. 7A A fan-out package having a conductive plate and a conductive layer coupled to the conductive plate is shown according to one aspect.

[0022] Figure 7B A fan-out package assembly having a plurality of fan-out packages is shown according to one aspect.

[0023] Figure 7C A package configuration diagram of a fan-out package assembly according to one aspect is shown.

[0024] Fig.7D A top view of a fan-out package assembly is shown according to one aspect.

[0025] Fig. 7E A bottom view of a fan-out package assembly according to one aspect is shown.

[0026] Figure 8 A double-sided cooled power module with multiple fan-out packages according to one aspect is shown.

[0027] Fig. 9 A single-sided cooled power module with multiple fan-out packages according to one aspect is shown.

[0028] FIG. 10A to FIG. 10C A manufacturing process for creating various fan-out packages according to one aspect is shown.

[0029] Fig.11 A flow chart depicting example operations for fabricating a fan-out package is shown according to one aspect. DETAILED DESCRIPTION

[0030] The present disclosure relates to a fan-out package that enables the back side of a power semiconductor die to be used as an electrode. In some examples, the fan-out package includes a plurality of semiconductor dies, a redistribution layer coupled to each of the plurality of semiconductor dies, and a die back conductive member coupled to each of the plurality of semiconductor dies. The semiconductor die may include a power semiconductor die, such as a silicon insulated gate bipolar transistor or a silicon carbide metal oxide semiconductor field effect transistor. In some examples, the die back conductive member is coupled to the back side (e.g., drain or collector) of the semiconductor die. The die back conductive member enables the back side of the die to be used as an electrode. In some examples, the die back conductive member may form a drain or collector contact (e.g., contact pad) shared by the semiconductor die. In some examples, the die back conductive member includes a conductive spacer. The conductive spacer is a single (single) body of conductive material coupled to each of the semiconductor dies in the semiconductor die. In some examples, the die back conductive member includes a plurality of conductive plates, each of which is coupled to a separate semiconductor die. In some examples, a conductive layer (eg, a copper electroplating layer) is coupled to the plurality of conductive plates.

[0031] In some examples, the present disclosure relates to a power module including one or more fan-out packages. In some examples, the power module includes a first fan-out package and a second fan-out package. In some examples, the power module includes a double-sided cooling (DSC) power module. For example, the power module may include a first substrate (e.g., a direct bonded copper (DBC) substrate), a second substrate (e.g., a DBC substrate), and a first fan-out package and a second fan-out package disposed between the first substrate and the second substrate and coupled to the first substrate and the second substrate. In some examples, the power module includes a lead frame portion disposed between the first substrate and the second substrate and coupled to the first substrate and the second substrate. The redistribution layer of the first fan-out package is coupled to the first substrate, and the redistribution layer of the second fan-out package is coupled to the second substrate (e.g., one of the fan-out packages is flipped relative to the other fan-out package).

[0032] In some examples, the power module includes a single-side cooling (SSC) power module. For example, the power module may include a substrate (e.g., a direct bond copper (DBC) substrate), a clamping member, and a first fan-out package and a second fan-out package disposed between the substrate and the clamping member and coupled to the substrate and the clamping member. In some examples, the power module includes a lead frame portion disposed between the substrate and the clamping member and coupled to the substrate and the clamping member. The back-die conductive member of the first fan-out package can be coupled to the substrate, and the back-die conductive member of the second fan-out package can be coupled to the substrate. The redistribution layer of the first fan-out package can be coupled to the clamping member, and the redistribution layer of the second fan-out package can be coupled to the clamping member.

[0033] The design of the fan-out package can improve thermal and / or electrical performance by increasing the size of the contact pads (e.g., source pads, drain pads), reduce the overall size (and / or cost) of the power module, increase package scalability, and provide better compatibility for DSC and / or SSC power modules. For example, the design of the fan-out package can avoid the use of a lead frame to provide electrical functions to the back of the die, which can increase design flexibility, making it suitable for more power applications. Moreover, the design of the fan-out package uses a redistribution layer on the front side of the semiconductor die (e.g., source terminal, gate terminal), which can make a single common source pad have a relatively large area (thereby improving heat dissipation). In some conventional power modules, the front side of the semiconductor die (e.g., source, gate) is directly attached to the substrate (e.g., without using a redistribution layer), but these types of designs may limit the effective source pad size, thereby limiting the heat dissipation through the source pad. Additionally, the fan-out package design can avoid additional manufacturing processes and / or additional metallization because the die backside conductive features are exposed after overmold grinding (e.g., during the manufacturing process of an individual fan-out package) but before molding is formed on the entire power module.

[0034] Figure 1A to Figure 1B A fan-out package 102 is shown according to one aspect. The fan-out package 102 can be a subcomponent within a larger power module. In some examples, the fan-out package 102 is included in a single-side cooling (SSC) power module or a double-side cooling (DSC) power module. In some examples, the fan-out package 102 enables the back side of the semiconductor die 104 to be used as an electrode. The fan-out package 102 can improve thermal and / or electrical performance by increasing the size of the contact pads (e.g., source pad 132, drain pad 130). In some examples, the fan-out package 102 can increase its scalability and / or provide better compatibility for incorporation into a power module. In some examples, the structure of the fan-out package 102 can reduce the overall size (and / or cost) of the power module including the fan-out package.

[0035] Fan-out package 102 includes multiple semiconductor dies 104. Semiconductor dies 104 are power semiconductor dies. Semiconductor dies 104 include transistors. In some examples, semiconductor dies 104 include metal oxide semiconductor field effect transistors (MOSFETs). In some examples, semiconductor dies 104 include insulated gate bipolar transistors (IGBTs). In some examples, semiconductor dies 104 include thyristors. In some examples, semiconductor dies 104 are multiple instances of the same type of transistor. Semiconductor dies 104 may include semiconductor die 104-1, semiconductor die 104-2, and semiconductor die 104-3. Although in Figure 1A Three semiconductor dies 104 are depicted in FIG. 1 , but the number of semiconductor dies 104 may be two or any number greater than three, such as four, five, six, seven, eight, etc. In some examples, fan-out package 102 includes three or more semiconductor dies 104 .

[0036] like Figure 1B As shown, each semiconductor die 104 includes a first surface 111 (e.g., a top surface) and a second surface 113 (e.g., a bottom surface) opposite to the first surface 111. The second surface 113 may be disposed parallel to the first surface 111. The distance between the first surface 111 and the second surface 113 may define the thickness of the semiconductor die 104 in the direction A1. In some examples, the first surfaces 111 of each semiconductor die 104 are aligned with each other in the direction A1. The first surfaces 111 are aligned in a plane A4. The direction A1 is aligned perpendicular to the plane A4, and the direction A2 is perpendicular to the direction A1. The direction A3 (in the direction A1) entering the page Figure 1A and Figure 1B104. The semiconductor die 104 is shown as a dot in FIG. 104 and is aligned parallel to the plane A4 and is orthogonal to the directions A1 and A2. For simplicity, the directions A1, A2, and A3 and the plane A4 are used in several of the various views of the embodiments described throughout the figures. Each semiconductor die 104 includes a source terminal 101, a gate terminal 103, and a drain terminal 105. In some examples, the drain terminal 105 is referred to as a collector terminal. In some examples, the drain terminal 105 is referred to as an emitter terminal. The source terminal 101, the gate terminal 103, and the drain terminal 105 can be metallization regions in the semiconductor die 104.

[0037] The fan-out package 102 includes a redistribution layer 108 coupled to the semiconductor die 104. The redistribution layer 108 includes a metal layer (e.g., patterned metallization) that redistributes current. The redistribution layer 108 is coupled to the first surface 111 of each semiconductor die 104. In some examples, the redistribution layer 108 is connected to the source terminal 101 of each semiconductor die 104. The redistribution layer 108 includes a portion 131 that contacts the source terminal 101 of the semiconductor die 104-1 and extends in the direction A1. The redistribution layer 108 includes a portion 133 that contacts the source terminal 101 of the semiconductor die 104-2 and extends in the direction A1. The redistribution layer 108 includes a portion 135 that contacts the source terminal 101 of the semiconductor die 104-3 and extends in the direction A1. The redistribution layer 108 includes a portion 137 that extends between the portion 131 and the portion 133 along the direction A2. Redistribution layer 108 includes portion 139 extending between portion 133 and portion 135. Redistribution layer 108 includes source pad 132 on an outer surface of redistribution layer 108. In some examples, source pad 132 is a contact pad common to semiconductor die 104. Source pad 132 is configured to connect to an external component (e.g., outside fan-out package 102).

[0038] The fan-out package 102 includes a die back conductive member 106 coupled to the semiconductor die 104. For example, the die back conductive member 106 is coupled to the second surface 113 of the semiconductor die 104. In some examples, the die back conductive member 106 is connected to the drain terminal 105 of each semiconductor die 104. In some examples, the die back conductive member 106 is coupled to the back side (e.g., the drain terminal 105) of the semiconductor die 104. The die back conductive member 106 can enable the back side of the die to be used as an electrode. The die back conductive member 106 includes a drain pad 130. In other words, the outer surface of the die back conductive member 106 can define the drain pad 130. In some examples, the drain pad 130 is a contact pad shared by the semiconductor die 104. The drain pad 130 is configured to be connected to an external component (e.g., outside the fan-out package 102).

[0039] In some examples, die back side conductive member 106 comprises a conductive spacer. The conductive spacer is a single (single) body of conductive material coupled to each semiconductor die in semiconductor die 104. In some examples, the conductive spacer is a single piece of metal that has been cut to a desired size. In some examples, the conductive spacer comprises a single conductive body having a rectangular shape. The conductive material comprises a metallic material such as copper or aluminum.

[0040] In some examples, die back side conductive member 106 includes a plurality of conductive plates, where each conductive plate is coupled to a separate semiconductor die 104. In some examples, the conductive plates include copper plates. Each conductive plate is coupled to second surface 113 and can extend in direction A1. In some examples, the conductive plates are formed by coupling a conductive layer on second surface 113 of each semiconductor die 104 and removing portions 140 of conductive material between adjacent semiconductor die 104. In some examples, the conductive layer (e.g., 7A to 7C The conductive layer 780 in is coupled to the conductive plate.

[0041] The fan-out package 102 includes an encapsulation material 114 coupled to the semiconductor die 104 and the die back conductive member 106. For example, the encapsulation material 114 can contact the edge 107 of each semiconductor die 104 and the edge 109 of each semiconductor die 104. In some examples, the encapsulation material 114 extends along a length (e.g., the entire length) of the edge 107. In some examples, the encapsulation material 114 extends along a length (e.g., the entire length) of the edge 109. The edge 107 and the edge 109 can be opposite edges in the direction A2. The edge 107 and the edge 109 can extend between the first surface 111 and the second surface 113 along the direction A1.

[0042] The encapsulation material 114 may contact an edge 117 of the die back conductive member 106 and an edge 119 of the die back conductive member 106. In some examples, the encapsulation material 114 extends along a length (e.g., the entire length) of the edge 117 in the direction A1. In some examples, the encapsulation material 114 extends along a length (e.g., the entire length) of the edge 119 in the direction A1. The edge 117 and the edge 119 may be opposite edges in the direction A2. The edge 117 and the edge 119 may extend between a first surface 121 of the die back conductive member 106 and a second surface 123 of the die back conductive member 106 in the direction A1. The distance between the first surface 121 and the second surface 123 defines the thickness of the die back conductive member 106 in the direction A1. In some examples, when the die back conductive member 106 is a conductive plate, the encapsulation material 114 is disposed in a space between adjacent conductive plates (e.g., the location of the portion 140).

[0043] FIG. 2A to FIG. 2E A fan-out package 202 is shown according to one aspect. Figure 2A A side view of a single fan-out package 202 is shown according to one aspect. FIG. 2B to FIG. 2E Various views of a fan-out package assembly 285 having a plurality of fan-out packages 202 are shown. Figure 2B 2 shows a side view of a fan-out package assembly 285 having two fan-out packages 202 (eg, before the fan-out packages 202 are separated during the manufacturing process). Figure 2B As shown, the fan-out package assembly 285 includes a first fan-out package 202-1 and a second fan-out package 202-2. The second fan-out package 202-2 is the same as the first fan-out package 202-1. Figure 2C A package configuration diagram of a fan-out package assembly 285 is shown. Figure 2D A top view of the fan-out package assembly 285 is shown, depicting the source pad 232 and the gate pad 236 . Figure 2E A bottom view of the fan-out package assembly 285 is shown, depicting the drain pad 230 .

[0044] The fan-out package 202 may be Figure 1A and Figure 1B 1 and may include any details discussed with reference to these figures. Fan-out package 202 may be a subcomponent within a larger power module. In some examples, fan-out package 202 is included in a single-side cooling (SSC) power module or a double-side cooling (DSC) power module. In some examples, fan-out package 202 enables the back side of semiconductor die 104 to be used as an electrode.

[0045] Fan-out package 202 includes multiple semiconductor dies 204. Semiconductor die 204 is a power semiconductor die. Semiconductor die 204 includes transistors. In some examples, semiconductor die 204 includes a metal oxide semiconductor field effect transistor (MOSFET). In some examples, semiconductor die 204 includes an insulated gate bipolar transistor (IGBT). In some examples, semiconductor die 204 includes a semiconductor thyristor. In some examples, semiconductor die 204 is multiple instances of the same type of transistor. Semiconductor die 204 may include semiconductor die 204-1, semiconductor die 204-2, and semiconductor die 204-3. Although in FIG. 2A to FIG. 2E Three semiconductor dies 104 are depicted in FIG. 2 , but the number of semiconductor dies 204 may be two or any number greater than three, such as four, five, six, seven, eight, etc. In some examples, power module 202 includes three or more semiconductor dies 204 .

[0046] Each semiconductor die 204 includes a first surface 211 (e.g., a top surface) and a second surface 213 (e.g., a bottom surface) opposite to the first surface 211. The second surface 213 may be disposed parallel to the first surface 211. The distance between the first surface 211 and the second surface 213 may define the thickness of the semiconductor die 204 in the direction A1. In some examples, the first surfaces 211 of each semiconductor die 204 are aligned with each other in the direction A1. The first surfaces 211 are aligned in a plane A4. The direction A1 is aligned perpendicular to the plane A4, and the direction A2 is perpendicular to the direction A1. The direction A3 entering the page is aligned parallel to the plane A4 and is orthogonal to the directions A1 and A2. Each semiconductor die 204 includes a first edge 207 and a second edge 209. The distance between the first edge 207 and the second edge 209 defines the length of the semiconductor die 204 in the direction A2. The edge 207 and the edge 209 may extend between the first surface 211 and the second surface 213 along the direction A1.

[0047] The fan-out package 202 includes a redistribution layer 208 coupled to the semiconductor die 204. The redistribution layer 108 includes a metal layer (e.g., patterned metallization) that redistributes current. The redistribution layer 208 is coupled to a first surface 211 of each semiconductor die 204. In some examples, the redistribution layer 208 is connected to a source terminal of each semiconductor die 204. The redistribution layer 208 includes a source pad 232 on an outer surface of the redistribution layer 208. In some examples, the source pad 232 is a contact pad shared by the semiconductor die 204. The source pad 232 is configured to connect to an external component (e.g., outside the fan-out package 102).

[0048] The fan-out package 202 includes a passivation layer 210 coupled to a first surface 211 of the semiconductor die 204. The passivation layer 210 may include materials silicon dioxide (SiO2), silicon nitride (Si3N4), and / or titanium dioxide (TiO2). In some examples, the passivation layer 210 is aligned in the same plane as the redistribution layer 208 (in direction A1). In some examples, the passivation layer 210 is disposed on the semiconductor die 104, and the redistribution layer 208 is disposed on the passivation layer 210. In some examples, the passivation layer 210 includes multiple layers, such as a passivation layer 210-1 and a passivation layer 210-2. In some examples, the passivation layer 210-1 contacts the semiconductor die 204 and the passivation layer 210-2 contacts the passivation layer 210-1.

[0049] The fan-out package 202 includes a conductive spacer 206 coupled to the semiconductor die 204. In some examples, the conductive spacer 206 is coupled to the semiconductor die 204 via the sintering material 212. The conductive spacer 206 is coupled to the second surface 213 of the semiconductor die 204. In some examples, the conductive spacer 206 is connected to the drain terminal (e.g., Figure 1B 204 ). In some examples, the conductive spacer 206 is coupled to the back side (e.g., drain terminal) of the semiconductor die 204. The conductive spacer 206 can enable the back side of the die to act as an electrode. The conductive spacer 206 includes a drain pad 230. The drain pad 230 can be a portion of the second surface 223 of the conductive spacer 206. In some examples, the drain pad 230 is a portion of the conductive spacer 206 exposed by the packaging material 214. In some examples, the drain pad 230 is a contact pad shared by the semiconductor die 204. The drain pad 230 is configured to be connected to an external component (e.g., outside the fan-out package 202).

[0050] Conductive spacer 206 can be a single (unitary) body of conductive material coupled to each of semiconductor dies 204. In some examples, conductive spacer 206 is a single piece of metal that has been cut to a desired size. In some examples, conductive spacer 206 includes a single conductive body having a rectangular shape. The conductive material includes a metallic material such as copper or aluminum.

[0051] Conductive spacer 206 includes a first surface 221 and a second surface 223 opposite to first surface 221. The distance between first surface 221 and second surface 223 defines the thickness of conductive spacer 206 in direction A1. In some examples, the thickness of conductive spacer 206 is greater than the thickness of semiconductor die 204 in direction A1. In some examples, the thickness of conductive spacer 206 is greater than the thickness of redistribution layer 208 in direction A1. Conductive spacer 206 includes a first edge 217 and a second edge 219. The distance between first edge 217 and second edge 219 defines the length of conductive spacer 206 in direction A2. Edge 217 and edge 219 may be opposite edges in direction A2. Edge 217 and edge 219 may extend between first surface 211 and second surface 213 along direction A1.

[0052] Fan-out package 202 includes encapsulation material 214 coupled to semiconductor die 204 and conductive spacers 206. For example, encapsulation material 214 can contact edge 207 of each semiconductor die 204 and edge 209 of each semiconductor die 204. In some examples, encapsulation material 214 extends along a length (e.g., the entire length) of edge 207. In some examples, encapsulation material 214 extends along a length (e.g., the entire length) of edge 209. Encapsulation material 214 can contact first edge 217 of conductive spacer 206 and second edge 219 of conductive spacer 206. In some examples, encapsulation material 214 extends along a length (e.g., the entire length) of edge 217. In some examples, encapsulation material 214 extends along a length (e.g., the entire length) of edge 219.

[0053] Figure 3 An example of a power module 300 is shown. In some examples, the power module 300 includes a double-side cooling (DSC) power module. The power module 300 includes a plurality of fan-out packages, such as fan-out package 302-1 and fan-out package 302-1. The fan-out package 302-1 and the fan-out package 302-2 may be Figure 1A and Figure 1B The fan-out package 102 and / or FIG. 2A to FIG. 2E An example of a fan-out package 202 of the present invention and may include any details discussed with reference to these figures. The power module 300 may include a substrate 320-1 (e.g., a direct bond copper (DBC) substrate), a substrate 320-2 (e.g., a DBC substrate), and fan-out packages 302-1, 302-2 disposed between and coupled to the substrate 320-1 and the substrate 320-2. In some examples, the power module 300 includes a lead frame portion 338-1 and a lead frame portion 338-2, which are disposed between and coupled to the substrate 320-1 and the substrate 320-2. The redistribution layer 308 of the fan-out package 302-1 is coupled to the substrate 320-1, and the redistribution layer 308 of the fan-out package 302-2 is coupled to the substrate 320-2 (e.g., one of the fan-out packages is flipped relative to the other fan-out package).

[0054] Substrate 320-1 includes a dielectric layer 324. Dielectric layer 324 includes an insulating material. In some examples, dielectric layer 324 includes a ceramic material. In some examples, substrate 320-1 includes a single dielectric layer 324. In some examples, substrate 320-1 includes multiple dielectric layers 324. In some examples, substrate 320-1 includes a printed circuit board (PCB) substrate (e.g., a single-layer PCB or a multi-layer PCB). In some examples, substrate 320-1 includes a conductive layer 322 coupled to one surface of dielectric layer 324 and a conductive layer 326 coupled to another surface of dielectric layer 324. In some examples, conductive layer 322 includes a copper layer. In some examples, conductive layer 326 includes a copper layer. In some examples, substrate 320-1 is a direct bonded metal (DBM) substrate (e.g., a substrate having a dielectric disposed between two metal layers), such as a direct bonded copper (DBC) substrate. Substrate 320-2 may be the same / similar to substrate 320-1. For example, substrate 320 - 2 further includes dielectric layer 324 , conductive layer 322 , and conductive layer 326 .

[0055] Conductive layer 322 of substrate 320-1 includes inner surface 333 aligned in plane A4. Conductive layer 322 of substrate 320-2 includes inner surface 335 aligned in plane A5. Plane A5 is arranged parallel to plane A4. Direction A1 is aligned perpendicular to plane A4, and direction A2 is perpendicular to direction A1. Direction A3 (into the page) Figure 1A and Figure 1B ) is aligned parallel to plane A4 and orthogonal to directions A1 and A2.

[0056] Fan-out package 302-1 and fan-out package 302-2 are coupled to substrate 320-1 and substrate 320-2 and disposed therebetween. Fan-out package 302-1 includes semiconductor die 304, a redistribution layer 308 coupled to a front side (e.g., source, gate) of semiconductor die 304, and a conductive spacer 306 coupled to a back side (e.g., drain) of semiconductor die 304. Furthermore, fan-out package 302-1 includes a passivation layer 310 applied to a back side of semiconductor die 304 and an encapsulation material 314 contacting semiconductor die 304 and conductive spacer 306.

[0057] The fan-out package 302-2 includes a semiconductor die 304, a redistribution layer 308 coupled to a front side (e.g., source, gate) of the semiconductor die 304, and a conductive spacer 306 coupled to a back side (e.g., drain) of the semiconductor die 304. Furthermore, the fan-out package 302-2 includes a passivation layer 310 applied to the back side of the semiconductor die 304 and an encapsulation material 314 contacting the semiconductor die 304 and the conductive spacer 306.

[0058] The fan-out package 302-1 may be coupled to the substrate 320-1 via the attachment layer 328, and the fan-out package 302-1 may be coupled to the substrate 320-2 via the attachment layer 328. The attachment layer 328 may include a bonding material (e.g., solder, sinter, or other adhesive) that can bond conductive components together. The conductive spacer 306 of the fan-out package 302-1 is coupled to the conductive layer 322 of the substrate 320-1 via the attachment layer 328. The redistribution layer 308 of the fan-out package 302-1 is coupled to the conductive layer 322 of the substrate 320-2 via the attachment layer 328.

[0059] The fan-out package 302-2 may be coupled to the substrate 320-1 via the attachment layer 328, and the fan-out package 302-2 may be coupled to the substrate 320-2 via the attachment layer 328. The conductive spacer 306 of the fan-out package 302-2 is coupled to the conductive layer 322 of the substrate 320-2 via the attachment layer 328. The redistribution layer 308 of the fan-out package 302-2 is coupled to the conductive layer 322 of the substrate 320-1 via the attachment layer 328.

[0060] Lead frame portion 338-1 may be disposed between substrate 320-1 and substrate 320-2 and coupled to substrate 320-1 and substrate 320-2. For example, lead frame portion 338-1 is coupled to conductive layer 322 of substrate 320-1 and conductive layer 322 of substrate 320-2. Lead frame portion 338-2 may be disposed between substrate 320-1 and substrate 320-2 and coupled to substrate 320-1 and substrate 320-2. For example, lead frame portion 338-2 is coupled to conductive layer 322 of substrate 320-1 and conductive layer 322 of substrate 320-2. Fan-out package 302-1 and fan-out package 302-2 are disposed between lead frame portion 338-1 and lead frame portion 338-2 along direction A2.

[0061] Power module 300 includes encapsulation material 346. Encapsulation material 346 may contact an edge of substrate 320-1 and an edge of substrate 320-2. Encapsulation material 346 may contact portions of lead frame portion 338-1 and portions of lead frame portion 338-2. In addition, encapsulation material 346 may contact fan-out package 302-1 and fan-out package 302-2.

[0062] Figure 4 An example of a power module 400 is shown. In some examples, the power module 400 includes a single-side cooling (DSC) power module. The power module 400 includes a plurality of fan-out packages, such as fan-out package 402-1 and fan-out package 402-1. The fan-out package 402-1 and the fan-out package 402-2 may be Figure 1A and Figure 1BThe fan-out package 102 and / or FIG. 2A to FIG. 2E 2 and may include any of the details discussed with reference to those figures.

[0063] The power module 400 may include a substrate 420 (e.g., a direct bond copper (DBC) substrate), a clamping member 442, and fan-out packages 402-1, 402-2 disposed between and coupled to the substrate 420 and the clamping member 442. In some examples, the power module 400 includes a lead frame portion 438-1 and a lead frame portion 438-2 disposed between and coupled to the substrate 420 and the clamping member 442. The conductive spacer 406 of the fan-out package 402-1 is coupled to the substrate 420, and the conductive spacer 406 of the fan-out package 402-2 is coupled to the substrate 420 (e.g., the fan-out packages 402-1, 402-2 have the same orientation).

[0064] Substrate 420 includes a dielectric layer 424. Dielectric layer 424 includes an insulating material. In some examples, dielectric layer 424 includes a ceramic material. In some examples, substrate 420 includes a single dielectric layer 424. In some examples, substrate 420 includes multiple dielectric layers 424. In some examples, substrate 420 includes a printed circuit board (PCB) substrate (e.g., a single-layer PCB or a multi-layer PCB). In some examples, substrate 420 includes a conductive layer 422 coupled to one surface of dielectric layer 424 and a conductive layer 426 coupled to another surface of dielectric layer 424. In some examples, conductive layer 422 includes a copper layer. In some examples, conductive layer 426 includes a copper layer. In some examples, substrate 420 is a direct bonded metal (DBM) substrate (e.g., a substrate having a dielectric disposed between two metal layers), such as a direct bonded copper (DBC) substrate. Conductive layer 422 of substrate 420 includes an inner surface 433 aligned in plane A4. Direction A1 is aligned perpendicular to plane A4, and direction A2 is perpendicular to direction A1. Direction A3 entering the page (at Figure 1A and Figure 1B ) is aligned parallel to plane A4 and orthogonal to directions A1 and A2.

[0065] Clamping member 442 includes a conductive material. In some examples, clamping member 442 may include portions extending in direction A1 and direction A2. In some examples, clamping member 442 includes portions disposed parallel to each other at multiple planes in direction A2. In some examples, clamping member 442 includes portions disposed at an angle (e.g., a non-zero, non-perpendicular angle) relative to each other. Fan-out package 402-1 and fan-out package 402-2 are coupled to substrate 420 and clamping member 442 and disposed therebetween.

[0066] The fan-out package 402-1 includes a semiconductor die 404, a redistribution layer 408 coupled to a front side (e.g., source, gate) of the semiconductor die 404, and a conductive spacer 406 coupled to a back side (e.g., drain) of the semiconductor die 404. Furthermore, the fan-out package 402-1 includes a passivation layer 410 applied to the back side of the semiconductor die 404 and an encapsulation material 414 contacting the semiconductor die 404 and the conductive spacer 406.

[0067] The fan-out package 402-2 includes a semiconductor die 404, a redistribution layer 408 coupled to a front side (e.g., source, gate) of the semiconductor die 404, and a conductive spacer 406 coupled to a back side (e.g., drain) of the semiconductor die 404. Furthermore, the fan-out package 402-2 includes a passivation layer 410 applied to the back side of the semiconductor die 404 and an encapsulation material 414 contacting the semiconductor die 404 and the conductive spacer 406.

[0068] The fan-out package 402-1 may be coupled to the substrate 420 via the attachment layer 428, and the fan-out package 402-2 may contact (e.g., directly contact) the clamping member 442. The attachment layer 428 may include a bonding material (e.g., solder, sinter, or other adhesive) that can bond conductive components together. The conductive spacer 406 of the fan-out package 402-1 is coupled to the conductive layer 422 of the substrate 420 via the attachment layer 428. The redistribution layer 408 of the fan-out package 402-1 contacts the clamping member 442. The fan-out package 402-2 may be coupled to the substrate 420 via the attachment layer 428, and the fan-out package 402-2 may contact the clamping member 442. The conductive spacer 406 of the fan-out package 402-2 is coupled to the conductive layer 422 of the substrate 420 via the attachment layer 428. The redistribution layer 408 of the fan-out package 402 - 2 contacts the clamping member 442 .

[0069] The lead frame portion 438-1 can be disposed between the substrate 420 and the clamping member 442 and coupled to the substrate 420 and the clamping member 442. For example, the lead frame portion 438-1 is coupled to the conductive layer 422 of the substrate 420 and the clamping member 442. The lead frame portion 438-2 can be disposed between the substrate 420 and the clamping member 442 and coupled to the substrate 420 and the clamping member 442. For example, the lead frame portion 438-2 is coupled to the conductive layer 422 of the substrate 420 and the clamping member 442. The fan-out package 402-1 and the fan-out package 402-2 are disposed between the lead frame portion 438-1 and the lead frame portion 438-2 along the direction A2. The power module 400 includes an encapsulation material 448. The encapsulation material 448 can contact portions of the substrate 420 and the clamping member 442. Encapsulation material 448 may contact portions of leadframe portion 438-1 and portions of leadframe portion 438-2. Additionally, encapsulation material 448 may contact fan-out package 402-1 and fan-out package 402-2.

[0070] FIG. 5A to FIG. 5D A manufacturing process 500 for creating various fan-out packages (eg, fan-out package 502-1, fan-out package 502-2) is shown. Fan-out package 502-1 and fan-out package 502-2 may be Figure 1A and Figure 1B Fan-out package 102, FIG. 2A to FIG. 2E Fan-out package 202, Figure 3 Fan-out packages and / or Figure 4 Examples of fan-out packages and may include any of the details discussed with reference to these figures.

[0071] Operation 550 includes providing a carrier assembly 548 including a carrier 553 and a film 551 coupled to a surface of the carrier 553. Operation 552 includes a pick and place operation (e.g., die reconstitution) of attaching the die assembly 501-1 and the die assembly 501-2 to the carrier assembly 548. The die assembly 501-1 includes a plurality of semiconductor dies 504, a conductive pad 555 coupled to each semiconductor die 504, and a conductive spacer 506 coupled to the semiconductor die 504 via a sintering material 512. The die assembly 501-2 includes a plurality of semiconductor dies 504, a conductive pad 555 coupled to each semiconductor die 504, and a conductive spacer 506 coupled to the semiconductor die 504 via a sintering material 512. The conductive pad 555 is coupled to the film 551.

[0072] Operation 554 includes applying encapsulation material 514 to die assembly 501-1, die assembly 501-2, and carrier assembly 548. Operation 556 includes removing carrier assembly 548 from encapsulation material 514, die assembly 501-1, and die assembly 501-2. Operation 558 includes applying passivation layer 510-1 to conductive pad 555 and encapsulation material 514. Operation 560 includes removing portions of passivation layer 510-1 to create gap 511. Operation 562 includes applying a sputtering operation to apply sputtered metallization 513 to passivation layer 510-1. Operation 564 includes applying photoresist material 515 to sputtered metallization 513 on passivation layer 510-1. Operation 566 includes removing portions of photoresist material 515.

[0073] Operation 568 includes applying metal plating to form a redistribution layer 508 on the conductive pads 555 and the passivation layer 510-1. Operation 570 includes removing the photoresist material 515. Operation 572 includes a wet etching operation to remove a portion of the sputtered metallization 513 on the passivation layer 510-1. Operation 574 includes applying a passivation layer 510-2 to the passivation layer 510-1. Operation 576 includes removing a portion of the passivation layer 510-2 on top of the redistribution layer 508. Operation 578 includes removing a portion of the encapsulation material 514 to expose the top surface of the conductive spacer 506, thereby creating a source contact pad 530. Operation 580 includes a singulation process to separate the fan-out packages (e.g., fan-out package 502-1 and fan-out package 502-2).

[0074] FIG. 6A to FIG. 6E A fan-out package 602 is shown according to one aspect. Fig. 6A A side view of a single fan-out package 602 is shown according to one aspect. FIG. 6B to FIG. 6E Various views of a fan-out package assembly 685 having a plurality of fan-out packages 602 are shown. Figure 6B 6 shows a side view of a fan-out package assembly 685 having two fan-out packages 602 (eg, before the fan-out packages 602 are separated during the manufacturing process). Figure 6B As shown, the fan-out package assembly 685 includes a first fan-out package 602-1 and a second fan-out package 602-2. The second fan-out package 602-2 is the same as the first fan-out package 602-1. Figure 6C A package configuration diagram of a fan-out package assembly 685 is shown. Fig.6D A top view of the fan-out package assembly 685 is shown, depicting the source pad 632 and the gate pad 636 . Fig. 6E A bottom view of the fan-out package assembly 685 is shown, depicting the drain pad 630 .

[0075] The fan-out package 602 may be Figure 1A and Figure 1B 100 and may include any details discussed with reference to these figures. The fan-out package 602 may be a subcomponent within a larger power module. In some examples, the fan-out package 602 is included in a single-side cooling (SSC) power module or a double-side cooling (DSC) power module. In some examples, the fan-out package 602 enables the back side of the semiconductor die 604 to be used as an electrode.

[0076] refer to Fig. 6A , fan-out package 602 includes a plurality of semiconductor dies 604. Semiconductor die 604 is a power semiconductor die. Semiconductor die 604 may include semiconductor die 604-1, semiconductor die 604-2, and semiconductor die 604-3. FIG. 6A to FIG. 6E Three semiconductor dies 604 are depicted in FIG. 6 , but the number of semiconductor dies 604 may be two or any number greater than three, such as four, five, six, seven, eight, etc. In some examples, power module 602 includes three or more semiconductor dies 604 .

[0077] Each semiconductor die 604 includes a first surface 611 (e.g., a top surface) and a second surface 613 (e.g., a bottom surface). The second surface 613 may be disposed parallel to the first surface 611. The distance between the first surface 611 and the second surface 613 may define the thickness of the semiconductor die 604 in the direction A1. In some examples, the first surfaces 611 of each semiconductor die 604 are aligned with each other in the direction A1. The first surfaces 611 are aligned in a plane A4. The direction A1 is aligned perpendicular to the plane A4, and the direction A2 is perpendicular to the direction A1. The direction A3 entering the page is aligned parallel to the plane A4 and is orthogonal to the directions A1 and A2. Each semiconductor die 204 includes a first edge 607 and a second edge 609. The distance between the first edge 607 and the second edge 609 defines the length of the semiconductor die 604 in the direction A2. The edge 607 and the edge 609 may extend between the first surface 611 and the second surface 613 along the direction A1.

[0078] The fan-out package 602 includes a redistribution layer 608 coupled to the semiconductor die 604. The redistribution layer 608 includes a metal layer (e.g., patterned metallization) that redistributes current. The redistribution layer 608 is coupled to a first surface 611 of each semiconductor die 604. In some examples, the redistribution layer 608 is connected to a source terminal of each semiconductor die 604. The redistribution layer 608 includes a source pad 632 on an outer surface of the redistribution layer 608. In some examples, the source pad 632 is a contact pad shared by the semiconductor die 604. The source pad 632 is configured to connect to an external component (e.g., outside the fan-out package 602).

[0079] The fan-out package 602 includes a passivation layer 610 coupled to a first surface 611 of a semiconductor die 604. The passivation layer 610 may include materials silicon dioxide (SiO2), silicon nitride (Si3N4), and / or titanium dioxide (TiO2). In some examples, the passivation layer 610 is aligned in the same plane as the redistribution layer 608 (in direction A1). In some examples, the passivation layer 610 is disposed on the semiconductor die 604, and the redistribution layer 608 is disposed on the passivation layer 610. In some examples, the passivation layer 610 includes multiple layers, such as a passivation layer 610-1 and a passivation layer 610-2. In some examples, the passivation layer 610-1 contacts the semiconductor die 604 and the passivation layer 610-2 contacts the passivation layer 610-1.

[0080] The fan-out package 602 includes a plurality of conductive plates 606. The conductive plates 606 include a conductive plate 606-1 coupled to a surface 613 of the semiconductor die 604-1, a conductive plate 606-2 coupled to a surface 613 of the semiconductor die 604-2, and a conductive plate 606-3 coupled to a surface 613 of the semiconductor die 604-3. In some examples, the conductive plates 606 are connected to the drain terminals (e.g., Figure 1B 604). In some examples, the conductive plate 606 is coupled to the back side (e.g., drain terminal) of the semiconductor die 604. The conductive plate 606 enables the back side of the die to act as an electrode. Each conductive plate 606 may include a drain pad 630. In some examples, the drain pad 630 is a surface 623 of the conductive plate 606. In some examples, the drain pad 630 is a portion of the conductive plate 606 exposed by the packaging material 614. In some examples, the drain pad 630 is a contact pad associated with the semiconductor die 604 (e.g., not shared between the dies). The drain pad 630 is configured to connect to an external component (e.g., outside the fan-out package 602).

[0081] Each conductive plate 606 includes a first surface 621 and a second surface 623. The distance between the first surface 621 and the second surface 623 may define the thickness of the conductive plate 606 in the direction A1. In some examples, the length of the conductive plate 606 is greater than the length of the semiconductor die 604 in the direction A1. In some examples, the thickness of the conductive plate 606 is greater than the thickness of the redistribution layer 608 in the direction A1. Each conductive plate 606 includes a first edge 617 and a second edge 619. The distance between the first edge 617 and the second edge 619 defines the length of the conductive plate in the direction A2. The edge 617 and the edge 619 may be opposite edges in the direction A2. The edge 617 and the edge 619 may extend between the first surface 611 and the second surface 613 along the direction A1.

[0082] The fan-out package 602 includes an encapsulation material 614 coupled to the semiconductor die 604 and the conductive plate 606. For example, the encapsulation material 614 can contact an edge 607 of each semiconductor die 604 and an edge 609 of each semiconductor die 604. In some examples, the encapsulation material 614 extends along a length (e.g., the entire length) of the edge 607. In some examples, the encapsulation material 614 extends along a length (e.g., the entire length) of the edge 609. The encapsulation material 214 can contact a first edge 617 of the conductive plate 606 and a second edge 619 of the conductive plate 606. In some examples, the encapsulation material 614 extends along a length (e.g., the entire length) of the edge 617. In some examples, the encapsulation material 614 extends along a length (e.g., the entire length) of the edge 619. In some examples, the encapsulation material 614 includes a portion 614-1 extending from the edge 607 of the semiconductor die 604-1 to the edge of the fan-out package 602 along the direction A2.

[0083] In some examples, encapsulation material 614 includes a portion 614-2 disposed between conductive plate 606-1 and conductive plate 606-2 (and between semiconductor die 604-1 and semiconductor die 604-2) along direction A2. In some examples, encapsulation material 614 includes a portion 614-3 disposed between conductive plate 606-2 and conductive plate 606-3 (and between semiconductor die 604-2 and semiconductor die 604-3) along direction A2. In some examples, encapsulation material 614 includes a portion 614-4 extending from edge 609 of semiconductor die 604-3 to an edge of fan-out package 602 along direction A2.

[0084] 7A to 7E A fan-out package 702 is shown according to one aspect. Fig. 7A A side view of a single fan-out package 702 is shown according to one aspect. FIG. 7B to FIG. 7E Various views of a fan-out package assembly 785 having a plurality of fan-out packages 702 are shown. Figure 7B 7 shows a side view of a fan-out package assembly 785 having two fan-out packages 702 (eg, before the fan-out packages 702 are separated during the manufacturing process). Figure 7B As shown, the fan-out package assembly 785 includes a first fan-out package 702-1 and a second fan-out package 702-2. The second fan-out package 702-2 is the same as the first fan-out package 702-1. Figure 7C A package configuration diagram of a fan-out package assembly 685 is shown. Fig.7D A top view of the fan-out package assembly 785 is shown, depicting the source pad 732 and the gate pad 736 . Fig. 7EA bottom view of a fan-out package assembly 785 is shown, depicting a single relatively large drain pad 730 provided by the exposed conductive layer 780 .

[0085] The fan-out package 702 may be Figure 1A and Figure 1B The fan-out package 102 and FIG. 6A to FIG. 6E 602 and may include any details discussed with reference to these figures. The fan-out package 702 may be a subcomponent within a larger power module. In some examples, the fan-out package 702 is included in a single-side cooling (SSC) power module or a double-side cooling (DSC) power module. In some examples, the fan-out package 702 enables the back side of the semiconductor die 704 to be used as an electrode.

[0086] The fan-out package 702 may be the same as the fan-out package 602, except that the fan-out package 702 includes a conductive layer 780 coupled to the conductive plate 706. For example, the fan-out package 702 includes a plurality of semiconductor dies 705, a plurality of conductive plates 706 coupled to the back side of the semiconductor die 704, and a redistribution layer 708 coupled to the front side of the semiconductor die 704. The fan-out package 702 also includes a passivation layer 710 coupled to the front side of the semiconductor die 704. The conductive layer 780 may be used as a drain contact pad shared by the plurality of semiconductor dies 704.

[0087] Figure 8 An example of a power module 800 is shown. In some examples, the power module 800 includes a double-side cooling (DSC) power module. The power module 800 includes a plurality of fan-out packages, such as fan-out package 802-1 and fan-out package 802-1. The fan-out package 802-1 and the fan-out package 802-2 may be Figure 1A and Figure 1B Fan-out package 102, FIG. 6A to FIG. 6E The fan-out package 602 and / or 7A to 7E An example of a fan-out package 702 and may include any of the details discussed with reference to these figures.

[0088] The power module 800 may include a substrate 820-1 (e.g., a direct bond copper (DBC) substrate), a substrate 820-2 (e.g., a DBC substrate), and fan-out packages 802-1, 802-2 disposed between and coupled to the substrates 820-1 and 820-2. In some examples, the power module 800 includes a lead frame portion 838-1 and a lead frame portion 838-2 disposed between and coupled to the substrates 820-1 and 820-2. The conductive plate 806 of the fan-out package 802-1 is coupled to the substrate 820-1, and the conductive plate 806 of the fan-out package 802-2 is coupled to the substrate 820-2 (e.g., one of the fan-out packages is flipped relative to the other fan-out package).

[0089] Substrate 820-1 includes a dielectric layer 824. Dielectric layer 824 includes an insulating material. In some examples, dielectric layer 824 includes a ceramic material. In some examples, substrate 820-1 includes a single dielectric layer 824. In some examples, substrate 820-1 includes multiple dielectric layers 824. In some examples, substrate 820-1 includes a printed circuit board (PCB) substrate (e.g., a single-layer PCB or a multi-layer PCB). In some examples, substrate 820-1 includes a conductive layer 822 coupled to one surface of dielectric layer 824 and a conductive layer 826 coupled to another surface of dielectric layer 824. In some examples, conductive layer 822 includes a copper layer. In some examples, conductive layer 826 includes a copper layer. In some examples, substrate 820-1 is a direct bonded metal (DBM) substrate (e.g., a substrate having a dielectric disposed between two metal layers), such as a direct bonded copper (DBC) substrate. Substrate 820-2 can be the same / similar to substrate 820-1. For example, the substrate 820 - 2 further includes a dielectric layer 824 , a conductive layer 822 , and a conductive layer 826 .

[0090] Conductive layer 822 of substrate 820-1 includes inner surface 833 aligned in plane A4. Direction A1 is aligned perpendicular to plane A4, and direction A2 is perpendicular to direction A1. Direction A3 into the page (in Figure 1A and Figure 1B The fan-out package 802-1 and the fan-out package 802-2 are coupled to the substrate 820-1 and the substrate 820-2 and are disposed between them.

[0091] The fan-out package 802-1 includes a semiconductor die 804, a redistribution layer 808 coupled to a front side (e.g., source, gate) of the semiconductor die 804, and a plurality of conductive plates 806 coupled to a back side (e.g., drain) of the semiconductor die 804. Furthermore, the fan-out package 802-1 includes a passivation layer 810 applied to the back side of the semiconductor die 804 and a packaging material 814 contacting the semiconductor die 804 and the conductive plates 806.

[0092] The fan-out package 802-2 includes a semiconductor die 804, a redistribution layer 808 coupled to a front side (e.g., source, gate) of the semiconductor die 804, and a plurality of conductive plates 806 coupled to a back side (e.g., drain) of the semiconductor die 804. In addition, the fan-out package 802-2 includes a passivation layer 810 applied to the back side of the semiconductor die 804 and an encapsulation material 814 contacting the semiconductor die 804 and the conductive plates 806.

[0093] The fan-out package 802-1 can be coupled to the substrate 820-1 via the attachment layer 828, and the fan-out package 802-1 can be coupled to the substrate 820-2 via the attachment layer 828. The attachment layer 828 may include a bonding material (e.g., solder, sinter, or other adhesive) that can bond conductive components together. The conductive plate 806 of the fan-out package 802-1 is coupled to the conductive layer 822 of the substrate 820-1 via the attachment layer 828. The redistribution layer 808 of the fan-out package 802-1 is coupled to the conductive layer 822 of the substrate 820-2 via the attachment layer 828.

[0094] The fan-out package 802-2 may be coupled to the substrate 820-1 via the attachment layer 828, and the fan-out package 802-2 may be coupled to the substrate 820-2 via the attachment layer 828. The conductive plate 806 of the fan-out package 802-2 is coupled to the conductive layer 822 of the substrate 820-2 via the attachment layer 828. The redistribution layer 808 of the fan-out package 802-2 is coupled to the conductive layer 822 of the substrate 820-1 via the attachment layer 828.

[0095] The lead frame portion 838-1 may be disposed between the substrate 820-1 and the substrate 820-2 and coupled to the substrate 820-1 and the substrate 820-2. For example, the lead frame portion 838-1 is coupled to the conductive layer 822 of the substrate 820-1 and the conductive layer 822 of the substrate 820-2. The lead frame portion 838-2 may be disposed between the substrate 820-1 and the substrate 820-2 and coupled to the substrate 820-1 and the substrate 820-2. For example, the lead frame portion 838-2 is coupled to the conductive layer 822 of the substrate 820-1 and the conductive layer 822 of the substrate 820-2. The fan-out package 802-1 and the fan-out package 802-2 are disposed between the lead frame portion 838-1 and the lead frame portion 838-2 along the direction A2.

[0096] The power module 800 includes packaging material 846. The packaging material 846 can contact the edge of the substrate 820-1 and the edge of the substrate 820-2. The packaging material 846 can contact portions of the lead frame portion 838-1 and portions of the lead frame portion 838-2. In addition, the packaging material 846 can contact the fan-out package 802-1 and the fan-out package 802-2.

[0097] Fig. 9 An example of a power module 900 is shown. In some examples, the power module 900 includes a single-side cooling (DSC) power module. The power module 900 includes a plurality of fan-out packages, such as fan-out package 902-1 and fan-out package 902-1. The fan-out package 902-1 and the fan-out package 902-2 may be Figure 1A and Figure 1B Fan-out package 102, FIG. 6A to FIG. 6E The fan-out package 602 and / or 7A to 7E An example of a fan-out package 702 of the present invention and may include any details discussed with reference to these figures. The power module 900 may include a substrate 920 (e.g., a direct bond copper (DBC) substrate), a clamping member 942, and fan-out packages 902-1, 902-2 disposed between the substrate 920 and the clamping member 942 and coupled to the substrate and the clamping member. In some examples, the power module 900 includes a lead frame portion 938-1 and a lead frame portion 938-2, which are disposed between the substrate 920 and the clamping member 942 and coupled to the substrate and the clamping member. The conductive plate 906 of the fan-out package 902-1 is coupled to the substrate 920, and the conductive plate 906 of the fan-out package 902-2 is coupled to the substrate 920 (e.g., the fan-out packages 902-1, 902-2 have the same orientation).

[0098] Substrate 920 includes a dielectric layer 924. Dielectric layer 924 includes an insulating material. In some examples, dielectric layer 924 includes a ceramic material. In some examples, substrate 920 includes a single dielectric layer 924. In some examples, substrate 920 includes multiple dielectric layers 924. In some examples, substrate 920 includes a printed circuit board (PCB) substrate (e.g., a single-layer PCB or a multi-layer PCB). In some examples, substrate 920 includes a conductive layer 922 coupled to one surface of dielectric layer 924 and a conductive layer 926 coupled to another surface of dielectric layer 924. In some examples, conductive layer 922 includes a copper layer. In some examples, conductive layer 926 includes a copper layer. In some examples, substrate 920 is a direct bonded metal (DBM) substrate (e.g., a substrate having a dielectric disposed between two metal layers), such as a direct bonded copper (DBC) substrate. Conductive layer 922 of substrate 920 includes an inner surface 933 aligned in plane A4. Direction A1 is aligned perpendicular to plane A4, and direction A2 is perpendicular to direction A1. Direction A3 entering the page (at Figure 1A and Figure 1B ) is aligned parallel to plane A4 and orthogonal to directions A1 and A2.

[0099] The clamping member 942 includes a conductive material. In some examples, the clamping member 942 may include portions extending in the direction A1 and the direction A2. In some examples, the clamping member 942 includes portions arranged parallel to each other at multiple planes in the direction A2. In some examples, the clamping member 942 includes portions arranged at a certain angle (e.g., a non-zero, non-vertical angle) relative to each other. The fan-out package 902-1 and the fan-out package 902-2 are coupled to the substrate 920 and the clamping member 942 and are arranged between them.

[0100] The fan-out package 902-1 includes a semiconductor die 904, a redistribution layer 908 coupled to a front side (e.g., source, gate) of the semiconductor die 904, and a conductive plate 906 coupled to a back side (e.g., drain) of the semiconductor die 904. Furthermore, the fan-out package 902-1 includes a passivation layer 910 applied to the back side of the semiconductor die 904 and an encapsulation material 914 contacting the semiconductor die 904 and the conductive plate 906.

[0101] The fan-out package 902-2 includes a semiconductor die 904, a redistribution layer 908 coupled to a front side (e.g., source, gate) of the semiconductor die 904, and a conductive plate 906 coupled to a back side (e.g., drain) of the semiconductor die 904. In addition, the fan-out package 902-2 includes a passivation layer 910 applied to the back side of the semiconductor die 904 and an encapsulation material 914 contacting the semiconductor die 909 and the conductive plate 906.

[0102] The fan-out package 902-1 can be coupled to the substrate 920 via the attachment layer 928, and the fan-out package 902-2 can contact (e.g., directly contact) the clamping member 942. The attachment layer 928 may include a bonding material (e.g., solder, sinter, or other adhesive) that can bond the conductive components together. The conductive plate 906 of the fan-out package 902-1 is coupled to the conductive layer 922 of the substrate 920 via the attachment layer 928. The redistribution layer 908 of the fan-out package 902-1 contacts the clamping member 942. The fan-out package 902-2 can be coupled to the substrate 920 via the attachment layer 328, and the fan-out package 902-2 can contact the clamping member 942. The conductive plate 906 of the fan-out package 902-2 is coupled to the conductive layer 922 of the substrate 920 via the attachment layer 928. The redistribution layer 908 of the fan-out package 902-2 contacts the clamping member 942.

[0103] The lead frame portion 938-1 can be disposed between the substrate 920 and the clamping member 942 and coupled to the substrate 920 and the clamping member 942. For example, the lead frame portion 938-1 is coupled to the conductive layer 922 of the substrate 920 and the clamping member 942. The lead frame portion 938-2 can be disposed between the substrate 920 and the clamping member 942 and coupled to the substrate 920 and the clamping member 942. For example, the lead frame portion 938-2 is coupled to the conductive layer 922 of the substrate 920 and the clamping member 942. The fan-out package 902-1 and the fan-out package 902-2 are disposed between the lead frame portion 938-1 and the lead frame portion 938-2 along the direction A2. The power module 900 includes an encapsulation material 948. The encapsulation material 948 can contact portions of the substrate 920 and the clamping member 942. Encapsulation material 948 may contact portions of leadframe portion 938-1 and portions of leadframe portion 938-2. Additionally, encapsulation material 948 may contact fan-out package 902-1 and fan-out package 902-2.

[0104] FIG. 10A to FIG. 10C A manufacturing process 1000 for manufacturing a fan-out package is shown according to one aspect. In some examples, the manufacturing process 1000 creates FIG. 6A to FIG. 6E The fan-out package 602 or 7A to 7E A fan-out package 702 is provided.

[0105] Operation 1052 includes bonding a silicon wafer 1075 having conductive pads 1073 to a wafer 1079 (e.g., a glass wafer) using an adhesive material 1071. Operation 1054 includes applying a conductive plating 1005 to a back side of the silicon wafer 1075. Operation 1056 includes removing the wafer 1079 from the silicon wafer 1075. Operation 1060 includes applying a die saw operation to produce individual semiconductor dies 1004, wherein the conductive pads 1073 are coupled to the front side of the semiconductor dies 1004 and the conductive plates 1006 are coupled to the back side of the semiconductor dies 1004. Operation 1062 includes a pick and place operation (e.g., die construction) of attaching a carrier assembly 1048 (having the carrier 1053 coupled to the film 1051) to the conductive pads 1073. Operation 1064 includes applying an encapsulation material 1014 to the carrier assembly 1048, the semiconductor dies 1004, the conductive pads 1073, and the conductive plates 1006. Operation 1066 includes removing carrier assembly 1048. Operation 1070 includes forming redistribution layer 1008 and passivation layer 1010. Operation 1072 includes removing a portion of packaging material 1014 to expose a surface of conductive plate 1006. Operation 1074 includes a singulation process that separates fan-out packages (e.g., fan-out package 1002-1 and fan-out package 1002-2).

[0106] Fig.11 A flowchart 1100 depicting a method having example operations for manufacturing a fan-out package is depicted according to one aspect. Figure 1A and Figure 1B Flowchart 1100 is described for a fan-out package 102 of FIG. 1 , but the flow chart is applicable to any fan-out package discussed herein. Fig.11 The flowchart 1100 shows the operations in a sequential order, but it should be understood that this is merely exemplary and may include additional or alternative operations. Fig.11 The operations and related operations may be performed in a different order than shown, or in a parallel or overlapping manner.

[0107] Operation 1102 includes coupling a die back conductive member to a first surface of each semiconductor die in a plurality of semiconductor dies. Operation 1104 includes applying an encapsulation material to the die back conductive member and the plurality of semiconductor dies. Operation 1106 includes forming a redistribution layer on a second surface of each semiconductor die in the plurality of semiconductor dies. Operation 1108 includes removing a portion of the encapsulation material to expose a surface of the die back conductive member.

[0108] Item 1. A fan-out package comprising: a plurality of semiconductor dies, each of the semiconductor dies comprising a first surface and a second surface opposite to the first surface; a redistribution layer coupled to the first surface of each of the plurality of semiconductor dies; a die back side conductive member coupled to the second surface of each of the plurality of semiconductor dies; and a packaging material coupled to the plurality of semiconductor dies and the die back side conductive member.

[0109] Clause 2. The fan-out package of Clause 1, wherein the die back side conductive member comprises a single conductive spacer coupled to the plurality of semiconductor dies.

[0110] Clause 3. The fan-out package of Clause 1 or 2, wherein the die back conductive member comprises a plurality of conductive plates, each conductive plate of the plurality of conductive plates coupled to a separate semiconductor die of the plurality of semiconductor dies.

[0111] Clause 4. The fan-out package of any one of clauses 1 to 3, further comprising: a passivation layer coupled to the plurality of semiconductors.

[0112] Clause 5. The fan-out package of any of Clauses 1 to 4, wherein the plurality of semiconductors comprises a first semiconductor die, a second semiconductor die, and a third semiconductor die.

[0113] Clause 6. The fan-out package of any of Clauses 1 to 5, wherein the redistribution layer comprises a source contact pad common to the plurality of semiconductor dies.

[0114] Clause 7. The fan-out package of any of Clauses 1 to 6, wherein the die back conductive member comprises a drain contact pad common to the plurality of semiconductor dies.

[0115] Item 8. A power module, comprising: a substrate; a first fan-out package coupled to the substrate; and a second fan-out package coupled to the substrate, each of the first fan-out package and the second fan-out package comprising: a plurality of semiconductor dies, each of the semiconductor dies comprising a first surface and a second surface opposite to the first surface; a redistribution layer, the redistribution layer coupled to the first surface of each of the plurality of semiconductor dies; a die back conductive member, the die back conductive member coupled to the second surface of each of the plurality of semiconductor dies; and a packaging material, the packaging material coupled to the plurality of semiconductor dies and the die back conductive member.

[0116] Clause 9. The power module of clause 8, wherein the substrate is a first substrate, the power module further comprising: a second substrate, the first fan-out package and the second fan-out package being disposed between the first substrate and the second substrate and coupled to the first substrate and the second substrate.

[0117] Clause 10. The power module of Clause 9, wherein the die back conductive member of the first fan-out package is coupled to the first substrate, and the die back conductive member of the second fan-out package is coupled to the second substrate.

[0118] Clause 11. The power module according to any one of clauses 8 to 10 further includes: a first lead frame portion, which is arranged between the first substrate and the second substrate and coupled to the first substrate and the second substrate; and a second lead frame portion, which is arranged between the first substrate and the second substrate and coupled to the first substrate and the second substrate.

[0119] Clause 12. The power module of any one of clauses 8 to 11, further comprising: a clamping member, the first fan-out package and the second fan-out package being disposed between and coupled to the substrate and the clamping member.

[0120] Clause 13. The power module of Clause 12, wherein the die back side conductive member of the first fan-out package is coupled to the substrate, and the die back side conductive member of the second fan-out package is coupled to the substrate.

[0121] Clause 14. The power module of Clause 12, wherein the substrate comprises a first conductive layer, a second conductive layer, and a dielectric layer disposed between and coupled to the first conductive layer and the second conductive layer.

[0122] Clause 15. A power module according to any one of clauses 8 to 14, wherein the packaging material is a first packaging material, the power module further comprising: a second packaging material, the second packaging material coupled to the substrate, the first fan-out package, and the second fan-out package.

[0123] Item 16. A method for manufacturing a fan-out package, the method comprising: coupling a die back conductive member to a first surface of each semiconductor die in a plurality of semiconductor dies; applying a packaging material to the die back conductive member and the plurality of semiconductor dies; forming a redistribution layer on a second surface of each semiconductor die in the plurality of semiconductor dies; and removing a portion of the packaging material to expose a surface of the die back conductive member.

[0124] Clause 17. The method of Clause 16, wherein the die back conductive member comprises a single conductive spacer coupled to the plurality of semiconductor dies.

[0125] Clause 18. The method of Clause 16 or 17, wherein the die back conductive member comprises a plurality of conductive plates, each conductive plate of the plurality of conductive plates coupled to a separate semiconductor die of the plurality of semiconductor dies.

[0126] Clause 19. The method of Clause 18, further comprising: applying a metal layer to the first surface of each semiconductor die in a plurality of semiconductor dies; and removing a portion of the metal layer between adjacent semiconductor dies to form the plurality of conductive plates.

[0127] Clause 20. The method of any one of Clauses 16 to 19, further comprising: forming a passivation layer on the first surface of each semiconductor die in the plurality of semiconductor dies.

[0128] It should be understood that in the foregoing description, when an element is referred to as being connected to another element, electrically connected to another element, coupled to another element or electrically coupled to another element, the element may be directly connected or coupled to another element, or one or more intermediate elements may be present. On the contrary, when an element is referred to as being directly connected to another element or being directly coupled to another element, there is no intermediate element. Although the term directly connected to or directly coupled to may not be used throughout the detailed description, the element shown as being directly connected or directly coupled may be mentioned in this manner. The claims of the present application (if any) may be revised to narrate the exemplary relationship described in the specification or shown in the accompanying drawings. The embodiments of various technologies described herein may be implemented (for example, included therein) in digital electronic circuits, computer hardware, firmware, software or a combination thereof. The part of the method may also be performed by a dedicated logic circuit such as FPGA (field programmable gate array) or ASIC (application specific integrated circuit), and the device may be implemented as the dedicated logic circuit.

[0129] Some implementations may be implemented using various semiconductor processing and / or packaging technologies. Some implementations may be implemented using various types of semiconductor processing technologies associated with semiconductor substrates, including but not limited to, for example, silicon (Si), gallium arsenide (GaAs), gallium nitride (GaN), silicon carbide (SiC), etc.

[0130] Although certain features of the specific implementation described have been described as described herein, those skilled in the art will now expect many modifications, alternatives, variations and equivalents. Therefore, it should be understood that the appended claims are intended to cover all such modifications and variations that fall within the scope of the embodiments. It should be understood that these modifications and variations are presented only by way of example and not limitation, and various changes in form and detail may be made. In addition to mutually exclusive combinations, any part of the apparatus and / or method described herein may be combined in any combination. The embodiments described herein may include various combinations and / or sub-combinations of the functions, components and / or features of the different embodiments described.

Claims

1. A fan-out package (102) (202) (302-1) (302-2) (402-1) (402-2) (502-1) (502-2) (602) (702) (802-1) (802-2) (902-1) (902-2) (1002-1) (1002-2), comprising: A plurality of semiconductor dies (104)(204)(304)(404)(504)(604)(704)(804)(904)(1004), each semiconductor die in the plurality of semiconductor dies comprising a first surface and a second surface opposite the first surface; a redistribution layer (108)(208)(308)(408)(508)(608)(708)(808)(908)(1008) coupled to the first surface of each semiconductor die of the plurality of semiconductor dies; a die back side conductive member (106)(206)(306)(406)(506)(606)(706)(806)(906)(1006) coupled to the second surface of each semiconductor die of the plurality of semiconductor dies; and A packaging material (114)(214)(314)(414)(514)(614)(814)(914)(1014) is coupled to the plurality of semiconductor dies and the die back side conductive features.

2. The fan-out package of claim 1, wherein the die back side conductive member comprises a single conductive spacer (206) (306) (406) (506) (606) coupled to the plurality of semiconductor dies.

3. The fan-out package of claim 1 , wherein the die back side conductive member ( 106 ) comprises a plurality of conductive plates ( 706 ) ( 806 ) ( 906 ) ( 1006 ), each of the plurality of conductive plates being coupled to a separate semiconductor die of the plurality of semiconductor dies.

4. The fan-out package according to claim 1, further comprising: A passivation layer (210)(310)(410)(510-1)(510-2)(610)(610-1)(610-2)(710)(810)(910)(1010) is coupled to the plurality of semiconductors. 5 . The fan-out package of claim 1 , wherein the plurality of semiconductors comprises a first semiconductor die, a second semiconductor die, and a third semiconductor die.

6. The fan-out package of claim 1, wherein the redistribution layer comprises a source contact pad (530) common to the plurality of semiconductor dies.

7. The fan-out package of claim 1, wherein the die back side conductive member (106) comprises a drain contact pad common to the plurality of semiconductor dies.

8. A power module (300) (400) (800) (900), comprising: Substrate (320-1)(420)(820-1)(920); A first fan-out package (302-1)(402-2)(802-1)(902-1) coupled to the substrate; as well as A second fan-out package (302-2) (402-2) (802-2) (902-2), the second fan-out package coupled to the substrate, each of the first fan-out package and the second fan-out package comprising: A plurality of semiconductor dies (304)(404)(804)(904), each semiconductor die in the plurality of semiconductor dies comprising a first surface and a second surface opposite the first surface; a redistribution layer (308)(408)(808)(908) coupled to the first surface of each semiconductor die in the plurality of semiconductor dies; a die back side conductive member (306)(406)(806)(906) coupled to the second surface of each semiconductor die in the plurality of semiconductor dies; and An encapsulation material (314) (414) (814) (914) coupled to the plurality of semiconductor dies and the die back side conductive features.

9. The power module according to claim 8, wherein the substrate is a first substrate (320-1)(420)(820-1)(920), and the power module further comprises: A second substrate (320-2)(820-2), the first fan-out package and the second fan-out package are disposed between the first substrate and the second substrate and coupled to the first substrate and the second substrate. 10 . The power module of claim 9 , wherein the die back side conductive member of the first fan-out package is coupled to the first substrate, and the die back side conductive member of the second fan-out package is coupled to the second substrate.

11. The power module according to claim 8, further comprising: a first lead frame portion (338-1)(438-1)(838-1)(938-1) disposed between and coupled to the first substrate and the second substrate; and A second lead frame portion (338-2) (438-2) (838-2) (938-2) is disposed between the first substrate and the second substrate and coupled to the first substrate and the second substrate.

12. The power module according to claim 8, further comprising: A clamping member (442)(942), the first fan-out package and the second fan-out package are disposed between the substrate and the clamping member and coupled to the substrate and the clamping member. 13 . The power module of claim 12 , wherein the die back side conductive member of the first fan-out package is coupled to the substrate, and the die back side conductive member of the second fan-out package is coupled to the substrate. 14 . The power module of claim 12 , wherein the substrate comprises a first conductive layer, a second conductive layer, and a dielectric layer disposed between and coupled to the first conductive layer and the second conductive layer.

15. The power module according to claim 8, wherein the packaging material is a first packaging material, and the power module further comprises: A second encapsulation material is coupled to the substrate, the first fan-out package, and the second fan-out package.

16. A method for manufacturing a fan-out package (102) (202) (302-1) (302-2) (402-1) (402-2) (502-1) (502-2) (602) (702) (802-1) (802-2) (902-1) (902-2) (1002-1) (1002-2), the method comprising: coupling a die back side conductive member (106)(206)(306)(406)(506)(606)(706)(806)(906)(1006) to a first surface of each semiconductor die in a plurality of semiconductor dies (104)(204)(304)(404)(504)(604)(704)(804)(904)(1004); applying an encapsulation material (114)(214)(314)(414)(514)(614)(814)(914)(1014) to the die back side conductive member and the plurality of semiconductor dies; forming a redistribution layer (108)(208)(308)(408)(508)(608)(708)(808)(908)(1008) on a second surface of each semiconductor die of the plurality of semiconductor dies; as well as A portion of the encapsulation material is removed to expose a surface of the die back side conductive feature. 17 . The method of claim 16 , wherein the die back side conductive member comprises a single conductive spacer coupled to the plurality of semiconductor dies. 18 . The method of claim 16 , wherein the die back conductive member comprises a plurality of conductive plates, each conductive plate of the plurality of conductive plates being coupled to a separate semiconductor die of the plurality of semiconductor dies.

19. The method according to claim 18, further comprising: applying a metal layer to the first surface of each semiconductor die of the plurality of semiconductor dies; as well as A portion of the metal layer between adjacent semiconductor dies is removed to form the plurality of conductive plates.

20. The method of claim 16, further comprising: A passivation layer is formed on the first surface of each semiconductor die in the plurality of semiconductor dies.

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