IGBT defect positioning method and device based on turn-off process gate current

Abstract

The application provides an IGBT defect positioning method and device based on turn-off process gate current, which comprises the following steps: obtaining the total number of chips of a target IGBT, a first normal gate current in a gate voltage drop stage, a first actual gate current, a second normal gate current in a Miller platform stage, and a second actual gate current; determining a first normal gate discharge charge amount in the gate voltage drop stage, a first actual gate discharge charge amount, a second normal gate discharge charge amount in the Miller platform stage, and a second actual gate discharge charge amount; and completing internal defect positioning of the target IGBT according to the total number of chips, the first normal gate discharge charge amount, the first actual gate discharge charge amount, the second normal gate discharge charge amount, and the second actual gate discharge charge amount. The application can realize positioning of internal defects of an insulated gate bipolar transistor, and is convenient for subsequent maintenance of the insulated gate bipolar transistor.

Description

Technical Field

[0001] This application relates to the field of insulated gate bipolar transistor (IGBT) technology, and in particular to an IGBT defect localization method and apparatus based on gate current during the turn-off process. Background Technology

[0002] Insulated Gate Bipolar Transistor (IGBT) devices combine the advantages of fast switching speed of Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) devices with low conduction losses of bipolar devices, and have been widely used in new energy converters, flexible DC transmission equipment and dynamic reactive power compensation equipment.

[0003] Existing methods for detecting defects in insulated gate bipolar transistors (IGBTs) are limited. For example, analyzing the gate discharge charge can partially reflect whether defects have occurred inside the IGBT, but it cannot locate the internal defects of the IGBT. Summary of the Invention

[0004] To address at least one problem in the prior art, this application proposes a method and apparatus for IGBT defect localization based on gate current during the turn-off process, which can locate internal defects in insulated gate bipolar transistors, facilitating subsequent maintenance of the insulated gate bipolar transistors.

[0005] To address the aforementioned technical problems, this application provides the following technical solution:

[0006] In a first aspect, this application provides a method for IGBT defect localization based on gate current during the turn-off process, including:

[0007] The total number of chips in the target IGBT is obtained, the first normal gate current during the gate voltage drop phase, the first actual gate current, the second normal gate current during the Miller plateau phase, and the second actual gate current. The turn-off process includes the gate voltage drop phase and the Miller plateau phase.

[0008] Based on the first normal gate current during the gate voltage drop phase, the first actual gate current, the second normal gate current during the Miller plateau phase, and the second actual gate current, determine the first normal gate discharge charge, the first actual gate discharge charge, the second normal gate discharge charge, and the second actual gate discharge charge during the Miller plateau phase.

[0009] Based on the total number of chips, the first normal gate discharge charge during the gate voltage drop phase, the first actual gate discharge charge, the second normal gate discharge charge during the Miller plateau phase, and the second actual gate discharge charge, the internal defect location of the target IGBT is completed.

[0010] In one embodiment, the step of locating the internal defect of the target IGBT based on the total number of chips, the first normal gate discharge charge during the gate voltage drop phase, the first actual gate discharge charge, the second normal gate discharge charge during the Miller plateau phase, and the second actual gate discharge charge includes:

[0011] If the first normal gate discharge charge is greater than the first actual gate discharge charge, then the internal defects of the target IGBT, including gate-emitter circuit defects, are located.

[0012] If the second normal gate discharge charge is greater than the second actual gate discharge charge, the internal defects of the target IGBT, including collector-gate circuit defects, are located.

[0013] In one embodiment, after locating the internal defects of the target IGBT, including gate-emitter circuit defects, the method further includes:

[0014] The number of chips in the target IGBT with gate-emitter circuit defects is determined based on the first normal gate discharge charge, the first actual gate discharge charge, and the total number of chips.

[0015] In one embodiment, after locating the internal defects of the target IGBT, including gate circuit defects, the method further includes:

[0016] The number of chips in the target IGBT that have a collector-gate circuit defect is determined based on the second normal gate discharge charge, the second actual gate discharge charge, and the total number of chips.

[0017] In one embodiment, the IGBT defect localization method based on gate current during the turn-off process further includes:

[0018] If the internal defects of the target IGBT include gate-emitter circuit defects and collector-gate circuit defects, then the defect type of the target IGBT is determined to be a gate defect.

[0019] In one embodiment, the IGBT defect localization method based on gate current during the turn-off process further includes:

[0020] If the internal defects of the target IGBT include gate-emitter circuit defects but not collector-gate circuit defects, then the defect type of the target IGBT is determined to be an emitter defect.

[0021] In one embodiment, the IGBT defect localization method based on gate current during the turn-off process further includes:

[0022] If the internal defects of the target IGBT include collector-gate circuit defects but not gate-emitter circuit defects, then the defect type of the target IGBT is determined to be a collector defect.

[0023] Secondly, this application discloses an IGBT defect location device based on the gate current during the turn-off process, comprising:

[0024] The acquisition module is used to acquire the total number of chips of the target IGBT, the first normal gate current during the gate voltage drop phase, the first actual gate current, the second normal gate current and the second actual gate current during the Miller plateau phase. The turn-off process includes the gate voltage drop phase and the Miller plateau phase.

[0025] The charge quantity determination module is used to determine the first normal gate discharge charge, the first actual gate discharge charge, the second normal gate discharge charge, and the second actual gate discharge charge during the gate voltage drop phase, based on the first normal gate current during the gate voltage drop phase, the first actual gate current, the second normal gate current during the Miller plateau phase, and the second actual gate current.

[0026] The detection module is used to locate the internal defects of the target IGBT based on the total number of chips, the first normal gate discharge charge during the gate voltage drop phase, the first actual gate discharge charge, the second normal gate discharge charge during the Miller plateau phase, and the second actual gate discharge charge.

[0027] In one embodiment, the detection module includes:

[0028] The first detection unit is used to detect whether the first normal gate discharge charge is greater than the first actual gate discharge charge. If so, the internal defects of the target IGBT, including gate-emitter circuit defects, are located.

[0029] The second detection unit is used to detect whether the second normal gate discharge charge is greater than the second actual gate discharge charge. If so, the internal defects of the target IGBT, including gate circuit defects, are located.

[0030] In one embodiment, the IGBT defect location device based on the gate current during the turn-off process further includes:

[0031] The first chip quantity determination module is used to determine the number of chips in the target IGBT that have a gate-emitter circuit defect based on the first normal gate discharge charge, the first actual gate discharge charge, and the total number of chips.

[0032] In one embodiment, the IGBT defect location device based on the gate current during the turn-off process further includes:

[0033] The second chip quantity determination module is used to determine the number of chips in the target IGBT that have a collector-gate circuit defect based on the second normal gate discharge charge, the second actual gate discharge charge, and the total number of chips.

[0034] In one embodiment, the IGBT defect location device based on the gate current during the turn-off process further includes:

[0035] A gate defect determination module is used to determine that the defect type of the target IGBT is a gate defect if the internal defects of the target IGBT include gate-emitter circuit defects and collector-gate circuit defects.

[0036] In one embodiment, the IGBT defect location device based on the gate current during the turn-off process further includes:

[0037] An emitter defect determination module is used to determine that the defect type of the target IGBT is an emitter defect if the internal defects of the target IGBT include gate-emitter circuit defects but do not include collector-gate circuit defects.

[0038] In one embodiment, the IGBT defect location device based on the gate current during the turn-off process further includes:

[0039] The collector defect determination module is used to determine the defect type of the target IGBT as a collector defect if the internal defects of the target IGBT include collector-gate circuit defects but do not include gate-emitter circuit defects.

[0040] Thirdly, this application provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the IGBT defect localization method based on the gate current during the turn-off process.

[0041] Fourthly, this application provides a computer-readable storage medium storing computer instructions thereon, which, when executed by a processor, implement the IGBT defect localization method based on gate current during the turn-off process.

[0042] As can be seen from the above technical solution, this application provides a method and apparatus for IGBT defect localization based on gate current during the turn-off process. The method includes: obtaining the total number of chips in the target IGBT, the first normal gate current during the gate voltage drop phase, the first actual gate current, the second normal gate current during the Miller plateau phase, and the second actual gate current; the turn-off process includes the gate voltage drop phase and the Miller plateau phase; determining the first normal gate discharge charge during the gate voltage drop phase, the first actual gate discharge charge during the gate voltage drop phase, and the second normal gate discharge charge during the Miller plateau phase based on the first normal gate current during the gate voltage drop phase, the first actual gate discharge charge during the gate voltage drop phase, and the second normal gate discharge charge during the Miller plateau phase; and completing the internal defect location of the target IGBT based on the total number of chips, the first normal gate discharge charge during the gate voltage drop phase, the first actual gate discharge charge during the gate voltage drop phase, and the second normal gate discharge charge during the Miller plateau phase. This method enables the location of internal defects in insulated gate bipolar transistors (IGBTs), is efficient and reliable, and facilitates subsequent maintenance of the IGBTs. It can also achieve IGBT defect state detection and location based on the gate current waveform during the turn-off delay process, and can be achieved by observing the gate current i during the IGBT device's turn-off delay process. G Waveform analysis of whether a device has a defect and its location are of certain significance for IGBT condition detection. Attached Figure Description

[0043] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0044] Figure 1 This is a first flowchart illustrating the IGBT defect localization method based on gate current during the turn-off process in an embodiment of this application.

[0045] Figure 2 This is a schematic diagram of the commutation loop structure of the half-bridge circuit model in the embodiments of this application;

[0046] Figure 3 This is a schematic diagram of the internal structure of the IGBT in the embodiments of this application;

[0047] Figure 4 This is a schematic diagram of the IGBT turn-off delay process in the embodiments of this application;

[0048] Figure 5This is a second flowchart illustrating the IGBT defect localization method based on gate current during the turn-off process in an embodiment of this application.

[0049] Figure 6 This is a first structural schematic diagram of the IGBT defect location device based on the gate current during the turn-off process in the embodiments of this application.

[0050] Figure 7 This is a second structural schematic diagram of the IGBT defect location device based on the gate current during the turn-off process in the embodiments of this application;

[0051] Figure 8 This is a schematic block diagram of the system configuration of an electronic device according to an embodiment of this application. Detailed Implementation

[0052] To enable those skilled in the art to better understand the technical solutions in this specification, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0053] To address the problems existing in the prior art, this application provides an IGBT defect localization method and apparatus based on the gate current during the turn-off delay process. By analyzing the gate current waveform during the turn-off delay process, the process is divided into a gate voltage drop stage and a Miller plateau stage. The response of the gate current waveform to collector, emitter, and gate defects in each stage is studied separately. The method proposes to comprehensively analyze the gate current characteristics of both stages of the turn-off delay process to locate defects at different locations within the IGBT, thereby enhancing the understanding of internal IGBT defects and providing value for IGBT device performance testing. The method can locate defects by observing the gate current i during the IGBT device's turn-off delay process. G Waveform analysis can help determine whether a device has a defect and locate the defect, thus improving the reliability and ease of IGBT defect localization.

[0054] The following examples illustrate this in detail.

[0055] To locate internal defects in Insulated Gate Bipolar Transistors (IGBTs) and facilitate subsequent maintenance, this embodiment provides an IGBT defect location method based on the gate current during the turn-off process. This IGBT defect location device, which is executed by a gate current-based turn-off process defect location device, includes, but is not limited to, a server. Figure 1As shown, this method specifically includes the following:

[0056] Step 100: Obtain the total number of chips of the target IGBT, the first normal gate current during the gate voltage drop phase, the first actual gate current, the second normal gate current and the second actual gate current during the Miller plateau phase. The turn-off process includes the gate voltage drop phase and the Miller plateau phase.

[0057] Specifically, the first normal gate current can be the gate current of the target IGBT in its normal state during the gate voltage drop phase; the first actual gate current can be the actual gate current of the target IGBT during the gate voltage drop phase; the second normal gate current can be the gate current in its normal state during the Miller plateau phase; and the second actual gate current can be the actual gate current during the Miller plateau phase. The turn-off process can include a turn-off delay process, where the gate voltage drop phase can be the gate voltage drop phase of the turn-off delay process, and the Miller plateau phase can be the Miller plateau phase of the turn-off delay process.

[0058] Step 200: Determine the first normal gate discharge charge, the first actual gate discharge charge, the second normal gate discharge charge, and the second actual gate discharge charge during the gate voltage drop phase based on the first normal gate current, the first actual gate current, the second normal gate current, and the second actual gate current during the Miller plateau phase.

[0059] Specifically, the gate current i G The following relationship exists between the amount of gate discharge charge and the amount of gate discharge charge:

[0060]

[0061] Where n is the total number of chips, and Q is the gate discharge charge of a single chip. The gate current of the insulated-gate bipolar transistor (IGBT) during the turn-off delay process can be measured, generating a gate current waveform. By combining the relationship between the gate current and the gate discharge charge, the actual gate discharge charge during the gate voltage drop phase and the Miller plateau phase of the turn-off delay process can be determined. Similarly, the gate current waveform of the IGBT under normal conditions during the turn-off delay process can be obtained, and by combining the relationship between the gate current and the gate discharge charge, the normal gate discharge charge during the gate voltage drop phase and the Miller plateau phase of the turn-off delay process can be determined. It is understood that, assuming i... G If the first actual gate current is given, then the actual gate discharge charge of a single chip during the gate voltage drop phase can be Q, where Q is the first actual gate discharge charge. tA,fault It can be n×Q; assuming i GIf the first normal gate current is given, then the normal gate discharge charge of a single chip during the gate voltage drop phase can be Q, where Q is the first normal gate discharge charge. tA It can be n×Q; assuming i G If the second normal gate current is given, then the normal gate discharge charge of a single chip during the Miller plateau stage can be Q, and the second normal gate discharge charge Q is given. G It can be n×Q; assuming i G If the second actual gate current is given, then the actual gate discharge charge of a single chip during the Miller plateau stage can be Q, and the second actual gate discharge charge Q is given. G,fault It can be n×Q.

[0062] Specifically, Figure 2 For the commutation loop structure of a half-bridge circuit model containing IGBTs, u GE U is the gate voltage. CE The collector-emitter voltage, u chip,CE The chip collector-emitter voltage, turn-off delay process u chip,CE =u CE u CG This is the collector-gate voltage. C For collector current, L s,1 u is the parasitic inductance value of the IGBT circuit. GE Given the device gate voltage, this half-bridge circuit model should include the gate current i. G Measurement points for key parameters; Figure 2 In the diagram, dashed box 1 represents the IGBT, dashed box 2 represents the collector-gate circuit, and dashed box 3 represents the gate-emitter circuit. The reference directions for voltage and current are... Figure 2 The bid was won. L s,F and L s,CE These represent the parasitic parameters of the internal package main circuit of the FWD and IGBT devices, respectively. s,F Including parasitic inductances on the anode and cathode sides of the FWD, L s,CE Including L s,C L s,E2 part.

[0063] Figure 3 This represents the internal circuit structure of an IGBT, where n is the total number of chips. IGBT device packaging defects can be categorized into three types: gate defects, collector defects, and emitter defects. Figure 3 The marking ① indicates a gate defect. Figure 3 The marking ② indicates a collector defect. Figure 3 The label ③ indicates an emitter defect. Figure 4 The t0~t2 stage is the turn-off delay process, which includes two stages: ① gate voltage decrease stage (t0~t1), ② gate voltage Miller plateau stage (t1~t2). Figure 4Includes gate current i G Waveform.

[0064] Step 300: Based on the total number of chips, the first normal gate discharge charge during the gate voltage drop phase, the first actual gate discharge charge, the second normal gate discharge charge during the Miller plateau phase, and the second actual gate discharge charge, complete the internal defect location of the target IGBT.

[0065] Specifically, the first normal gate discharge charge can be the gate discharge charge of the target IGBT in its normal state during the gate voltage drop phase; the first actual gate discharge charge can be the actual gate discharge charge of the target IGBT in the gate voltage drop phase, which may be the gate discharge charge of the target IGBT after a defect occurs in the gate voltage drop phase. The second normal gate discharge charge can be the gate discharge charge of the target IGBT in its normal state during the Miller plateau phase; the second actual gate discharge charge can be the actual gate discharge charge of the target IGBT in the Miller plateau phase, which may be the gate discharge charge of the target IGBT after a defect occurs in the Miller plateau phase.

[0066] To improve the efficiency and ease of locating internal defects in insulated-gate bipolar transistors, such as... Figure 5 As shown, in one embodiment, step 300 includes:

[0067] Step 301: Detect whether the first normal gate discharge charge is greater than the first actual gate discharge charge. If so, locate the internal defects of the target IGBT, including gate-emitter circuit defects.

[0068] Specifically, during the gate voltage drop phase, when the gate discharge charge decreases (ΔQ) tA =(Q tA,fault —Q tA If Q < 0, it indicates a gate-emitter (GE) circuit defect in the IGBT. Where Q... tA,fault Q can represent the first actual gate discharge charge. tA It can represent the amount of charge discharged at the first normal gate.

[0069] Step 302: Detect whether the second normal gate discharge charge is greater than the second actual gate discharge charge. If so, locate the internal defects of the target IGBT, including collector-gate circuit defects.

[0070] Specifically, during the Miller plateau phase, when the gate charge changes by ΔQ G =(Q G —Q G,fault A value greater than 0 indicates a defect in the collector-gate (CG) circuit of the IGBT. Wherein, Q...G,fault Q can represent the second actual gate discharge charge. G It can represent the amount of charge discharged at the second normal gate.

[0071] To quantify the detection results of defects in insulated gate bipolar transistors, in one embodiment, after step 301, the method further includes:

[0072] Step 303: Determine the number of chips in the target IGBT that have gate-emitter circuit defects based on the first normal gate discharge charge, the first actual gate discharge charge, and the total number of chips.

[0073] Specifically, the number m1 of chips with gate-emitter circuit defects in the target IGBT can be determined according to the following formula:

[0074]

[0075] To quantify the detection results of defects in insulated gate bipolar transistors, in one embodiment, after step 302, the method further includes:

[0076] Step 304: Determine the number of chips in the target IGBT that have a collector-gate circuit defect based on the second normal gate discharge charge, the second actual gate discharge charge, and the total number of chips.

[0077] Specifically, the number m2 of chips with collector-gate circuit defects in the target IGBT can be determined according to the following formula:

[0078]

[0079] To improve the reliability of locating gate defects, in one embodiment, the IGBT defect location method based on gate current during the turn-off process further includes:

[0080] Step 305: If the internal defects of the target IGBT include gate-emitter circuit defects and collector-gate circuit defects, then the defect type of the target IGBT is determined to be a gate defect.

[0081] Specifically, if the first normal gate discharge charge is greater than the first actual gate discharge charge, and the second normal gate discharge charge is greater than the second actual gate discharge charge, then the defect type of the target IGBT can be determined to be a gate defect.

[0082] To improve the reliability of locating emitter defects, in one embodiment, the IGBT defect location method based on gate current during the turn-off process further includes:

[0083] Step 306: If the internal defects of the target IGBT include gate-emitter circuit defects but do not include collector-gate circuit defects, then the defect type of the target IGBT is determined to be an emitter defect.

[0084] Specifically, if the first normal gate discharge charge is greater than the first actual gate discharge charge, and the second normal gate discharge charge is less than or equal to the second actual gate discharge charge, then the defect type of the target IGBT can be determined to be an emitter defect.

[0085] To improve the reliability of locating collector defects, in one embodiment, the IGBT defect location method based on gate current during the turn-off process further includes:

[0086] Step 307: If the internal defects of the target IGBT include collector-gate circuit defects but not gate-emitter circuit defects, then the defect type of the target IGBT is determined to be a collector defect.

[0087] Specifically, if the first normal gate discharge charge is less than or equal to the first actual gate discharge charge, and the second normal gate discharge charge is greater than the second actual gate discharge charge, then the defect type of the target IGBT can be determined to be a collector defect.

[0088] To improve the reliability of the defective chip count, in one embodiment, the IGBT defect location method based on the gate current during the turn-off process may further include: if the defect type is a gate defect, it can be determined whether the number of chips with gate-emitter circuit defects and collector-gate circuit defects are the same, and then the number of chips with gate defects in the target IGBT is determined to be the number of chips with collector-gate circuit defects; otherwise, an abnormal warning is output. If the defect type is an emitter defect, the number of chips with emitter defects in the target IGBT is determined to be the number of chips with gate-emitter circuit defects. If the defect type is a collector defect, the number of chips with collector defects in the target IGBT is determined to be the number of chips with collector-gate circuit defects.

[0089] To further illustrate this solution, this application provides an application example of an IGBT defect location method based on gate current during the turn-off process, as described in detail below:

[0090] During the IGBT turn-off transient process, the gate-emitter capacitance (C) GE ) and Miller capacitance (C CG Current direction as follows Figure 2 As shown.

[0091] 1) For C GE If the voltage reference direction is G→E, then the process C GEDischarge, gate voltage u GE reduce.

[0092] 2) For C CG If the voltage reference direction is C→G, then in this process C CG Charging, u CG and u CE Increase.

[0093] Gate current i G The following relationship exists between voltage and (Q is the gate discharge charge of a single chip):

[0094]

[0095] Where n is the total number of chips, C GE For the gate-emitter capacitance, u GE C is the gate voltage. CG For Miller capacitance, u CG This is the collector-gate voltage.

[0096] If we consider the collector-gate voltage u CG ≈Collector-emitter voltage u CE ,exist:

[0097]

[0098] 1) During the gate voltage drop phase (t0~t1), u GE Change, and u CG No change.

[0099] 2) Miller plateau phase (t1~t2), u CG Change, and u GE No change.

[0100] C GE It is a constant (not dependent on u) GE (Changes with change), and C CG It is a variable (which varies with u) CG (Changes with change).

[0101] Table 1 summarizes the changes in voltage and capacitance during each stage of the turn-off delay process:

[0102] Table 1

[0103]

[0104] Considering the changes in voltage and capacitance at different stages, equation (2) can be simplified to:

[0105]

[0106] I. Gate voltage drop phase (t0~t1):

[0107] Gate voltage u during this stage GE Waveforms can be used to analyze gate-emitter (GE) circuit defects, which include both gate defects and emitter defects.

[0108] Define the gate-emitter loop time constant τ0 of a single chip as:

[0109] τ0=R G,off C ies (4)

[0110] The overall time constant τ of the gate circuit is:

[0111] τ=n×τ0=R G,off ×nC ies (5)

[0112] In equation (4), R G,off For gate turn-on resistance, C ies For the gate input capacitance (C) of a single IGBT chip ies =C GE +C CG ).

[0113] During the gate voltage drop phase (t0~t1), due to u CE Maintaining the on-state saturation voltage drop (approximately 3V), therefore the process C CG It can be approximated as a constant C. CG,sat .

[0114] Gate discharge during process t0~t1 satisfies the following relationship:

[0115]

[0116] Among them, U G,on To enable the gate power supply voltage during the turn-on process, U G,off The gate power supply voltage is the turn-off process voltage. Both parameters are constant and do not change with time.

[0117] Gate voltage u GE For collector current i C The control relationship is as follows:

[0118]

[0119] Where, μ n For electron mobility, α pnp Here, w is the transistor transport coefficient, w is the gate channel width, l is the gate channel length, and c is the gate channel length. ox U is the gate-channel capacitance per unit area. T This is the gate threshold voltage.

[0120] Miller platform height is determined by load current I L The size determines this. The Miller plateau value for the gate voltage is:

[0121]

[0122] Gate voltage u GE From U G,on Reduce to u miller The gate discharge charge Q during the process (i.e., the time from t0 to t1) tA This can be equivalent to the first normal gate discharge charge, Q. tA for:

[0123]

[0124] If a gate (G) or emitter (E) contact defect occurs in the gate-emitter circuit, the gate circuit discharge time constant will decrease. Referring to equation (4), when the gate or emitter contact of m IGBT chips is abnormal, the gate circuit time constant changes as follows:

[0125] τ=(nm)×τ0=R G,off ×(nm)C ies (10)

[0126] In the above case, the Miller plateau value of the gate voltage is u. miller,fault :

[0127]

[0128] Change in gate Miller plateau height Δu miller for:

[0129]

[0130] Gate voltage u GE From U G,on Reduce to u miller,fault Gate discharge charge Q during the process (i.e., t0~t1) tA,fault This can be equivalent to the first actual gate discharge charge mentioned above, Q tA,fault for:

[0131]

[0132] The following conclusions can be obtained from equations (9) and (12):

[0133] Case 1: When the gate discharge charge decreases (ΔQ) tA =(Q tA,fault —Q tA If the value is less than 0, it indicates that the IGBT has a gate-emitter (GE) circuit defect.

[0134] If we disregard the change in Miller platform height Δu caused by defects... miller (i.e., approximately consider u) miller ≈u miller,fault The change in gate discharge charge ΔQ tA The number of defective chips, m, is:

[0135]

[0136] II. Miller plateau phase (t1~t2):

[0137] The gate current i during this stage G Waveforms can be used to analyze defects in the gate-collector (GC) circuit. These defects include both gate defects and collector defects.

[0138] Gate voltage u GE During the Miller plateau process (t1~t2), the collector-emitter voltage u CE From near 0 to U DC .

[0139] u CG (or u) CE The larger C is, the better. CG The smaller. C CG with u CE The functional relationship between them is:

[0140]

[0141] Where q is the electron charge, N D For the doping concentration in the drift region, p SC To traverse the hole concentration of the depleted layer, n SC Let n be the electron concentration passing through the depletion layer, n be the total number of chips, and ε be the dielectric constant of silicon.

[0142] Miller plateau process gate charge Q G This can be equivalent to the second normal gate discharge charge mentioned above, Q G for:

[0143]

[0144] When defects occur at the collector gates of m chips, the gate charge during the Miller plateau process can be equivalent to the second actual gate discharge charge mentioned above, Q. G，fault for:

[0145]

[0146] The following conclusions can be obtained from equation (17):

[0147] Scenario 2: When an IGBT experiences a collector-gate (CG) circuit defect, the gate voltage u GE Gate charge Q during the Miller plateau process (t1 to t2) G,fault The gate charge decreases. The change in gate charge during this process is ΔQ. G =(Q G —Q G,fault )>0.

[0148] Combining equations (16) and (17), the change in gate charge is ΔQ G Solve for the number of defective chips, m:

[0149]

[0150] III. IGBT Defect Localization Methods:

[0151] Combining scenarios 1 and 2, the method for locating defects in IGBT devices is as follows:

[0152] 1) Gate defects: Both cases 1 and 2 exist;

[0153] 2) Collector defects: Case 1 does not exist, Case 2 exists.

[0154] 3) Emitter defects: Case 1 exists, Case 2 does not exist;

[0155] Table 2 shows the IGBT defect types and corresponding conditions. "√" indicates that the corresponding condition exists, and "×" indicates that the corresponding condition does not exist.

[0156] Table 2

[0157] Gate defects Collector defects emitter defects Case 1 √ × √ Case 2 √ √ ×

[0158] From a software perspective, in order to locate internal defects in insulated-gate bipolar transistors (IGBTs) and facilitate subsequent maintenance, this application provides an embodiment of an IGBT defect location device based on the gate current during the turn-off process, which implements all or part of the aforementioned IGBT defect location method based on gate current during the turn-off process. See [link to embodiment]. Figure 6 The IGBT defect location device based on gate current during the turn-off process specifically includes the following components:

[0159] The acquisition module 01 is used to acquire the total number of chips of the target IGBT, the first normal gate current during the gate voltage drop phase, the first actual gate current, the second normal gate current and the second actual gate current during the Miller plateau phase. The turn-off process includes the gate voltage drop phase and the Miller plateau phase.

[0160] The charge quantity determination module 02 is used to determine the first normal gate discharge charge, the first actual gate discharge charge, the second normal gate discharge charge, and the second actual gate discharge charge during the gate voltage drop phase, based on the first normal gate current during the gate voltage drop phase, the first actual gate current, the second normal gate current during the Miller plateau phase, and the second actual gate current.

[0161] The detection module 03 is used to locate the internal defects of the target IGBT based on the total number of chips, the first normal gate discharge charge during the gate voltage drop phase, the first actual gate discharge charge, the second normal gate discharge charge during the Miller plateau phase, and the second actual gate discharge charge.

[0162] like Figure 7 As shown, in one embodiment, the detection module 02 includes:

[0163] The first detection unit 021 is used to detect whether the first normal gate discharge charge is greater than the first actual gate discharge charge. If so, the internal defects of the target IGBT, including gate-emitter circuit defects, are located.

[0164] The second detection unit 022 is used to detect whether the second normal gate discharge charge is greater than the second actual gate discharge charge. If so, the internal defects of the target IGBT, including gate circuit defects, are located.

[0165] In one embodiment, the IGBT defect location device based on the gate current during the turn-off process further includes:

[0166] The first chip quantity determination module is used to determine the number of chips in the target IGBT that have a gate-emitter circuit defect based on the first normal gate discharge charge, the first actual gate discharge charge, and the total number of chips.

[0167] In one embodiment, the IGBT defect location device based on the gate current during the turn-off process further includes:

[0168] The second chip quantity determination module is used to determine the number of chips in the target IGBT that have a collector-gate circuit defect based on the second normal gate discharge charge, the second actual gate discharge charge, and the total number of chips.

[0169] In one embodiment, the IGBT defect location device based on the gate current during the turn-off process further includes:

[0170] A gate defect determination module is used to determine that the defect type of the target IGBT is a gate defect if the internal defects of the target IGBT include gate-emitter circuit defects and collector-gate circuit defects.

[0171] In one embodiment, the IGBT defect location device based on the gate current during the turn-off process further includes:

[0172] An emitter defect determination module is used to determine that the defect type of the target IGBT is an emitter defect if the internal defects of the target IGBT include gate-emitter circuit defects but do not include collector-gate circuit defects.

[0173] In one embodiment, the IGBT defect location device based on the gate current during the turn-off process further includes:

[0174] The collector defect determination module is used to determine the defect type of the target IGBT as a collector defect if the internal defects of the target IGBT include collector-gate circuit defects but do not include gate-emitter circuit defects.

[0175] The embodiments of the IGBT defect location device based on the gate current during the turn-off process provided in this specification can be used to execute the processing flow of the embodiments of the IGBT defect location method based on the gate current during the turn-off process described above. Its functions will not be repeated here, but can be referred to the detailed description of the embodiments of the IGBT defect location method based on the gate current during the turn-off process described above.

[0176] Figure 8 This is a schematic diagram of the physical structure of an electronic device provided in an embodiment of the present invention, such as... Figure 8 As shown, the electronic device includes: a memory 801, a processor 802, and a computer program stored in the memory 801 and executable on the processor 802. When the processor 802 executes the computer program, it implements the following method:

[0177] The total number of chips in the target IGBT is obtained, the first normal gate current during the gate voltage drop phase, the first actual gate current, the second normal gate current during the Miller plateau phase, and the second actual gate current. The turn-off process includes the gate voltage drop phase and the Miller plateau phase.

[0178] Based on the first normal gate current during the gate voltage drop phase, the first actual gate current, the second normal gate current during the Miller plateau phase, and the second actual gate current, determine the first normal gate discharge charge, the first actual gate discharge charge, the second normal gate discharge charge, and the second actual gate discharge charge during the Miller plateau phase.

[0179] Based on the total number of chips, the first normal gate discharge charge during the gate voltage drop phase, the first actual gate discharge charge, the second normal gate discharge charge during the Miller plateau phase, and the second actual gate discharge charge, the internal defect location of the target IGBT is completed.

[0180] This embodiment provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the following method:

[0181] The total number of chips in the target IGBT is obtained, the first normal gate current during the gate voltage drop phase, the first actual gate current, the second normal gate current during the Miller plateau phase, and the second actual gate current. The turn-off process includes the gate voltage drop phase and the Miller plateau phase.

[0182] Based on the first normal gate current during the gate voltage drop phase, the first actual gate current, the second normal gate current during the Miller plateau phase, and the second actual gate current, determine the first normal gate discharge charge, the first actual gate discharge charge, the second normal gate discharge charge, and the second actual gate discharge charge during the Miller plateau phase.

[0183] Based on the total number of chips, the first normal gate discharge charge during the gate voltage drop phase, the first actual gate discharge charge, the second normal gate discharge charge during the Miller plateau phase, and the second actual gate discharge charge, the internal defect location of the target IGBT is completed.

[0184] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, systems, or computer program products. Therefore, the present invention can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0185] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0186] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0187] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0188] In the description of this specification, the references to terms such as "an embodiment," "a specific embodiment," "some embodiments," "for example," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0189] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above descriptions are merely specific embodiments of the present invention and are not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. An IGBT defect location method based on turn-off process gate current, characterized in that, The method comprises the following steps: acquiring the total number of chips of a target IGBT, a first normal gate current in a gate voltage drop stage, a first actual gate current, a second normal gate current in a Miller plateau stage, and a second actual gate current, wherein the turn-off process comprises the gate voltage drop stage and the Miller plateau stage; determining a first normal gate discharge charge amount, a first actual gate discharge charge amount, a second normal gate discharge charge amount, and a second actual gate discharge charge amount in the gate voltage drop stage according to the first normal gate current, the first actual gate current, the second normal gate current, and the second actual gate current in the gate voltage drop stage and the Miller plateau stage; completing internal defect positioning of the target IGBT according to the total number of chips, the first normal gate discharge charge amount, the first actual gate discharge charge amount, the second normal gate discharge charge amount, and the second actual gate discharge charge amount in the gate voltage drop stage and the Miller plateau stage; the step of completing internal defect positioning of the target IGBT according to the total number of chips, the first normal gate discharge charge amount, the first actual gate discharge charge amount, the second normal gate discharge charge amount, and the second actual gate discharge charge amount in the gate voltage drop stage and the Miller plateau stage comprises: detecting whether the first normal gate discharge charge amount is greater than the first actual gate discharge charge amount, and if yes, positioning the internal defect of the target IGBT as including a gate-emitter loop defect; detecting whether the second normal gate discharge charge amount is greater than the second actual gate discharge charge amount, and if yes, positioning the internal defect of the target IGBT as including a collector-gate loop defect.

2. The turn-off process gate current based IGBT defect localization method of claim 1, wherein, after the step of positioning the internal defect of the target IGBT as including a gate-emitter loop defect, the method further comprises: determining the number of chips of the target IGBT having a gate-emitter loop defect according to the first normal gate discharge charge amount, the first actual gate discharge charge amount, and the total number of chips.

3. The turn-off process gate current based IGBT defect localization method of claim 1, wherein, after the step of positioning the internal defect of the target IGBT as including a collector-gate loop defect, the method further comprises: determining the number of chips of the target IGBT having a collector-gate loop defect according to the second normal gate discharge charge amount, the second actual gate discharge charge amount, and the total number of chips.

4. The turn-off process gate current based IGBT defect localization method of claim 1, wherein, the method further comprises: if the internal defect of the target IGBT includes a gate-emitter loop defect and a collector-gate loop defect, determining the defect type of the target IGBT as a gate defect.

5. The turn-off process gate current based IGBT defect localization method of claim 1, wherein, the method further comprises: if the internal defect of the target IGBT includes a gate-emitter loop defect but does not include a collector-gate loop defect, determining the defect type of the target IGBT as an emitter defect.

6. The turn-off process gate current based IGBT defect localization method of claim 1, wherein, the method further comprises: if the internal defect of the target IGBT includes a collector-gate loop defect but does not include a gate-emitter loop defect, determining the defect type of the target IGBT as a collector defect.

7. An IGBT defect locating device based on turn-off process gate current, characterized in that, the method comprises the following steps: The acquisition module is configured to acquire a total number of chips of a target IGBT, a first normal gate current in a gate voltage falling stage, a first actual gate current, a second normal gate current in a Miller plateau stage, and a second actual gate current, and the turn-off process includes the gate voltage falling stage and the Miller plateau stage. The determination charge amount module is configured to determine a first normal gate discharge charge amount in the gate voltage falling stage, a first actual gate discharge charge amount, a second normal gate discharge charge amount in the Miller plateau stage, and a second actual gate discharge charge amount according to the first normal gate current, the first actual gate current, the second normal gate current, and the second actual gate current in the gate voltage falling stage and the Miller plateau stage. The detection module is configured to complete internal defect positioning of the target IGBT according to the total number of chips, the first normal gate discharge charge amount, the first actual gate discharge charge amount in the gate voltage falling stage, the second normal gate discharge charge amount, and the second actual gate discharge charge amount in the Miller plateau stage. The detection module includes: A first detection unit is configured to detect whether the first normal gate discharge charge amount is greater than the first actual gate discharge charge amount, and if yes, the internal defect positioning of the target IGBT includes gate-emitter loop defect. A second detection unit is configured to detect whether the second normal gate discharge charge amount is greater than the second actual gate discharge charge amount, and if yes, the internal defect positioning of the target IGBT includes collector-gate loop defect.

8. An electronic device comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, characterized in that, The processor executes the program to implement the IGBT defect positioning method based on gate current in a turn-off process according to any one of claims 1 to 6.

9. A computer readable storage medium having stored thereon computer instructions, wherein, The instructions are executed by the processor to implement the IGBT defect positioning method based on gate current in a turn-off process according to any one of claims 1 to 6.

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