Process level equipment debugging method and device, electronic equipment and storage medium

Abstract

The invention discloses a process level equipment debugging method and device, electronic equipment and a storage medium. The method comprises the steps of collecting a feedback signal generated by target process level equipment in a process of testing a target test item of the target process level equipment; performing signal segment segmentation on the feedback signal to obtain at least two feedback signal segments, and determining full-time-domain significant transfer aggregation representation vectors of the at least two feedback signal segments; and determining a debugging result of the target process layer equipment according to the full-time-domain significant transfer aggregation representation vector and a predetermined debugging result determination model. According to the technical scheme provided by the embodiment of the invention, the influence of human factors on the debugging result can be reduced, the accuracy and reliability of the debugging result are improved, and technical support is provided for safe and stable operation of a power system.

Description

Technical Field

[0001] The present invention relates to the field of intelligent substations, and in particular to a process layer equipment debugging method, device, electronic equipment and storage medium. Background Art

[0002] In the power system, the substation is an important part of the power grid, responsible for voltage conversion and power distribution. With the continuous expansion of the scale of the power system and the advancement of technology, the automation level of the substation is getting higher and higher, especially the secondary system is becoming more and more complex. The secondary system mainly includes relay protection devices, automation devices, communication equipment, etc. These devices work together to ensure the safe and stable operation of the primary system (main circuit system). In the secondary system, process layer equipment (such as circuit breakers, switches, transformers, mutual inductors, etc.) are directly connected to the electrical equipment of the primary system. Their status directly affects the safe operation of the power system. Therefore, the reliability and stability of these devices are crucial. The traditional manual debugging method is not only time-consuming and labor-intensive, but also in the process of manual debugging, any small operation error may lead to deviations in the debugging results. In addition, the experience, technical level and working status of the debugging personnel will affect the quality of debugging. Summary of the invention

[0003] The present invention provides a process layer equipment debugging method, device, electronic equipment and storage medium, which can reduce the impact of human factors on debugging results, improve the accuracy and reliability of debugging results, and provide technical support for the safe and stable operation of the power system.

[0004] According to one aspect of the present invention, a process layer device debugging method is provided. The method comprises:

[0005] In the process of testing the target test item of the target process layer device, collecting the feedback signal generated by the target process layer device;

[0006] Dividing the feedback signal into signal segments to obtain at least two feedback signal segments, and determining full-time domain significant transfer aggregate representation vectors of the at least two feedback signal segments;

[0007] The debugging result of the target process layer device is determined according to the full-time domain significant transfer aggregation representation vector and a predetermined debugging result determination model.

[0008] According to another aspect of the present invention, a process layer device debugging device is provided. The device comprises:

[0009] A feedback signal acquisition module, used for acquiring feedback signals generated by the target process layer device during the process of testing the target test item of the target process layer device;

[0010] a representation vector determination module, configured to segment the feedback signal into signal segments to obtain at least two feedback signal segments, and determine a full-time domain significant transfer aggregate representation vector of the at least two feedback signal segments;

[0011] The debugging result determination module is used to determine the debugging result of the target process layer device according to the full-time domain significant transfer aggregation representation vector and a predetermined debugging result determination model.

[0012] According to another aspect of the present invention, an electronic device is provided, the electronic device comprising:

[0013] at least one processor; and

[0014] a memory communicatively connected to the at least one processor; wherein,

[0015] The memory stores a computer program executable by the at least one processor, and the computer program is executed by the at least one processor so that the at least one processor can execute the process layer device debugging method described in any embodiment of the present invention.

[0016] According to another aspect of the present invention, a computer-readable storage medium is provided, wherein the computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a processor to implement the process layer device debugging method described in any embodiment of the present invention when executed.

[0017] The technical solution of the embodiment of the present invention, in the process of testing the target test item of the target process layer device, collects the feedback signal generated by the target process layer device; divides the feedback signal into signal segments to obtain at least two feedback signal segments, and determines the full-time domain significant transfer aggregation representation vector of the at least two feedback signal segments; determines the debugging result of the target process layer device according to the full-time domain significant transfer aggregation representation vector and a predetermined debugging result determination model. The technical solution of the embodiment of the present invention, by dividing the feedback signal obtained in the process of debugging the target process layer device based on the target test item, determines the full-time domain significant transfer aggregation representation vector that can represent the full-time domain information of the feedback signal segment obtained after the division, and determines the debugging result according to the full-time domain significant transfer aggregation representation vector and the debugging result determination model, can reduce the impact of human factors on the debugging result, improve the accuracy and reliability of the debugging result, and provide technical support for the safe and stable operation of the power system.

[0018] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0020] Figure 1 is a flowchart of a process layer device debugging method provided according to Embodiment 1 of the present invention;

[0021] Figure 2 is a flow chart of a process layer device debugging method provided according to Embodiment 2 of the present invention;

[0022] Figure 3 It is a structural schematic diagram of a process layer equipment debugging device provided according to Embodiment 3 of the present invention;

[0023] Figure 4 It is a structural schematic diagram of an electronic device for implementing the process layer device debugging method according to an embodiment of the present invention. DETAILED DESCRIPTION

[0024] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0025] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0026] Embodiment 1

[0027] Figure 1A flowchart of a process layer device debugging method is provided for the first embodiment of the present invention. This embodiment is applicable to the case of debugging process layer devices in a substation. The method can be executed by a process layer device debugging device. The process layer device debugging device can be implemented in the form of hardware and / or software. The process layer device debugging device can be configured in an electronic device. Figure 1 As shown, the method includes:

[0028] S110 . In the process of testing the target test item of the target process layer device, a feedback signal generated by the target process layer device is collected.

[0029] Among them, the target process layer equipment includes at least one of circuit breakers, knife switches, transformers, mutual inductors, sensors, actuators, communication equipment and time synchronization equipment. Circuit breakers are used to open or close circuits in power systems, and automatically cut off fault currents when lines or equipment fail, so as to protect the safe and stable operation of power systems. Knife switches are used to isolate power supplies, perform switching operations, and connect and disconnect low-current circuits. Mutual inductors are used to convert high voltage or high current into low voltage or low current to facilitate the access of measurement and protection equipment. Actuators are devices used to execute control commands in power systems, such as electric operating mechanisms, pneumatic operating mechanisms, etc. Communication equipment is equipment used to realize information transmission and exchange in power systems, such as Ethernet switches, fiber optic transceivers, etc. Time synchronization equipment is equipment used to realize time synchronization in power systems, such as GPS clocks, NTP servers, etc.

[0030] Among them, the target test items are a series of test tasks designed for the target process layer equipment, aiming to comprehensively evaluate the performance, function, reliability, safety, etc. of the target process layer equipment. Generally speaking, the target test items can be divided into functional test, performance test, compatibility test and safety test. Feedback signal refers to various information and data generated by the target process layer equipment in the process of executing the test task, such as voltage, current, frequency and temperature.

[0031] In the embodiment of the present invention, the target process layer device can be tested based on the target test item through the automated debugging device, and in the process of testing the target test item of the target process layer device, the feedback signal generated by the target process layer device when executing the test task in the target test item is collected through various sensors installed on the target process layer device, such as voltage sensors, temperature sensors, etc. It can be understood that the feedback signal can reflect the operating status, performance, abnormal conditions, etc. of the target process layer device. By collecting the feedback signal, the behavior data of the target process layer device under specific circumstances can be obtained, potential problems and improvement points can be found, and then the debugging result of the target process layer device can be obtained.

[0032] S120, dividing the feedback signal into signal segments to obtain at least two feedback signal segments, and determining full-time domain significant transfer aggregate representation vectors of the at least two feedback signal segments.

[0033] The full-time significant transfer aggregation representation vector refers to a higher quality feature representation obtained by dynamically propagating the feature time series of the corresponding time domain feature information in at least two feedback signal segments. The processing method of the dynamic propagation of the feature time series is to capture the trend of the time domain feature information of the feedback signal segment changing over time by combining principal component analysis and gradient attenuation mechanism, and use these trends for effective information propagation and aggregation.

[0034] In an embodiment of the present invention, the feedback signal may be first segmented into signal segments to obtain at least two feedback signal segments. By segmenting the feedback signal into signal segments, it is easier to perform time-frequency analysis on the feedback signal, such as short-time Fourier transform, wavelet transform, etc., to simultaneously capture the time and frequency information of the feedback signal. Afterwards, for each of the at least two feedback signal segments, the corresponding time domain feature information is determined. Finally, since the time domain feature information of each feedback signal segment in the at least two feedback signal segments is different, and different time domain feature information has different importance and contribution to the subsequent task of determining the debugging result of the target process layer device, therefore, in order to extract meaningful key feature information from the time domain feature information corresponding to the at least two feedback signal segments, and establish a connection between multiple time domain feature information, so as to better understand the behavior of the feedback signal and provide a basis for the subsequent task of determining the debugging result, in the technical solution of the present invention, it is necessary to further perform feature time series dynamic propagation on the at least two feedback signal segments to obtain the full time domain significant transfer aggregation representation of the at least two feedback signal segments.

[0035] S130, determining a model according to the full-time domain significant transfer aggregation representation vector and a predetermined debugging result, and determining a debugging result of a target process layer device.

[0036] Among them, the debugging result determines that the model is a classifier-based machine learning model. Common classifier-based machine learning models include logistic regression, decision tree, support vector machine, random forest, etc.

[0037] In an embodiment of the present invention, a classifier-based machine learning model can be pre-trained according to a training set composed of historical data to obtain a debugging result determination model, and then the debugging result of the target process layer device can be determined according to the full-time domain significant transfer aggregation representation vector and the predetermined debugging result determination model. Specifically, the full-time domain significant transfer aggregation representation vector can be input into the classifier-based debugging result determination model to obtain the debugging result of the target process layer device. By determining the debugging result of the target process layer device according to the full-time domain significant transfer aggregation representation vector and the predetermined performance evaluation model, the impact of human factors on the debugging result can be reduced, the accuracy and reliability of the debugging result can be ensured, and technical support can be provided for the safe and stable operation of the power system.

[0038] The technical solution of the embodiment of the present invention, in the process of testing the target test item of the target process layer device, collects the feedback signal generated by the target process layer device; divides the feedback signal into signal segments to obtain at least two feedback signal segments, and determines the full-time domain significant transfer aggregation representation vector of at least two feedback signal segments; determines the debugging result of the target process layer device according to the full-time domain significant transfer aggregation representation vector and a predetermined debugging result determination model. The technical solution of the embodiment of the present invention, by dividing the feedback signal obtained in the process of debugging the target process layer device based on the target test item, determines the full-time domain significant transfer aggregation representation vector that can represent the full-time domain information of the feedback signal segment obtained after the division, and determines the debugging result according to the full-time domain significant transfer aggregation representation vector and the debugging result determination model, can reduce the impact of human factors on the debugging result, improve the accuracy and reliability of the debugging result, and provide technical support for the safe and stable operation of the power system.

[0039] Embodiment 2

[0040] Figure 2 This is a flow chart of a process layer device debugging method provided by Embodiment 2 of the present invention. The embodiment of the present invention is optimized based on the above embodiment. For solutions not described in detail in the embodiment of the present invention, please refer to the above embodiment. Figure 2 As shown, the method includes:

[0041] S210: Determine a target test item for a target process layer device, and control an automated debugging device connected to the target process layer device to generate a test signal corresponding to the target test item.

[0042] In the embodiment of the present invention, before testing the target test item for the target process layer device, it is necessary to first connect the automated debugging device to the target process layer device through the quick connection plug of the automated debugging device, and then the automated debugging device generates a test signal corresponding to the target test item based on the target test item, so as to test the target process layer device through the generated test signal. Compared with the traditional manual debugging test process, the test efficiency can be improved by generating the test signal through the automated debugging device.

[0043] Optionally, a target test item for the target process layer device is determined, and an automated debugging device connected to the target process layer device is controlled to generate a test signal corresponding to the target test item, including: determining the device type and characteristic parameters of the target process layer device according to information in a standard debugging case library, and determining the target test item for the target process layer device according to the device type and the characteristic parameters; based on the target test item, controlling an analog terminal of the automated debugging device connected to the target process layer device to generate a test signal corresponding to the target test item.

[0044] The standard debugging case library includes standard test cases for all process layer devices in the substation, and the standard test cases include device types and characteristic parameters corresponding to the process layer devices.

[0045] In an embodiment of the present invention, the device type and characteristic parameters of the target process layer device can be determined based on the information in the standard debugging case library. Specifically, the device identification of the target process layer device can be matched with the information in the standard debugging case library to determine the device type and characteristic parameters of the target process layer device. After that, the target test items for the target process layer device are determined based on the device type and characteristic parameters of the target process layer device. It can be understood that by using the information in the standard debugging case library to determine the target test items for the target process layer device, it can be ensured that different debuggers perform consistent debugging steps on the same process layer device, reducing the differences caused by human factors. After determining the target test items for the target process layer device, the analog terminals of the automated debugging device connected to the target process layer device can be controlled to generate test signals corresponding to the target test items.

[0046] S220 , feeding back the test signal to the target process layer device to test the target process layer device, and collecting a feedback signal generated by the target process layer device after receiving the test signal.

[0047] In an embodiment of the present invention, after generating a test signal corresponding to a target test item, the test signal can be fed back to a target process layer device to test the target process layer device. At the same time, by collecting a feedback signal generated by the target process layer device after receiving the test signal, it is possible to verify whether the target process layer device responds normally to the test signal, that is, to verify whether the various functions of the target process layer device are working normally, and also to provide data support for determining subsequent debugging results.

[0048] S230: Divide the feedback signal into signal segments to obtain at least two feedback signal segments.

[0049] In the embodiment of the present invention, the feedback signal may be segmented into signal segments to obtain at least two feedback signal segments. By segmenting the feedback signal into signal segments, it is easier to perform time-frequency analysis on the feedback signal, such as short-time Fourier transform, wavelet transform, etc., to simultaneously capture the time and frequency information of the feedback signal.

[0050] S240. Determine a feedback signal segment sequence based on at least two feedback signal segments, and determine a time domain coding feature vector sequence corresponding to the feedback signal segment sequence.

[0051] Among them, the feedback signal segment sequence is obtained by arranging at least two feedback signal segments in chronological order, the time domain coding feature vector sequence is obtained by arranging the time domain coding feature vectors extracted from at least two feedback signal segments in chronological order, and the time domain feature coding vector is a vector representation of the time domain feature information extracted from the vector.

[0052] In the embodiment of the present invention, a feedback signal segment sequence can be first determined based on at least two feedback signal segments, and then a time domain coding feature vector sequence can be obtained based on the determined feedback signal sequence. It can be understood that the feedback signal segments in the feedback signal segment sequence and the time domain coding feature vectors in the time domain coding feature vector sequence are in a one-to-one correspondence.

[0053] Optionally, determining a time domain coding feature vector sequence corresponding to the feedback signal segment sequence includes: extracting local time domain features of each feedback signal segment in the feedback signal segment sequence through a predetermined feature extraction model to obtain at least two local time domain feature information corresponding to the at least two feedback signal segments; determining at least two time domain coding feature vectors corresponding to the at least two local time domain feature information, and determining a time domain coding feature vector sequence corresponding to the feedback signal segment sequence based on the at least two time domain coding feature vectors.

[0054] In an embodiment of the present invention, feature mining can be performed on the local time domain features of each feedback signal segment in the feedback signal segment sequence through a feature extraction model based on the 1D-CNN model to obtain the local time domain feature information of each feedback signal segment. After that, the time domain coding feature vector corresponding to the local time domain feature information of each feedback signal segment can be determined, and the time domain coding feature vector sequence corresponding to the feedback signal segment sequence can be determined based on the at least two determined time domain coding feature vectors.

[0055] S250, performing feature time series dynamic propagation on the time domain coding feature vector sequence to obtain full time domain significant transfer aggregate representation vectors of at least two feedback signal segments.

[0056] In an embodiment of the present invention, the time domain coded feature vector sequence can be dynamically propagated in feature time series to generate a full time domain significant transfer aggregation representation vector that can reflect the dynamic changes of the time domain feature information of the feedback signal in the time series, which is used to determine the debugging results of the target process layer equipment.

[0057] Optionally, the time-domain coding feature vector sequence is subjected to feature time series dynamic propagation to obtain a full-time-domain significant transfer aggregate representation vector of the at least two feedback signal segments, including: for the time-domain coding feature vectors in the time-domain coding feature vector sequence, principal component extraction is performed on the current time-domain coding feature vector to obtain a current principal component representation; other time-domain coding feature vectors in the time-domain coding feature vector sequence except the current time-domain coding feature vector are used as reference time-domain coding feature vectors; principal component extraction is performed on each reference time-domain coding feature vector to obtain a reference principal component representation of the reference time-domain coding feature vector; and time-series attenuation dynamic aggregation is performed on the current principal component representation and the reference principal component representation to obtain a full-time-domain significant transfer aggregate representation vector of the at least two feedback signal segments.

[0058] Among them, principal component extraction is a commonly used data dimensionality reduction technique that can identify the main change directions in the data set and convert these directions into new orthogonal feature vectors, namely principal components. Through principal component extraction, noise can be removed and important information features can be highlighted. Time series decay dynamic aggregation is a powerful time series data analysis technology that combines the two key elements of time decay and dynamic aggregation to more effectively extract key features and information from the data.

[0059] In an embodiment of the present invention, for a time domain coding feature vector in a time domain coding feature vector sequence, a time domain coding feature vector at any time node is selected as the current time domain coding feature vector, and principal component extraction is performed on the current time domain coding feature vector to obtain a current principal component representation vector as the current principal component representation. Afterwards, other time domain coding feature vectors in the time domain coding feature vector sequence except the current time domain coding feature vector are used as reference time domain coding feature vectors, and principal component extraction is performed on each reference time domain coding feature vector to obtain a reference principal component representation vector of each reference time domain coding feature vector as a reference principal component representation. Finally, the current principal component representation vector and the reference principal component representation vector are dynamically aggregated with time series attenuation to obtain a full time domain significant transfer aggregate representation vector of at least two feedback signal segments.

[0060] Optionally, the specific process of performing time-series decay dynamic aggregation on the current principal component representation vector and the reference principal component representation vector is as follows:

[0061] The first step is to calculate the absolute factors of the time series propagation attenuation entropy of each reference principal component representation vector relative to the current principal component representation vector, and obtain a sequence of absolute factors of the time series propagation attenuation entropy. By calculating the absolute factors of the time series propagation attenuation entropy, the uncertainty of the random variable can be quantified, and the trend of the time domain coding feature vector of the feedback signal segment evolving over time and the information loss can be captured.

[0062] In the second step, based on the time span between each reference principal component representation vector and the current principal component representation vector, each time-series propagation attenuation entropy absolute factor in the time-series propagation attenuation entropy absolute factor sequence is modulated in the time dimension to obtain a time-series span modulated propagation attenuation entropy factor sequence. Here, in order to further enhance the model's ability to understand the transmission of the time-domain coding feature vector of the feedback signal fragment under long time intervals, the time-series span modulated propagation attenuation entropy factor is introduced to form a time-series span modulated propagation attenuation entropy factor sequence. This adjustment enables the model to handle the relationship between long and short-term memories more reasonably, ensuring that even large differences in the time-domain coding feature vectors between feedback signal fragments that are far apart are considered to be changes within the normal range.

[0063] In the third step, the sequence of time-span modulated propagation attenuation entropy factors is input into the information transfer screening module based on the gating function to obtain the sequence of time-span modulated propagation attenuation weights. By inputting the sequence modulated in the time dimension into an information transfer screening module using a gating mechanism, it is possible to adaptively determine which time-domain coding feature vectors of the feedback signal segments should continue to be calculated according to the context, thereby identifying the most influential propagation path and assigning the corresponding weight accordingly.

[0064] The fourth step is to calculate the weighted sum of each reference principal component representation vector based on the time span modulation propagation attenuation weight sequence to obtain the reference principal component significant transfer aggregation representation vector. This process effectively integrates the long-term trend and short-term fluctuation in the time domain coding feature vector of the feedback signal, providing a solid foundation for the final full time domain information transfer aggregation representation.

[0065] The fifth step is to calculate the positional sum of the reference principal component significant transfer aggregation representation vector and the current principal component representation vector to obtain the full-time domain significant transfer aggregation representation vector. The full-time domain significant transfer aggregation representation vector not only reflects the state of the target process layer device at the current time point, but also includes the historical trend of the target process layer device state over time. This comprehensively reflects the feedback signal and the state transition of the target process layer device within a given time period, which is very helpful for understanding the behavior of the target process layer device.

[0066] Optionally, the process of determining the absolute factor sequence of time series propagation attenuation entropy is as follows: the first step is to calculate the positional division of each reference principal component representation vector relative to the corresponding position of the current principal component representation vector to obtain the time domain coding feature principal component attenuation vector; the second step is to calculate the logarithmic function value with base two of the absolute value of each eigenvalue of the time domain coding feature principal component attenuation vector to obtain the time domain coding feature principal component attenuation logarithmic vector; the third step is to calculate the positional dot product of each reference principal component representation vector and the time domain coding feature principal component attenuation logarithmic vector, and then perform positional dot addition on each positional eigenvalue in the obtained dot product vector to obtain the time series propagation attenuation value; the fourth step is to calculate an exponential function with the natural constant e as the base and the time series propagation attenuation value as the exponent to obtain the absolute factor sequence of time series propagation attenuation entropy.

[0067] Optionally, the process of determining the sequence of time span modulated propagation attenuation entropy factors is as follows: the first step is to subtract the timestamp of the current principal component representation vector from the timestamp of each reference principal component representation vector and round down the result to obtain the time span value; the second step is to calculate an exponential function with the natural constant e as the base and the time span value as the exponent to obtain the time span modulation value; the third step is to divide the absolute factors of the time span modulated propagation attenuation entropy corresponding to each reference principal component representation vector by the time span modulation value to obtain the sequence of time span modulated propagation attenuation entropy factors.

[0068] Optionally, the process of determining the sequence of timing span modulation propagation attenuation weights is as follows: comparing each timing span modulation propagation attenuation entropy factor in the timing span modulation propagation attenuation entropy factor sequence with a predetermined threshold to obtain a sequence of timing span modulation propagation attenuation weights; wherein, if the timing span modulation propagation attenuation entropy factor is greater than the predetermined threshold, the timing span modulation propagation attenuation entropy factor greater than the predetermined threshold is input into the sigmoid function; if the timing span modulation propagation attenuation entropy factor is less than or equal to the predetermined threshold, the timing span modulation propagation attenuation entropy factor less than or equal to the predetermined threshold is set to zero.

[0069] Optionally, the relevant formula used in step S250 is as follows:

[0070] X={x1,x2,...,x i , ..., x p};

[0071] v i = PCA(x i );

[0072]

[0073] V = {v1, v2, ..., v i , ..., v p};

[0074]

[0075] Where X is the time domain coding feature vector sequence, x1, x2, ..., x i , ..., x p are the 1st, 2nd, ..., ith, ..., pth time-domain coded feature vectors in the time-domain coded feature vector sequence, pCA(x i ) is x i Perform principal component extraction based on eigenvalues, v i For x i The corresponding principal component representation vector, x i T For x i The transposed vector of n is the number of eigenvalues ​​in the time domain coding feature vector, C i is the covariance matrix corresponding to x, U i is x i The corresponding principal component orthogonal matrix, U i T For U i The transposed matrix, v i1 , v i2 , ..., v im For each principal component vector in the sequence of principal component vectors, Λi For x i The corresponding diagonal matrix, diag(λ i1 ,λ i2 , ..., λ im ) is the matrix whose diagonal elements are λ i1 ,λ i2 , ..., λ im The diagonal matrix of i1 ,λ i2 , ..., λ im are the weight values ​​of each principal component vector, arg max k (·) is the k value corresponding to the maximum value returned, j is the maximum approximate matching value, and V is the sequence of principal component representation vectors, v1, v2, ..., v i , ..., v p are the 1st, 2nd, ..., th, ..., pth principal component representation vectors in the sequence of principal component representation vectors, v is v i The eigenvalues ​​at each position in the ps v p The eigenvalues ​​of each position in, L is v i The number of eigenvalues ​​in the equation, log represents the logarithmic function value with base 2, exp(·) represents the exponential function with the natural constant e as the base, d i v i and v p The absolute factor of the temporal propagation attenuation entropy between p and t i Respectively represent the timestamps of the pth and ith principal component representation vectors, For floor rounding operation, e (i→p) Yes i and v p The time span between them modulates the propagation attenuation entropy factor, mask(·) is the masking process, sigmoid(·) is the sigmoid function, θ is the predetermined threshold, and w i is the time span modulation propagation attenuation weight, p is the number of principal component representation vectors, V p+1 is the aggregate representation vector of the full-time saliency transfer.

[0076] S260, determining a model according to the full-time domain significant transfer aggregation representation vector and a predetermined debugging result, and determining a debugging result of a target process layer device.

[0077] The technical solution of the embodiment of the present invention determines a target test item for a target process layer device, and controls an automated debugging device connected to the target process layer device to generate a test signal corresponding to the target test item; feeds back the test signal to the target process layer device to test the target process layer device, and collects a feedback signal generated by the target process layer device after receiving the test signal; divides the feedback signal into signal segments to obtain at least two feedback signal segments; determines a feedback signal segment sequence based on the at least two feedback signal segments, and determines a time domain coding feature vector sequence corresponding to the feedback signal segment sequence; performs feature time sequence dynamic propagation on the time domain coding feature vector sequence to obtain a full time domain significant transfer aggregate representation vector of at least two feedback signal segments; and determines a debugging result of the target process layer device according to the full time domain significant transfer aggregate representation vector and a predetermined debugging result determination model. The technical solution of the embodiment of the present invention tests the target process layer equipment by generating a test signal, and segments the obtained feedback signal to determine the full-time domain significant transfer aggregation representation vector that can represent the full-time domain information of the feedback signal segment after the segmentation, and then determines the debugging result based on the full-time domain significant transfer aggregation representation vector and the debugging result determination model. This can realize an automated closed-loop process for debugging the target process layer equipment, reduce the risks in the testing process, reduce the impact of human factors on the debugging results, improve the accuracy and reliability of the debugging results, and provide technical support for the safe and stable operation of the power system.

[0078] Embodiment 3

[0079] Figure 3 This is a schematic diagram of the structure of a process layer device debugging device provided by the third embodiment of the present invention. Figure 3 As shown, the device comprises:

[0080] The feedback signal acquisition module 310 is used to acquire the feedback signal generated by the target process layer device during the process of testing the target test item of the target process layer device;

[0081] A representation vector determination module 320, configured to segment the feedback signal into signal segments to obtain at least two feedback signal segments, and determine a full-time domain significant transfer aggregate representation vector of the at least two feedback signal segments;

[0082] The debugging result determination module 330 is used to determine the debugging result of the target process layer device according to the full-time domain significant transfer aggregation representation vector and a predetermined debugging result determination model.

[0083] Optionally, the feedback signal acquisition module 310 includes:

[0084] A test signal generating unit, used to determine a target test item for the target process layer device, and control an automated debugging device connected to the target process layer device to generate a test signal corresponding to the target test item;

[0085] The feedback signal acquisition unit is used to feed back the test signal to the target process layer device to test the target process layer device, and to acquire a feedback signal generated by the target process layer device after receiving the test signal.

[0086] Optionally, the test signal generating unit includes:

[0087] A target test item determination subunit is used to determine the device type and characteristic parameters of the target process layer device according to the information in the standard debugging case library, and determine the target test items for the target process layer device according to the device type and the characteristic parameters;

[0088] The test signal generating subunit is used to control the analog terminal of the automatic debugging equipment connected to the target process layer equipment to generate the test signal corresponding to the target test item based on the target test item.

[0089] Optionally, the representation vector determination module 320 includes:

[0090] a vector sequence determining unit, configured to determine a feedback signal segment sequence based on the at least two feedback signal segments, and determine a time domain coding feature vector sequence corresponding to the feedback signal segment sequence;

[0091] The representation vector determination unit is used to perform feature time sequence dynamic propagation on the time domain coding feature vector sequence to obtain the full time domain significant transfer aggregation representation vector of the at least two feedback signal segments.

[0092] Optionally, the vector sequence determining unit includes:

[0093] a feature information determination subunit, configured to extract the local time domain features of each feedback signal segment in the feedback signal segment sequence by using a predetermined feature extraction model, to obtain at least two local time domain feature information corresponding to the at least two feedback signal segments;

[0094] The vector sequence determination subunit is used to determine at least two time domain coding feature vectors corresponding to the at least two local time domain feature information, and determine the time domain coding feature vector sequence corresponding to the feedback signal segment sequence based on the at least two time domain coding feature vectors.

[0095] Optionally, the representation vector determining unit includes:

[0096] A current principal component representation determination subunit is used to extract the principal component of the current time-domain coding feature vector in the time-domain coding feature vector sequence to obtain the current principal component representation;

[0097] A reference feature vector determination subunit, configured to use other time domain coding feature vectors in the time domain coding feature vector sequence except the current time domain coding feature vector as reference time domain coding feature vectors;

[0098] A reference principal component representation determination subunit is used to extract principal components for each reference time-domain coding feature vector to obtain a reference principal component representation of the reference time-domain coding feature vector;

[0099] The representation vector determination subunit is used to perform time-series attenuation dynamic aggregation on the current principal component representation and the reference principal component representation to obtain a full-time domain significant transfer aggregated representation vector of the at least two feedback signal segments.

[0100] Optionally, the target process layer device includes at least one of a circuit breaker, a switch, a transformer, a mutual inductor, a sensor, an actuator, a communication device and a time synchronization device.

[0101] The process layer device debugging apparatus provided in the embodiment of the present invention can execute the process layer device debugging method provided in any embodiment of the present invention, and has the corresponding functional modules and beneficial effects of the execution method.

[0102] Embodiment 4

[0103] Figure 4 A schematic diagram of the structure of an electronic device 10 that can be used to implement an embodiment of the present invention is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processing, cellular phones, smart phones, wearable devices (such as helmets, glasses, watches, etc.) and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the present invention described and / or required herein.

[0104] like Figure 4As shown, the electronic device 10 includes at least one processor 11, and a memory connected to the at least one processor 11, such as a read-only memory (ROM) 12, a random access memory (RAM) 13, etc., wherein the memory stores a computer program that can be executed by at least one processor, and the processor 11 can perform various appropriate actions and processes according to the computer program stored in the read-only memory (ROM) 12 or the computer program loaded from the storage unit 18 to the random access memory (RAM) 13. In the RAM 13, various programs and data required for the operation of the electronic device 10 can also be stored. The processor 11, the ROM 12, and the RAM 13 are connected to each other through a bus 14. An input / output (I / O) interface 15 is also connected to the bus 14.

[0105] A number of components in the electronic device 10 are connected to the I / O interface 15, including: an input unit 16, such as a keyboard, a mouse, etc.; an output unit 17, such as various types of displays, speakers, etc.; a storage unit 18, such as a disk, an optical disk, etc.; and a communication unit 19, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 19 allows the electronic device 10 to exchange information / data with other devices through a computer network such as the Internet and / or various telecommunication networks.

[0106] The processor 11 may be a variety of general and / or special processing components with processing and computing capabilities. Some examples of the processor 11 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, a digital signal processor (DSP), and any appropriate processor, controller, microcontroller, etc. The processor 11 executes the various methods and processes described above, such as a process layer device debugging method.

[0107] In some embodiments, the process layer device debugging method can be implemented as a computer program, which is tangibly contained in a computer-readable storage medium, such as a storage unit 18. In some embodiments, part or all of the computer program can be loaded and / or installed on the electronic device 10 via the ROM 12 and / or the communication unit 19. When the computer program is loaded into the RAM 13 and executed by the processor 11, one or more steps of the process layer device debugging method described above can be performed. Alternatively, in other embodiments, the processor 11 can be configured to execute the process layer device debugging method in any other appropriate manner (for example, by means of firmware).

[0108] Various implementations of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chips (SOCs), load programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various implementations can include: being implemented in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which can be a special purpose or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

[0109] Computer programs for implementing the methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, so that when the computer program is executed by the processor, the functions / operations specified in the flow chart and / or block diagram are implemented. The computer program may be executed entirely on the machine, partially on the machine, partially on the machine and partially on a remote machine as a stand-alone software package, or entirely on a remote machine or server.

[0110] In the context of the present invention, a computer-readable storage medium may be a tangible medium that may contain or store a computer program for use by or in combination with an instruction execution system, device or equipment. A computer-readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices or equipment, or any suitable combination of the foregoing. Alternatively, a computer-readable storage medium may be a machine-readable signal medium. A more specific example of a machine-readable storage medium may include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0111] To provide interaction with a user, the systems and techniques described herein may be implemented on an electronic device having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and a pointing device (e.g., a mouse or trackball) through which the user can provide input to the electronic device. Other types of devices may also be used to provide interaction with the user; for example, the feedback provided to the user may be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user may be received in any form (including acoustic input, voice input, or tactile input).

[0112] The systems and techniques described herein may be implemented in a computing system that includes backend components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes frontend components (e.g., a user computer with a graphical user interface or a web browser through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such backend components, middleware components, or frontend components. The components of the system may be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: a local area network (LAN), a wide area network (WAN), a blockchain network, and the Internet.

[0113] A computing system may include a client and a server. The client and the server are generally remote from each other and usually interact through a communication network. The client and server relationship is generated by computer programs running on the corresponding computers and having a client-server relationship with each other. The server may be a cloud server, also known as a cloud computing server or cloud host, which is a host product in the cloud computing service system to solve the defects of difficult management and weak business scalability in traditional physical hosts and VPS services.

[0114] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0115] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A process layer device debugging method, characterized in that: The method comprises: In the process of testing the target test item of the target process layer device, collecting the feedback signal generated by the target process layer device; Dividing the feedback signal into signal segments to obtain at least two feedback signal segments, and determining full-time domain significant transfer aggregate representation vectors of the at least two feedback signal segments; The debugging result of the target process layer device is determined according to the full-time domain significant transfer aggregation representation vector and a predetermined debugging result determination model.

2. The method according to claim 1, characterized in that In the process of testing a target test item for a target process layer device, collecting a feedback signal generated by the target process layer device includes: Determine a target test item for the target process layer device, and control an automated debugging device connected to the target process layer device to generate a test signal corresponding to the target test item; The test signal is fed back to the target process layer device to test the target process layer device, and a feedback signal generated by the target process layer device after receiving the test signal is collected.

3. The method according to claim 2, characterized in that Determining a target test item for the target process layer device, and controlling an automated debugging device connected to the target process layer device to generate a test signal corresponding to the target test item, including: Determine the device type and characteristic parameters of the target process layer device according to the information in the standard debugging case library, and determine the target test items for the target process layer device according to the device type and the characteristic parameters; Based on the target test item, an analog terminal of an automation debugging device connected to the target process layer device is controlled to generate a test signal corresponding to the target test item.

4. The method according to claim 1, characterized in that Determining the full-time domain significant transfer aggregate representation vector of the at least two feedback signal segments comprises: Determine a feedback signal segment sequence based on the at least two feedback signal segments, and determine a time domain coding feature vector sequence corresponding to the feedback signal segment sequence; The time-domain coded feature vector sequence is subjected to feature time-series dynamic propagation to obtain a full-time-domain significant transfer aggregate representation vector of the at least two feedback signal segments.

5. The method according to claim 4, characterized in that Determining a time domain coding feature vector sequence corresponding to the feedback signal segment sequence includes: Extracting the local time domain features of each feedback signal segment in the feedback signal segment sequence by using a predetermined feature extraction model to obtain at least two local time domain feature information corresponding to the at least two feedback signal segments; At least two time domain coding feature vectors corresponding to the at least two local time domain feature information are determined, and a time domain coding feature vector sequence corresponding to the feedback signal segment sequence is determined based on the at least two time domain coding feature vectors.

6. The method according to claim 4, characterized in that Performing feature time sequence dynamic propagation on the time domain coded feature vector sequence to obtain a full time domain significant transfer aggregate representation vector of the at least two feedback signal segments, including: For the time domain coding feature vector in the time domain coding feature vector sequence, performing principal component extraction on the current time domain coding feature vector to obtain a current principal component representation; Taking other time domain coding feature vectors in the time domain coding feature vector sequence except the current time domain coding feature vector as reference time domain coding feature vectors; Performing principal component extraction on each reference time-domain coding feature vector to obtain a reference principal component representation of the reference time-domain coding feature vector; The current principal component representation and the reference principal component representation are dynamically aggregated in a time-series decay manner to obtain a full-time domain significant transfer aggregate representation vector of the at least two feedback signal segments.

7. The method according to claim 1, characterized in that The target process layer equipment includes at least one of a circuit breaker, a switch, a transformer, a mutual inductor, a sensor, an actuator, a communication device and a time synchronization device.

8. A process layer equipment debugging device, characterized in that: The device comprises: A feedback signal acquisition module, used for acquiring feedback signals generated by the target process layer device during the process of testing the target test item of the target process layer device; a representation vector determination module, configured to segment the feedback signal into signal segments to obtain at least two feedback signal segments, and determine a full-time domain significant transfer aggregate representation vector of the at least two feedback signal segments; The debugging result determination module is used to determine the debugging result of the target process layer device according to the full-time domain significant transfer aggregation representation vector and a predetermined debugging result determination model.

9. An electronic device, characterized in that: The electronic device comprises: at least one processor; and a memory communicatively connected to the at least one processor; wherein, The memory stores a computer program executable by the at least one processor, and the computer program is executed by the at least one processor so that the at least one processor can execute the process-layer device debugging method according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a processor to implement the process-layer device debugging method according to any one of claims 1 to 7 when executed.

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