LDO circuit, chip and electronic device

Abstract

The embodiment of the present application provides a kind of LDO circuit, chip and electronic equipment, belong to analog chip technical field.The LDO circuit includes: input circuit, access reference current, and at least by main transistor to corresponding output reference voltage;Amplification circuit, which accesses reference voltage and amplifies;And feedback circuit, one end is connected to the output end of the amplification circuit through transistor pair, and the other end is fed back to the amplification circuit voltage and as the output end of the LDO circuit.Wherein, the main transistor and the transistor pair are all worked in sub-threshold region, and the amplification factor of the amplification circuit is configured so that the current flowing through the main transistor and the transistor pair is equal.The LDO circuit of the embodiment of the present application utilizes the transistor in sub-threshold region, and cooperates with the amplification factor of amplification circuit, generates the voltage that can be determined for LDO circuit output, does not need reference circuit, and circuit is simple and low in power consumption.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of analog chip, in particular to an LDO circuit, a chip and an electronic device. BACKGROUND

[0002] LDO (Low Drop-Out Regulator) can provide clean and stable power supply in the circuit to ensure that the elements and devices in the circuit can work normally, and reduce the influence of power supply noise and fluctuation on the performance of the circuit. As shown in the figure, the traditional LDO circuit is composed of reference circuit, error amplifier, power tube, feedback network and the like, and its working process is as follows: the circuit detects the output voltage from the resistance feedback network, compares it with the reference voltage provided by the bandgap reference, and then amplifies the difference signal after comparison by the error amplifier, and transmits it to the power tube for linear adjustment, so that the output voltage and the reference voltage input maintain a corresponding ratio unchanged, and a stable voltage output is generated. Figure 1

[0003] However, the present inventors found in the process of implementing the present application that the traditional LDO circuit needs modules with high complexity and power consumption such as reference circuit and error amplifier, and when applied in a specific system, it is necessary to ensure that the MOS tube works in the saturation region, which further increases the power consumption of the circuit, making the system implementation cost higher.

[0004] Therefore, the present application aims to propose a new design for LDO circuit. SUMMARY

[0005] The purpose of the embodiments of the present application is to provide an LDO circuit, a chip and an electronic device, which are used to at least partially solve the above technical problems.

[0006] In order to achieve the above-mentioned purpose, the embodiments of the present application provide an LDO circuit, comprising: an input circuit comprising a main transistor, the input circuit being connected to a reference current and outputting a reference voltage through at least the main transistor; an amplification circuit connected to the reference voltage and amplifying the reference voltage; and a feedback circuit comprising a transistor pair, one end of the feedback circuit being connected to an output end of the amplification circuit through the transistor pair, and the other end of the feedback circuit feeding back a voltage to the amplification circuit and serving as an output end of the LDO circuit. Wherein, the main transistor and the transistor pair both work in the sub-threshold region, and the amplification factor of the amplification circuit is configured to make the current flowing through the main transistor and the transistor pair equal.

[0007] ​Optionally, the input circuit comprises: a twelfth transistor M12, whose drain and gate are connected and accessed by a first bias current BIAS1; an eleventh transistor as the main transistor, whose drain and gate are connected and connected to the source of the twelfth transistor M12; and a tenth transistor M10, whose drain and gate are connected and accessed by a second bias current BIAS2, and whose source is connected to the source of the eleventh transistor M11 and grounded. Wherein the gate of the twelfth transistor M12 and the gate of the tenth transistor M10 are respectively used to output a reference voltage.

[0008] Optionally, the amplification circuit comprises: a common-gate eighth transistor M8 and a common-gate ninth transistor M9, and the sources of both are grounded, and the gates are accessed by a reference voltage; a common-gate fourth transistor M4 and a common-gate seventh transistor M7, and the gates of both are accessed by another reference voltage, wherein the source of the fourth transistor M4 is connected to the drain of the eighth transistor M8 and serves as the output terminal of the amplification circuit, and the source of the seventh transistor M7 is connected to the drain of the ninth transistor M9; and a common-gate fifth transistor M5 and a common-gate sixth transistor M6, and the sources of both are accessed by a working voltage, wherein the drain of the fifth transistor M5 is connected to the drain of the fourth transistor M4, and the drain of the sixth transistor M6 is connected to the drain of the seventh transistor M7, and the gate of the sixth transistor M6 is also connected to its drain.

[0009] Optionally, the amplification circuit further comprises: a fourteenth transistor M14, whose gate and drain are connected and connected to the drain of the eighth transistor M8; and a thirteenth transistor M13, whose gate and drain are connected and connected to the source of the fourteenth transistor M14.

[0010] Optionally, the feedback circuit comprises: a second transistor M2 and a third transistor M3 forming the transistor pair, wherein the drain and gate of each of the second transistor M2 and the third transistor M3 are connected and connected to each other, the source of the second transistor M2 serves as the output terminal of the LDO circuit, and the source of the third transistor M3 is connected to the output terminal of the amplification circuit; and a first transistor M1, whose drain is connected to the source of the second transistor M2, whose source is accessed by a working voltage, and whose gate is connected to the amplification circuit with a feedback voltage.

[0011] Optionally, the feedback circuit further comprises: a PMOS transistor M0, whose gate is accessed by a preset bias current, whose source is connected to the source of the second transistor M2, and whose drain is grounded.

[0012] Optionally, the feedback circuit further comprises a fifteenth transistor M15 having its drain and gate connected to the gate of the first transistor M1, and a sixteenth transistor M16 having its drain and gate connected to the source of the fifteenth transistor M15, and its source connected to a working voltage.

[0013] Optionally, the LDO circuit further comprises a compensation circuit arranged on a feedback loop in which the feedback circuit feeds back the voltage to the amplification circuit, for realizing frequency compensation for the LDO circuit.

[0014] In another aspect, the embodiments of the present application further provide a chip integrated with any of the above LDO circuits.

[0015] In another aspect, the embodiments of the present application further provide an electronic device comprising any of the above chips.

[0016] Through the above technical solutions, the LDO circuit of the embodiments of the present application utilizes one main transistor and a group of transistor pairs in the sub-threshold region, and cooperates with the amplification factor of the amplification circuit, to generate a voltage for the LDO circuit to determine the output, so that the reference circuit can be avoided, the circuit is simple, and the power consumption is low.

[0017] Other features and advantages of the embodiments of the present application will be described in detail in the following specific implementation part. BRIEF DESCRIPTION OF DRAWINGS

[0018] The accompanying drawings are included to provide a further understanding of the embodiments of the present application, and constitute a part of the specification, and are used together with the following specific implementation part to explain the embodiments of the present application, but do not constitute a limitation to the embodiments of the present application. In the drawings:

[0019] Figure 1 is a structural schematic diagram of a conventional LDO circuit;

[0020] Figure 2 is a structural schematic diagram of an LDO circuit of the embodiments of the present application; and

[0021] Figure 3 is a structural schematic diagram of an example design of the LDO circuit of the embodiments of the present application.

[0022] EXPLANATION OF REFERENCE NUMERALS

[0023] 100, input circuit; 200, amplification circuit; 300, feedback circuit; 400, compensation circuit. DETAILED DESCRIPTION

[0024] The specific embodiments of the present application will be described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are merely intended to illustrate and explain the present application, and are not intended to limit the present application.

[0025] It should be noted that the "connection" and "access" involved in the embodiments of the present application mainly refer to "electrical connection", which is used to describe the signal connection between two components, for example, through a circuit connection, and the "connection" and "access" involved can be a direct electrical connection between two components, or an indirect electrical connection through other components or circuits.

[0026] Figure 2 is a structural schematic diagram of the LDO circuit of the embodiments of the present application. As shown in Figure 2 the LDO circuit includes an input circuit 100 including a main transistor, the input circuit 100 accessing a reference current and outputting a reference voltage through at least the main transistor, an amplification circuit 200 accessing the reference voltage and performing amplification, and a feedback circuit 300 including a transistor pair, one end of the feedback circuit 300 being connected to the output end of the amplification circuit through the transistor pair, and the other end feeding back a voltage to the amplification circuit 200 and serving as the output end of the LDO circuit. Among them, the main transistor and the transistor pair both work in the sub-threshold region, and the amplification factor of the amplification circuit 200 is configured to make the currents flowing through the main transistor and the transistor pair equal. Among them, the reference current and the reference voltage are two paths, which will be further described in conjunction with examples below.

[0027] Among them, when the gate voltage of the transistor (MOSFET) is lower than the threshold voltage, the electrons cannot completely flow from the source to the drain, thereby generating a sub-threshold region. The characteristic of the sub-threshold region is that there are still some electrons flowing from the source to the drain, but the current is small, because in the sub-threshold region, the channel formation of the MOSFET is limited and cannot be completely opened.

[0028] Therefore, the LDO circuit of the embodiments of the present application utilizes one main transistor and a group of transistor pairs in the sub-threshold region, and cooperates with the amplification factor of the amplification circuit to generate a voltage that can be determined by the LDO circuit, thereby equivalent to realizing the function of outputting the reference voltage by the reference circuit, so as to avoid using the reference circuit and reduce the power consumption of the system applying the LDO circuit.

[0029] The design of the LDO circuit of the embodiments of the present application will be specifically introduced below through examples.

[0030] Figure 3 is a structural schematic diagram of the example design of the LDO circuit of the embodiments of the present application. As shown in Figure 3As shown, the input circuit 100 comprises: a twelfth transistor M12, whose drain and gate are connected and connected to a first bias current BIAS1; an eleventh transistor M11 as the main transistor, whose drain and gate are connected and connected to the source of the twelfth transistor M12; a tenth transistor M10, whose drain and gate are connected and connected to a second bias current BIAS2, and whose source is connected to the source of the eleventh transistor M11 and grounded. Wherein the gate of the twelfth transistor M12 and the gate of the tenth transistor M10 are respectively used to output a reference voltage. Wherein the first bias current BIAS1 and the second bias current BIAS2 are two reference currents from a preset power supply.

[0031] The amplification circuit 200 comprises: a common-gate eighth transistor M8 and a common-gate ninth transistor M9, and the sources of both are grounded, and the gates are connected to a reference voltage; a common-gate fourth transistor M4 and a common-gate seventh transistor M7, and the gates of both are connected to another reference voltage, wherein the source of the fourth transistor M4 is connected to the drain of the eighth transistor M8 and serves as the output end of the amplification circuit, and the source of the seventh transistor M7 is connected to the drain of the ninth transistor M9; and a common-gate fifth transistor M5 and a common-gate sixth transistor M6, and the sources of both are connected to a working voltage V+, wherein the drain of the fifth transistor M5 is connected to the drain of the fourth transistor M4, and the drain of the sixth transistor M6 is connected to the drain of the seventh transistor M7, and the gate of the sixth transistor M6 is also connected to its drain.

[0032] The feedback circuit 300 comprises: a second transistor M2 and a third transistor M3 forming a transistor pair, wherein the drain and gate of each of the second transistor M2 and the third transistor M3 are connected to each other, the source of the second transistor M2 serves as the output end of the LDO circuit, and the source of the third transistor M3 is connected to the output end of the amplification circuit; and a first transistor M1, whose drain is connected to the source of the second transistor M2, whose source is connected to a working voltage, and whose gate is connected to the amplification circuit with a feedback voltage.

[0033] For the above-mentioned LDO circuit comprising the input circuit 100, the amplification circuit 200 and the feedback circuit 300, in an example, two bias currents are 5uA, and are respectively recorded as BIAS1_0P5uA and BIAS2_0P5uA, and the output voltage of the LDO circuit is recorded as VDD_DIG, and each transistor adopts a PMOS tube or an NMOS tube as shown in Figure 3 The working principle of the LDO circuit can be described as follows:

[0034] Bias current BIAS1_0P5uA flows through transistors M11 and M12, and a bias voltage is obtained at the gate of transistor M12, which is the sum of the gate-source voltages of transistors M11 and M12. Since the ratio of transistors M8 and M9 is 2:1, the currents through transistors M4, M7 and M12 are the same, and the currents through transistors M2, M3 and M11 are also the same. Ignoring the channel modulation effect, the drain voltage of transistor M8 is approximately the gate-source voltage of transistor M11. The other half of the current mirrored by transistor M8 flows through transistors M2, M3 to generate a voltage. Since transistors M2, M3 and M11 are in the sub-threshold region, the voltage of VDD_DIG under no load is:

[0035]

[0036] wherein:

[0037] NMOS sub-threshold current = I tn *(W / L)*exp[(V gs -V t ) / (nV T )];

[0038] PMOS sub-threshold current = I tp *(W / L)*exp[(V sg -V t ) / (nV T )];

[0039] V SG2 is the difference between the source-gate voltage of PMOS transistor M2, V t2 is the threshold voltage of PMOS transistor M2;

[0040] V GS3 is the difference between the gate-source voltage of NMOS transistor M3, V t3 is the threshold voltage of NMOS transistor M3;

[0041] V GS11 is the difference between the gate-source voltage of NMOS transistor M11, V t11 is the threshold voltage of NMOS transistor M11;

[0042] n is an empirical coefficient, V T is the thermal voltage, S is the width-length ratio (W / L) of the MOS transistor, wherein S2 corresponds to transistor M2, S3 corresponds to transistor M3, and S 11 corresponds to transistor M11; I is the on current of the MOS transistor, and the on currents of transistors M2, M3 and M11 are all equal to 0.5uA; I tp is the sub-threshold current of the PMOS transistor when W / L=1, I tnThe sub-threshold current of the NMOS transistor when W / L = 1.

[0043] It should be noted that the ratio of the transistors M8 and M9 is consistent with the amplification of the amplification circuit 200, but it is not limited to 2:1, and the ratio can be adjusted adaptively according to the specific circuit device, as long as the same current is ensured on the transistors M2, M3 and M11.

[0044] That is, the output end VDD_DIG of the LDO circuit generates a stable output voltage V o The negative feedback loop formed by the transistors M1-M2-M3-M4-M1 is beneficial to ensure the stability of the voltage.

[0045] Further, in combination with Figure 2 and Figure 3 In the preferred embodiment, the LDO circuit further comprises a compensation circuit 400 arranged on the feedback loop of the feedback circuit 300 feeding back the voltage to the amplification circuit 200, for realizing frequency compensation for the LDO circuit. Referring to Figure 3 The compensation circuit 400 is arranged between the gate and the source of the first transistor M1, which can be a TYPE-2 compensator composed of a resistor R1, a resistor R2 and a capacitor C2, for ensuring the stability of the entire feedback loop. In addition, for the purpose of reducing overshoot and performing voltage withstand protection, Figure 3 The LDO circuit shown in the figure further comprises a resistor RL, a capacitor CL, a capacitor C1, a resistor R3 and the like.

[0046] Accordingly, from the perspective of the transfer function, Figure 3 The principle of loop compensation realized by the devices in the LDO circuit can be described as follows:

[0047] The loop is disconnected from the gate of the transistor M1, and the corresponding loop gain is calculated, ignoring the shunt of the load of the LDO circuit, to obtain the transfer function under no-load and light load:

[0048]

[0049] Where z1 is the main zero point, z2 is the secondary zero point, p1 is the main pole, p2 is the secondary pole, g m1 , g m2 and g m3 are the transconductances of the transistors M1, M2 and M3, r o5 is the channel resistance of the transistor M5, R1, R2, R L represent the resistance values of the corresponding resistors, C1, C2 and C LThe capacitance value corresponding to the capacitance is represented. The frequency of the second zero point z2 is much higher than the gain-bandwidth product GBW of the amplifier of the amplification circuit, so the entire loop is approximately a "two-pole + one-zero" system, and the stability of the entire loop can be ensured by compensating the second pole with the zero point. Under heavy load, the second pole moves to high frequency, at which time the zero point precedes the second pole, and the loop gain decreases, while the main pole remains unchanged, so the unity gain bandwidth decreases, making the entire loop more stable.

[0050] Further, the amplification circuit 200 further comprises a fourteenth transistor M14 having its gate connected to its drain and connected to the drain of the eighth transistor M8, and a thirteenth transistor M13 having its gate connected to its drain and connected to the source of the fourteenth transistor M14. That is, the transistors M13 and M14 cooperate to protect the transistor M8 from being broken down due to the over-high voltage at the drain of the transistor M8 caused by the capacitive coupling when the LDO circuit is powered on.

[0051] Still further, the feedback circuit 300 further comprises a fifteenth transistor M15 having its drain connected to its gate and connected to the gate of the first transistor M1, and a sixteenth transistor M16 having its drain connected to its gate and connected to the source of the fifteenth transistor M15, and its source connected to the working voltage. That is, the transistors M15 and M16 cooperate to limit the maximum gate-source voltage of the transistor M1, while also serving as a current limiter.

[0052] Still further, the feedback circuit 300 further comprises a PMOS transistor M0 having its gate connected to a preset bias current, its source connected to the source of the second transistor M2, and its drain connected to the ground. For example, referring to Figure 3 , the LDO_TEG signal provides a bias for the gate of the PMOS transistor M0 connected to the output of the LDO circuit, and when the load is switched from heavy load to light load, the output overshoots, the PMOS transistor M0 discharges, thereby limiting the overshoot to a certain extent.

[0053] It should be noted that, Figure 3 the division of the input circuit 100, the amplification circuit 200, the feedback circuit 300 and the compensation circuit 400 in Figure 3 is exemplary, and each circuit can comprise devices outside the corresponding dashed box, or even devices not shown in ​ , for example, protection circuits configured for the purpose of reducing overshoot and voltage withstand. In addition, not described above, which has little effect on the working principle of the LDO circuit of the embodiments of the present application, is not the device concerned by the embodiments of the present application, and the person skilled in the art can easily know its function, so it will not be described here.

[0054] In summary, the embodiment of the present application substantially provides a reference voltage-free sub-threshold region low-power LDO circuit, which directly generates a stable LDO output voltage by input current using a transistor in the sub-threshold region. Since the reference circuit is not needed, the circuit structure is simpler and the power consumption is lower. Since the transistor works in the sub-threshold region, the circuit power consumption is further reduced, and the problems of complexity and high power consumption in the traditional LDO circuit design can be solved.

[0055] The embodiment of the present application also provides a chip integrated with any of the above LDO circuits. The chip is, for example, a power management chip. The LDO circuit of the embodiment does not need a reference circuit, so that when integrated in the chip, the chip occupies less space, which is beneficial to reducing the size of the chip.

[0056] The embodiment of the present application also provides an electronic device comprising the above chip. The electronic device is, for example, a communication device, an automotive electronic device, etc.

[0057] It should be further noted that the terms "comprising", "containing" or any other variant thereof are intended to cover non-exclusive inclusion, so that processes, methods, articles or devices including a series of elements not only include those elements, but also include other elements not explicitly listed, or further include elements inherent in such processes, methods, articles or devices. Without more limitations, the element defined by the phrase "comprising a" does not exclude the presence of additional identical elements in the process, method, article or device including the element.

[0058] The above is only an embodiment of the present application and is not intended to limit the present application. The present application can have various modifications and changes for those skilled in the art. Any modification, equivalent replacement, improvement, etc. within the spirit and principle of the present application shall be included in the scope of claims of the present application.

Claims

1. A low dropout linear stabilizer (LDO) circuit, characterized in that: include: An input circuit (100) comprising a main transistor, the input circuit (100) being connected to a reference current and correspondingly outputting a reference voltage at least through the main transistor; an amplifier circuit (200), which is connected to the reference voltage and performs amplification; as well as A feedback circuit (300) comprises a transistor pair, one end of the feedback circuit (300) is connected to the output end of the amplifier circuit (200) via the transistor pair, and the other end feeds back voltage to the amplifier circuit (200) and serves as the output end of the LDO circuit; The main transistor and the transistor pair both operate in a subthreshold region, and the amplification factor of the amplifier circuit (200) is configured so that the currents flowing through the main transistor and the transistor pair are equal; Wherein, the input circuit includes: a twelfth transistor (M12), a drain of which is connected to the gate and connected to the first bias current (BIAS1); an eleventh transistor (M11) serving as the main transistor, the drain of which is connected to the gate and connected to the source of the twelfth transistor (M12); and a tenth transistor (M10), having a drain connected to the gate and connected to the second bias current (BIAS2), a source connected to the source of the eleventh transistor (M11) and grounded, wherein the gates of the twelfth transistor (M12) and the tenth transistor (M10) respectively output a reference voltage; Wherein, the amplifying circuit (200) comprises: an eighth transistor (M8) and a ninth transistor (M9) having a common gate, wherein the sources of the eighth transistor and the ninth transistor are both grounded and the gates are connected to a reference voltage; a fourth transistor (M4) and a seventh transistor (M7) with a common gate, and the gates of both transistors are connected to another reference voltage, wherein the source of the fourth transistor (M4) is connected to the drain of the eighth transistor (M8) and serves as the output end of the amplifier circuit (200), and the source of the seventh transistor (M7) is connected to the drain of the ninth transistor (M9); Wherein, the feedback circuit (300) comprises: a second transistor (M2) and a third transistor (M3) forming the transistor pair, wherein the drains and gates of the second transistor (M2) and the third transistor (M3) are connected to each other, the source of the second transistor (M2) serves as the output of the LDO circuit, and the source of the third transistor (M3) is connected to the output of the amplifier circuit; and The first transistor (M1) has a drain connected to the source of the second transistor (M2), a source connected to an operating voltage, and a gate connected to the amplifier circuit to feedback voltage.

2. The LDO circuit according to claim 1, wherein: The amplifying circuit (200) further includes: A fifth transistor (M5) and a sixth transistor (M6) having a common gate, and sources of both transistors are connected to an operating voltage, wherein the drain of the fifth transistor (M5) is connected to the drain of the fourth transistor (M4), and the drain of the sixth transistor (M6) is connected to the drain of the seventh transistor (M7), and the gate of the sixth transistor (M6) is also connected to its drain.

3. The LDO circuit according to claim 2, wherein: The amplifying circuit (200) further includes: a fourteenth transistor (M14), whose gate and drain are connected to the drain of the eighth transistor (M8); and The gate of the thirteenth transistor (M13) is connected to the drain and is also connected to the source of the fourteenth transistor (M14).

4. The LDO circuit according to claim 1, wherein: The feedback circuit (300) further includes: The PMOS tube (M0) has a gate connected to a preset bias current, a source connected to the source of the second transistor (M2), and a drain connected to the ground.

5. The LDO circuit according to claim 1, wherein: The feedback circuit (300) further includes: a fifteenth transistor (M15), the drain and gate of which are connected to the gate of the first transistor (M1); and The drain of the sixteenth transistor (M16) is connected to the gate and the source of the fifteenth transistor (M15), and the source is connected to the operating voltage.

6. The LDO circuit according to any one of claims 1 to 5, wherein: The LDO circuit further includes: A compensation circuit (400) is provided on a feedback loop in which the feedback circuit (300) feeds back a voltage to the amplifier circuit (200), and is used to achieve frequency compensation for the LDO circuit.

7. A chip, characterized in that: The chip integrates the LDO circuit according to any one of claims 1 to 6.

8. An electronic device, characterized in that: Comprising the chip according to claim 7.

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