A high precision reference voltage circuit

Abstract

The application provides a high-precision reference voltage circuit, which comprises an anti-interference circuit module, a gain circuit module and an amplification buffer circuit module, so that the output voltage of the circuit has a low temperature coefficient, high precision and large output voltage swing. The circuit also comprises a bias circuit and a voltage stabilizing output circuit. The bias circuit comprises an anti-interference circuit, so that the bias circuit can work normally in a high-frequency electromagnetic interference environment. The bias circuit is based on the circuit structure, so that the output bias voltage is stable and unchanged. The voltage stabilizing output circuit comprises a gain circuit, so that the system has high gain and high power supply rejection ratio. The amplification buffer circuit in the voltage stabilizing output circuit has a frequency compensation function, so that the system can work stably in a low-frequency and high-frequency range. Meanwhile, the amplification buffer circuit is based on the circuit structure, so that the system has low output impedance, the current output capacity of the system is improved, and the output voltage has a large voltage swing.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and more specifically, to a high-precision reference voltage circuit. Background Technology

[0002] A reference voltage circuit provides a precise and stable reference voltage for an integrated circuit system, serving as a reference voltage or threshold. To ensure a low temperature coefficient for the output voltage of the reference voltage circuit, techniques such as curvature compensation and bandgap linearization are typically used for temperature compensation. However, the operational amplifier circuits used in the aforementioned temperature offset compensation schemes based on resistance ratios exhibit significant offset voltages, severely impacting the output voltage accuracy of the reference voltage circuit. Furthermore, integrated circuit systems often contain multiple high-frequency switching transistors, whose high-frequency electromagnetic interference also significantly affects the output accuracy of the reference voltage circuit. Summary of the Invention

[0003] The problem solved by this invention is to propose a high-precision reference voltage circuit, which includes an anti-interference circuit module, a gain circuit module, and an amplification buffer circuit module, so that the circuit output voltage has a low temperature coefficient, high accuracy, and a large output voltage swing.

[0004] To address the aforementioned problems, the present invention provides a high-precision reference voltage circuit comprising a bias circuit and a regulated output circuit.

[0005] The bias circuit is connected to the regulated output circuit, and the bias circuit outputs a precise and stable bias voltage to the regulated output circuit.

[0006] The bias circuit includes anti-interference circuitry, enabling it to operate normally in environments with high-frequency electromagnetic interference. Based on its circuit structure, the bias circuit effectively shields against the effects of power supply voltage fluctuations, ensuring a stable output bias voltage.

[0007] The regulated output circuit includes a gain circuit, giving the system a high gain and consequently a high power supply rejection ratio. The amplification buffer circuit in the regulated output circuit has frequency compensation functionality, ensuring stable operation of the system across both low and high frequency ranges. Simultaneously, based on its circuit structure, the amplification buffer circuit gives the system a low output impedance, improving the system's current output capability and enabling a larger voltage swing. The merging circuit in the regulated output circuit is primarily used to generate a reference voltage with a low temperature coefficient.

[0008] The bias circuit includes the VPES port. The regulated output circuit includes the VCLS and VOUT ports.

[0009] Port VPES is connected to port VCLS and is used to transmit the bias voltage Vbe. Port VOUT is the system output port and is used to output the reference voltage Vrt.

[0010] The bias circuit includes an anti-interference circuit and a bias voltage circuit.

[0011] The anti-interference circuit is connected to the bias voltage circuit, providing an anti-interference voltage to the bias voltage circuit, enabling it to operate normally in high-frequency electromagnetic interference environments. The bias voltage circuit outputs a precise and stable bias voltage to the regulated output circuit.

[0012] The regulated output circuit includes a gain circuit, an amplification buffer circuit, and a merging circuit.

[0013] The gain circuit is connected to the amplification buffer circuit, and the gain circuit outputs a high-gain voltage to the amplification buffer circuit. Through frequency compensation, the amplification buffer circuit can stably output a high-gain voltage in both low and high frequency ranges, and provides a large voltage swing. The amplification buffer circuit is also connected to the merging circuit, and the output voltage from the amplification buffer circuit is fed into the merging circuit. The merging circuit processes the voltage and outputs a reference voltage with a low temperature coefficient.

[0014] Compared with existing technologies, the beneficial effects of this invention are as follows: This invention proposes a high-precision reference voltage circuit, including a bias circuit and a regulated output circuit. The bias circuit outputs a precise and stable bias voltage to the regulated output circuit, giving the regulated output circuit high stability and accuracy. The bias circuit includes an anti-interference circuit, enabling it to operate normally in high-frequency electromagnetic interference environments. Based on its circuit structure, the bias circuit effectively shields the effects of power supply voltage fluctuations, ensuring a stable output bias voltage. The regulated output circuit includes a gain circuit, giving the system high gain and thus a high power supply rejection ratio. The amplification buffer circuit in the regulated output circuit has a frequency compensation function, ensuring stable operation of the system in both low and high frequency ranges. Simultaneously, based on its circuit structure, the amplification buffer circuit gives the system low output impedance, improving the system's current output capability and enabling a larger voltage swing in the output voltage. Attached Figure Description

[0015] Figure 1 This is a schematic diagram of the system structure of the present invention;

[0016] Figure 2 This is a schematic diagram of the bias circuit of the present invention.

[0017] Figure 3 This is a schematic diagram of the principle structure of the voltage regulator output circuit of the present invention.

[0018] Explanation of reference numerals in the attached figures:

[0019] 1-Bias circuit; 2-Regulated output circuit; 11-Anti-interference circuit; 12-Bias voltage circuit; 21-Gain circuit; 22-Amplification buffer circuit; Combining circuit. Detailed Implementation

[0020] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0021] like Figure 1 As shown, a high-precision reference voltage circuit includes a bias circuit 1 and a regulated output circuit 2.

[0022] The bias circuit 1 is connected to the regulated output circuit 2, and the bias circuit 1 outputs a precise and stable bias voltage Vbe to the regulated output circuit 2.

[0023] The bias circuit 1 includes an anti-interference circuit, enabling it to operate normally in high-frequency electromagnetic interference environments. Based on its circuit structure, the bias circuit 1 effectively shields against the effects of power supply voltage fluctuations, ensuring a stable output bias voltage.

[0024] The regulated output circuit 2 includes a gain circuit, giving the system a high gain and consequently a high power supply rejection ratio. The amplification buffer circuit in regulated output circuit 2 has frequency compensation functionality, ensuring stable operation of the system across both low and high frequency ranges. Simultaneously, based on its circuit structure, the amplification buffer circuit provides the system with low output impedance, improving the system's current output capability and enabling a larger voltage swing in the output voltage. The merging circuit in regulated output circuit 2 is primarily used to generate a reference voltage Vrt with a low temperature coefficient.

[0025] Bias circuit 1 includes port VPES.

[0026] The regulated output circuit 2 includes ports VCLS and VOUT.

[0027] Port VPES is connected to port VCLS and is used to transmit the bias voltage Vbe. Port VOUT is the system output port and is used to output the reference voltage Vrt.

[0028] like Figure 1 As shown, the bias circuit 1 includes an anti-interference circuit 11 and a bias voltage circuit 12.

[0029] The anti-interference circuit 11 is connected to the bias voltage circuit 12. The anti-interference circuit 11 provides an anti-interference voltage Vgs to the bias voltage circuit 12, enabling the bias voltage circuit 12 to operate normally in a high-frequency electromagnetic interference environment. The bias voltage circuit 12 outputs a precise and stable bias voltage Vbe to the regulated output circuit 2.

[0030] like Figure 1 As shown, the regulated output circuit 2 includes a gain circuit 21, an amplification buffer circuit 22, and a merging circuit 23.

[0031] Gain circuit 21 is connected to amplification buffer circuit 22, and the high-gain voltage Veh output by gain circuit 21 is fed into amplification buffer circuit 22. Through frequency compensation, amplification buffer circuit 22 can stably output a high-gain voltage in both low and high frequency ranges, and provides a large voltage swing. Amplification buffer circuit 22 is connected to merging circuit 23, and the output voltage Vpr of amplification buffer circuit 22 is fed into merging circuit 23. Merging circuit 23 processes voltage Vpr and outputs a reference voltage Vrt with a low temperature coefficient.

[0032] like Figure 2 As shown, the anti-interference circuit 11 includes a self-biased power supply circuit 111 and a current-limiting output circuit 112.

[0033] The self-biased power supply circuit 111 is connected to the current limiting output circuit 112, and the self-biased power supply circuit 111 outputs an anti-interference voltage Vgs to the current limiting output circuit 112.

[0034] The self-biased power supply circuit 111 includes MOSFETs M1, M2, M3, and M4.

[0035] The source of MOSFET M1 is connected to the power supply VDD, the gate of MOSFET M1 is connected to the gate of MOSFET M2, and the drain of MOSFET M1 is connected to the drain of MOSFET M2. The drain of MOSFET M2 is connected to the drain of MOSFET M1, the gate of MOSFET M2 is connected to the drain of MOSFET M2, and the source of MOSFET M2 is connected to the drain of MOSFET M3. The drain of MOSFET M3 is connected to the source of MOSFET M2, the gate of MOSFET M3 is connected to the drain of MOSFET M3, and the source of MOSFET M3 is connected to the drain of MOSFET M4. The drain of MOSFET M4 is connected to the source of MOSFET M3, the gate of MOSFET M4 is connected to the gate of MOSFET M3, and the source of MOSFET M4 is grounded.

[0036] MOSFETs M1, M2, M3, and M4 form a regulated self-biased power supply structure, providing MOSFET M5 with a stable turn-on voltage Vqk that is undisturbed.

[0037] The current-limiting output circuit 112 includes MOSFET M5 and MOSFET M6.

[0038] The drain of MOSFET M5 is connected to the source of MOSFET M1, the gate of MOSFET M5 is connected to the drain of MOSFET M1, and the source of MOSFET M5 is connected to the drain of MOSFET M6. The drain of MOSFET M6 is connected to the source of MOSFET M5, the gate of MOSFET M6 is connected to the drain of MOSFET M6, and the source of MOSFET M6 is connected to the drain of MOSFET M7.

[0039] MOSFETs M5 and M6 form a current-limiting output structure, outputting an anti-interference voltage Vgs to the bias voltage circuit 12.

[0040] The bias voltage circuit 12 includes a shielding circuit 121 and a load circuit 122.

[0041] The shielding circuit 121 is connected to the load circuit 122, and the shielding circuit 121 outputs a precise and stable bias voltage Vbe through the load circuit 122.

[0042] The shielding circuit 121 includes MOSFETs M8, M9, M10, and M11.

[0043] The source of MOSFET M8 is connected to the power supply VDD, the gate of MOSFET M8 is connected to the gate of MOSFET M10, and the drain of MOSFET M8 is connected to the drain of MOSFET M9. The drain of MOSFET M9 is connected to the gate of MOSFET M9, the gate of MOSFET M9 is connected to the gate of MOSFET M11, and the source of MOSFET M9 is connected to the gate of MOSFET M7. The source of MOSFET M10 is connected to the source of MOSFET M8, the gate of MOSFET M10 is connected to the drain of MOSFET M10, and the drain of MOSFET M10 is connected to the drain of MOSFET M11. The drain of MOSFET M11 is connected to the gate of MOSFET M10, the gate of MOSFET M11 is connected to the drain of MOSFET M8, and the source of MOSFET M11 is connected to the drain of MOSFET M12.

[0044] The circuit structure formed by connecting MOSFETs M8, M9, M10, and M11 can shield the influence of power supply voltage fluctuations on related branches, ensuring that the source voltages of MOSFETs M9 and M11 remain stable, thereby improving the accuracy of the VPES output voltage at the port.

[0045] The load circuit 122 includes MOSFETs M7, M12, and M13, as well as the VPES port.

[0046] The drain of MOSFET M7 is connected to the source of MOSFET M9, the gate of MOSFET M7 is connected to the drain of MOSFET M7, and the source of MOSFET M7 is grounded. The drain of MOSFET M12 is connected to the source of MOSFET M11, the gate of MOSFET M12 is connected to the drain of MOSFET M12, and the source of MOSFET M12 is connected to the drain of MOSFET M13. The drain of MOSFET M13 is connected to the source of MOSFET M12, the gate of MOSFET M13 is connected to the gate of MOSFET M7, and the source of MOSFET M13 is connected to port VPES.

[0047] MOSFETs M7, M12, and M13 are connected to form the output load of bias voltage circuit 12. High-frequency electromagnetic interference in the environment will cause the gate voltage of MOSFET M9 to rise, which in turn will cause the gate voltage of MOSFET M13 to fall, resulting in the turn-off of MOSFETs M13 and M7. The drain-source branch current of MOSFET M13 will be zero, and bias voltage circuit 12 will stop working. The anti-interference circuit 11 is connected to the source of MOSFET M9 through the source of MOSFET M6, outputting an anti-interference voltage Vgs to the source of MOSFET M9, which will raise the source voltage of MOSFET M9, thereby turning on MOSFETs M13 and M7. After MOSFETs M13 and M7 are turned on, the gate voltage of MOSFET M9 can be pulled down, thereby restoring the normal operation of bias voltage circuit 12. Bias voltage circuit 12 outputs a suitable bias voltage Vbe to the regulated output circuit 2 through port VPES.

[0048] MOSFETs M18 and M10 have the same size ratio. The channel width of MOSFET M13 is four times that of MOSFET M7. Based on the bias voltage circuit connection structure, the expression for the gate-source voltage Vgs13 of MOSFET M13 is shown in formula (1).

[0049]

[0050] In formula (1), Ibe is the current flowing through the drain and source of MOSFET M13, which is the bias current output by the circuit. B13 is the width-to-length ratio of the conductive channel of MOSFET M13, and Vth13 is the threshold voltage of MOSFET M13. Similarly, the expression for the gate-source voltage Vgs7 of MOSFET M7 is shown in formula (2).

[0051]

[0052] In formula (2), Ibe is the bias current output by the circuit. K is the size ratio of MOSFET M13 to M7, and in this example, K = 4. B7 is the width-to-length ratio of the conductive channel of MOSFET M7, and Vth7 is the threshold voltage of MOSFET M7.

[0053] The bias current Ibe of the circuit output can be derived from formulas (1) and (2), and its expression is shown in formula (3).

[0054]

[0055] In formula (3), R is the on-resistance of MOSFET M13, B13 is the width-to-length ratio of the conductive channel of MOSFET M13, and K is the size ratio of MOSFET M13 to M7. In this example, K = 4.

[0056] like Figure 3 As shown, the gain circuit 21 includes a coupling circuit 211 and a constant current region circuit 212.

[0057] The coupling circuit 211 is connected to the constant current region circuit 212, which provides a bias current to keep the MOSFET in the coupling circuit 211 operating in the constant current region. The coupling circuit 211 generates and outputs a high-gain voltage Veh to the amplification buffer circuit 22, thereby increasing the power supply rejection ratio of the regulated output circuit 2 and improving the system output accuracy. The coupling circuit 211, through its connection with the merging circuit 23, participates in the generation of the low temperature coefficient reference voltage.

[0058] The coupling circuit 211 includes MOSFETs M14, M15, M17, and M18.

[0059] The source of MOSFET M14 is connected to the power supply VDD, the gate of MOSFET M14 is connected to the gate of MOSFET M17, and the drain of MOSFET M14 is connected to the drain of MOSFET M15. The drain of MOSFET M15 is connected to the gate of MOSFET M14, the gate of MOSFET M15 is connected to the drain of MOSFET M28, and the source of MOSFET M15 is connected to the drain of MOSFET M16. The source of MOSFET M17 is connected to the source of MOSFET M14, the gate of MOSFET M17 is connected to the drain of MOSFET M15, and the drain of MOSFET M17 is connected to the drain of MOSFET M18. The drain of MOSFET M18 is connected to the drain of MOSFET M17, the gate of MOSFET M18 is connected to the drain of MOSFET M27, and the source of MOSFET M18 is connected to the drain of MOSFET M19.

[0060] The interconnection structure of MOSFETs M14 and M17 has current source load characteristics and makes the drain voltage difference between MOSFETs M15 and M18 zero, thereby ensuring the output accuracy of the gain circuit 21.

[0061] MOSFETs M15 and M18 have the same channel width-to-length ratio and form a source-coupled structure based on their connection. The voltage Veh at the junction of the drain of MOSFET M17 and the drain of MOSFET M18 has a large gain and is transmitted to the amplification buffer circuit 22 through the connection between the drain of MOSFET M17 and the gate of MOSFET M20. The gates of MOSFETs M15 and M18 are connected to the merging circuit 23 to participate in the generation of the low temperature coefficient reference voltage.

[0062] The constant current region circuit 212 includes MOSFET M19, MOSFET M16, and VCLS port.

[0063] The drain of MOSFET M16 is connected to the source of MOSFET M19, the gate of MOSFET M16 is connected to the VCLS port, and the source of MOSFET M16 is grounded. The drain of MOSFET M19 is connected to the source of MOSFET M18, the gate of MOSFET M19 is connected to the drain of MOSFET M19, and the source of MOSFET M19 is connected to the source of MOSFET M15.

[0064] The gate of MOSFET M16 is connected to port VCLS, and the bias voltage Vbe is obtained through the connection between port VCLS and port VPES. Based on the relevant circuit connection structure of MOSFETs M16 and M19, the constant current circuit 212 provides bias current for MOSFETs M15 and M18, enabling MOSFETs M15 and M18 to operate in the constant current region.

[0065] like Figure 3 As shown, the amplification buffer circuit 22 includes a frequency compensation circuit 221 and a common-source amplifier circuit 222.

[0066] The frequency compensation circuit 221 is connected to the common-source amplifier circuit 222. The frequency compensation circuit 221 generates the dominant pole of the system, maintaining the stable operation of the common-source amplifier circuit 222 in the high-frequency range. The common-source amplifier circuit 222 outputs a voltage Vpr with high gain and high swing to the merging circuit 23.

[0067] The frequency compensation circuit 221 includes a resistor R1, a capacitor C1, a MOSFET M20, a MOSFET M21, and a MOSFET M24.

[0068] The source of MOSFET M20 is connected to the source of MOSFET M17, the gate of MOSFET M20 is connected to the drain of MOSFET M17, and the drain of MOSFET M20 is connected to the drain of MOSFET M21. The upper end of resistor R1 is connected to the lower end of capacitor C1, and the lower end of resistor R1 is connected to the drain of MOSFET M18. The upper end of capacitor C1 is connected to the drain of MOSFET M20, and the lower end of capacitor C1 is connected to the upper end of resistor R1. The drain of MOSFET M21 is connected to the drain of MOSFET M20, the gate of MOSFET M21 is connected to the gate of MOSFET M24, and the source of MOSFET M21 is connected to the source of MOSFET M22. The drain of MOSFET M24 is connected to the source of MOSFET M20, the gate of MOSFET M24 is connected to the drain of MOSFET M21, and the source of MOSFET M24 is connected to the source of MOSFET M25.

[0069] Resistor R1, capacitor C1, MOSFETs M20, M21, and M24 are connected to form a frequency compensation circuit, generating the dominant pole of the amplification buffer circuit 22. The frequency compensation circuit ensures stable operation of the amplification buffer circuit 22 in both low and high frequency ranges, and provides a 70° phase margin for the entire circuit system, including bias circuit 1 and voltage regulator output circuit 2. When the system phase shift reaches 180°, the system gain is less than -20dB. In the 0 to 10kHz frequency range, the system open-loop gain is 50dB, ensuring stable system operation and meeting the system design specifications.

[0070] The common-source amplifier circuit 222 includes MOSFETs M22, M23, M25, and M26.

[0071] The source of MOSFET M22 is connected to the source of MOSFET M21, the gate of MOSFET M22 is connected to the gate of MOSFET M25, and the drain of MOSFET M22 is connected to the drain of MOSFET M23. The drain of MOSFET M23 is connected to the gate of MOSFET M22, and the gate of MOSFET M23 is connected to the gate of MOSFET M16. The source of MOSFET M23 is grounded. The source of MOSFET M25 is connected to the gate of MOSFET M27, the gate of MOSFET M25 is connected to the drain of MOSFET M22, and the drain of MOSFET M25 is connected to the drain of MOSFET M26. The drain of MOSFET M26 is connected to the drain of MOSFET M25, the gate of MOSFET M26 is connected to the drain of MOSFET M26, and the source of MOSFET M26 is grounded.

[0072] The circuit connection structure of MOSFETs M22, M23, M25, and M26 has a common-source amplification function and a small output impedance, resulting in a large voltage amplitude at the connection node between the source of MOSFET M24 and the source of MOSFET M25. By connecting the gate of MOSFET M27 to the source of MOSFET M25, the voltage Vpr is output to the merging circuit 23 to improve the gain and voltage swing of the output reference voltage Vrt of the merging circuit 23. Based on the circuit connection structure of the common-source amplifier circuit 222, the expression for voltage Vpr is shown in equation (4).

[0073]

[0074] In formula (4), Vdd is the power supply voltage, Ia is the current in the branch where the gate and source of MOS transistor M24 are located, u is the electron mobility, Cox is the gate oxide capacitance of MOS transistor, B25 is the width-to-length ratio of the conductive channel of MOS transistor M25, B26 is the width-to-length ratio of the conductive channel of MOS transistor M26, Vth25 is the threshold voltage of MOS transistor M25, and Vth26 is the threshold voltage of MOS transistor M26.

[0075] like Figure 3 As shown, the merging circuit 23 includes an input circuit 231, a branch current circuit 232, and an output circuit 233.

[0076] Input circuit 231 is connected to branch current circuit 232, providing operating voltage to branch current circuit 232 to generate branch currents Ib and Ic respectively. Input circuit 231 is also connected to output circuit 233, copying the currents Ib and Ic from branch current circuit 232 to output circuit 233, combining them to generate current Io. Output circuit 233 generates a reference voltage Vrt based on current Io.

[0077] The input circuit 231 includes MOSFETs M27, M28 and M29.

[0078] The source of MOSFET M27 is connected to the power supply VDD, the gate of MOSFET M27 is connected to the gate of MOSFET M28, and the drain of MOSFET M27 is connected to the emitter of transistor Q1. The source of MOSFET M28 is connected to the source of MOSFET M27, the gate of MOSFET M28 is connected to the gate of MOSFET M29, and the drain of MOSFET M28 is connected to the upper end of resistor R3. The source of MOSFET M29 is connected to the source of MOSFET M28, the gate of MOSFET M29 is connected to the gate of MOSFET M27, and the drain of MOSFET M29 is connected to the drain of MOSFET M30.

[0079] MOSFETs M27, M28, and M29 are connected to form input circuit 231, which receives voltage Vpr and replicates the current Ib from the drain-source branch of MOSFET M27 and the current Ic from the drain-source branch of MOSFET M28 to the drain-source branch of MOSFET M29. Currents Ib and Ic are then combined in the drain-source branch of MOSFET M29 to form the output current Io.

[0080] The branch current circuit 232 includes resistors R2, R3, and R4, transistors Q1, Q2, Q3, and Q4.

[0081] The upper end of resistor R2 is connected to the drain of MOSFET M27, and the lower end of resistor R2 is connected to the base of transistor Q1. The emitter of transistor Q1 is connected to the drain of MOSFET M27, the base of transistor Q1 is connected to the collector of transistor Q1, and the collector of transistor Q1 is connected to the emitter of transistor Q2. The emitter of transistor Q2 is connected to the lower end of resistor R2, the base of transistor Q2 is connected to the collector of transistor Q2, and the collector of transistor Q2 is grounded. The upper end of resistor R3 is connected to the drain of MOSFET M28, and the lower end of resistor R3 is connected to the emitter of transistor Q3. The upper end of resistor R4 is connected to the upper end of resistor R3, and the lower end of resistor R4 is connected to the base of transistor Q3. The emitter of transistor Q3 is connected to the lower end of resistor R3, the base of transistor Q3 is connected to the lower end of resistor R4, and the collector of transistor Q3 is connected to the emitter of transistor Q4. The emitter of transistor Q4 is connected to the collector of transistor Q3, the base of transistor Q4 is connected to the collector of transistor Q4, and the collector of transistor Q4 is grounded.

[0082] The connection structure of resistor R2, transistor Q1 and transistor Q2 is mainly used to generate branch current Ib, and the expression of current Ib is shown in formula (5).

[0083]

[0084] In formula (5), Vd27 is the drain voltage of MOS transistor M27, Vqe1 is the collector-emitter voltage of transistor Q1, and r2 is the resistance value of resistor R2.

[0085] The connection structure of resistor R3, resistor R4, transistor Q3, and transistor Q4 is mainly used to generate branch current Ic. The expression of current Ic is shown in formula (6).

[0086]

[0087] In formula (6), Vd28 is the drain voltage of MOSFET M28, Vqe3 is the collector-emitter voltage of transistor Q3, r3 is the resistance value of resistor R3, and r4 is the resistance value of resistor R4.

[0088] The output circuit 233 includes MOSFET M30, MOSFET M31, and port VOUT.

[0089] The drain of MOSFET M30 is connected to port VOUT, the gate of MOSFET M30 is connected to the drain of MOSFET M30, and the source of MOSFET M30 is connected to the drain of MOSFET M31. The drain of MOSFET M31 is connected to the source of MOSFET M30, the gate of MOSFET M31 is connected to the gate of MOSFET M30, and the source of MOSFET M31 is grounded.

[0090] The circuit connection structure of MOSFETs M30 and M31 forms the output load, with an impedance of Rn. The current Io is the sum of the currents Ib and Ic, while the system output reference voltage Vrt is the product of the current Io and the impedance Rn. Therefore, the expression for the system output reference voltage Vrt is shown in formula (7).

[0091]

[0092] In formula (7), rn is the impedance value of Rn, r4 is the resistance value of R4, Vqe1 is the collector-emitter voltage of transistor Q1, r3 is the resistance value of R3, Vt is the thermal voltage, and LnN is the subthreshold slope factor of MOS transistor.

[0093] In formula (7), Vqe1 has a negative temperature coefficient, while (r4 / r3×Vt×LnN) has a positive temperature coefficient. The two terms cancel each other out, resulting in a near-zero temperature coefficient for the reference voltage Vrt. Since the reference voltage Vrt is generated based on the voltage Vqr, it has both a low temperature coefficient and high accuracy, as well as a large output voltage swing. The reference voltage Vrt is output through port VOUT.

Claims

1. A high-precision reference voltage circuit, characterized in that, It includes a bias circuit (1) and a regulated output circuit (2); The bias circuit (1) is connected to the voltage regulation output circuit (2), and the bias circuit (1) outputs a precise and stable bias voltage (Vbe) to the voltage regulation output circuit (2); The bias circuit (1) includes an anti-interference circuit, which enables the bias circuit (1) to work normally in a high-frequency electromagnetic interference environment. The bias circuit (1) is designed based on its circuit structure, which can effectively shield the influence of power supply voltage jitter and make the output bias voltage stable and constant. The regulated output circuit (2) includes a gain circuit, which gives the system a higher gain and thus a higher power supply rejection ratio; the amplification buffer circuit in the regulated output circuit (2) has a frequency compensation function, which enables the system to maintain stable operation in both low and high frequency ranges; the merging circuit in the regulated output circuit (2) is mainly used to generate a reference voltage Vrt with a low temperature coefficient. The bias circuit (1) includes an anti-interference circuit (11) and a bias voltage circuit (12); The anti-interference circuit (11) is connected to the bias voltage circuit (12). The anti-interference circuit (11) provides the anti-interference voltage Vgs to the bias voltage circuit (12), enabling the bias voltage circuit (12) to work normally in the high-frequency electromagnetic interference environment. The bias voltage circuit (12) outputs a precise and stable bias voltage (Vbe) to the voltage regulator output circuit (2). The regulated output circuit (2) includes a gain circuit (21), an amplification buffer circuit (22), and a merging circuit (23). The gain circuit (21) is connected to the amplification buffer circuit (22). The gain circuit (21) outputs a high-gain voltage Veh to the amplification buffer circuit (22). The amplification buffer circuit (22) can stably output a high-gain voltage in both low and high frequency ranges through frequency compensation, and the output voltage has a large voltage swing. The amplification buffer circuit (22) is connected to the merging circuit (23). The amplification buffer circuit (22) outputs a voltage Vpr to the merging circuit (23). The merging circuit (23) processes the output voltage Vpr and outputs a reference voltage Vrt with a low temperature coefficient. The anti-interference circuit (11) includes a self-biased power supply circuit (111) and a current-limiting output circuit (112); the self-biased power supply circuit (111) is connected to the current-limiting output circuit (112), and the self-biased power supply circuit (111) outputs an anti-interference voltage Vgs to the current-limiting output circuit (112); The bias voltage circuit (12) includes a shielding circuit (121) and a load circuit (122); the shielding circuit (121) is connected to the load circuit (122), and the shielding circuit (121) outputs a precise and stable bias voltage (Vbe) through the load circuit (122). The gain circuit (21) includes a coupling circuit (211) and a constant current region circuit (212); the coupling circuit (211) is connected to the constant current region circuit (212), and the constant current region circuit (212) provides a bias current to make the MOS transistor in the coupling circuit (211) work in the constant current region; the coupling circuit (211) generates and outputs a high gain voltage Veh to the amplification buffer circuit (22), thereby increasing the power supply rejection ratio of the regulated output circuit (2) and thus improving the system output accuracy; the coupling circuit (211) participates in the generation of a low temperature coefficient reference voltage through its connection with the merging circuit (23); The amplification buffer circuit (22) includes a frequency compensation circuit (221) and a common-source amplifier circuit (222); the frequency compensation circuit (221) is connected to the common-source amplifier circuit (222), the frequency compensation circuit (221) generates the system's dominant pole, and maintains the stable operation of the common-source amplifier circuit (222) in the high-frequency range; the common-source amplifier circuit (222) outputs an output voltage Vpr with high gain and high swing to the merging circuit (23); The merging circuit (23) includes an input circuit (231), a branch current circuit (232), and an output circuit (233). The input circuit (231) is connected to the branch current circuit (232), and the input circuit (231) provides the operating voltage to the branch current circuit (232) so that it generates branch currents Ib and Ic respectively. The input circuit (231) is connected to the output circuit (233), and the input circuit (231) copies the currents Ib and Ic in the branch current circuit (232) to the output circuit (233) to generate a current Io. The output circuit (233) generates a reference voltage Vrt based on the current Io. The self-biased power supply circuit (111) includes MOSFETs M1, M2, M3, and M4; The source of MOSFET M1 is connected to the power supply VDD, the gate of MOSFET M1 is connected to the gate of MOSFET M2, and the drain of MOSFET M1 is connected to the drain of MOSFET M2. The drain of MOSFET M2 is connected to the drain of MOSFET M1, the gate of MOSFET M2 is connected to the drain of MOSFET M2, and the source of MOSFET M2 is connected to the drain of MOSFET M3. The drain of MOSFET M3 is connected to the source of MOSFET M2, the gate of MOSFET M3 is connected to the drain of MOSFET M3, and the source of MOSFET M3 is connected to the drain of MOSFET M4. The drain of MOSFET M4 is connected to the source of MOSFET M3, the gate of MOSFET M4 is connected to the gate of MOSFET M3, and the source of MOSFET M4 is grounded. The coupling circuit (211) includes MOSFETs M14, M15, M17, and M18; The source of MOSFET M14 is connected to the power supply VDD, the gate of MOSFET M14 is connected to the gate of MOSFET M17, and the drain of MOSFET M14 is connected to the drain of MOSFET M15. The drain of MOSFET M15 is connected to the gate of MOSFET M14, the gate of MOSFET M15 is connected to the drain of MOSFET M28, and the source of MOSFET M15 is connected to the drain of MOSFET M16. The source of MOSFET M17 is connected to the source of MOSFET M14, the gate of MOSFET M17 is connected to the drain of MOSFET M15, and the drain of MOSFET M17 is connected to the drain of MOSFET M18. The drain of MOSFET M18 is connected to the drain of MOSFET M17, the gate of MOSFET M18 is connected to the drain of MOSFET M27, and the source of MOSFET M18 is connected to the drain of MOSFET M19. The constant current region circuit (212) includes MOSFET M19, MOSFET M16, and VCLS port; The drain of MOSFET M16 is connected to the source of MOSFET M19, the gate of MOSFET M16 is connected to the VCLS port, and the source of MOSFET M16 is grounded; the drain of MOSFET M19 is connected to the source of MOSFET M18, the gate of MOSFET M19 is connected to the drain of MOSFET M19, and the source of MOSFET M19 is connected to the source of MOSFET M15. The frequency compensation circuit (221) includes resistor R1, capacitor C1, MOSFET M20, MOSFET M21 and MOSFET M24; The source of MOSFET M20 is connected to the source of MOSFET M17, the gate of MOSFET M20 is connected to the drain of MOSFET M17, and the drain of MOSFET M20 is connected to the drain of MOSFET M21. The upper end of resistor R1 is connected to the lower end of capacitor C1, and the lower end of resistor R1 is connected to the drain of MOSFET M18. The upper end of capacitor C1 is connected to the drain of MOSFET M20, and the lower end of capacitor C1 is connected to the upper end of resistor R1. The drain of MOSFET M21 is connected to the drain of MOSFET M20, the gate of MOSFET M21 is connected to the gate of MOSFET M24, and the source of MOSFET M21 is connected to the source of MOSFET M22. The drain of MOSFET M24 is connected to the source of MOSFET M20, the gate of MOSFET M24 is connected to the drain of MOSFET M21, and the source of MOSFET M24 is connected to the source of MOSFET M25. The common-source amplifier circuit (222) includes MOSFETs M22, M23, M25, and M26; The source of MOSFET M22 is connected to the source of MOSFET M21, the gate of MOSFET M22 is connected to the gate of MOSFET M25, and the drain of MOSFET M22 is connected to the drain of MOSFET M23. The drain of MOSFET M23 is connected to the gate of MOSFET M22, the gate of MOSFET M23 is connected to the gate of MOSFET M16, and the source of MOSFET M23 is grounded. The source of MOSFET M25 is connected to the gate of MOSFET M27, the gate of MOSFET M25 is connected to the drain of MOSFET M22, and the drain of MOSFET M25 is connected to the drain of MOSFET M26. The drain of MOSFET M26 is connected to the drain of MOSFET M25, the gate of MOSFET M26 is connected to the drain of MOSFET M26, and the source of MOSFET M26 is grounded. The branch current circuit (232) includes resistors R2, R3, and R4, transistors Q1, Q2, Q3, and Q4; The upper end of resistor R2 is connected to the drain of MOSFET M27, and the lower end of resistor R2 is connected to the base of transistor Q1. The emitter of transistor Q1 is connected to the drain of MOSFET M27, the base of transistor Q1 is connected to the collector of transistor Q1, and the collector of transistor Q1 is connected to the emitter of transistor Q2. The emitter of transistor Q2 is connected to the lower end of resistor R2, the base of transistor Q2 is connected to the collector of transistor Q2, and the collector of transistor Q2 is grounded. The upper end of resistor R3 is connected to MOSFET M28. The drain of transistor Q3 is connected to the emitter of transistor Q3. The upper end of resistor R4 is connected to the upper end of resistor R3, and the lower end of resistor R4 is connected to the base of transistor Q3. The emitter of transistor Q3 is connected to the lower end of resistor R3, and the base of transistor Q3 is connected to the lower end of resistor R4. The collector of transistor Q3 is connected to the emitter of transistor Q4. The emitter of transistor Q4 is connected to the collector of transistor Q3, and the base of transistor Q4 is connected to the collector of transistor Q4. The collector of transistor Q4 is grounded. The output circuit (233) includes MOSFET M30, MOSFET M31, and port VOUT; The drain of MOSFET M30 is connected to port VOUT, the gate of MOSFET M30 is connected to the drain of MOSFET M30, and the source of MOSFET M30 is connected to the drain of MOSFET M31; the drain of MOSFET M31 is connected to the source of MOSFET M30, the gate of MOSFET M31 is connected to the gate of MOSFET M30, and the source of MOSFET M31 is grounded.

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