Dual compression in memory devices

Abstract

Various applications may include memory devices that implement a dual compression scheme. A memory subsystem of the memory device may be arranged into a plurality of regions. A first region of the memory subsystem may be used to store incompressible data. The second region may be used to store compressible data. The second region may have a first sub-region and a second sub-region. The first sub-region may be used to accept compressible data as non-compressed data corresponding to a compression ratio less than a threshold compression ratio. The second sub-region may be used to accept compressed data corresponding to a compression ratio greater than the threshold compression ratio. Additional apparatus, systems, and methods are disclosed.

Description

Technical Field

[0001] Embodiments of the present disclosure relate generally to electronic devices, and more particularly, to storage memory devices and operations thereof. Background Art

[0002] Memory devices are typically provided as internal semiconductor integrated circuits in computers or other electronic devices in various manufactured products. There are many different types of memory, including volatile and non-volatile memory. Volatile memory requires power to maintain its data, and examples of volatile memory include random access memory (RAM), dynamic random access memory (DRAM), static RAM (SRAM), or synchronous dynamic random access memory (SDRAM), etc. Non-volatile memory can retain stored data when power is not supplied, and examples of non-volatile memory include flash memory, read-only memory (ROM), electrically erasable programmable ROM (EEPROM), erasable programmable ROM (EPROM), resistance variable memory (such as phase change random access memory (PCRAM)), resistive random access memory (RRAM), magnetoresistive random access memory (MRAM), and three-dimensional (3D) XPoint TM Memory, etc.

[0003] Various types of memory may be used in applications where manufacturers of consumer products use a memory device architecture that may include one or more memory subsystems with multiple individual storage memory media, where the memory device interacts with a host device to store user data in the one or more memory subsystems of the memory device. The host device and the memory device may operate using one or more protocols that may include standardized protocols. The operation and properties of the memory devices and other electronic devices in the system may be improved by enhancing the programming and design of these electronic devices for their introduction into the system where the electronic devices are desired. Summary of the invention BRIEF DESCRIPTION OF THE DRAWINGS

[0004] The drawings, which are not necessarily drawn to scale, generally illustrate the various embodiments discussed in this document by way of example and not limitation.

[0005] Figure 1 An example effect of compression with a compression ratio threshold equal to 2 is illustrated according to various embodiments.

[0006] Figure 2 An example storage medium of a memory device arranged into multiple regions according to various embodiments is illustrated.

[0007] Figure 3 Description of various embodiments Figure 2 An example of defragmentation of a sub-area of ​​a storage medium.

[0008] Figure 4 Representations of an example system including a memory device implementing a double compression ratio scheme are illustrated in accordance with various embodiments.

[0009] Figure 5 is a graph of expansion of memory capacity as a function of the fraction of modes having a compression ratio of at least 2 according to various embodiments.

[0010] Figure 6 is a graph of expansion of memory capacity as a function of the fraction of modes for different compression ratios according to various embodiments.

[0011] Figure 7 is a flow diagram of features of an example method of directing data within a memory device in accordance with various embodiments.

[0012] Figure 8 is a flow chart of features of an example method of operating a memory device according to various embodiments.

[0013] Fig. 9 A block diagram illustrating example component features of a compute fast link system including a dual compression scheme for user data in accordance with various embodiments.

[0014] Fig.10 Description of various embodiments Fig. 9 An instance of a compression zone manager for a computationally fast link controller.

[0015] Fig.11 Description of various embodiments Figure 7 An embodiment of an instance of a table manager of a compression zone manager.

[0016] Fig.12 is a block diagram of an example system including a host operating with a memory device having one or more memory media, wherein the memory device may implement a dual compression scheme for user data, according to various embodiments. DETAILED DESCRIPTION

[0017] The following detailed description refers to the accompanying drawings, which show various embodiments in which the present invention can be practiced by way of illustration and not limitation. These embodiments are described in sufficient detail to enable those skilled in the art to practice these and other embodiments. Other embodiments may be utilized, and structural, logical, mechanical and electrical changes may be made to these embodiments. The various embodiments are not necessarily mutually exclusive, because some embodiments may be combined with one or more other embodiments to form new embodiments. Therefore, the following detailed description should not be understood in a limiting sense.

[0018] In order to improve physical space utilization in a memory device, a data compression feature may be implemented in the memory device to compress data received from a host. The memory device may include one or more memory media to store user data. This feature may be structured to compress data when writing host data and decompress the compressed data when reading in response to a host read request. Compression of user data may change the target capacity of the memory device and provide better physical capacity utilization compared to a memory device without compression. Compression may be characterized by a data compression ratio or simply a compression ratio (CR), which may depend on the properties of the data blocks used as the basis for storing data in the memory device. CR is defined herein as the ratio between the uncompressed size of a given data set and the compressed size of a given data set.

[0019] The memory devices may be implemented in a number of different memory device architectures. For example, compression may be performed in, but not limited to, a compute express link (CXL) memory device, a solid state drive (SSD), or other memory device. One or more memory devices may be coupled to a host (for example, a host computing device) to store data, commands, and / or instructions for use by the host when the computer or electronic system is operating. Data, commands, or instructions may be transferred between the host and the one or more memory devices during operation of the computing or other electronic system.

[0020] Various protocols or standards may be applied to facilitate communication between a host and one or more other devices (e.g., memory devices, memory buffers, accelerators, or other input / output devices). For example, an out-of-order protocol such as CXL may be used to provide high bandwidth and low latency connectivity. Other protocols may be used in place of or in conjunction with CXL.

[0021] CXL is an open standard interconnect configured for high-bandwidth, low-latency connectivity between host devices and other devices, such as accelerators, memory buffers, and other input / output (I / O) devices. CXL is designed to facilitate high-performance computing workloads by supporting heterogeneous processing and memory systems. CXL implements coherency and memory semantics on top of Peripheral Component Interconnect Express (PCIe)-based I / O semantics to optimize performance.

[0022] CXL can be used in applications such as artificial intelligence, machine learning, analytics, cloud infrastructure, edge computing devices, communication systems, and elsewhere. Data processing in such applications can use various scalar, vector, matrix, and spatial architectures that can be deployed in central processing units (CPUs), graphics processing units (GPUs), field programmable gate arrays (FPGAs), digital signal processors (DSPs), application specific integrated circuits (ASICs), other programmable logic devices, intelligent network interface cards (NICs), or other accelerators that can be coupled using CXL links. Processing modules such as CPUs can be implemented as host devices or host processors in the architecture of structured CPUs.

[0023] CXL supports dynamic multiplexing using a set of protocols including input / output (CXL.io, based on PCIe), cache (CXL.cache), and memory (CXL.memory) semantics. CXL can be used to maintain a unified, consistent memory space between the CPU and any memory on an attached CXL device. This configuration allows the CPU and CXL devices to share resources and operate on the same memory region to improve performance, reduce data movement, and reduce software stack complexity. In an example, the CPU may be primarily responsible for maintaining or managing consistency in a CXL environment. Therefore, CXL can be utilized to help reduce device cost and complexity, as well as the overhead traditionally associated with consistency across I / O links.

[0024] CXL runs on top of the PCIe physical layer (PHY) and provides full interoperability with PCIe. CXL devices can start link training from PCIe Gen 1 data rates and can negotiate CXL as their operating protocol if their link partner supports CXL. CXL can be used as an operating protocol, for example, using the alternative protocol negotiation mechanism defined in the PCIe 5.0 specification. As a result, devices and platforms can more easily adopt CXL by leveraging the PCIe infrastructure without having to design and validate PHYs, channels, channel extension devices, or other upper layers of PCIe.

[0025] CXL technology can maintain memory consistency between the CPU memory space and the memory on the attached device, which enables resource sharing to improve performance, reduce software stack complexity and reduce overall system cost. Three main types of devices can adopt the CXL interconnect protocol. Type 1 devices may include accelerators, such as smart NICs that typically lack local memory. Via CXL, these type 1 devices can communicate with the memory of the host processor to which they are coupled. Type 1 devices can use CXL.io+CXL.cache protocols. Type 2 devices may include GPUs, ASICs, and FPGAs, which are equipped with tools such as but not limited to double data rate (DDR) memory or high bandwidth memory (HBM) and can use CXL to make the host processor's memory locally available to the accelerator and the accelerator's memory locally available to the host processor. Type 2 devices can also be co-located in the same cache coherent domain and help improve heterogeneous workloads. Type 2 devices can use CXL.io+CXL.cache+CXL.memory protocols. Type 3 devices may include memory devices that can be attached via CXL to provide additional bandwidth and capacity to the host processor. The type of memory is independent of the host's main memory. Type 3 devices can use the CXL.io+CXL.memory protocol.

[0026] In various embodiments, a CR threshold (CR th ), and only if the pattern of the compressed data has CR ≥ CR th The data pattern can be compressed for storage. Optionally, with CR th The comparison can be set to whether the compressed data has CR>CR th If CR <CR th , then the data compressed for the compression calculation can be stored in its original version as uncompressed data. In general, if CR is at least equal to CR th If the number of typical application modes is large, this approach may provide interesting benefits. th Can be set to the value 2 or a power of 2. A power of 2 is of the form 2 n where n is an integer. For example, CR th It can be but not limited to 4 or 8. This scheme is a double compression scheme. Depending on the memory device, multiple compression procedures other than the double compression scheme can be implemented.

[0027] Figure 1 DescriptionCR th=2. A pattern 101 of size B is received from a host device for storage in a memory medium, and the compressed pattern may be a saturated pattern 102 to B or a saturated pattern 104 to B / 2. If 50% of the host patterns can be compressed with CR≥2, then the capacity of the memory medium available to the host device is increased by 33% relative to the original capacity of the memory medium. This increase may be demonstrated in the following manner. In the case where a total of N patterns of size B is the amount that can be stored in the medium, the total number of patterns that can be stored in the same medium may be given by N' in the following numerical evaluation, where 50% of the patterns are compressed with CR=2 and 50% of the patterns are not compressed.

[0028] NB=(N' / 2)B+(N' / 2)(B / 2)

[0029] N' / N=4 / 3,

[0030] This indicates that N' is 33% greater than N.

[0031] Figure 2 An embodiment of an example memory medium 200 of a memory device arranged into multiple zones is described. The memory medium 200 may include two zones defined as an uncompressed (U) zone 205 and a compressed (C) zone 210. Each of the multiple zones may be defined by a set of consecutive physical addresses (PA) for each of the multiple zones, and the progression from one of the multiple zones to the next zone follows the PA of one zone to the next PA in the next zone. With respect to the memory device, the address and page supplied by the host are virtual addresses (VAs) and virtual pages (VPs), which are mapped to PAs by the memory device. PAs are addresses used by the memory device to point to a memory medium (e.g., a memory die or a packaged memory die), a row, and a column to store one or more bits of data, where the pointing mechanism may include calculations that depend on the type of memory used for the memory medium. The U zone 205 and the C zone 210 may be defined when the memory device is powered on. The establishment of multiple zones may be performed at the initial power-on in the life of the memory device. The generation of multiple zones may be performed by a controller of the memory device executing instructions stored in the memory device.

[0032] The C region 210 may be arranged into a plurality of sub-regions. The plurality of sub-regions of the C region 210 may include two sub-regions (S1 sub-region 215 and S2 sub-region 220), wherein the sub-regions are determined by a threshold compression ratio CR th Effectively defined. CR th It can be a power of 2. A sub-region 225 can be generated between the S1 sub-region 215 and the S2 sub-region 220. The S1 sub-region 215 can be composed of CR th Defined as an area that accepts data as uncompressed data, for which the CR of the data in S1 sub-area 215 is less than CR th , which is CR <CR thThe uncompressed data in the S1 sub-area 215 is the compressible data that is selectively not compressed for storage. The S2 sub-area 220 may be composed of CR th Defined as a zone that accepts data in compressed format for which the CR of the compressed data is greater than the CR th , which is CR ≥ CR th Optionally, depending on design considerations, the controller of the memory device may use CR=CR th to set data as part of S1 subarea 215 or S2 subarea 220. Subarea 225 may be formed as an area of ​​storage medium 200 where data is not actively stored as part of subarea 225, but may be used for defragmentation of S1 subarea 215 or S2 subarea 220.

[0033] The U region 205 may be located at PAs ranging from the 0th PA to and including the (N-1)th PA (PA[0, N-1]) in the memory medium 200, where N may be defined when the memory device of the memory medium 200 is powered on. The S1 sub-region 215 may be defined starting from the Nth PA immediately following the (N-1)th PA. The S2 sub-region 220 may be defined starting from the (M-1)th PA, where M is the total number of PAs in the memory medium 200.

[0034] The S1 sub-region 215, the S2 sub-region 220, and the sub-region 225 may have different sizes. The S1 sub-region 215 is increased by increasing the PA of the uncompressed data added to the S1 sub-region 215. The S1 sub-region 215 has a current upper boundary indicated and tracked by a pointer P, where the upper boundary is defined relative to the value of the PA of the S1 sub-region 215. The S2 sub-region 220 is increased by decreasing the PA of the compressed data added to the S2 sub-region 220. The S2 sub-region 220 has a current lower boundary indicated and tracked by a pointer Q, where the lower boundary is defined relative to the value of the PA of the S2 sub-region 220. If the difference 227 between the values ​​of the pointers Q and P is less than a specified limit ((QP)<specified limit), then the defragmentation process of the S1 sub-region 215 or the S2 sub-region 220 may be triggered.

[0035] Figure 3 illustrate Figure 2 200 of the storage medium 200. Defragmentation in storage media (which may be referred to as defragmentation) is the compaction of storage media. Defragmentation is the process of freeing up storage space. Figure 3, the S1 sub-region 215 has an invalid page 317, and the S2 sub-region 220 has an invalid page 322. The invalid page 317 is removed, and the valid data of the S1 sub-region 215 below the PA of the invalid page 317 is moved up to the PA of the invalid page 317, and the pointer P is moved up. The invalid page 322 is removed, and the valid data of the S2 sub-region 220 above the PA of the invalid page 322 is moved down to the PA of the invalid page 322, and the pointer Q is moved down. The difference 227 between the pointer Q and the pointer P increases. This defragmentation can be straightforward because the invalid location can be easily replaced with a valid block at a higher position in the S1 sub-region 215 or a lower position in the S2 sub-region 220.

[0036] In the case where the CR of the compressed data is equal to 2 or a power of 2 (e.g., 4 or 8), addressing can be similar to addressing using a logical to physical (L2P) table. Simplification can also be attributed to using an effective compression ratio CR th The S2 sub-region 220 grows from top to bottom. A disadvantage may occur when the average CR value is low, for example, all received data have CR <CR th , resulting in uncompressed data.

[0037] Figure 4 A representation of an embodiment of an example system 400 is illustrated that includes a memory device 440 that implements a dual compression ratio scheme. The system 400 includes a host device 435 that transmits data to the memory device 440 via a link 450. The memory device 440 may be structured with a memory controller 445 that is coupled to a memory subsystem 442 via a link 457 to communicate with the memory device 440. Figure 2 and 3 The memory controller 445 may include a compressor / decompressor 459, a CR calculation 412, and a zone management 430. Each of the compressor / decompressor 459, the CR calculation 412, and the zone management 430 may be implemented by one or more hardware to hold and process data or stored instructions executable by the processing circuitry of the memory controller 445 to perform the corresponding functions of the dual compression scheme to store data from the host device 435 to the memory subsystem 442.

[0038] The zone management 430 may be structured to include an uncompressed zone for accepting incompressible data, a zone for accepting a zone in response to a CR less than CR for compressible data, and a zone for accepting a zone in response to a CR less than CR for compressible data. th The sub-area of ​​the non-compressed compressible data and the CR for responding to the compressed data is greater than or equal to CR thThe sub-area that accepts compressed data controls the storage of data in the memory subsystem 442. The incompressible data in the uncompressed area is data that is identified as data that will not be compressed. Identification can be provided in the communication between the host device 435 and the memory device 440. The uncompressed area that accepts incompressible data can be communicated with Figure 2 and 3 The sub-area that accepts compressible data as uncompressed data may be the same as or similar to the U area 205 of the storage medium 200 of FIG. Figure 2 and 3 The subarea receiving compressed data may be structured the same as or similar to the S1 subarea 215 of the storage medium 200. Figure 2 and 3 The zone management 430 may include CR th 432 , a manager for uncompressed areas (U MNG) 406 , a manager for sub-areas that accept compressible data as uncompressed data (S1 MNG) 416 , a manager for sub-areas that accept compressed data (S2 MNG) 426 , an L2P table 434 , and an invalid (INV) bitmap 436 .

[0039] U MNG 406 may manage data received from host device 435 that will not be compressed. U MNG 406 may use line 407 or other mechanisms to mark data that will not be compressed. Since the data will not be compressed, the original version 409-1 of the received data that will not be compressed may be stored in memory subsystem 442 via link 457.

[0040] S1 MNG 416 can manage compressible data received from host device 435 and can manage the storage of this compressible data as uncompressed data in memory subsystem 442 via link 457. The received compressible data is compressed by compressor / decompressor 459, and a CR is generated for the received compressible data using CR calculation 412. The generated CR is compared to the data stored in CR. th CR in 432 th The comparison can be done by calculating CR 412 or CR th 432. In response to determining from the comparison that the generated CR is less than CR th , the original version 409-2 of the compressible data may be stored in the memory subsystem 442. th The S1 MNG 416 may be provided for use in managing the compressible data, which may include interacting with the compressor / decompressor 459 via line 418 or other mechanism to mark this compressible data as storable as the original version 409-2.

[0041] S2 MNG 426 can manage compressible data received from host device 435 and can manage the storage of this compressible data as compressed data in memory subsystem 442 via link 457. The received compressible data is compressed by compressor / decompressor 459, and a CR is generated for the received compressible data using CR calculation 412. The generated CR is compared with the data stored in CR. th CR in 432 th The comparison can be done by calculating CR 412 or CR th 432. In response to determining from the comparison that the generated CR is greater than or equal to CR th , the original version is compressed to provide a compressed version 409-3, and can be stored in the memory subsystem 442. th The S2 MNG 416 may be provided for use in managing the compressed data, which may include interacting with the compressor / decompressor 459 via line 421 or other mechanism to mark this compressible data as storable as a compressed version 409-3.

[0042] The S1 MNG 416 may be configured to manage a region of the memory subsystem 442 that contains compressible data as non-compressed data about invalid pages and a boundary pointer for this region. The invalidity of the pages in this region may be tracked in the INV bitmap 436, and the PA of the pages may be tracked in the L2P table 434. The L2P table 434 stores the L2P mapping to access the correct data in the memory subsystem 442. The INV bitmap 436 may store a bitmap of invalid blocks and may facilitate defining the L2P mapping of the L2P table 434. The S1 MNG 416 may use the INV bitmap 436 and the L2P table 434 to control the defragmentation of the region that contains compressible data as non-compressed data. The S1 MNG 416 may update the boundary pointer for this region.

[0043] S2 MNG 426 may be configured to manage a region of memory subsystem 442 containing compressed data about invalid pages and a boundary pointer for this region. The invalidity of pages in this region may be tracked in INV bitmap 436, and the PA of the pages may be tracked in L2P table 434. S2 MNG 426 may control defragmentation of the region containing compressed data using INV bitmap 436 and L2P table 434. S2 MNG 416 may update the boundary pointer for this region.

[0044] The zone management 430 may use the boundary pointers maintained by the S1 MNG 416 and S2 MNG 426 to initiate defragmentation in the S1 MNG 416 and S2 MNG 426. The initiation of defragmentation may be triggered by the difference between the two boundaries being less than a specified limit. The boundary may be the end PA of the contiguous PAs of the two zones.

[0045] The uncompressed area, compressible area, and compressed area of ​​the memory subsystem 442 may be arranged between the columns and channels of the memory subsystem 442, wherein the PAs associated with these areas are arranged as continuous areas. The uncompressed data of the uncompressed area, the non-compressed data of the compressible sub-area, and the compressed data of the compressed area of ​​the memory subsystem 442 may be provided to the host device 453 via the link 450. The data of each format may be processed by the compressor / decompressor 459 before being transmitted via the link 450. Alternatively, the uncompressible data and the non-compressed data may be provided to the link 450 bypassing the compressor / decompressor 459.

[0046] Figure 5 is a graph of the expansion (E) of the memory capacity as a function of the fraction (r) of patterns with a compression of at least 2. As previously mentioned, in the case where 50% of the patterns are compressed with a CR of at least 2, the resulting expansion is 33%. In general, it is assumed that r is the fraction of patterns compressed with a CR of at least 2. In the case where a total of N patterns of size B is the amount that can be stored in the medium, the total number of patterns that can be stored in the same medium can be given by N' in the following numerical evaluation, where a given percentage of patterns are compressed with a CR=2 and (1-the given percentage) of patterns are not compressed.

[0047] NB=(1-r)N'B+rN'(B / 2),

[0048] This provides

[0049] (N' / N)=1 / (1–r+(r / 2))=2 / (2-r)

[0050] The expansion of capacity is given by

[0051] E=(2 / (2-r)–1)=r / (2-r).

[0052] Figure 6 is a graph of the expansion (E) of the memory capacity as a function of the fraction (r) of patterns for different CRs. By substituting different CRs for CR=2 in the above equation, the following relationship emerges.

[0053] NB=(1-r)N'B+rN'(B / CR),

[0054] This provides

[0055] N' / N=1 / (1–r+(r / CR)=CR / (CR–(CR-1)r)

[0056] The expansion of capacity is given by

[0057] E=CR / (CR–(CR-1)r)-1=(CR–1)r / (CR–(CR-1)r).

[0058] Figure 7 7 is a flow chart of features of an embodiment of an example method 700 for routing data within a memory device. The method 700 may be implemented by a controller of the memory device. The controller may execute instructions stored in one or more components of the memory device to route data within the memory device. The controller may be implemented by a processing circuit system, which may include but is not limited to one or more processing devices. At 710, data is received from a host device at a memory device. The data may be received at different time periods. At 720, a first portion of the data is routed to a first sub-region of a compressible designated region of a memory subsystem of the memory device as uncompressed data. This routing is based on the first CR being less than the CR th The compressible designated area is defined to store user data, which is compressible data that is not marked as uncompressible. The first CR is a compression of the first portion of the data, wherein the first CR may be determined before directing the first portion to the first sub-area.

[0059] At 730, the second portion of the data is directed to a second sub-area of ​​the compressible designated area as compressed data. This routing is based on the second CR being greater than the CR after compressing the second portion of the data. th The second CR is a compression of the second portion of the data, wherein the second CR may be determined before directing the second portion to the second sub-area. In response to the CR of the third portion of the data being equal to the CR th , the third part can be directed to the second sub-area or the first sub-area. th In case of 2, 4 or 8, the third part can be directed to the second sub-area.

[0060] Method 700 or variations of methods similar to method 700 may include a number of different embodiments that may be combined depending on the application of such methods and / or the architecture of systems including electronic devices implementing such methods. Such methods may include directing another portion of the data to an area of ​​the memory subsystem as incompressible data, wherein the area is designated to store incompressible data. The incompressible data includes data designated to be not compressed. Directing the another portion of the data may be performed based on identifying that the another portion of the data from the host device is marked as data to be not compressed. Variations may include CR th Set equal to a power of 2.

[0061] Figure 88 is a flow chart featuring an embodiment of an example method 800 of operating a memory device. The method 800 may be implemented by a controller of a memory device. The controller may execute instructions stored in one or more components of the memory device to operate the memory device. The controller may be implemented by a processing circuit system, which may include but is not limited to one or more processing devices. At 810, a memory subsystem is arranged to have an uncompressed area and a compressed area. The uncompressed area is configured to store incompressible data, and the compressed area is configured to store compressible data. The incompressible data includes data that is designated as not to be compressed.

[0062] At 820, the compression region is arranged to include a first sub-region and a second sub-region. The first sub-region is arranged to accept a first CR less than CR th The second sub-area is arranged to accept non-compressed data corresponding to a second CR greater than CR th The first CR is a compression of the first portion of the data, wherein the first CR may be determined before directing the second portion to the second sub-area. The second CR is a compression of the second portion of the data, wherein the second CR may be determined before directing the second portion to the second sub-area. In response to the CR of another portion of the data being equal to the CR th , depending on the architecture of the memory device, this further portion may be directed to the second sub-area or the first sub-area. th In case of 2, 4 or 8, another part may be directed to the second sub-area.

[0063] At 830, data received from the host device is directed to one of the uncompressed area, the first sub-area, or the second sub-area. The routing of the data to one of the three areas may be based on the CR of the received data. The CR may be determined before directing the data to the storage device and may be related to the CR. th Make a comparison.

[0064] Method 800 or variations of methods similar to method 800 may include multiple different embodiments, which may be combined depending on the application of such methods and / or the architecture of systems including electronic devices implementing such methods. Such methods may include defining an uncompressed area and a compressed area when a memory device is powered on. The memory device may have a total of M PAs, where M is a positive integer. The uncompressed area may be located in a PA from the 0th PA to and including the (N-1)th PA, where N is a positive integer. When the memory device is powered on, a first sub-area may be defined as starting from the Nth PA and a second sub-area may be defined as starting from the (M-1)th PA. The range of PAs of the memory device is continuous from the 0th PA to the Nth PA to the (M-1)th PA.

[0065] Method 800 or a variation of a method similar to method 800 may include arranging a compressed area to include arranging a third sub-area between a first sub-area and a second sub-area. The third sub-area may have a first boundary at an end of the first sub-area opposite the uncompressed area, and a second boundary at the beginning of the second sub-area. In operation, the first sub-area may be increased by increasing the PA from the first boundary, and the second sub-area may be increased by decreasing the PA from the second boundary. A first pointer may be set at the first boundary, and a second pointer may be set at the second boundary. The first pointer and the second pointer may be used to control the initiation of defragmentation of the compressed area. Defragmentation of the compressed area may be initiated in response to a difference between the value of the second pointer and the value of the first pointer being less than a specified limit.

[0066] Fig. 9 is a block diagram of an embodiment of example component features of a CXL system 900 including a dual compression scheme for user data. The CXL system 900 may include a CXL host 935 and a CXL memory device 940 that may operate according to the CXL protocol. The CXL memory device 940 may include a controller 945 that interfaces with the CXL host 935 and a medium 942 of the CXL memory device 940 to write user data directed from the CXL host 935 to the medium 942 using one or more write requests, and to read user data for the CXL host 935 from the medium 942 using one or more read requests. As taught herein, execution of the write request may be performed using the dual compression scheme. Execution of the read request may be performed to retrieve user data from a region of the medium 942, where the region has been defined in an implementation of the dual compression scheme. The dual compression scheme may provide a relatively high-speed method to store data with compression suitable for the CXL memory device 940.

[0067] The controller 945 may include a CXL front end (FE) 941 that interfaces with the CXL host 935 using the CXL protocol and a cache manager 943 that manages user data flows associated with read and write requests received from the CXL host 935. The user data may be stored in a medium 942, where the medium 942 may be structured as one or more memory structures arranged as channels for data storage. The user data may be processed with an Advanced Encryption Standard (AES) 947 and ECC 948. Processing the user data with the ECC 948 may be performed by a memory controller (MC) and an interface (INF) 949 that controls input and output of the user data with respect to the medium 942. The user data operated by the AES 947, the ECC 948, and the MC&INF 949 may be compressed data. Compressing the user data and decompressing the user data may be controlled by a compression region manager (CRM) 946.

[0068] Fig.10 illustrate Fig. 9946. The CRM 946 may include a read buffer 1051 to handle user data for read requests and a write buffer 1053 to handle user data for write requests. The read buffer 1051 and the write buffer 1053 may be first-in-first-out (FIFO) structures, which may be implemented in a number of formats including one or more registers or one or more other buffer structures that may cache user data. Data from the read buffer 1051 and the write buffer 1053 may be directed to a table manager 1055 and compression logic 1059 via a multiplexer (MUX) 1052. The CRM 946 also includes a decompression logic 1058 to decompress received compressed read data using logic circuitry within the decompression logic 1058, wherein the compressed read data is compressed data received from the media 942 in response to the read request. If the input user data meets the compression criteria, the compression logic 1059 may use the received compression ratio data to compress the input user data using logic circuitry within the compression logic 1059. The criteria may be provided in the compression ratio data or from the table manager 1055. The compression logic 1059 may provide the compressed data to the table manager 1055, which may output the compressed data, or may alternatively or in conjunction with the table manager 1055 output the compressed data. The compression logic 1059 may also provide the compression ratio data for subsequent operations associated with compression. The compression logic 1059 may be structured to perform compression calculations. In addition to operating on the output of read / write compressed data, the table manager 1055 may also operate on read / write map data to receive and output read / write map data. The table manager 1055 may be operable to manage a dual compression scheme with compressed data as taught herein.

[0069] Fig.11 illustrate Fig.10 1055 of the CRM 946 of the embodiment of the present invention. The table manager 1055 may include registers 1162. The registers 1162 may be a FIFO structure, which may be implemented in a number of formats including one or more register structures or one or more other buffer structures that can hold data. The table manager 1055 may include one or more tables (table(s)) 1167. The table(s) 1167 may include tables for mapping and looking up information about cached data and updating mappings associated with read and write requests. The table(s) 1167 may include sub-region management 1130, which may be associated with Figure 4430 of . Table(s) 1167 may operate with free space manager (FSM) 1165 and sub-region management 1130 to make the PA available for invalidation processes, including evicting data pages from identified memory locations in response to write operations, as taught herein. Table(s) 1167 may include a mapping table that may update information translating received VAs with associated PAs. Frequently read data may be cached, and table(s) 1167 may be used to determine if such data is currently part of a read or write (read / write) request. Determining current data for a cached read / write request is a hit, and determining current data for an uncached read / write request is a miss. Table(s) 1167 may provide data from lookup hit data, data from lookup miss data, and data for page evictions associated with mappings for write operations.

[0070] Fig.12 is a block diagram of an embodiment of an example system 1200 including a host device 1235 operating with a memory device 1240 having one or more memory media, wherein the memory device 1240 may implement a dual compression scheme for user data in an application implementing the memory device 1240. Figure 2 and 3 Related technologies, Figure 7 and Figure 8 methods and Figures 9 to 11 The system 1200 and its components may be structured in a number of different arrangements. For example, the system 1200 may be arranged with various types of components, including a host device 1235, an interface 1250, a memory device 1240, memory media 1242-1, 1242-2, 1242-3, 1242-4, 1242-5, and 1242-6, a processing device 1245, one or more buffers 1254, firmware 1255, a storage device 1244, and a bus 1257.

[0071] Host device 1235 is coupled to memory device 1240 through interface 1250, wherein host device 1235 is a host device that may include one or more processors that may vary in type compatible with interface 1250 and memory device 1240. Memory device 1240 may include processing device 1245 coupled to memory media 1242-1, 1242-2, 1242-3, 1242-4, 1242-5, and 1242-6 through bus 1257, wherein each memory medium has one or more memory cell arrays. Memory media 1242-1, 1242-2, 1242-3, 1242-4, 1242-5, and 1242-6 may be implemented as a memory structure that may be selected from different types of memory. Although in Fig.12 12 shows six memory media, but memory device 1240 may be implemented with more or less than six memory media, i.e., memory device 1240 may include one or more memory media. The memory media may be implemented in a variety of formats including, but not limited to, multiple memory dies or multiple packaged memory dies.

[0072] Processing device 1245 may include processing circuitry or be structured as one or more processors. Processing device 1245 may be structured as a memory system controller for memory device 1240. Processing device 1245 may be implemented in a variety of different formats. Processing device 1245 may include or be structured as one or more types of processors compatible with memory media 1242-1, 1242-2, 1242-3, 1242-4, 1242-5, and 1242-6. Processing device 1245 may include processing circuitry that may be structured with a DSP, an ASIC, other types of processing circuitry including a processor group or a multi-core device, or a combination thereof.

[0073] Memory device 1240 may include firmware 1255 having code executable by processing device 1245 to manage at least memory media 1242-1, 1242-2, 1242-3, 1242-4, 1242-5, and 1242-6. Firmware 1255 may reside in a storage device of memory device 1240 coupled to processing device 1245. Firmware 1255 may be coupled to processing device 1245 using bus 1257 or some other interface on memory device 1240. Alternatively, firmware 1255 may reside in processing device 1245 or may be distributed in memory device 1240 along with firmware components (e.g., but not limited to, code, including one or more components in processing device 1245). The firmware 1255 may include code having instructions executable by the processing device 1245 to operate on the memory media 1242-1, 1242-2, 1242-3, 1242-4, 1242-5, and 1242-6. The instructions may include instructions for performing operations to store user data as compressed data on one or more of the memory media 1242-1, 1242-2, 1242-3, 1242-4, 1242-5, and 1242-6 using a dual compression scheme as taught herein.

[0074] Memory device 1240 may include storage device 1244, which may be implemented to provide data or parameters used in the maintenance of memory device 1240. Storage device 1244 may include one or more of a non-volatile memory structure or RAM. Although storage device 1244 is Fig.121240, but the storage device 1244 may be integrated into the processing device 1245. The storage device 1244 may be coupled to the bus 1257 for communication with other components of the memory device 1240. Alternatively, the storage device 1244 may be coupled to the processing device 1245, where the processing device 1245 handles communications between the storage device 1244 and the other components of the memory device 1240. The storage device 1244 may be coupled to the bus 1257 and the processing device 1245.

[0075] Each of the memory media 1242-1, 1242-2, 1242-3, 1242-4, 1242-5, and 1242-6, firmware 1255, storage device 1244, and other memory structures of memory device 1240 are implemented as machine-readable media. Non-limiting examples of machine-readable media may include solid-state memory, optical media, and magnetic media. Specific examples of non-transitory machine-readable media may include nonvolatile memory, such as semiconductor memory media (e.g., EPROM, EEPROM), and flash memory devices; magnetic disks, such as internal hard disks and removable magnetic disks; magneto-optical disks; and compact disk-ROM (CD-ROM) and digital versatile disk read-only memory (DVD-ROM) disks.

[0076] Firmware 1255, storage device 1244, or other components of memory device 1240 may include hardware or instructions to implement and Figure 2 and 3 The firmware 1255, storage device 1244, or other components of the memory device 1240 may have instructions executable by the processing device 1245 to operate on user data to store the user data in one or more of the memory media 1242-1, 1242-2, 1242-3, 1242-4, 1242-5, and 1242-6 in a compressed format according to the dual compression scheme, as taught herein. The firmware 1255, storage device 1244, or other components of the memory device 1240 may have instructions executable by the processing device 1245 to operate on incompressible data, non-compressed data, and compressed user data to read and generate uncompressed user data from one or more of the memory media 1242-1, 1242-2, 1242-3, 1242-4, 1242-5, and 1242-6.

[0077] The processing device 1245 may execute instructions stored on one or more components in the memory device 1240, which, when executed by the processing device 1245, cause the memory device 1240 to perform operations. The operations may include operations of method 700, method 800, methods similar to method 700 or method 800 and associated with these methods, and operations associated with Figures 2 to 4 And the functions of the structures associated with 9 to 11.

[0078] The operation may include an operation to direct data within the memory device 1240. The operation to direct data within the memory device 1240 may include receiving data at the memory device 1240 from the host device 1235. The operation may include directing a first portion of the data to a first sub-region of a compressible designated region of a memory subsystem of the memory device as uncompressed data. The memory subsystem may include one or more of the memory media 1242-1, 1242-2, 1242-3, 1242-4, 1242-5, and 1242-6. The routing may be based on the first CR being less than the CR th , wherein the compressible designated area is defined as storing user data that is compressible data. The operation may include directing a second portion of the data to a second sub-area of ​​the compressible designated area as compressed data. The routing of the compressed data may be based on the second CR being greater than the CR after compressing the second portion of the data. th .

[0079] The operation may include determining that the CR corresponding to the third portion is equal to the CR th Directs the third portion of the data to the second sub-area or the first sub-area. th Can be equal to a power of 2.

[0080] The operation may include directing the other portion of the data to a region of the memory subsystem as incompressible data, wherein the region is designated to store incompressible data.Directing the other portion of the data may be performed based on identifying that the other portion of the data from the host device 1235 is marked as data that is not to be compressed.

[0081] The processing device 1245 may execute instructions stored on one or more components in the memory device 1240 that, when executed by the processing device 1245, cause the memory device 1240 to perform operations. The operations may include operations of the memory device 1240 operating with respect to multiple regions of one or more of the memory media 1242-1, 1242-2, 1242-3, 1242-4, 1242-5, and 1242-6.

[0082] The operation may include arranging the memory subsystem to have an uncompressed area and a compressed area, wherein the uncompressed area is arranged to store incompressible data and the compressed area is arranged to store compressible data. The memory subsystem may include one or more of the memory media 1242-1, 1242-2, 1242-3, 1242-4, 1242-5, and 1242-6. The operation may include arranging the compressed area to include a first sub-area and a second sub-area. The first sub-area may be arranged to accept a data corresponding to a first CR less than CR thThe second sub-area may be arranged to accept data corresponding to a second CR greater than CR th The operation may include directing data received from the host device 1235 to one of the uncompressed area, the first sub-area, or the second sub-area.

[0083] Arranging the operation of the memory subsystem may include defining an uncompressed area and a compressed area when the memory device is powered on. Arranging the operation of the memory subsystem may include a memory device 1240 having a total of M PAs, M being a positive integer, and the uncompressed area is located in PAs from the 0th PA to and including the (N-1)th PA. When the memory device 1240 is powered on, the first sub-area may be defined to start from the Nth PA, and the second sub-area may be defined to start from the (M-1)th PA. The range of PAs may be continuous from the 0th PA to the Nth PA to the (M-1)th PA.

[0084] Arranging the memory subsystem operation may include arranging the compressed area by arranging the third subarea between the first subarea and the second subarea. The third subarea may have a first boundary at an end of the first subarea opposite the uncompressed area, and a second boundary at the beginning of the second subarea. The first subarea may be increased by increasing the PA from the first boundary, and the second subarea may be increased by decreasing the PA from the second boundary. Arranging the memory subsystem operation may include setting a first pointer at the first boundary and setting a second pointer at the second boundary, and controlling the initiation of defragmentation of the compressed area using the first pointer and the second pointer.

[0085] Arranging the operation of the memory subsystem may include initiating defragmentation of the compressed area in response to the difference between the value of the second pointer and the value of the first pointer being less than a specified limit. The defragmentation of the compressed area may be defragmentation of the first sub-area. The defragmentation of the compressed area may be defragmentation of the second sub-area. The defragmentation of the compressed area may be defragmentation of the first sub-area and the second sub-area.

[0086] Following are example embodiments of devices and methods according to the teachings herein.

[0087] The example memory device 1 may include a memory subsystem and a controller. The controller may be arranged to configure a first region of the memory subsystem to store incompressible data and a second region to store compressible data, the second region having a first subregion and a second subregion, the first subregion accepting a corresponding first CR less than CR th The second sub-area accepts non-compressed data corresponding to a second CR greater than the CR th of compressed data.

[0088] Example memory device 2 may include features of example memory device 1, and may include a controller arranged to respond to CR being equal to the CR thThe second sub-area is configured to accept compressed data or the first sub-area is configured to accept uncompressed data.

[0089] The example memory device 3 may include features of any of the foregoing example memory devices, and may include a controller configured to store data from a host device as uncompressed data in the first region in response to identifying that data from the host device is marked as data that is not to be compressed.

[0090] Example memory device 4 may include features of any of the foregoing example memory devices and may include defining the first region in the memory device when the memory device is initially powered on.

[0091] The example memory device 5 may include features of any of the foregoing example memory devices, and may include the CR th Equal to a power of 2.

[0092] Example memory device 6 may include features of any of the foregoing example memory devices, and may include the first sub-regions having different upper boundaries and the second sub-regions having different lower boundaries.

[0093] Example memory device 7 may include features of example memory device 6 and any of the foregoing example memory devices, and may include the controller being configured to initiate defragmentation in response to determining that a difference between the lower boundary and the upper boundary is less than a specified limit.

[0094] Example memory device 8 may include features of any of the aforementioned example memory devices and may include that the second region includes a third sub-region between the first sub-region and the second sub-region.

[0095] In example memory device 9, any of the memory devices of example memory devices 1-8 may include a memory device incorporated into an electronic device further including a host processor and a communication bus extending between the host processor and the memory device.

[0096] In example memory device 10, any of the memory devices of example memory devices 1-9 may be modified to include any structure presented in another of example memory devices 1-9.

[0097] In example memory device 11, any apparatus associated with the memory devices of example memory devices 1-10 may further include a machine-readable storage device configured to store instructions as a physical state, wherein the instructions may be used to perform one or more operations of the apparatus.

[0098] In example memory device 12, any of the memory devices of example memory devices 1-11 may operate according to any of the following methods 1-9 of directing data within a memory device and example methods 1-12 of operating a memory device.

[0099] An example method 1 for directing data in a memory device may include: receiving data at the memory device from a host device; based on a first CR being less than a CR th , directing a first portion of the data to a first sub-area of ​​a compressible designated area of ​​a memory subsystem of the memory device as uncompressed data, the compressible designated area being defined as storing user data that is compressible data; and after compressing a second portion of the data, based on a second CR being greater than the CR th , directing the second part of the data to a second sub-area of ​​the compressible designated area as compressed data.

[0100] Example method 2 for directing data in a memory device may include features of example method 1 for directing data in a memory device, and may include directing data in a memory device based on the CR corresponding to the third portion being equal to the CR th , directing the third part of the data to the second sub-area or the first sub-area.

[0101] Example method 3 of directing data within a memory device may include features of any of the foregoing example methods of directing data within a memory device, and may include directing another portion of the data to a region of the memory subsystem as incompressible data, the region being designated to store incompressible data.

[0102] Example method 4 of directing data within a memory device may include features of method 3 of directing data within a memory device and any of the foregoing example methods of directing data within a memory device, and may include directing the other portion of the data from the host device based on identifying that the other portion of the data is marked as data that is not to be compressed.

[0103] Example method 5 of directing data within a memory device may include features of any of the foregoing example methods of directing data within a memory device, and may include the CR th Equal to a power of 2.

[0104] In example method 6 of directing data within a memory device, any of example methods 1-5 of directing data within a memory device may be performed while operating an electronic device further comprising a host processor and a communication bus extending between the host processor and the memory device.

[0105] In example method 7 of directing data within a memory device, any of example methods 1-6 of directing data within a memory device may be modified to include operations set forth in any other of example methods 1-6.

[0106] In example method 8 of directing data within a memory device, any of example methods 1-7 of directing data within a memory device may be implemented at least in part by using instructions stored as a physical state in one or more machine-readable storage devices.

[0107] Example method 9 of directing data within a memory device may include features of any of the foregoing example methods 1-8 of directing data within a memory device, and may include performing functions associated with any features of example memory devices 1-12 of operating a memory device or directing data within a memory device.

[0108] An example method 1 of operating a memory device may include: arranging a memory subsystem to have an uncompressed area and a compressed area, the uncompressed area storing incompressible data and the compressed area storing compressible data; arranging the compressed area to include a first sub-area and a second sub-area, the first sub-area accepting a data corresponding to a first CR less than CR th The second sub-area accepts non-compressed data corresponding to the second CR greater than the CR th and directing data received from a host device to one of the uncompressed area, the first sub-area, or the second sub-area.

[0109] Example method 2 of operating a memory device may include features of example method 1 of operating a memory device, and may include defining an uncompressed region and a compressed region when the memory device is powered on.

[0110] Example method 3 for operating a memory device may include features of any of the aforementioned example methods for operating a memory device, and may include a memory device having a total of M PAs, M being a positive integer, the uncompressed area being positioned in a PA from the 0th PA to and including the (N-1)th PA, when the memory device is powered on, the first sub-area being defined as starting from the Nth PA, the second sub-area being defined as starting from the (M-1)th PA, and the range of the PAs being continuously from the 0th PA to the Nth PA to the (M-1)th PA.

[0111] Example method 4 of operating a memory device may include features of any of the aforementioned example methods of operating a memory device, and may include arranging the compressed region to include arranging a third subregion between the first subregion and the second subregion, the third subregion having a first boundary at an end of the first subregion opposite the uncompressed region and having a second boundary at the beginning of the second subregion.

[0112] Example method 5 of operating a memory device may include features of example method 4 of operating a memory device and any of the foregoing example methods of operating a memory device, and may include the first sub-region increasing by increasing the PA from the first boundary and the second sub-region increasing by decreasing the PA from the second boundary.

[0113] Example method 6 of operating a memory device may include features of example method 4 of operating a memory device and any of the foregoing example methods of operating a memory device, and may include setting a first pointer at the first boundary and setting a second pointer at the second boundary, and using the first pointer and the second pointer to control the initiation of defragmentation of the compressed area.

[0114] Example method 7 of operating a memory device may include features of example method 6 of operating a memory device and any of the foregoing example methods of operating a memory device, and may include initiating defragmentation of the compressed area in response to a difference between the value of the second pointer and the value of the first pointer being less than a specified limit.

[0115] In example method 8 of operating a memory device, any of example methods 1-7 of operating a memory device may be performed while operating an electronic device further including a host processor and a communication bus extending between the host processor and the memory device.

[0116] In example method 9 of operating a memory device, any of the example methods 1-8 of operating a memory device may be modified to include operations set forth in any other of the example methods 1-8 of operating a memory device.

[0117] In example method 10 of operating a memory device, any of example methods 1-9 of operating a memory device may be implemented at least in part by using instructions stored as a physical state in one or more machine-readable memory devices.

[0118] The example method 11 of operating a memory device may include features of any of the foregoing example methods 1-10 of operating a memory device, and may include performing functions associated with any features of the example memory devices 1-12.

[0119] Example method 12 of operating a memory device may include features of any of the foregoing example methods 1-11 of operating a memory device and example methods 1-9 of directing data within a memory device, and may include performing functions associated with any features of example memory devices 1-12.

[0120] An example machine-readable storage device storing instructions that, when executed by one or more processors, cause the machine to perform operations may include instructions to perform functions associated with any features of example memory devices 1-12 or to perform methods associated with example methods 1-9 of directing data within a memory device and any features of example methods 1-12 of operating a memory device.

[0121] Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that any arrangement calculated to achieve the same purpose may be substituted for the specific embodiments shown. Various embodiments use permutations and / or combinations of the embodiments described herein. It should be understood that the above description is intended to be illustrative and not limiting, and that the phrases or terms employed herein are for descriptive purposes.

Claims

1. A memory device, comprising: Memory subsystem; and A controller configures a first area of ​​the memory subsystem to store incompressible data and a second area to store compressible data, wherein the second area has a first sub-area and a second sub-area, the first sub-area accepting uncompressed data corresponding to a first compression ratio less than a threshold compression ratio, and the second sub-area accepting compressed data corresponding to a second compression ratio greater than the threshold compression ratio.

2. The memory device of claim 1, wherein the controller is arranged to configure the second sub-area to accept compressed data or to configure the first sub-area to accept uncompressed data in response to a compression ratio being equal to the threshold compression ratio.

3. The memory device of claim 1, wherein the controller is configured to store data from a host device as uncompressed data in the first region in response to identifying that data from the host device is marked as data that is not to be compressed.

4. The memory device of claim 1, wherein the first region is defined in the memory device upon initial power-up of the memory device.

5. The memory device of claim 1, wherein the threshold compression ratio is equal to a power of 2.

6. The memory device of claim 1, wherein the first sub-regions have different upper boundaries and the second sub-regions have different lower boundaries.

7. The memory device of claim 6, wherein the controller is configured to initiate defragmentation in response to determining that a difference between the lower boundary and the upper boundary is less than a specified limit.

8. The memory device of claim 1, wherein the second region includes a third sub-region between the first sub-region and the second sub-region.

9. A method of directing data in a memory device, the method comprising: receiving data at the memory device from a host device; directing a first portion of the data to a first sub-area of ​​a compressible designated area of ​​a memory subsystem of the memory device as uncompressed data based on the first compression ratio being less than a threshold compression ratio, the compressible designated area being defined to store user data that is compressible data; and After compressing the second portion of the data, based on a second compression ratio being greater than the threshold compression ratio, directing the second portion of the data to a second sub-area of ​​the compressible designated area as compressed data.

10. The method of claim 9, wherein the method includes directing a third portion of the data to the second sub-area or the first sub-area based on a compression ratio corresponding to the third portion being equal to the threshold compression ratio.

11. The method of claim 9, wherein the method includes directing another portion of the data to a region of the memory subsystem as incompressible data, the region being designated to store incompressible data.

12. The method of claim 11, wherein directing the another portion of the data is performed based on identifying the another portion of the data from the host device as data that is not to be compressed.

13. The method of claim 9, wherein the threshold compression ratio is equal to a power of 2.

14. A method of operating a memory device, the method comprising: arranging a memory subsystem to have an uncompressed area and a compressed area, the uncompressed area storing incompressible data and the compressed area storing compressible data; arranging the compression area to include a first sub-area accepting uncompressed data corresponding to a first compression ratio less than a threshold compression ratio and a second sub-area accepting compressed data corresponding to a second compression ratio greater than the threshold compression ratio; as well as Data received from a host device is directed to one of the uncompressed area, the first sub-area, or the second sub-area.

15. The method of claim 14, wherein the method includes defining the uncompressed area and the compressed area when the memory device is powered on.

16. The method of claim 14, wherein the memory device has a total of M physical addresses, M is a positive integer, the uncompressed area is located in physical addresses from the 0th physical address to and including the (N-1)th physical address, when the memory device is powered on, the first sub-area is defined as starting from the Nth physical address, the second sub-area is defined as starting from the (M-1)th physical address, and the range of the physical addresses is continuous from the 0th physical address to the Nth physical address to the (M-1)th physical address.

17. The method of claim 14, wherein arranging the compressed zone includes arranging a third sub-zone between the first sub-zone and the second sub-zone, the third sub-zone having a first boundary at an end of the first sub-zone opposite the uncompressed zone and having a second boundary at the beginning of the second sub-zone.

18. The method of claim 17, wherein the first sub-area increases by increasing a physical address from the first boundary, and the second sub-area increases by decreasing a physical address from the second boundary.

19. The method of claim 17, wherein the method includes setting a first pointer at the first boundary and setting a second pointer at the second boundary, and using the first pointer and the second pointer to control initiation of defragmentation of the compressed area.

20. The method of claim 19, wherein the method includes initiating defragmentation of the compressed area in response to a difference between a value of the second pointer and a value of the first pointer being less than a specified limit.

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