Online upgrading method for bootstrap program of multi-core microcontroller

Abstract

The invention discloses an online upgrading method for a multi-core microcontroller boot program, which comprises the following steps of: pointing a PC (Personal Computer) pointer to an RAM (Random Access Memory) before erasing FLASH, enabling a core B to sleep and wait for an instruction, when a core A has an upgrading request, receiving an IPC interrupt request by the core B, jumping the PC pointer to a storage area of an interrupt vector table, searching a corresponding IPC interrupt service function address, and updating the IPC interrupt service function address; and after the execution is finished, the PC pointer skips back to the RAM, so that the PC pointer is prevented from pointing to an invalid address, the abnormal jamming of the core B is avoided, and the boot program upgrading operation is smoothly finished.

Description

Technical Field

[0001] The invention relates to the field of computer technology, and in particular to an online upgrading method for starting a boot program of a multi-core microcontroller. Background Art

[0002] Some MCUs (Micro Controller Units) are divided into two cores, one core is dedicated to running the bootloader (bootloader), referred to as the B core, and the other core is dedicated to running the application (application), referred to as the A core. Generally speaking, the FLASH (flash memory, non-volatile memory) operation interface of this MCU is stored in the B core, and the A core erases and writes the FLASH of the B core through IPC (Inter-processor Communication). When the A core needs to perform an online upgrade of the bootloader of the B core, it first needs to erase the bootloader code area of ​​the B core (the area in the FLASH that stores the program code). At this time, because the PC pointer of the B core points to the bootloader code area, the address pointed to by the PC pointer of the B core after the bootloader code area is erased is an invalid address, causing the B core to be abnormally stuck and unable to continue operating.

[0003] Therefore, how to avoid the jamming caused by the current upgrade operation is a technical problem that needs to be solved urgently. Summary of the invention

[0004] In order to solve the shortcomings of the prior art, the present invention provides an online upgrade method for a boot program of a multi-core microcontroller. Before erasing FLASH, a PC pointer (program counter) is pointed to a RAM (Random Access Memory), and a B core is put into sleep mode to wait for instructions. When an upgrade request is made to an A core, an IPC interrupt request is received by the B core, and a PC pointer jumps to a storage area of ​​an interrupt vector table (IVT), and a corresponding IPC interrupt service function address is searched. The corresponding upgrade service processing is executed, and after the execution is completed, the PC pointer jumps back to the RAM, so as to avoid the PC pointer pointing to an invalid address, thereby avoiding abnormal freezing of the B core and successfully completing the boot program upgrade operation.

[0005] The embodiment of the present invention provides the following solution:

[0006] An embodiment of the present invention provides an online upgrade method for a multi-core microcontroller boot program, the method comprising:

[0007] S1. When the device is powered on, the PC pointer of the B core in the MCU, which is used to run the bootloader, jumps to point to the RAM and injects a loop. The B core enters the sleep state and waits for new instructions to generate an interrupt. At this time, the PC pointer of the B core is in the RAM.

[0008] S2. When the A core in the MCU used to run the application has an upgrade request, an inter-core communication interrupt processing request for erasing FLASH is sent to the inter-core communication hardware controller;

[0009] S3, the inter-core communication hardware controller generates an inter-core communication interrupt processing request;

[0010] S4, core B receives the inter-core communication interrupt processing request, and the PC pointer of core B jumps to the storage area of ​​the interrupt vector table stored in RAM to find the corresponding inter-core communication interrupt processing service function address;

[0011] S5, the PC pointer of core B jumps to the ROM storing the inter-core communication interrupt service according to the inter-core communication interrupt service function address, and executes the corresponding inter-core communication interrupt processing service, that is, performs FLASH erasure processing. At this time, the bootloader code area of ​​core B is erased;

[0012] S6, the PC pointer of core B returns to RAM, core B enters sleep state and waits for new instructions to generate interrupts;

[0013] S7, core A sends an inter-core communication interrupt processing request for programming FLASH to the inter-core communication hardware controller;

[0014] S8, the inter-core communication hardware controller generates an inter-core communication interrupt processing request;

[0015] S9, core B receives the inter-core communication interrupt processing request, and the PC pointer of core B jumps to the storage area of ​​the interrupt vector table stored in the RAM to find the corresponding inter-core communication interrupt processing service function address;

[0016] S10, the PC pointer of core B jumps to the ROM (Read Only Memory) storing the inter-core communication interrupt service according to the inter-core communication interrupt service function address, and executes the corresponding inter-core communication interrupt processing service, that is, performs FLASH programming processing, and completes the programming operation of the new version of the bootloader code;

[0017] S11, the PC pointer of core B returns to RAM, core B enters sleep state and waits for new instructions to generate interrupts.

[0018] In an optional embodiment, when the device is powered on in step S1, the PC pointer of the B core in the MCU for running the boot program immediately jumps from originally pointing to the FLASH area to pointing to the RAM.

[0019] In an optional embodiment, the inter-core communication interrupt processing service function address described in step S4 is filled into the interrupt vector table when the B core is started and initialized.

[0020] In an optional embodiment, the inter-core communication interrupt processing service function address described in step S9 is filled into the interrupt vector table when the B core is started and initialized.

[0021] The beneficial effects of the present invention based on its technical solution are:

[0022] (1) The present invention provides an online upgrade method for a bootloader of a multi-core microcontroller, which moves the main loop sleep function of the B core to the RAM area. In this way, after the B core erases the bootloader code area, the PC pointer pointing to an abnormality error will not occur, thereby solving the problem of being unable to upgrade online.

[0023] (2) The present invention provides an online upgrade method for a boot program of a multi-core microcontroller. It only requires improving the processing order of the two cores of the multi-core processor, without having to modify the hardware interface of the product to be upgraded. It also eliminates the need to physically connect the burner to the SWD (serial debug interface protocol) interface or the step of disassembling the machine, thereby enabling batch and remote online upgrades. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the embodiments of this specification or the technical solutions in the prior art, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this specification. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0025] Figure 1 Schematic diagram of hardware connection of an embodiment of the present invention.

[0026] Figure 2 It is a schematic diagram of PC pointer jump according to an embodiment of the present invention. DETAILED DESCRIPTION

[0027] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention belong to the scope of protection of the embodiments of the present invention.

[0028] The present invention provides an online upgrade method for a boot program of a multi-core microcontroller, which is applicable to a multi-core microcontroller in which all boot programs and application programs are placed separately in two cores and the FLASH operation interface is stored in the boot core, such as a vehicle terminal, a personal computer, an industrial computer, etc. Therefore, correspondingly, all products that use this type of multi-core microcontroller and need to upgrade the boot program are applicable.

[0029] This embodiment is described by taking TBOX (Telematics BOX, vehicle-mounted communication terminal) as an example.

[0030] Reference Figure 1 , the hardware connection preparations before upgrading are:

[0031] Step 1: The cloud server and TBOX are connected via a wireless network, and the upgrade firmware package is also sent from the cloud server to the MPU of TBOX;

[0032] Step 2: The MPU (Micro Processor Unit) inside the TBOX and the MCU are connected via a serial data interface, and the upgraded firmware package is transmitted from the MPU to the MCU;

[0033] Step 3: The application core (core A) and the boot core (core B) inside the MCU are connected through the internal IPC component, and the application core will complete the program flashing of the boot core.

[0034] Reference Figure 2 The upgrade process includes:

[0035] S1. When the device is powered on, the PC pointer of the B core in the MCU, which is used to run the boot program, immediately jumps from the original FLASH area to the RAM, as shown in the process ① in the figure.

[0036] A loop is injected into RAM, and core B goes into sleep state and waits for a new instruction to generate an interrupt, at which time the PC pointer of core B is in RAM.

[0037] S2. When the A core in the MCU used to run the application program has an upgrade request, an inter-core communication interrupt processing request for erasing FLASH is sent to the inter-core communication hardware controller.

[0038] S3. The inter-core communication hardware controller generates an inter-core communication interrupt processing request (IPC interrupt), as shown in the process ② in the figure.

[0039] S4. Core B receives the inter-core communication interrupt processing request, and the PC pointer of core B jumps to the storage area of ​​the interrupt vector table stored in RAM to find the corresponding inter-core communication interrupt processing service function address, as shown in the process ③ in the figure.

[0040] The inter-core communication interrupt processing service function address is filled into the interrupt vector table when the B core is started and initialized.

[0041] S5, the PC pointer of core B jumps to the ROM storing the inter-core communication interrupt service according to the inter-core communication interrupt service function address, and executes the corresponding inter-core communication interrupt processing service, that is, performs FLASH erasure processing, as shown in the process ④ in the figure. At this time, the bootloader code area of ​​core B is erased;

[0042] S6. The PC pointer of core B returns to RAM, and core B enters sleep state and waits for new instructions to generate interrupts, as shown in the process ⑤ in the figure.

[0043] S7. Core A sends an inter-core communication interrupt processing request for programming FLASH to the inter-core communication hardware controller.

[0044] S8. The inter-core communication hardware controller generates an inter-core communication interrupt processing request.

[0045] S9, core B receives the inter-core communication interrupt processing request, and the PC pointer of core B jumps to the storage area of ​​the interrupt vector table stored in the RAM to find the corresponding inter-core communication interrupt processing service function address.

[0046] The inter-core communication interrupt processing service function address is filled into the interrupt vector table when the B core is started and initialized.

[0047] S10, the PC pointer of core B jumps to the ROM (Read Only Memory) storing the inter-core communication interrupt service according to the inter-core communication interrupt service function address, executes the corresponding inter-core communication interrupt processing service, that is, performs FLASH programming processing, and completes the programming operation of the new version of the bootloader code;

[0048] S11, the PC pointer of core B returns to RAM, core B enters sleep state and waits for new instructions to generate interrupts.

[0049] Those skilled in the art will appreciate that embodiments of the present invention may be provided as methods, systems, or computer program products. Therefore, the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0050] The present invention is described with reference to flowcharts and / or block diagrams of methods, devices (modules, systems), and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded computer, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0051] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0052] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0053] Although the preferred embodiments of the present invention have been described, those skilled in the art may make other changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0054] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims

1. A method for online upgrading of a boot program of a multi-core microcontroller, characterized in that: The method comprises: S1. When the device is powered on, the PC pointer of the B core in the MCU, which is used to run the bootloader, jumps to point to the RAM and injects a loop. The B core enters the sleep state and waits for new instructions to generate an interrupt. At this time, the PC pointer of the B core is in the RAM. S2. When the A core in the MCU used to run the application has an upgrade request, an inter-core communication interrupt processing request for erasing FLASH is sent to the inter-core communication hardware controller; S3, the inter-core communication hardware controller generates an inter-core communication interrupt processing request; S4, core B receives the inter-core communication interrupt processing request, and the PC pointer of core B jumps to the storage area of ​​the interrupt vector table stored in RAM to find the corresponding inter-core communication interrupt processing service function address; S5, the PC pointer of core B jumps to the ROM storing the inter-core communication interrupt service according to the inter-core communication interrupt service function address, and executes the corresponding inter-core communication interrupt processing service, that is, performs FLASH erasure processing. At this time, the bootloader code area of ​​core B is erased; S6, the PC pointer of core B returns to RAM, core B enters sleep state and waits for new instructions to generate interrupts; S7, core A sends an inter-core communication interrupt processing request for programming FLASH to the inter-core communication hardware controller; S8, the inter-core communication hardware controller generates an inter-core communication interrupt processing request; S9, core B receives the inter-core communication interrupt processing request, and the PC pointer of core B jumps to the storage area of ​​the interrupt vector table stored in the RAM to find the corresponding inter-core communication interrupt processing service function address; S10, the PC pointer of core B jumps to the ROM storing the inter-core communication interrupt service according to the inter-core communication interrupt service function address, and executes the corresponding inter-core communication interrupt processing service, that is, performs FLASH programming processing, and completes the programming operation of the new version of the bootloader code; S11, the PC pointer of core B returns to RAM, core B enters sleep state and waits for new instructions to generate interrupts.

2. The online upgrade method of the multi-core microcontroller boot program according to claim 1, characterized in that: When the device is powered on in step S1, the PC pointer of the B core in the MCU for running the boot program immediately jumps from pointing to the FLASH area to pointing to the RAM.

3. The online upgrade method of the multi-core microcontroller boot program according to claim 1, characterized in that: The inter-core communication interrupt processing service function address described in step S4 is filled into the interrupt vector table when the B core is started and initialized.

4. The online upgrade method of the multi-core microcontroller boot program according to claim 1, characterized in that: The address of the inter-core communication interrupt processing service function described in step S9 is filled into the interrupt vector table when the B core is started and initialized.

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