Microcontroller and operating method thereof

Abstract

The embodiment of the invention discloses a microcontroller and an operation method thereof. The microcontroller includes a processor, an instruction memory, and an instruction read circuit. The instruction reading circuit comprises a cache, a decoder, a branch predictor and an address arbiter. And the cache receives the current instruction address I sent by the processor. And the decoder obtains an instruction corresponding to the next instruction address I + 1 from the cache, decodes the instruction and judges whether the instruction is a branch instruction or not. When the instruction corresponding to the instruction address I + 1 is a branch instruction and jumps, the branch predictor determines a target instruction address J; and the target instruction address J is arbitrated by the address arbiter and then is sent to the instruction memory. And the instruction reading circuit reads instructions corresponding to the target instruction address J to the instruction address J + P from the instruction memory and stores the instructions in the cache. And if the processor requests to access any instruction address from the target instruction address J to the instruction address J + P, the processor reads the instruction corresponding to the instruction address requested to be accessed from the cache, so that the instruction fetching speed of the processor is increased.

Description

Technical Field

[0001] The present invention generally relates to the field of integrated circuits, and more particularly, to a microcontroller and an operating method of the microcontroller. Background Art

[0002] Microcontrollers (MCU) are widely used in industrial control, electric vehicles, consumer electronics and other fields. Microcontrollers usually include a processor and an instruction memory. The instruction memory is a non-volatile memory. The processor can execute programs, and the instructions of the program are stored in the instruction memory. The processor obtains instructions by accessing the instruction memory. Therefore, the speed at which the processor executes the program is affected by the speed at which instructions are read from the non-volatile memory. For example, the operating frequency of the processor is above 72MHz, and the flash memory as a non-volatile memory takes 25 to 40ns to perform a read operation, and the performance of the processor cannot be fully utilized. Summary of the invention

[0003] In view of this, an embodiment of the present invention provides a microcontroller and a control method of the microcontroller to improve the instruction fetching speed of a processor.

[0004] According to one aspect of an embodiment of the present invention, a microcontroller is provided. The microcontroller includes: a processor, an instruction memory, and an instruction reading circuit. The processor is configured to issue an instruction address. The instruction memory stores a plurality of instructions. The instruction reading circuit includes: a cache, a decoder, a branch predictor, and an address arbitrator. The cache of the instruction reading circuit receives a request from the processor to access the current instruction address I, where I is an integer. If the cache stores an instruction corresponding to the next instruction address I+1 of the current instruction address I, the decoder obtains the instruction corresponding to the instruction address I+1 from the cache, the decoder decodes the instruction corresponding to the instruction address I+1 and determines whether the instruction corresponding to the instruction address I+1 is a branch instruction, and the branch predictor determines a target instruction address J when the instruction corresponding to the instruction address I+1 is a branch instruction and the branch instruction jumps, where J is an integer, and the instruction corresponding to the instruction address J is not in the cache. The target instruction address J is sent to the instruction memory after arbitration by the address arbitrator. When the instruction address received by the instruction memory is the target instruction address J, the instruction reading circuit reads the instructions corresponding to the target instruction address J to instruction address J+P from the instruction memory and stores them in the cache. If the processor requests to access any instruction address from the target instruction address J to instruction address J+P, the processor reads the instruction corresponding to the instruction address requested to be accessed from the cache, where P is a positive integer greater than or equal to 1 and P is less than the maximum number of instructions that can be stored in the cache.

[0005] In some embodiments, the instruction reading circuit further includes a multiplexer. If there is an instruction corresponding to the instruction address I in the cache, the instruction corresponding to the instruction address I is provided to the processor via the multiplexer. If there is no instruction corresponding to the instruction address I in the cache, the instruction address I and the target instruction address J are arbitrated by the address arbitrator, and the instruction address I is first sent to the instruction memory, and the instructions corresponding to the instruction address I to the instruction address I+P are read from the instruction memory and stored in the cache. If the processor requests any instruction address from the instruction address I to the instruction address I+P, the instruction corresponding to the instruction address requested to be accessed is read from the cache, and then the target instruction address J is sent to the instruction memory, and the instructions corresponding to the target instruction address J to the instruction address J+P are read from the instruction memory and stored in the cache. If the processor requests to access any instruction address from the target instruction address J to the instruction address J+P, the processor reads the instruction corresponding to the instruction address requested to be accessed from the cache.

[0006] In some embodiments, if there is an instruction corresponding to the instruction address I in the cache, the instruction corresponding to the instruction address I is provided to the processor via the multiplexer. If there is no instruction corresponding to the instruction address I and the instruction corresponding to the instruction address I+P+1 in the cache, the instruction address I, the instruction address I+P+1 and the target instruction address J are arbitrated by the address arbitrator, and the instruction address I is first sent to the instruction memory, and the instructions corresponding to the instruction addresses I to I+P are read from the instruction memory and stored in the cache. If the processor requests any instruction address from the instruction address I to the instruction address I+P, the instruction corresponding to the instruction address requested to be accessed is read from the cache, and then the instruction address I+P+1 is sent to the instruction memory, and the instructions corresponding to the instruction address I to the instruction address I+P+1 are read from the instruction memory. The instructions corresponding to instruction address I+P+1 to instruction address I+2P+1 are stored in the cache. If the processor requests to access any instruction address from instruction address I+P+1 to instruction address I+2P+1, the processor reads the instruction corresponding to the instruction address requested to be accessed from the cache, and finally sends the target instruction address J to the instruction memory, reads the instructions corresponding to the target instruction address J to instruction address J+P from the instruction memory and stores them in the cache. If the processor requests to access any instruction address from instruction address J to instruction address J+P, the processor reads the instruction corresponding to the instruction address requested to be accessed from the cache.

[0007] In some embodiments, the step size is P+1.

[0008] In some embodiments, P=1 or 2.

[0009] In some embodiments, the cache includes a plurality of cache areas, each cache area being used to store an instruction and an instruction address of the instruction.

[0010] In some embodiments, the cache is a first-in-first-out cache.

[0011] In some embodiments, the cache is a static random access memory or a register, and the instruction memory is a non-volatile memory.

[0012] According to another aspect of an embodiment of the present invention, a control method for a microcontroller is provided. The microcontroller includes: a processor, an instruction memory, and an instruction reading circuit. The microcontroller includes: a processor, configured to issue an instruction address; an instruction memory, configured to store a plurality of instructions; and an instruction reading circuit, including a cache, a decoder, a branch predictor, and an address arbitrator. The operation method includes: the cache of the instruction reading circuit receives a request for accessing the current instruction address I issued by the processor, wherein I is an integer; if the cache stores an instruction corresponding to the next instruction address I+1 of the current instruction address I, the decoder obtains the instruction corresponding to the instruction address I+1 from the cache, the decoder decodes the instruction corresponding to the instruction address I+1 and determines whether the instruction corresponding to the instruction address I+1 is a branch instruction, and the branch predictor determines the target instruction address J when the instruction corresponding to the instruction address I+1 is a branch instruction and the branch instruction jumps, wherein J is an integer, and the instruction address The instruction corresponding to target instruction address J is not in the cache; the target instruction address J is sent to the instruction memory after arbitration by the address arbitrator; when the instruction address received by the instruction memory is the target instruction address J, the instruction reading circuit reads the instructions corresponding to the target instruction address J to instruction address J+P from the instruction memory and stores them in the cache, and if the processor requests to access any instruction address from the target instruction address J to instruction address J+P, the processor reads the instruction corresponding to the instruction address requested to be accessed from the cache, wherein P is a positive integer greater than or equal to 1 and P is less than the maximum number of instructions that can be stored in the cache.

[0013] In some embodiments, the instruction reading circuit further includes a multiplexer. The operation method further includes: if there is an instruction corresponding to the instruction address I in the cache, the instruction corresponding to the instruction address I is provided to the processor via the multiplexer; if there is no instruction corresponding to the instruction address I in the cache, the instruction address I and the target instruction address J are arbitrated by the address arbitrator, the instruction address I is first sent to the instruction memory, the instructions corresponding to the instruction address I to the instruction address I+P are read from the instruction memory and stored in the cache, if the processor requests any instruction address from the instruction address I to the instruction address I+P, the instruction corresponding to the instruction address requested to be accessed is read from the cache, and then the target instruction address J is sent to the instruction memory, the instructions corresponding to the target instruction address J to the instruction address J+P are read from the instruction memory and stored in the cache, if the processor requests to access any instruction address from the target instruction address J to the instruction address J+P, the processor reads the instruction corresponding to the instruction address requested to be accessed from the cache.

[0014] In some embodiments, if there is an instruction corresponding to the instruction address I in the cache, the instruction corresponding to the instruction address I is provided to the processor via the multiplexer; if there is no instruction corresponding to the instruction address I and the instruction corresponding to the instruction address I+P+1 in the cache, the instruction address I, the instruction address I+P+1 and the target instruction address J are arbitrated by the address arbitrator, and the instruction address I is first sent to the instruction memory, and the instructions corresponding to the instruction addresses I to I+P are read from the instruction memory and stored in the cache; if the processor requests any one of the instruction addresses from the instruction address I to the instruction address I+P, the instruction corresponding to the instruction address requested to be accessed is read from the cache, and then the instruction address J is sent to the instruction memory. The address I+P+1 is sent to the instruction memory, and the instructions corresponding to the instruction addresses I+P+1 to I+2P+1 are read from the instruction memory and stored in the cache. If the processor requests to access any one of the instruction addresses from I+P+1 to I+2P+1, the processor reads the instruction corresponding to the instruction address requested to be accessed from the cache. Finally, the target instruction address J is sent to the instruction memory, and the instructions corresponding to the target instruction address J to instruction address J+P are read from the instruction memory and stored in the cache. If the processor requests to access any one of the instruction addresses from instruction address J to instruction address J+P, the processor reads the instruction corresponding to the instruction address requested to be accessed from the cache.

[0015] In some embodiments, P=1 or 2.

[0016] According to the microcontroller and control method of the embodiment of the present invention, instructions are pre-fetched from the instruction memory in a manner combining sequential pre-fetching and branch prediction. Before the processor executes the branch instruction, the instruction reading circuit predicts the target instruction of the branch instruction and pre-fetches it from the instruction memory to the cache. By decoding and branch prediction of the instruction corresponding to the next instruction address of the current instruction address requested by the processor stored in the cache, in the case of a branch instruction jump, the target instruction address of the branch instruction jump can be determined in advance and the target instruction can be pre-fetched from the instruction memory to the cache in advance. When the processor performs an instruction fetch operation of the target instruction, the instruction can be fetched from the cache, thereby improving the instruction fetch speed of the processor.

[0017] Furthermore, the instruction memory has an extended output bit width, and the instruction reading circuit obtains instructions corresponding to at least two consecutive instruction addresses from the instruction memory. Therefore, when obtaining the instruction corresponding to the currently requested instruction address from the instruction memory, the next instruction address of the currently requested instruction address is also stored in the cache, so that branch prediction can be performed on the instruction of the next instruction address of the currently requested instruction address.

[0018] Furthermore, the instruction reading circuit will sequentially pre-fetch instructions corresponding to instruction address I+P+1 to instruction address I+2P+1. Before the processor requests instruction address I+P+1 to instruction address I+2P+1, it can access the instruction storage in advance to store the instructions from instruction address I+P+1 to instruction address I+2P+1 into the cache in advance. Therefore, when the processor requests instruction address I+P+1 to instruction address I+2P, the instruction corresponding to the requested instruction address is directly read from the cache, thereby improving the processor's instruction fetching speed. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The above and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

[0020] Figure 1 A microcontroller in the related art is shown;

[0021] Figure 2 The invention shows the instruction sequence prefetching method in the related art;

[0022] Figure 3 An exemplary microcontroller of the present invention is shown;

[0023] Figure 4 An exemplary instruction fetch circuit of the present invention is shown;

[0024] Figure 5 An exemplary cache of the present invention is shown;

[0025] Figure 6 An exemplary address arbitrator of the present invention is shown;

[0026] Fig. 7A and Figure 7B shows the storage contents of the cache after 2 instruction prefetch operations;

[0027] Figure 8 An exemplary address arbitration process is shown;

[0028] Fig. 9 An exemplary method of operation of an instruction fetch circuit is shown;

[0029] Fig.10 An exemplary method of operating a microcontroller is shown;

[0030] Fig.11 shows the processing timing of multiple instruction addresses;

[0031] Fig.12 shows the instruction pipeline timing of the processor;

[0032] FIG. 13A to FIG. 13E Shows Fig.11 The cache content changes corresponding to the operation method. DETAILED DESCRIPTION

[0033] The present application is described below based on embodiments, but the present application is not limited to these embodiments. In the detailed description of the present application below, some specific details are described in detail. It is possible for those skilled in the art to fully understand the present application without the description of these details. In order to avoid confusing the essence of the present application, known methods, processes, flows, components and circuits are not described in detail.

[0034] In addition, persons of ordinary skill in the art will appreciate that the drawings provided herein are for illustration purposes and are not necessarily drawn to scale.

[0035] Unless the context clearly requires otherwise, words such as “include”, “including” and the like throughout the application should be interpreted as including rather than exclusive or exhaustive, that is, as meaning “including but not limited to”.

[0036] In the description of this application, it should be understood that the terms "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance. In addition, in the description of this application, unless otherwise specified, the meaning of "plurality" is two or more.

[0037] Figure 1It is a schematic block diagram of a microcontroller of the related art. In order to increase the speed at which the processor obtains instructions from the instruction memory, a cache is set in the processor and the instruction memory. When the processor processes the instructions that have been taken out, the instructions corresponding to the sequential address are pre-fetched into the cache in advance. If the processor determines that the instructions are sequential after executing the previous instructions (that is, the next instruction is a sequential instruction of the previous instruction), the processor can directly read the next instruction from the cache. The time overhead of the processor's instruction fetching can be reduced by pre-fetching instructions. Figure 2 It is a flowchart of sequential prefetching of instructions in the related art. The processor performs an instruction fetch operation and sends instruction address N to the cache. The processor accesses the cache and compares instruction address N with the instruction address in the cache. If a hit occurs, the processor obtains the instruction corresponding to instruction address N from the cache. In addition, the instruction corresponding to instruction address N+1 is read from the instruction memory and written into the cache. It can be understood that instruction addresses N and N+1 are addresses recognized and used by the processor, and can be converted into addresses recognized by the instruction memory through mapping. If instruction address N is not hit in the cache, it is necessary to access the instruction memory to obtain the instruction corresponding to instruction address N. In addition, the instruction corresponding to instruction address N+1 is read from the instruction memory and written into the cache. In the above method, when the instructions are not executed sequentially, the processor's instruction fetch operation needs to wait for the read operation of the instruction memory. When there are many branch instructions, the efficiency of sequential prefetching is low, which restricts the performance of the processor.

[0038] Figure 3 An exemplary microcontroller of the present invention is shown. The microcontroller includes: a processor 20, an instruction memory 30, and an instruction reading circuit 10. The processor 20 sends a read request and an instruction address to the instruction reading circuit 10, and the instruction reading circuit 10 provides the corresponding instruction to the processor. The processor 20 is configured to run instructions. The instruction memory 30 is a non-volatile memory for storing instructions. Non-volatile memory is, for example, a flash memory (Flash Memory), a resistive random access memory (RRAM), a ferroelectric memory (FRAM), a magnetic random access memory (MRAM), a phase change random access memory (PCRAM), etc. The flash memory can be NOR Flash or NAND Flash. The microcontroller may also include one or more of a sensor, an analog-to-digital converter, and a counter.

[0039] The processor 20 is, for example, a central processing unit based on an ARM or RISC-V core. The processor 20 may include an instruction address register, an instruction register, a data register, an arithmetic logic unit ALU, a control unit, etc. The instruction address register is also called a program counter, which is used to store an instruction address. The instruction address is, for example, a binary number. By adding 1 to the program counter, instruction address I becomes instruction address I+1. The instruction memory 30 includes a plurality of storage units, and the storage unit is addressed by a memory address. The memory address is used to identify the storage location of data in the instruction memory 30. The instruction address can be converted into a memory address by a mapping table.

[0040] The process of the processor 20 processing instructions includes: a fetching stage, a decoding stage, and an executing stage. In the fetching stage, the processor 20 sends an instruction fetching request and an instruction address to the instruction reading circuit 10 according to the instruction address in the instruction address register, and the instruction reading circuit 10 provides the processor 20 with the instruction corresponding to the instruction address. The processor 20 processes instructions in a pipeline form. For example, the processor 20 simultaneously performs the instruction fetching operation of instruction n+1 during the decoding operation of instruction n, and simultaneously performs the decoding operation of instruction n+1 and the instruction fetching operation of instruction n+2 during the execution operation of instruction n. The sequential instruction fetching of the above-mentioned instruction n, instruction n+1, and instruction n+2 is realized by adding 1 to the program counter. For a branch instruction, after the execution stage of the branch instruction is completed, the processor 20 knows the next instruction to be executed and modifies the value in the instruction address register. The instruction reading circuit 10 is used for the instruction fetching operation of the processor 20. The instruction reading circuit 10 of the present invention performs branch prediction on the branch instruction before the processor 20 executes the branch instruction, and pre-fetches the instruction from the instruction memory 30 according to the prediction result. The branch predictor predicts the jump direction and the target instruction address. The jump direction includes a jump (taken) and a jump (not taken). If the jump direction of the instruction corresponding to instruction address I is not taken, the target instruction address is instruction address I+1. In this article, the branch instruction with a jump direction of not taking is referred to as a branch instruction that does not take, and the branch instruction with a jump direction of taking is referred to as a branch instruction that takes.

[0041] In some embodiments, the processor 20, the instruction memory 30 and the instruction fetch circuit 10 are fabricated on the same wafer, and the instruction memory 30 is also called an embedded or on-chip memory. In other embodiments, the processor 20 and the instruction fetch circuit 10 are fabricated on the same wafer, and the instruction memory 30 is fabricated on another wafer. The manufacturing processes of the processor 20 and the instruction memory 30 are different, and the processor 20 and the instruction memory 30 are fabricated on different wafers so that both the processor 20 and the instruction memory 30 can be manufactured with appropriate processes.

[0042] Figure 4 An exemplary instruction reading circuit of the present invention is shown. The instruction reading circuit 10 includes: a cache 100, a decoder 300, a branch predictor 500, an address arbitrator 700, and a multiplexer 900. When the processor 20 performs an instruction fetch operation on the current instruction address I, the processor 20 sends a request for the instruction address I to the instruction reading circuit 10, and the cache 100 of the instruction reading circuit 10 receives the request for accessing the current instruction address I issued by the processor, where I is an integer. The decoder 300 obtains the instruction corresponding to the next instruction address I+1 of the current instruction address I from the cache 100 and decodes it. The branch predictor 500 determines whether the instruction corresponding to the instruction address I+1 is a branch instruction; when the instruction corresponding to the instruction address I+1 is a branch instruction, the branch predictor 500 also determines whether the branch instruction jumps and determines the target instruction address J, where J is an integer, and the instruction corresponding to the instruction address J is not in the cache. The instruction fetch circuit 10 fetches instructions corresponding to the target instruction address J to the instruction address J+P from the instruction memory 30 and stores the instructions into the cache 100 .

[0043] The cache 100 is, for example, a static random access memory (SRAM) or a register, etc. Compared with the instruction memory 30 , the cache 100 has a faster reading and writing speed. Figure 5 An exemplary cache 100 of the present invention is shown. The cache 100 includes a plurality of cache areas, each of which is used to store an instruction address and an instruction corresponding to the instruction address, the instruction being obtained from the instruction memory 30. Figure 5 In the illustrated embodiment, the cache 100 includes cache areas 111-116, each of which is used to store a set of instructions and addresses. The number of cache areas in the cache 100 is not limited to 6, and can also be other integers greater than 6. The instruction memory 30 has an extended output bit width. Therefore, each time the instruction reading circuit 10 accesses the instruction memory 30, the instruction reading circuit 10 obtains instructions corresponding to at least two consecutive instruction addresses from the instruction memory 30. For example, each time the instruction memory 30 is accessed, the instruction reading circuit 10 obtains instructions corresponding to P+1 consecutive instruction addresses from the instruction memory 30, where P+1 is the step length. P is a positive integer greater than or equal to 1, and P is less than the maximum number of instructions that can be stored in the cache 100. P is, for example, equal to 1 or 2. The cache 100 is, for example, a first-in, first-out cache. The instructions obtained by the instruction reading circuit 10 from the instruction memory 30 are written to the cache 100. Fig. 7A and Figure 7BCache 100 after two write operations is shown (cache areas 115 and 116 are omitted). For example, after the first write operation, instruction n and its corresponding instruction address N are stored in cache area 112, and instruction n+1 and its corresponding instruction address N+1 are stored in cache area 111. After the second write operation, instruction n and its corresponding instruction address N are transferred to cache area 114, instruction n+1 and its corresponding instruction address N+1 are transferred to cache area 113, instruction m and its corresponding instruction address M are stored in cache area 112, and instruction m+1 and its corresponding instruction address M+1 are stored in cache area 111.

[0044] The instruction reading circuit 10 obtains the instruction address I from the processor 20, and compares the instruction address I with the instruction address stored in the cache 100. When the instruction address I is in the cache 100, the instruction reading circuit 10 sends the instruction corresponding to the instruction address I stored in the cache 100 to the processor 20. When the instruction address I is not in the cache 100, the instruction reading circuit 10 reads the instruction corresponding to the instruction address I from the instruction memory 30.

[0045] The instruction reading circuit 10 also pre-fetches the corresponding instruction address I+P+1 according to the generation order of the instruction address I, and compares the instruction address I+P+1 with the instruction address of the cache 100 .

[0046] The instruction reading circuit 10 includes, for example, an address comparator, which is used to implement address comparison. The address comparator can be implemented by a digital circuit.

[0047] The decoder 300 is used to decode the instruction obtained from the cache 100. The branch predictor 500 determines whether the instruction is a branch instruction according to the decoded instruction, and determines whether to jump and the target instruction address J when the instruction is a branch instruction. The branch predictor 500 is, for example, a history-based branch predictor, a local / global branch predictor, a static branch predictor, a dynamic branch predictor, a bimodal branch predictor, etc. In some embodiments, the decoder 300 and the branch predictor 500 are implemented by a circuit module.

[0048] Each time the instruction memory 30 is accessed, the number of instructions read from the instruction memory 30 is equal to the step length P+1, which depends on the output bit width of the instruction memory 30. The instruction memory 30 of the present invention has an extended output bit width, and can output instructions corresponding to at least 2 consecutive instruction addresses each time it is accessed.

[0049] The instruction fetch circuit 10 accesses the instruction memory 30 according to the instruction address C. The instruction address C is determined by the address arbitrator 700. For example, the address arbitrator 700 selects the instruction address C from the instruction address I, the instruction address I+P+1, and the target instruction address J. Figure 6As shown, the exemplary address arbiter 700 includes a multiplexer and a control circuit. The control circuit determines which of the output address C is the instruction address I, the instruction address I+P+1, and the target instruction address J according to signals 1-3. Signal 1 indicates whether the instruction address I is hit in the cache 100. Signal 2 indicates whether the instruction address I+P+1 is hit in the cache 100. Signal 3 indicates whether the instruction corresponding to the instruction address I+1 is a branch instruction of a jump. The instruction reading circuit 10 performs a prefetch operation according to the instruction address C, reads the instruction from the instruction memory 30 and stores it in the cache 100. In each prefetch operation, P+1 instructions with consecutive instruction addresses are read from the instruction memory 30, and the starting instruction address is address C.

[0050] The multiplexer 900 is controlled by a signal 1. When the signal 1 indicates that the instruction address I is hit in the cache 100, the processor 20 reads the instruction corresponding to the instruction address I from the cache 100. When the signal 1 indicates that the instruction address I is not hit in the cache 100, the processor 20 reads the instruction corresponding to the instruction address I from the instruction memory 30.

[0051] Figure 8 Each time the instruction fetch circuit 10 receives an instruction address from the processor 20, as a working cycle of the instruction fetch circuit 10, it executes a Figure 8 The address arbitration process shown is described by taking the instruction reading circuit 10 receiving a request for accessing the current instruction address I from the processor 20 as an example.

[0052] In step S01, it is determined whether the instruction address I is hit in the cache 100. For example, the instruction address I and the instruction address in the cache 100 may be compared by an address comparator.

[0053] If there is no instruction address I in the cache 100, signal 1 indicates that the instruction address I is not hit in the cache 100, and the address C output by the address arbiter 700 is the instruction address I. In step S02, the instruction memory 30 is accessed, and the instructions corresponding to the instruction address I to the instruction address I+P are read from the instruction memory 30. The instruction address I to the instruction address I+P are P+1 consecutive instruction addresses: instruction address I, instruction address I+1, ..., instruction address I+P. The instructions corresponding to the instruction address I to the instruction address I+P are stored in the cache 100. If the processor 20 requests any instruction address from the instruction address I to the instruction address I+P, the instruction corresponding to the instruction address requested to be accessed can be read from the cache 100. The instruction corresponding to the instruction address I is sent to the processor 20 through the multiplexer 900, and the processor 20 completes the instruction fetch of the instruction address I and enters step S03.

[0054] If there is instruction address I in cache 100, processor 20 reads the instruction corresponding to instruction address I from cache 100, processor 20 completes instruction fetch of instruction address I and enters step S03.

[0055] In step S03, it is determined whether the instruction address I+P+1 is hit in the cache 100. For example, the instruction address I+P+1 can be compared with the instruction address in the cache 100 by an address comparator. In some embodiments, the instruction reading circuit 10 includes two address comparators, one for comparing the instruction address I with the instruction address in the cache 100 to generate a signal 1, and the other for comparing the instruction address I+P+1 with the instruction address in the cache 100 to generate a signal 2.

[0056] If there is no instruction address I+P+1 in the cache 100, signal 2 indicates that the instruction address I+P+1 is not hit in the cache 100, and the address C output by the address arbiter 700 is the instruction address I+P+1, and step S04 is executed. In step S04, the instruction memory 30 is accessed, and the instructions corresponding to the instruction addresses I+P+1 to I+2P+1 are read from the instruction memory 30 and stored in the cache 100. Signal 2 changes to a level indicating that the instruction address I+P+1 is hit in the cache 100, and the sequential prefetch is completed, and the process proceeds to step S05. The instruction address I+P+1 to the instruction address I+2P+1 are P+1 consecutive instruction addresses: instruction address I+P+1, instruction address I+P+2, ..., instruction address I+2P+1. If the processor 20 requests to access any instruction address from the instruction address I+P+1 to the instruction address I+2P+1, the processor 20 reads the instruction corresponding to the instruction address requested to be accessed from the cache 100.

[0057] If there is an instruction address I+P+1 in the cache 100, there is no need to execute step S04, and the process goes to step S05.

[0058] In step S05, it is determined whether the instruction corresponding to the instruction address I+1 is a branch instruction. If the instruction corresponding to the instruction address I+1 is a branch instruction, it is further predicted whether to jump and the target instruction address J. Step S05 is completed by the decoder 300 and the branch predictor 500. For example, the decoder 300 obtains the instruction corresponding to the instruction address I+1 from the cache 100 and decodes the instruction. The branch predictor 500 determines whether the instruction corresponding to the instruction address I+1 is a branch instruction based on the decoded instruction, determines whether to jump and predicts the target instruction address J. If the instruction corresponding to the instruction address I+1 is a branch instruction and jumps, the signal 3 indicates that the instruction corresponding to the instruction address I+1 jumps, and the address C output by the address arbitrator 700 is the target instruction address J.

[0059] In step S06, the instruction memory 30 is accessed, and the instructions corresponding to the target instruction address J to the instruction address J+P are read from the instruction memory 30 and stored in the cache 100. The instruction address J to the instruction address J+P are P+1 consecutive instruction addresses: instruction address J, instruction address J+1, ..., instruction address J+P. If the processor 20 requests to access any instruction address from the target instruction address J to the instruction address J+P, the processor 20 reads the instruction corresponding to the instruction address requested to be accessed from the cache 100.

[0060] exist Figure 8 In the embodiment shown, the judgment of step S03 is first performed, and step S04 is performed according to the judgment result. After the instructions corresponding to instruction address I+P+1 to instruction address I+2P+1 are stored in cache 100 (for example, after the level of signal 2 changes), the judgment of step S05 is performed, and step S06 is performed according to the judgment result. In an optional embodiment, while executing steps S03 and S04, the decoder 300 and the branch predictor 500 decode the instruction corresponding to instruction address I+1, perform branch prediction judgment and predict the target instruction address J (step S05). After the instructions corresponding to instruction address I+P+1 to instruction address I+2P+1 are stored in cache 100 (after step S04 is executed), step S06 is performed.

[0061] When signal 1 is at a high level "1", it indicates that instruction address I is not hit in cache 100, and when signal 1 is at a low level "0", it indicates that instruction address I is hit in cache 100. When step S02 is executed, signal 1 changes from 1 to 0. When signal 2 is at a high level "1", it indicates that instruction address I+P+1 is not hit in cache 100, and when signal 2 is at a low level "0", it indicates that instruction address I+P+1 is hit in cache 100. When step S04 is executed, signal 2 changes from 1 to 0. When signal 3 is at a high level "1", it indicates that the instruction corresponding to instruction address I+1 is a branch instruction for jumping, and when signal 3 is at a low level "0", it indicates that the instruction corresponding to instruction address I+1 is not a branch instruction, or the instruction corresponding to instruction address I+1 is a branch instruction that does not jump. The address arbiter 700 determines the output address C based on signals 1-3. The instruction reading circuit 10 first determines whether signal 1 is 1 or 0. When signal 1 is 1, the instruction reading circuit 10 executes step S2 regardless of whether signals 2 and 3 are 1 or 0. After signal 1 becomes 0, if signal 2 is 1, step S04 is executed, and if signal 3 is 1, step S06 is executed.

[0062] In another embodiment, the address arbitration process includes steps S01-S02 and steps S05 and S06, but does not include steps S03-S04. When the processor 20 completes fetching the instruction address I, it proceeds to step S05.

[0063] Fig. 9FIG. 1 shows an exemplary operation method of the instruction reading circuit 10. Referring to FIG. Figure 4 and 9 The operation method of the instruction reading circuit 10 includes the following steps. Each time the instruction reading circuit receives an instruction address from the processor 20, the instruction reading circuit 10 executes Fig. 9 The operation method shown.

[0064] Step S101 : the instruction reading circuit 10 receives an instruction address I from the processor 20 . Specifically, the cache 100 of the instruction reading circuit 10 receives a request for accessing the current instruction address I from the processor 20 .

[0065] Step S102, determining whether instruction address I is stored in cache 100. For example, instruction addresses in cache 100 are compared with instruction address I one by one, so as to determine whether instruction address I is stored in cache 100. If instruction address I is stored in cache 100, the instruction corresponding to instruction address I stored in cache 100 is sent to processor 20 through multiplexer 900. If instruction address I is not stored in cache 100, step S103 is executed.

[0066] Step S103, access the instruction memory 300, read the instructions corresponding to the instruction address I to the instruction address I+P from the instruction memory 300 and store the instructions in the cache 100. The instruction corresponding to the instruction address I is sent to the processor 20 via the multiplexer 900. In this way, if the processor 20 requests any instruction address from the instruction address I to the instruction address I+P, the processor 20 can read the instruction corresponding to the instruction address requested to be accessed from the cache 100.

[0067] Step S104: processor 20 fetches the instruction corresponding to instruction address I.

[0068] Step S105, determining whether the instruction address I+P+1 is stored in the cache 100. For example, the instruction addresses in the cache 100 are compared with the instruction address I+P+1 one by one, so as to determine whether the instruction address I+P+1 is stored in the cache 100. If the instruction address I+P+1 is not stored in the cache 100, executing step S106.

[0069] Step S106, access the instruction memory 300, read the instructions corresponding to the instruction address I+P+1 to the instruction address I+2P+1 from the instruction memory 300, and store the instructions in the cache 100. In this way, if the processor 20 requests to access any instruction address from the instruction address I+P+1 to the instruction address I+2P+1, the processor 20 reads the instruction corresponding to the instruction address requested to be accessed from the cache 100.

[0070] Step S107 , the decoder 300 obtains the instruction corresponding to the instruction address I+1 from the cache 100 and decodes the instruction corresponding to the instruction address I+1.

[0071] Step S108, the branch predictor 500 obtains the decoded instruction and determines whether the instruction corresponding to the instruction address I+1 is a branch instruction. If the branch predictor 500 determines that the instruction corresponding to the instruction address I+1 is a branch instruction, step S109 is executed.

[0072] In step S109, the branch predictor 500 determines whether the instruction corresponding to the instruction address I+1 jumps. If the instruction corresponding to the instruction address I+1 jumps, step S110 is executed.

[0073] Step S110 , the branch predictor 500 determines the target instruction address J when the instruction corresponding to the instruction address I+1 jumps.

[0074] Step S111, access the instruction memory 300, read the instructions corresponding to the instruction address J to the instruction address J+P from the instruction memory 300 and store the instructions in the cache 100. In this way, if the processor 20 requests to access any instruction address from the target instruction address J to the instruction address J+P, the processor 20 reads the instruction corresponding to the instruction address requested to be accessed from the cache 100.

[0075] Fig.10 An exemplary operation method of a microprocessor is shown. The operation method is executed by the processor 20, the instruction reading circuit 10 and the instruction memory 30 in cooperation. Fig.10 In the example, steps S203-S206 in the red dashed box are executed by the processor 20, and the other steps are executed by the instruction reading circuit 10. The operation method starts at the instruction fetching stage of instruction address I. In the instruction fetching stage of instruction address I, the processor 20 sends a request to access instruction address I to the instruction reading circuit 10.

[0076] Step S201 , determining whether there is an instruction address I in the cache 100 by accessing the cache 100 .

[0077] If the instruction address I is hit in the cache 100, step S202 is executed.

[0078] If the instruction address I is not hit in the cache 100, step S212 is executed. In step S212, the instruction memory 30 is accessed to read the instructions corresponding to the instruction address I to the instruction address I+P. The instructions corresponding to the instruction address I to the instruction address I+P are stored in the cache 100 (step S211).

[0079] In step S202, the processor 20 receives the instruction corresponding to the instruction address I, and the instruction fetch operation corresponding to the instruction address I is completed. If the instruction address I is hit in the cache 100, the processor 20 obtains the instruction corresponding to the instruction address I from the cache 100. If the instruction address I is not hit in the cache 100, the instruction corresponding to the instruction address I read from the instruction memory 30 is sent to the processor 20 in step S212. Steps S202 and S211 can be performed simultaneously.

[0080] In step S203, the processor 20 decodes the instruction corresponding to the instruction address I. That is, the decoding stage of the instruction corresponding to the instruction address I.

[0081] In step S204, the processor 20 sends the instruction address I+1 to the instruction fetch circuit 10 to fetch instructions in sequence. That is, the instruction fetch phase of the instruction corresponding to the instruction address I+1. The instruction address I+1 is obtained by adding 1 to the value in the instruction counter. Since the processor 20 processes instructions in a pipeline manner, steps S203 and 204 are performed simultaneously.

[0082] Step S205, the processor 20 executes the instruction corresponding to the instruction address I. That is, the execution phase of the instruction corresponding to the instruction address I. In the execution phase, the processor 20 determines whether the instruction corresponding to the instruction address I is a branch instruction. After the instruction corresponding to the instruction address I is executed, the processor 20 can determine whether the branch instruction is a jump or not. If the branch instruction is not a jump, the next instruction address to be processed is I+1. If the branch instruction jumps, the operation related to step S204 is discarded, and the processor 20 determines the target instruction address J' of the jump of the instruction corresponding to the instruction address I according to the execution result of the instruction corresponding to the instruction address I.

[0083] Step S206 , the processor 20 sends the target instruction address J′ to the instruction fetch circuit 10 to perform a jump instruction fetch.

[0084] When the processor 20 decodes and executes the instruction corresponding to the instruction address I (steps S203 and S205), the instruction reading circuit 10 performs sequential prefetching based on the step length P+1, and determines whether the instruction corresponding to the instruction address I+1 is a branch instruction, whether to jump, predicts the target instruction address J of the jump of the instruction corresponding to the instruction address I+1, and performs jump prefetching based on the target instruction address J. For example, after the instruction fetching of the instruction address I is completed (step S202), step S207 is executed.

[0085] Step S207, pre-decode the instruction corresponding to instruction address I+1. Specifically, the decoder 300 of the instruction reading circuit 10 reads the instruction corresponding to instruction address I+1 from the cache 100 and decodes it. Step S207 and step 203 are performed simultaneously. Step S207 is performed by the decoder 300 of the instruction reading circuit 10, and step S203 is performed by the processor 20.

[0086] The branch predictor 300 of the instruction reading circuit 10 receives the decoded instruction and determines whether the instruction corresponding to the instruction address I+1 is a branch instruction. When the instruction corresponding to the instruction address I+1 is a branch instruction, the branch predictor 300 determines whether the instruction corresponding to the instruction address I+1 jumps. When the instruction corresponding to the instruction address I+1 is a branch instruction and jumps, step S208 is executed.

[0087] Step S208 , the branch predictor 300 predicts the target instruction address J.

[0088] Step S213, the instruction reading circuit 10 calculates the instruction address I+P+1 corresponding to the sequential prefetch according to the received instruction address I and the step length P+1. It can be understood that after the instruction reading circuit 10 receives the instruction address I from the processor 20, the instruction reading circuit 10 can calculate the instruction address I+P+1 corresponding to the sequential prefetch.

[0089] Step S209 , performing address arbitration to determine the address C used to access the instruction memory 30 .

[0090] For example, if signal 2 indicates that instruction address I+P+1 is not hit in cache 100, address C is instruction address I+P+1. If signal 3 indicates that the instruction corresponding to instruction address I+1 is a branch instruction and a jump occurs, address C is the target instruction address J.

[0091] Step S210, access the instruction memory 30 according to the address C.

[0092] Step S211 , storing the read instruction into the cache 100 .

[0093] In this embodiment, according to the timing of signal 2 and signal 3, sequential prefetching based on instruction address I+P+1 and jump area based on instruction address J are performed in sequence through address arbitration. For example, instruction memory 30 is first accessed according to instruction address I+P+1, instructions corresponding to instruction address I+P+1 to instruction address I+2P+1 are read out and stored in cache 100, and then instruction memory 30 is accessed according to target instruction address J, instructions corresponding to instruction address J to instruction address J+P are read out and stored in cache 100.

[0094] After the processor 20 sends the instruction address I+1 to the instruction reading circuit 10 (step S204), the instruction reading circuit 10 executes steps S201-S202 and S207-S213 in response to the instruction address I+1. After the processor 20 receives the instruction corresponding to the instruction address I+1 (step S202), the processor 20 executes steps S203-S206 corresponding to the instruction address I+1. If the instruction corresponding to the instruction address I+1 is a branch instruction that jumps, the processor 20 determines the target instruction address J of the instruction corresponding to the instruction address I+1 in step S206. Fig.10 In step S206, the instruction address J', the instruction address I+1 in step S204, the instruction address I+1 in step S207, the instruction address I+P in step S213, and the instruction address J in step S208 are the instruction addresses involved in the process corresponding to the instruction address I. That is, after the processor 20 sends the instruction address I to the instruction reading circuit 10, Fig.10 The addresses of instructions that may be involved in the method shown.

[0095] Steps S207-S213 based on instruction address I are completed before step S206 based on instruction address I+1. Thus, when accessing cache 100 according to instruction address J, instruction address J can be hit in cache 100, reducing the instruction fetch time of instruction address J.

[0096] Steps S212 and S211 based on instruction address I are completed before the instruction fetch request of instruction address I+1. In this way, when accessing cache 100 for instruction fetching according to instruction address I+1, instruction address I+1 can be hit in cache 100, reducing the instruction fetch time of instruction address I+1. The timing of processing multiple instruction addresses by the microcontroller of the present invention is introduced below through another embodiment. The processor 20 runs the instructions corresponding to multiple instruction addresses in a pipeline form. Fig.11 It is the processing timing of multiple instruction addresses. Fig.12 The pipeline timing of the processor 20 processing instructions is shown. FIG. 13A to FIG. 13E The changes of the stored contents in the cache 100 are shown.

[0097] In the example, instruction addresses I0-I10 are consecutive instruction addresses, where instruction address I0 is the first instruction and the step length P+1=2. Instruction address I1 corresponds to instruction D1 which is a branch instruction and jumps. The instructions corresponding to other instruction addresses are non-branch instructions or branch instructions that do not jump. Instruction address I8 is the jump target instruction address of instruction D1. Fig.12As shown, after the instruction D1 corresponding to the instruction address I1 is executed, the processor 20 will know that the jump target instruction address of the instruction D1 is I8, and fetch the instruction according to the instruction address I8 in the next instruction fetch operation. Although the processor 20 performs the instruction fetch operations of the instruction corresponding to the instruction address I2 and the instruction corresponding to the instruction address I3, it does not execute these two instructions, or discards the execution results of these two instructions.

[0098] First, the instruction fetch operation of instruction address I0 is performed. In clock cycle 2, processor 20 sends a read request and instruction address I0 to instruction fetch circuit 10. Instruction fetch circuit 10 compares instruction address I0 with the instruction address in cache 100, and determines that there is no instruction address I0 in cache 100. Address C output by address arbitrator 700 is instruction address I0.

[0099] In clock cycles 3 and 4, a read operation is performed on the instruction memory 30 to obtain instruction D0 corresponding to instruction address I0 and instruction D1 corresponding to instruction address I1. The processor 20 obtains instruction D0 corresponding to instruction address I0 in clock cycle 5, and the instruction fetching stage of instruction address I0 is completed. Instructions D0 and D1 read from the instruction memory 30 are stored in the cache 100. Specifically, refer to Fig.11 and Fig.13A , in clock cycles 5 and 6, instruction address I0 and instruction D0 are stored in cache area 112, and instruction address I1 and instruction D1 are stored in cache area 111.

[0100] After the instruction address I0 is fetched, the instruction reading circuit 10 determines the instruction address I2 corresponding to the sequential prefetch according to the prefetch step length P+1=2. The instruction reading circuit 10 compares the instruction address I2 with the instruction address in the cache 100, and determines that there is no instruction address I2 in the cache 100, so it is necessary to perform sequential prefetch. The address C output by the address arbiter 700 is the instruction address I2. The instruction D2 corresponding to the instruction address I2 and the instruction D3 corresponding to the instruction address I3 are read from the instruction memory 30 and stored in the cache 100. Specifically, refer to Fig.11 and Fig. 13B In clock cycles 7 and 8, instruction address I0 and instruction D0 are stored in cache area 114, instruction address I1 and instruction D1 are stored in cache area 113, instruction address I2 and instruction D2 are stored in cache area 112, and instruction address I3 and instruction D3 are stored in cache area 111.

[0101] The decoder 300 reads instruction D1 corresponding to instruction address I1 from the cache 100. The branch predictor 500 determines that instruction D1 is a branch instruction for a jump and needs to perform a jump prefetch. The branch predictor 500 predicts that the target instruction address J is I8. The address C output by the address arbitrator 700 is the instruction address I8. The instruction D8 corresponding to instruction address I8 and the instruction D9 corresponding to instruction address I9 are read from the instruction memory 30 and stored in the cache 100. Specifically, referring to Fig.11 and Fig. 13C , in clock cycles 9 and 10, instruction address I0 and instruction D0 are stored in cache area 116, instruction address I1 and instruction D1 are stored in cache area 115, instruction address I2 and instruction D2 are stored in cache area 114, instruction address I3 and instruction D3 are stored in cache area 113, instruction address I8 and instruction D8 are stored in cache area 112, and instruction address I9 and instruction D9 are stored in cache area 111.

[0102] After clock cycle 2-5, the instruction fetching stage of instruction address I0 is completed. Instruction fetching circuit 10 performs three judgments in clock cycle 2-8 (whether instruction address I0 is hit in cache 100, whether instruction address I2 is hit in cache, whether instruction D1 corresponding to instruction address I1 is a branch instruction of jump) and accesses instruction memory 30 three times based on the judgment results.

[0103] In clock cycle 6, the processor 20 sequentially fetches instruction I1, and the processor 20 sends a read request and instruction address I1 to the instruction fetch circuit 10. Fig.12 As shown, the processor 20 processes the instruction stream in a pipeline form. After the instruction fetch operation of the instruction address I0 is completed, the processor 20 simultaneously performs the decoding operation of the instruction D0 corresponding to the instruction address I0 and the instruction fetch operation of the instruction address I1. The instruction fetch circuit 10 receives the request of the instruction address I1. The instruction fetch circuit 10 compares the instruction address I1 with the instruction address in the cache 100, and hits the instruction address I1 in the cache 100. In clock cycle 7, the processor 20 obtains the instruction D1 corresponding to the instruction address I1 from the cache 100, and the instruction fetch stage of the instruction address I1 is completed.

[0104] like Fig.12As shown, when the instruction fetch operation of instruction address I1 is completed, the processor 20 simultaneously performs the decoding operation of instruction D1 corresponding to instruction address I1 and the instruction fetch operation of instruction address I2. At the same time, the instruction reading circuit 10 also performs the judgment of sequential prefetch and branch prediction based on the instruction address I1. The instruction reading circuit 10 determines the instruction address I3 corresponding to the sequential prefetch according to the prefetch step length P+1=2. The instruction reading circuit 10 compares the instruction address I3 with the instruction address in the cache 100, and determines that the instruction address I3 is in the cache 100, so there is no need to perform sequential prefetch. The decoder 300 reads the instruction D2 corresponding to the instruction address I2 from the cache 100. The branch predictor 500 determines that the instruction D2 corresponding to the instruction address I2 is a non-branch instruction or a branch instruction that does not jump, so there is no need to perform jump prefetch.

[0105] In clock cycle 8, processor 20 sequentially fetches instruction I2, and processor 20 sends a read request and instruction address I2 to instruction fetch circuit 10. Instruction fetch circuit 10 hits instruction address I2 in cache 100. In clock cycle 9, processor 20 obtains instruction D2 corresponding to instruction address I2 from cache 100, and the instruction fetch stage of instruction address I2 is completed.

[0106] After the instruction address I2 is fetched, the instruction reading circuit 10 determines the instruction address I4 corresponding to the sequential prefetch according to the prefetch step length P+1=2. The instruction reading circuit 10 compares the instruction address I4 with the instruction address in the cache 100. The instruction address I4 is not hit in the cache 100, so it is necessary to perform sequential prefetch. The address C output by the address arbiter 700 is the instruction address I4. The instruction D4 corresponding to the instruction address I4 and the instruction D5 corresponding to the instruction address I5 are read from the instruction memory 30 and stored in the cache 100. Specifically, referring to Fig.11 and Fig.13D , in clock cycles 11 and 12, instruction address I2 and instruction D2 are stored in cache area 116, instruction address I3 and instruction D3 are stored in cache area 115, instruction address I8 and instruction D8 are stored in cache area 114, instruction address I9 and instruction D9 are stored in cache area 113, instruction address I4 and instruction D4 are stored in cache area 112, and instruction address I5 and instruction D5 are stored in cache area 111.

[0107] The decoder 300 reads the instruction D3 corresponding to the instruction address I3 from the cache 100. The branch predictor 500 determines that the instruction D3 corresponding to the instruction address I3 is a non-branch instruction or a branch instruction that does not jump, so there is no need to perform jump prefetching.

[0108] In clock cycle 10, processor 20 sequentially fetches instruction I3, and processor 20 sends a read request and instruction address I3 to instruction fetch circuit 10. Instruction fetch circuit 10 hits instruction address I3 in cache 100. In clock cycle 11, processor 20 obtains instruction D3 corresponding to instruction address I3 from cache 100, and the instruction fetch stage of instruction address I3 is completed.

[0109] After the instruction fetch of instruction address I3 is completed, instruction fetch circuit 10 compares instruction address I5 with the instruction address in cache 100, and determines that instruction address I5 is in cache 100, so there is no need to perform sequential prefetch. Decoder 300 reads instruction D4 corresponding to instruction address I4 from cache 100. Branch predictor 500 determines that instruction D4 corresponding to instruction address I4 is a non-branch instruction or a branch instruction that does not jump, so there is no need to perform jump prefetch.

[0110] like Fig.12 As shown, in the instruction fetch stage of instruction address I3, processor 20 is simultaneously executing instruction D1 corresponding to instruction address I1. After executing instruction D1, processor 20 determines that the jump target address of instruction D1 is I8. In clock cycle 12, processor 20 sends a read request and instruction address I8 to instruction fetch circuit 10. Instruction fetch circuit 10 hits instruction address I8 in cache 100. In clock cycle 13, processor 20 obtains instruction D8 corresponding to instruction address I8 from cache 100, and the instruction fetch stage of instruction address I8 is completed.

[0111] If the instruction reading circuit 10 does not perform branch prediction for instruction D1 in advance, there is no instruction D8 corresponding to instruction address I8 in cache 100, and instruction memory 30 needs to be accessed to obtain instruction D8 corresponding to instruction address I8, which requires more time overhead and causes the pipeline to pause.

[0112] After the instruction address I8 is fetched, the instruction reading circuit 10 determines the instruction address I10 corresponding to the sequential prefetch according to the prefetch step length P+1=2. The instruction reading circuit 10 compares the instruction address I10 with the instruction address in the cache 100. The instruction address I10 is not hit in the cache 100, so it is necessary to perform sequential prefetch. The address C output by the address arbiter 700 is the instruction address I10. The instruction D10 corresponding to the instruction address I10 and the instruction D11 corresponding to the instruction address I11 are read from the instruction memory 30 and stored in the cache 100. Specifically, refer to Fig.11 and Fig.13E, in clock cycles 15 and 16, instruction address I8 and instruction D8 are stored in cache area 116, instruction address I9 and instruction D9 are stored in cache area 115, instruction address I4 and instruction D4 are stored in cache area 114, instruction address I5 and instruction D5 are stored in cache area 113, instruction address I10 and instruction D10 are stored in cache area 112, and instruction address I11 and instruction D11 are stored in cache area 111.

[0113] The decoder 300 reads the instruction D9 corresponding to the instruction address I9 from the cache 100. The branch predictor 500 determines that the instruction D9 corresponding to the instruction address I9 is ​​a non-branch instruction or a branch instruction that does not jump, so there is no need to perform jump prefetching.

[0114] In clock cycle 14, processor 20 sequentially fetches instruction I9, and processor 20 sends a read request and instruction address I9 to instruction fetch circuit 10. Instruction fetch circuit 10 hits instruction address I9 in cache 100. In clock cycle 15, processor 20 obtains instruction D9 corresponding to instruction address I9 from cache 100, and the instruction fetch stage of instruction address I9 is ​​completed.

[0115] After the instruction address I9 is ​​fetched, the instruction fetch circuit 10 hits the instruction address I11 in the cache 100 , so there is no need to perform sequential prefetching.

[0116] The decoder 300 reads the instruction D10 corresponding to the instruction address I10 from the cache 100. The branch predictor 500 determines that the instruction D10 is a non-branch instruction or a branch instruction that does not jump, so there is no need to perform jump prefetching.

[0117] In clock cycle 16, processor 20 sequentially fetches instruction I10, and processor 20 sends a read request and instruction address I10 to instruction fetch circuit 10. Instruction fetch circuit 10 hits instruction address I10 in cache 100. In clock cycle 17, processor 20 obtains instruction D10 corresponding to instruction address I10 from cache 100, and the instruction fetch stage of instruction address I10 is completed.

[0118] In the above embodiment, instruction fetching of instruction D0 requires 4 clock cycles ( Fig.11 In the clock cycles 2-5), it takes 2 cycles to fetch the addresses of other instructions, and only 2 cycles to fetch the jump target instruction D8 of the branch instruction D1. There is no pipeline pause, which reduces the fetching time when the branch instruction occurs.

[0119] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A microcontroller comprising: The processor issues the instruction address; An instruction memory storing a number of instructions; as well as An instruction reading circuit, wherein the instruction reading circuit includes a cache, a decoder, a branch predictor and an address arbitrator, The cache of the instruction reading circuit receives a request from the processor to access a current instruction address I, where I is an integer; If the cache stores an instruction corresponding to the next instruction address I+1 of the current instruction address I, the decoder obtains the instruction corresponding to the instruction address I+1 from the cache, the decoder decodes the instruction corresponding to the instruction address I+1 and determines whether the instruction corresponding to the instruction address I+1 is a branch instruction, and the branch predictor determines a target instruction address J when the instruction corresponding to the instruction address I+1 is a branch instruction and the branch instruction jumps, wherein J is an integer and the instruction corresponding to the instruction address J is not in the cache; The target instruction address J is sent to the instruction memory after being arbitrated by the address arbitrator; When the instruction address received by the instruction memory is the target instruction address J, the instruction reading circuit reads the instructions corresponding to the target instruction address J to instruction address J+P from the instruction memory and stores them in the cache. If the processor requests to access any instruction address from the target instruction address J to instruction address J+P, the processor reads the instruction corresponding to the instruction address requested to be accessed from the cache, where P is a positive integer greater than or equal to 1 and P is less than the maximum number of instructions that can be stored in the cache.

2. The microcontroller according to claim 1, characterized in that The instruction reading circuit also includes a multiplexer, If there is an instruction corresponding to the instruction address I in the cache, the instruction corresponding to the instruction address I is provided to the processor via a multiplexer; If there is no instruction corresponding to the instruction address I in the cache, the instruction address I and the target instruction address J are arbitrated by the address arbitrator, and the instruction address I is first sent to the instruction memory, and the instructions corresponding to the instruction address I to instruction address I+P are read from the instruction memory and stored in the cache. If the processor requests any instruction address from the instruction address I to the instruction address I+P, the instruction corresponding to the requested instruction address is read from the cache, and then the target instruction address J is sent to the instruction memory, and the instructions corresponding to the target instruction address J to instruction address J+P are read from the instruction memory and stored in the cache. If the processor requests to access any instruction address from the target instruction address J to the instruction address J+P, the processor reads the instruction corresponding to the requested instruction address from the cache.

3. The microcontroller according to claim 2, characterized in that: If there is an instruction corresponding to the instruction address I in the cache, the instruction corresponding to the instruction address I is provided to the processor via the multiplexer; If there is no instruction corresponding to the instruction address I and the instruction corresponding to the instruction address I+P+1 in the cache, the instruction address I, the instruction address I+P+1 and the target instruction address J are arbitrated by the address arbitrator, and the instruction address I is first sent to the instruction memory, and the instructions corresponding to the instruction addresses I to I+P are read from the instruction memory and stored in the cache. If the processor requests any instruction address from the instruction address I to the instruction address I+P, the instruction corresponding to the instruction address requested to be accessed is read from the cache, and then the instruction address I+P+1 is sent to the instruction memory, and the instructions corresponding to the instruction address I to I+P are read from the instruction memory. The instructions corresponding to instruction address I+P+1 to instruction address I+2P+1 are stored in the cache. If the processor requests to access any instruction address from instruction address I+P+1 to instruction address I+2P+1, the processor reads the instruction corresponding to the instruction address requested to be accessed from the cache, and finally sends the target instruction address J to the instruction memory, reads the instructions corresponding to the target instruction address J to instruction address J+P from the instruction memory and stores them in the cache. If the processor requests to access any instruction address from instruction address J to instruction address J+P, the processor reads the instruction corresponding to the instruction address requested to be accessed from the cache.

4. The microcontroller according to claim 3, characterized in that: The step size is P+1.

5. The microcontroller according to claim 3, characterized in that: P=1 or 2.

6. The microcontroller according to claim 1, characterized in that: The cache includes a plurality of cache areas, each of which is used to store an instruction address and an instruction corresponding to the instruction address.

7. The microcontroller according to claim 6, characterized in that: The cache is a first-in-first-out cache.

8. The microcontroller according to claim 1, characterized in that: The cache is a static random access memory or a register, and the instruction memory is a non-volatile memory.

9. A method for operating a microcontroller, the microcontroller comprising: The processor is configured to issue instruction addresses; an instruction memory configured to store a plurality of instructions; and instruction fetch circuits, including cache, decoder, branch predictor, and address arbiter, The operation method comprises: The cache of the instruction reading circuit receives a request from the processor to access a current instruction address I, where I is an integer; If the cache stores an instruction corresponding to the next instruction address I+1 of the current instruction address I, the decoder obtains the instruction corresponding to the instruction address I+1 from the cache, the decoder decodes the instruction corresponding to the instruction address I+1 and determines whether the instruction corresponding to the instruction address I+1 is a branch instruction, and the branch predictor determines a target instruction address J when the instruction corresponding to the instruction address I+1 is a branch instruction and the branch instruction jumps, wherein J is an integer and the instruction corresponding to the instruction address J is not in the cache; The target instruction address J is sent to the instruction memory after being arbitrated by the address arbitrator; When the instruction address received by the instruction memory is the target instruction address J, the instruction reading circuit reads the instructions corresponding to the target instruction address J to instruction address J+P from the instruction memory and stores them in the cache. If the processor requests to access any instruction address from the target instruction address J to instruction address J+P, the processor reads the instruction corresponding to the instruction address requested to be accessed from the cache, where P is a positive integer greater than or equal to 1 and P is less than the maximum number of instructions that can be stored in the cache.

10. The operating method according to claim 9, characterized in that: The instruction reading circuit further includes a multiplexer, and the operating method further includes: If there is an instruction corresponding to the instruction address I in the cache, the instruction corresponding to the instruction address I is provided to the processor via a multiplexer; If there is no instruction corresponding to the instruction address I in the cache, the instruction address I and the target instruction address J are arbitrated by the address arbitrator, and the instruction address I is first sent to the instruction memory, and the instructions corresponding to the instruction address I to instruction address I+P are read from the instruction memory and stored in the cache. If the processor requests any instruction address from the instruction address I to the instruction address I+P, the instruction corresponding to the requested instruction address is read from the cache, and then the target instruction address J is sent to the instruction memory, and the instructions corresponding to the target instruction address J to instruction address J+P are read from the instruction memory and stored in the cache. If the processor requests to access any instruction address from the target instruction address J to the instruction address J+P, the processor reads the instruction corresponding to the requested instruction address from the cache.

11. The operating method according to claim 10, characterized in that: If there is an instruction corresponding to the instruction address I in the cache, the instruction corresponding to the instruction address I is provided to the processor via the multiplexer; If there is no instruction corresponding to the instruction address I and the instruction corresponding to the instruction address I+P+1 in the cache, the instruction address I, the instruction address I+P+1 and the target instruction address J are arbitrated by the address arbitrator, and the instruction address I is first sent to the instruction memory, and the instructions corresponding to the instruction addresses I to I+P are read from the instruction memory and stored in the cache. If the processor requests any instruction address from the instruction address I to the instruction address I+P, the instruction corresponding to the instruction address requested to be accessed is read from the cache, and then the instruction address I+P+1 is sent to the instruction memory, and the instructions corresponding to the instruction address I to I+P are read from the instruction memory. The instructions corresponding to instruction address I+P+1 to instruction address I+2P+1 are stored in the cache. If the processor requests to access any instruction address from instruction address I+P+1 to instruction address I+2P+1, the processor reads the instruction corresponding to the instruction address requested to be accessed from the cache, and finally sends the target instruction address J to the instruction memory, reads the instructions corresponding to the target instruction address J to instruction address J+P from the instruction memory and stores them in the cache. If the processor requests to access any instruction address from instruction address J to instruction address J+P, the processor reads the instruction corresponding to the instruction address requested to be accessed from the cache.

12. The operating method according to any one of claims 9 to 11, characterized in that: P=1 or 2.

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