Single event latch-up resistant network based on spaceborne computer

Abstract

The invention discloses an anti-single-particle latch-up network based on spaceborne computers, and relates to the technical field of single-particle latch-up protection.According to the anti-single-particle latch-up network based on the spaceborne computers, the spaceborne computers are arranged in a distributed architecture, and each spaceborne computer is provided with a latch-up detection circuit, an anti-latch-up circuit and a temperature sensor; when a certain spaceborne computer detects that a single-particle latch-up effect is generated in a power domain of the spaceborne computer through a latch-up detection circuit, on one hand, a power supply is cut off through an anti-latch-up circuit to realize latch-up isolation, and on the other hand, a neighbor spaceborne computer is notified through the anti-latch-up circuit to realize latch-up isolation; the neighbor spaceborne computer judges whether the trigger environment is eliminated or not based on the temperature sensor on the fault spaceborne computer, and timely controls the fault spaceborne computer to be powered on again after the trigger environment is eliminated, so that the recovery efficiency of the fault spaceborne computer is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of single particle latch protection, and in particular to a single particle latch resistance network based on a satellite-borne computer. Background Art

[0002] At present, onboard computers are manufactured using CMOS integrated circuit technology. In the space radiation environment, when computer chips are exposed to radiation, semiconductor devices are ionized and generate photocurrent, which is called single-particle latch-up effect. The parasitic current generated by the single-particle latch-up effect usually manifests as a large current, which will have a great impact on the normal operation of the chip. Once the single-particle latch-up effect occurs, the latched state of the device can usually only be released by powering off and then powering on again. If the single-particle latch-up effect is not discovered in time and timely measures are not taken, the heat generated by the parasitic current will accumulate and burn the device.

[0003] In the prior art, whether the single-particle latch effect occurs is generally determined by current threshold detection. When it is detected that the current exceeds the preset current threshold, the load power supply is immediately cut off, and then the power is turned on again after a delay, so that the chip exits the single-particle latch state, thereby achieving protection against single-particle latch.

[0004] However, the traditional protection method against single-particle latch-up will not work normally for a period of time after the entire chip is powered off, and the power-on time is controlled by a fixed delay circuit. It is difficult to determine whether the triggering environment of the single-particle latch-up effect has been released, and the power-on time cannot be controlled autonomously, and the recovery efficiency is low. Summary of the invention

[0005] Based on this, it is necessary to provide a single-particle latch-resistant network based on a satellite-borne computer to address the above technical problems.

[0006] The present invention adopts the following technical solutions:

[0007] The present invention provides a single-particle latch-up resistant network based on onboard computers, comprising: a plurality of onboard computers in a distributed architecture;

[0008] Each of the onboard computers is provided with a latch detection circuit, an anti-latch circuit and a temperature sensor;

[0009] The temperature sensor is arranged in the power domain of the corresponding onboard computer, and the temperature sensor is connected to each neighboring onboard computer respectively;

[0010] The latch detection circuit is used to detect the power domain of the corresponding onboard computer and output a latch signal when a single-particle latch phenomenon occurs in the power domain of the corresponding onboard computer;

[0011] The anti-latch circuit comprises: a power control latch, a latch latch, a first NOT gate and a first AND gate;

[0012] The input end of the latch is connected to the output end of the latch detection circuit of the corresponding onboard computer, and the output end of the latch is connected to the neighbor onboard computer; the latch is used to output a latch interrupt signal to the neighbor onboard computer after an integral delay when receiving a latch signal, so that the neighbor onboard computer controls the temperature sensor in the power domain of the corresponding onboard computer to perform temperature detection; when it is determined through temperature detection that the trigger environment of the single-particle latch effect of the corresponding onboard computer is eliminated, the neighbor onboard computer outputs a reset signal to the power control latch;

[0013] The output end of the latch is also connected to the first input end of the first AND gate via the first NOT gate, the second input end of the first AND gate is connected to the output end of the latch detection circuit, and the output end of the first AND gate is linked to the input end of the power control latch; the set end of the power control latch is connected to the neighboring onboard computer, and the output end of the power control latch is connected to the power domain of the corresponding onboard computer; the power control latch is used to respond to the latch signal before the latch latch integrates the delay and turns off the power of the corresponding onboard computer; the input of the power control latch flips after the latch latch integrates the delay, and after the triggering environment of the single-particle latch effect is eliminated, the reset signal is received through the set end to flip the output and turn on the power of the corresponding onboard computer.

[0014] Optionally, the set end of the latch is connected to a control module of the onboard computer;

[0015] The latch register does not respond to the output signal of the latch detection circuit before receiving the latch signal and the onboard computer is powered on and started;

[0016] The latching latch flips its input after the triggering environment of the single-particle latch effect of the onboard computer is eliminated, and flips its output by receiving a startup completion signal through the set terminal after the onboard computer is powered on, and responds to the output signal of the latch detection circuit again.

[0017] Optionally, the power control latch and the latch latch both include: a second OR gate, a delay capacitor, a pull-up resistor, a second AND gate and a trigger;

[0018] The first input end of the second OR gate is used as the input end of the power control latch / latch latch, the output end of the second OR gate is connected to the delay capacitor and then grounded, the output end of the second OR gate is also connected to the input end of the trigger, the output end of the trigger is used as the output end of the power control latch / latch latch, the output end of the trigger is connected to the first output end of the second AND gate, and the second input end of the second AND gate is connected to the pull-up resistor and then used as the set end of the power control latch / latch latch;

[0019] The power control latch / latch latch is used to output a high level after delayed integration of the input positive pulse signal and maintain it relative to the input signal, and to output a low level under a set negative pulse signal and maintain it relative to the set signal.

[0020] Optionally, the latch detection circuit comprises: a current detection resistor, a subtractor, a differentiator circuit, an adder and a forward Schmitt trigger;

[0021] The current detection resistor is arranged in the power domain of the onboard computer;

[0022] The voltage across the current detection resistor is input to the positive input terminal and the negative input terminal of the subtractor, the output terminal of the subtractor is respectively connected to the input terminal of the differential circuit and the first input terminal of the adder, the output terminal of the differential circuit is connected to the second input terminal of the adder, the output terminal of the adder is connected to the input terminal of the positive Schmitt trigger, and the output terminal of the positive Schmitt trigger is respectively connected to the input terminal of the anti-latch circuit and the second input terminal of the first AND gate;

[0023] The subtractor is used to obtain the voltage difference across the current detection resistor, the differential circuit is used to obtain the change gradient of the voltage difference, the adder is used to perform weighted addition of the change gradient of the voltage difference and the voltage difference to obtain the voltage to be detected, and the Schmitt trigger is used to determine whether a single-particle latch phenomenon occurs in the power domain of the corresponding onboard computer based on the voltage to be detected.

[0024] Optionally, the power domains of the onboard computers in the distributed architecture are connected according to a mesh network structure;

[0025] The latch register is used to output a latch interrupt signal to the neighboring satellite computer after an integration delay when receiving a latch signal, so that the neighboring satellite computer cuts off the connection between the neighboring satellite computer power domain and the satellite computer power domain where the latch register is located.

[0026] Optionally, the anti-latch circuit further includes a first OR gate, a second NOT gate and a pull-up resistor;

[0027] The input end of the second NOT gate is connected to the neighboring satellite computer via a pull-up resistor, the output end of the second NOT gate is connected to the first input end of the first OR gate, the output end of the first AND gate is connected to the second input end of the first OR gate, and the output end of the first OR gate is connected to the input end of the power control latch;

[0028] The neighboring onboard computer sends a control signal to control the power supply of the onboard computer where the anti-latch circuit is located through the first OR gate, the second NOT gate and the pull-up resistor.

[0029] At least one of the above technical solutions adopted by the present invention can achieve the following beneficial effects:

[0030] The present invention arranges each onboard computer in a distributed architecture, and each onboard computer is provided with a latch detection circuit, an anti-latch circuit and a temperature sensor, and the anti-latch circuit includes a power control latch, a latch latch, a first NOT gate and a first AND gate.

[0031] When one of the onboard computers detects a single-particle latch effect, i.e., a fault, in its own power domain through a latch detection circuit, the output of the latch is first reversed through a first NOT gate before the latch is integrated and delayed, and the latch signal is input into an anti-latch circuit through a first AND gate, and the power supply is cut off through the anti-latch circuit to achieve latch isolation;

[0032] After the power is off, the single-particle latch effect of the faulty onboard computer cannot be maintained and will inevitably be eliminated. At this time, the latch latch outputs a latch interrupt signal to the neighboring onboard computer after an integral delay, so that the neighboring onboard computer controls the temperature sensor in the power domain of the corresponding onboard computer to perform temperature detection to determine whether the trigger environment is eliminated. If it is eliminated, the two input signals of the first AND gate will be flipped, thereby flipping the input of the power control latch. At the same time, the neighboring onboard computer will output a reset signal to the set end of the power control latch to flip the output of the power control latch, and timely control the faulty onboard computer to power on again. The automatic processing of the latch signal input and the automatic state transfer can be completed through a simple circuit structure, thereby improving the recovery efficiency of the faulty onboard computer. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0034] Figure 1 A schematic diagram of a satellite-borne computer network structure provided by the present invention;

[0035] Figure 2 A schematic diagram of the circuit principle of an anti-latch state machine provided by the present invention;

[0036] Figure 3 A schematic diagram of a state transition process of an anti-latch state machine after a single-particle latch occurs provided by the present invention;

[0037] Figure 4 A reset and shutdown signal line and function schematic diagram provided by the present invention;

[0038] Figure 5 A schematic diagram of a resettable latch circuit provided by the present invention;

[0039] Figure 6 A specific circuit diagram of a power control latch and a latch latch in an anti-latch circuit provided by the present invention;

[0040] Figure 7 A schematic diagram of the principle of a latch detection circuit provided by the present invention. DETAILED DESCRIPTION

[0041] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the specific embodiments of the present invention and the corresponding drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0042] At present, it is generally judged whether the single-particle latch effect occurs by performing current threshold detection. When protecting against the single-particle latch effect, one method is to immediately cut off the load power supply when the current exceeds the preset current threshold, and then re-power it after a delay to make the chip exit the single-particle latch state. Another method is to absorb or discharge the excessive single-particle latch current through a buffer after detecting the single-particle latch current pulse, thereby reducing the gain of the parasitic transistor, so that the conditions for the occurrence of the single-particle latch effect are no longer met, and latch protection is achieved.

[0043] Among them, the first method will lose power for a period of time after the entire chip is powered off and cannot work normally, and the power-on time is controlled by a fixed delay circuit. It is difficult to determine whether the latch trigger environment has been released, and the power-on time cannot be controlled independently. The second method adds additional thyristor rectifier devices to discharge the latch current. Although it can effectively suppress excessive latch current, it also puts higher requirements on the manufacturing process of integrated circuits.

[0044] The present invention proposes a distributed computer architecture, in which a computer is composed of a network of multiple nodes. When a single-particle latch occurs in a single node, the node is quickly powered off for latch isolation, and a latch interrupt message is sent to the surrounding nodes. When the node loses power and the single-particle latch is eliminated, the surrounding nodes restart the node, so that the computer can start powering on autonomously, which greatly improves the radiation resistance of the overall computer network. The anti-single-particle latch network proposed by the present invention uses basic CMOS devices to form an anti-latch state machine without adding other process devices, and uses circuit logic to realize the single-particle latch isolation function, so as to prevent the single-particle latch effect of a single node from affecting the upstream circuit, and can be reset under the control of neighboring nodes after the latch is released, and re-enter the single-particle latch detection mode.

[0045] The technical solutions provided by various embodiments of the present invention are described in detail below in conjunction with the accompanying drawings.

[0046] Figure 1 The figure is a schematic diagram of a satellite computer network structure in the present invention. In one or more embodiments of the present invention, the anti-single-particle latch network based on satellite computers may include multiple satellite computers in a distributed architecture. For example, the anti-single-particle latch network proposed in the present invention may be obtained by constructing computers in a Mesh network structure, and each node in the network processes information. When a single-particle latch occurs, the faulty node immediately loses the ability to process information, and the processing of the single-particle latch event requires the faulty node to cooperate with neighboring nodes.

[0047] Each onboard computer is provided with a latch detection circuit, an anti-latch circuit and a temperature sensor. The temperature sensor is provided in the power domain of the corresponding onboard computer, and the temperature sensor is connected to each neighboring onboard computer; the latch detection circuit is used to detect the power domain of the corresponding onboard computer, and output a latch signal when a single-particle latch phenomenon occurs in the power domain of the corresponding onboard computer. The anti-latch circuit will immediately send a latch interrupt signal to the neighboring node after detecting the latch signal, and automatically cut off the power supply of the faulty node. In one or more embodiments of the present invention, for a Mesh structure network, the latch interrupt of a node can be sent to the four neighboring nodes of the node to ensure reliability.

[0048] The anti-latch circuit may include a power control latch, a latch latch, a first NOT gate and a first AND gate.

[0049] The input end of the latch is connected to the output end of the latch detection circuit of the corresponding onboard computer, and the output end of the latch is connected to the neighboring onboard computer; the latch is used to output a latch interrupt signal to the neighboring onboard computer after an integral delay when receiving a latch signal, so that the neighboring onboard computer controls the temperature sensor in the power domain of the corresponding onboard computer to perform temperature detection; when it is determined through temperature detection that the trigger environment of the single-particle latch effect of the corresponding onboard computer is eliminated, the neighboring onboard computer outputs a reset signal to the power control latch.

[0050] The output end of the latch is also connected to the first input end of the first AND gate via the first NOT gate, the second input end of the first AND gate is connected to the output end of the latch detection circuit, and the output end of the first AND gate is linked to the input end of the power control latch; the set end of the power control latch is connected to the neighboring onboard computer, and the output end of the power control latch is connected to the power domain of the corresponding onboard computer; the power control latch is used to respond to the latch signal before the latch latch integration delay and turn off the power of the corresponding onboard computer; the input of the power control latch is flipped after the latch latch integration delay, and the output is flipped by receiving the reset signal through the set end after the trigger environment of the single-particle latch effect is eliminated, thereby turning on the power of the corresponding onboard computer.

[0051] Furthermore, in one or more embodiments of the present invention, the anti-latch circuit may further include a first OR gate, a second NOT gate and a pull-up resistor.

[0052] The input end of the second NOT gate is connected to the neighboring onboard computer via a pull-up resistor, the output end of the second NOT gate is connected to the first input end of the first OR gate, the output end of the first AND gate is connected to the second input end of the first OR gate, and the output end of the first OR gate is connected to the input end of the power control latch. Based on this, the neighboring onboard computer can send a control signal to control the power supply of the onboard computer where the anti-latch circuit is located via the first OR gate, the second NOT gate and the pull-up resistor.

[0053] Furthermore, in one or more embodiments of the present invention, power domains of each onboard computer in a distributed architecture are connected according to a mesh network structure.

[0054] The latch register is used to output a latch interrupt signal to the neighboring satellite computer after an integration delay when receiving a latch signal, so that the neighboring satellite computer cuts off the connection between the neighboring satellite computer power domain and the satellite computer power domain where the latch register is located.

[0055] The core logic component of the anti-latch circuit is the anti-latch state machine. The anti-latch state machine can stably and reliably process the input signal and generate the required control signal. Figure 2 As shown, it contains 4 input signals and 2 output signals.

[0056] Among them, the "shutdown" and "reset" signals are control signals used by neighbor nodes to control the current node, controlling the shutdown / opening of the power supply of the current node. Negative pulses are valid, and pull-up resistors are used inside the state machine.

[0057] The single-particle latch detection logic may be flipped erroneously between the time when the power of the node is turned off and the startup initialization of the node is completed and the operation is stable. Therefore, in one or more embodiments of the present invention, the set end of the latch register is connected to the control module of the onboard computer. The latch register does not respond to the output signal of the latch detection circuit before receiving the latch signal and the onboard computer is powered on and started. The input of the latch register flips after the triggering environment of the single-particle latch effect of the onboard computer is eliminated. After the onboard computer is powered on and started, the output is flipped through the set end to receive the startup completion signal to respond to the output signal of the latch detection circuit again. In this way, the anti-latch state machine keeps the power on and shields the latch detection result, and informs the anti-latch state machine of the startup completion through the "startup completion" signal, and can start working.

[0058] When the node detects a single-particle latch effect, it can inform the anti-latch state machine through the "latch" signal. After the "latch" signal is pulled high for a certain period of time, the "latch interrupt" signal switches to a high level to inform the neighboring node, and immediately switches the "switch" output signal from 0 to 1, thereby turning off the power supply of the node. Table 1 is a schematic diagram of all input and output signals of the anti-latch state machine.

[0059] Table 1 Schematic diagram of all input and output signals of the anti-latch state machine

[0060] Signal name direction Valid status Normal state Description Shutdown enter Negative pulse is effective Floating pull-up External control to shut down module power supply Reset enter Negative pulse is effective Floating pull-up External control to turn on the module power Latch enter Positive pulse is valid Low level Input positive pulse when latch event is detected Startup completed enter Negative pulse is effective Floating pull-up System startup completes input negative pulse switch Output Level effective High / Low Level A high level turns off the system power supply, and a low level turns on the system power supply Latch Interrupt Output Level effective Low level A latch event is detected and the output is high

[0061] Figure 3 FIG. 1 is a schematic diagram of a state transition process of an anti-latch state machine after a single-particle latch occurs in the present invention. Figure 1 Each node is connected to four neighboring nodes. The latch interrupt, shutdown, and reset signals are independently networked to ensure that information processing can be completed through the simplest circuit during the latch process. The reset and shutdown signals use OC (open collector output, which pulls up the voltage through a pull-up resistor when the output is high, and directly connects to the ground when the output is low) output form, providing a wired AND function (that is, all output signals are connected together) so that the outputs of all neighboring nodes can be directly interconnected, such as Figure 4 As shown, Figure 4 The figure is a schematic diagram of reset and shutdown signal lines and functions in the present invention.

[0062] To ensure the reliability of the circuit, the main input signals are in pulse valid form instead of level valid form to eliminate possible interference such as signal glitches or jitter. At the same time, in order to support the simultaneous control of multiple neighboring nodes and ensure that the signal is stable and reliable when the module is initialized, the main signals need to be in the form of OC output plus pull. Therefore, the resettable latch in the circuit is designed to meet the above requirements, and the resettable latch logic function is shown in Table 2 below. Table 2 is a schematic table of the resettable latch logic function in the present invention.

[0063] Table 2 Schematic diagram of resettable latch logic function

[0064]

[0065] The resettable latch is initialized to 0 after power-on. When the input In interface receives a positive pulse, the internal state of the latch switches to 1. After that, no matter what state the input In is in, the internal state remains 1 until the input Reset receives a negative pulse signal, and the internal state of the latch switches to 0 and remains in this state regardless of any state on the input Reset. The circuit schematic is shown in the figure below. Figure 5 As shown, Figure 5 A schematic diagram of a resettable latch circuit in the present invention.

[0066] Depend on Figure 5 It can be seen that the resettable latch of the power control latch and the latch latch both include: a second OR gate, a delay capacitor, a pull-up resistor, a second AND gate and a trigger.

[0067] The first input end of the second OR gate serves as the input end of the power control latch / latch latch, the output end of the second OR gate is connected to the delay capacitor and then grounded, the output end of the second OR gate is also connected to the input end of the trigger, the output end of the trigger serves as the output end of the power control latch / latch latch, the output end of the trigger is connected to the first output end of the second AND gate, and the second input end of the second AND gate is connected to the pull-up resistor and serves as the set end of the power control latch / latch latch.

[0068] The power control latch / latch latch is used to output a high level after delayed integration of the input positive pulse signal and maintain it relative to the input signal. Under the set negative pulse signal, the output flips to a low level and maintains it relative to the set signal.

[0069] Based on this, the resettable latch realizes delayed integration by including a capacitor, and cooperates with a positive Schmitt trigger for threshold judgment to achieve logic flip. The latch function can be realized by feeding back the output of the Schmitt trigger to the input, so that the circuit state has a self-stabilizing characteristic and can maintain the state after flipping. In order to realize the triggering and resetting of the latch, the OR gate is used to realize the cutoff of the feedback path by the input In, and the AND gate is used to realize the cutoff of the feedback path by the input Reset.

[0070] Figure 6 The present invention is a specific circuit diagram of a power control latch and a latch latch in an anti-latch circuit. Figure 6 In the embodiment, the power control latch is the resettable latch L1, and the latch latch is the resettable latch L2.

[0071] For latch detection circuits, the traditional method uses a threshold judgment method, that is, as long as the current exceeds the threshold, it is judged to be latched. However, the disadvantage of this method is that in order to avoid false triggering, the threshold is usually set to a higher current, and a higher threshold may miss micro-latch events and cause system failure.

[0072] In one or more embodiments of the present invention, in order to solve this problem, the following circuit is proposed. Due to latch detection, the decision threshold is not only based on the absolute value of the current, but also on the gradient of the current change, and then the result is output after the threshold decision. The circuit schematic diagram is shown in FIG. Figure 7 As shown, Figure 7 The figure is a schematic diagram of the principle of a latch detection circuit in the present invention.

[0073] The latch detection circuit may include: a current detection resistor, a subtractor, a differential circuit, an adder and a positive Schmitt trigger. The current detection resistor is arranged in the power domain of the onboard computer.

[0074] The voltage across the current detection resistor is input to the positive input and negative input of the subtractor, the output of the subtractor is respectively connected to the input of the differential circuit and the first input of the adder, the output of the differential circuit is connected to the second input of the adder, the output of the adder is connected to the input of the positive Schmitt trigger, and the output of the positive Schmitt trigger is respectively connected to the input of the anti-latch circuit and the second input of the first AND gate.

[0075] The subtractor is used to obtain the voltage difference across the current detection resistor, the differential circuit is used to obtain the change gradient of the voltage difference, the adder is used to perform weighted addition of the change gradient of the voltage difference and the voltage difference to obtain the voltage to be detected, and the Schmitt trigger is used to determine whether a single-particle latch phenomenon occurs in the power domain of the corresponding onboard computer based on the voltage to be detected.

[0076] The subtractor output formula is:

[0077] make We can get:

[0078] The detection current satisfies the formula:

[0079] The output formula of the differential circuit is:

[0080] The adder output formula is:

[0081] Arranged as:

[0082] Let the weight coefficient

[0083] The current threshold detection can be summarized as follows:

[0084] Wherein, L is the output signal of the latch detection circuit, I is the current value from Vin to Vout, dI is the current gradient, a1 and a2 are weight coefficients, T is the preset current threshold, and the activation function can be implemented by a positive Schmitt trigger.

[0085] The present invention adopts network topology to realize circuit anti-latch, which solves the problem that the power cannot be autonomously controlled after re-powering on after single-particle latching. Distributed nodes can realize latch reinforcement and latch isolation functions, prevent single-particle latching from affecting upstream current, and enhance the overall chip's anti-radiation ability. The anti-latch state machine can complete the automatic processing of latch signal input through a simple circuit structure and basic analog devices, automatically transfer the state, and notify multiple neighboring nodes at the same time. When reset is required, it is controlled by multiple neighboring nodes and has high reliability. When detecting the occurrence of latching, the micro-latch detection function considers the changes in the absolute value of the current and the current gradient at the same time, and the detection accuracy is higher.

[0086] It should also be noted that the terms “comprises”, “includes” or any other variations thereof in the present invention are intended to cover non-exclusive inclusion, that is, in addition to the elements listed in the present invention, other elements not explicitly listed may also be included.

[0087] The various embodiments of the present invention are described in a progressive manner, and the same or similar parts between the various embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments.

[0088] The above description is only an embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent substitution, improvement, etc. made within the spirit and principle of the present invention should be included in the scope of the claims of the present invention.

Claims

1. A single event latch-up resistant network based on a satellite-borne computer, characterized in that: include: Multiple onboard computers with distributed architecture; Each of the onboard computers is provided with a latch detection circuit, an anti-latch circuit and a temperature sensor; The temperature sensor is arranged in the power domain of the corresponding onboard computer, and the temperature sensor is connected to each neighboring onboard computer respectively; The latch detection circuit is used to detect the power domain of the corresponding onboard computer and output a latch signal when a single-particle latch phenomenon occurs in the power domain of the corresponding onboard computer; The anti-latch circuit comprises: a power control latch, a latch latch, a first NOT gate and a first AND gate; The input end of the latch is connected to the output end of the latch detection circuit of the corresponding onboard computer, and the output end of the latch is connected to the neighbor onboard computer; the latch is used to output a latch interrupt signal to the neighbor onboard computer after an integral delay when receiving a latch signal, so that the neighbor onboard computer controls the temperature sensor in the power domain of the corresponding onboard computer to perform temperature detection; when it is determined through temperature detection that the trigger environment of the single-particle latch effect of the corresponding onboard computer is eliminated, the neighbor onboard computer outputs a reset signal to the power control latch; The output end of the latch is also connected to the first input end of the first AND gate via the first NOT gate, the second input end of the first AND gate is connected to the output end of the latch detection circuit, and the output end of the first AND gate is linked to the input end of the power control latch; the set end of the power control latch is connected to the neighboring onboard computer, and the output end of the power control latch is connected to the power domain of the corresponding onboard computer; the power control latch is used to respond to the latch signal before the latch latch integrates the delay and turns off the power of the corresponding onboard computer; the input of the power control latch flips after the latch latch integrates the delay, and after the triggering environment of the single-particle latch effect is eliminated, the reset signal is received through the set end to flip the output and turn on the power of the corresponding onboard computer.

2. The single event latch-up resistant network based on a satellite computer as claimed in claim 1, characterized in that: The set end of the latch is connected to the control module of the onboard computer; The latch register does not respond to the output signal of the latch detection circuit before receiving the latch signal and the onboard computer is powered on and started; The input of the latch is flipped after the triggering environment of the single-particle latch effect of the onboard computer is eliminated. After the onboard computer is powered on, the output is flipped by receiving a startup completion signal through the set terminal, and the output signal of the latch detection circuit is responded to again.

3. The single event latch-up resistant network based on a satellite computer as claimed in claim 1, characterized in that: The power control latch and the latch latch both include: a second OR gate, a delay capacitor, a pull-up resistor, a second AND gate and a trigger; The first input end of the second OR gate is used as the input end of the power control latch / latch latch, the output end of the second OR gate is connected to the delay capacitor and then grounded, the output end of the second OR gate is also connected to the input end of the trigger, the output end of the trigger is used as the output end of the power control latch / latch latch, the output end of the trigger is connected to the first output end of the second AND gate, and the second input end of the second AND gate is connected to the pull-up resistor and then used as the set end of the power control latch / latch latch; The power control latch / latch latch is used to output a high level after delayed integration of the input positive pulse signal and maintain it relative to the input signal, and to output a low level under a set negative pulse signal and maintain it relative to the set signal.

4. The single event latch-up resistant network based on a satellite computer as claimed in claim 1, characterized in that: The latch detection circuit comprises: a current detection resistor, a subtractor, a differentiator circuit, an adder and a forward Schmitt trigger; The current detection resistor is arranged in the power domain of the onboard computer; The voltage across the current detection resistor is input to the positive input terminal and the negative input terminal of the subtractor, the output terminal of the subtractor is respectively connected to the input terminal of the differential circuit and the first input terminal of the adder, the output terminal of the differential circuit is connected to the second input terminal of the adder, the output terminal of the adder is connected to the input terminal of the positive Schmitt trigger, and the output terminal of the positive Schmitt trigger is respectively connected to the input terminal of the anti-latch circuit and the second input terminal of the first AND gate; The subtractor is used to obtain the voltage difference across the current detection resistor, the differential circuit is used to obtain the change gradient of the voltage difference, the adder is used to perform weighted addition of the change gradient of the voltage difference and the voltage difference to obtain the voltage to be detected, and the Schmitt trigger is used to determine whether a single-particle latch phenomenon occurs in the power domain of the corresponding onboard computer based on the voltage to be detected.

5. The single event latch-up resistant network based on a satellite computer as claimed in claim 1, characterized in that: The power domains of the onboard computers in the distributed architecture are connected according to a mesh network structure; The latch register is used to output a latch interrupt signal to the neighboring satellite computer after an integration delay when receiving a latch signal, so that the neighboring satellite computer cuts off the connection between the neighboring satellite computer power domain and the satellite computer power domain where the latch register is located.

6. The single event latch-up resistant network based on a satellite computer as claimed in claim 1, characterized in that: The anti-latch circuit also includes a first OR gate, a second NOT gate and a pull-up resistor; The input end of the second NOT gate is connected to the neighboring satellite computer via a pull-up resistor, the output end of the second NOT gate is connected to the first input end of the first OR gate, the output end of the first AND gate is connected to the second input end of the first OR gate, and the output end of the first OR gate is connected to the input end of the power control latch; The neighboring onboard computer sends a control signal to control the power supply of the onboard computer where the anti-latch circuit is located through the first OR gate, the second NOT gate and the pull-up resistor.

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