A retransmission cache system based on UCIE

Abstract

The present invention discloses a retransmission cache system based on UCIE, and relates to the technical field of data cache. The system comprises a data receiving module, a mapping module, a pointer management module, a direct write buffer module, and a data transmission and storage module; the present invention realizes an efficient retransmission cache system through a UCIE adaptation layer, and is compatible with data Flit transmission and storage of two different sizes of 68B and 256B. The introduced buffer write-through function effectively reduces the delay of the storage matrix, reduces the read delay, and improves the data transmission efficiency. At the same time, the structure improves the resource utilization rate, and solves the problems of the traditional cache structure being not specific, insufficient resource utilization, and data transmission delay; the present invention controls the data flow by using the data receiving module and the token bucket algorithm, avoids network congestion, and ensures a reasonable data packet transmission rate.

Description

Technical Field

[0001] The present invention relates to the technical field of data cache, and in particular to a retransmission cache system based on UCIE. Background Art

[0002] UCIE (Universal Chiplet Interconnect Express, a cache system with intelligent switching capabilities) works with the protocol layer and the physical layer at the adaptation layer to support multiple data transmission formats. Specifically, it supports two sizes of Flit Size, 68B and 256B. The role of the adaptation layer is to ensure reliable data transmission, including retransmission functions to deal with errors or losses that may occur during data transmission.

[0003] However, although the UCIE standard defines the protocol and requirements for data transmission, the industry does not have a unified solution for the specific cache structure implementation of the adaptation layer. In the field of chip design, designers pursue low power and low area implementation, but when adapting to cache designs of two different Flit Sizes, how to obtain a storage structure that is both universal and can reduce area and power consumption is an urgent problem to be solved. According to the UCIE protocol, when a 64B Flit is received from the protocol layer, a 2B header needs to be added to the head of the data packet, a 2B cyclic redundancy check needs to be added to the tail, and it needs to be sent after being aligned to 68B. In terms of storage structure selection, the 68B and 256B modes can be aligned at a 64B granularity. Although this storage structure is simple and easy to use, it is not the optimal solution. Summary of the invention

[0004] The purpose of the present invention is to provide a retransmission cache system based on UCIE, which solves the problems of unclear cache structure, insufficient resource utilization and data transmission delay existing in the prior art by introducing a buffer write-through function through a structure of a UCIE adaptation layer compatible with two different formats of data transmission and storage modules.

[0005] The purpose of the present invention can be achieved by the following technical solutions:

[0006] The present application provides a retransmission cache system based on UCIE, including a data receiving module, a mapping module, a pointer management module, a direct write buffer module and a data transmission and storage module.

[0007] The data receiving module is used to receive data from the protocol layer;

[0008] The mapping module is used to convert the write pointer to the corresponding address of the storage matrix according to the current mode, and provide the corresponding data address in the storage matrix during data transmission;

[0009] The pointer management module is used to store updated write pointers and read pointers;

[0010] The direct write buffer module is used to allow data to be written into a buffer when data Flit arrives for the first time or the storage matrix is ​​empty, the buffer is composed of read-write storage, and the direct write buffer module is also used to synchronously update the pointer management module;

[0011] The data transmission and storage module is used to obtain data from the storage matrix according to the data address provided by the mapping module, and output the data to the protocol layer;

[0012] The storage matrix adopts M×N granularity.

[0013] Furthermore, it also includes: a cache management and retransmission mechanism, which is used to use the mapping module and the pointer management module to perform read and write management, or retransmit data when necessary.

[0014] Furthermore, when receiving data from the protocol layer, the data receiving module controls the data flow by limiting the transmission rate of the data packet through the token bucket algorithm, and the specific contents include:

[0015] Initialize token bucket parameters and add tokens to the token bucket at each time interval according to the token addition rate;

[0016] When a data packet arrives at the token bucket, it checks whether there are enough tokens in the token bucket. If there are enough tokens, it removes the corresponding number of tokens from the bucket and then receives and processes the data packet.

[0017] If there are not enough tokens in the token bucket, a signal is sent to the sender to request it to reduce the sending rate;

[0018] At each time interval, the number of tokens in the token bucket is updated, new tokens are added, and tokens are consumed;

[0019] The adding of a new token is specifically represented as follows: ,

[0020] in, is the updated number of tokens, is the current number of tokens, is the token addition rate, is the capacity of the bucket, Represents each time interval.

[0021] Furthermore, the depth of the storage matrix is , where the value of N is an integer greater than or equal to 0, and the width of the storage matrix is ​​16B or 32B.

[0022] Furthermore, the mapping module is further configured to: when the length of the data Flit is 68B, the width of the storage matrix is ​​set to 16B, and the depth of the storage matrix is ​​set to , where N is an integer; when the length of the data Flit is 256B, the width of the storage matrix is ​​set to 32B, and the depth of the storage matrix is ​​set to .

[0023] Furthermore, according to the real-time data flow and data load, the width and depth of the storage matrix are dynamically adjusted through an adaptive storage matrix adjustment algorithm, specifically including:

[0024] Monitor the data flow and load of the data receiving module;

[0025] Calculate the required width and depth of the storage matrix based on the monitoring data;

[0026] When the calculated width and depth do not match the current storage matrix configuration, the data needs to be remapped to a new storage location and the management strategy of the write pointer and the read pointer needs to be updated.

[0027] Furthermore, the mapping module is also used for: when the length of the data Flit is 68B, the first column of the storage matrix stores the Header information of the data Flit, and the first column is the leftmost column of the storage matrix; when the length of the data Flit is 256B, the second column of the storage matrix stores the CRC information of the data Flit, and the second column is a column adjacent to the first column.

[0028] Furthermore, the data receiving module is further used to: receive type identification information of the data Flit sent by the protocol layer; and the mapping module is further used to: determine the length of the data Flit according to the type identification information.

[0029] Furthermore, the storage matrix i The address of a column is represented by , i is a positive integer, the mapping module is further used to: map the write pointer P to the first Columns, where:

[0030] , Represents the floor function.

[0031] Furthermore, the write-through buffer module further includes: processing data writing through an intelligent buffer management algorithm and adaptively adjusting buffer resources, specifically including:

[0032] Using a machine learning model, buffer resources are pre-allocated based on historical data traffic and the amount of data predicted by the current trend; the predicted amount of data is expressed as: ,in, f represents a machine learning model, P represents the amount of prediction data, H Indicates historical traffic. T Represents time series characteristics;

[0033] According to the prediction results, the data writing strategy is adaptively adjusted to optimize the buffer; the writing strategy is expressed as: ,in W Indicates the write priority, D Indicates the data type, P Indicates the amount of prediction data;

[0034] Adopt dynamic pointer management strategy to synchronously update write pointer and read pointer according to real-time data writing situation and buffer status;

[0035] Continuously monitor the usage status of the buffer, and dynamically adjust the buffer resource allocation through the adjustment factor according to the deviation between the actual data flow and the predicted data volume; the adjustment factor is expressed as: , where A represents the adjustment factor, R represents the actual flow rate, Represents the predicted flow rate.

[0036] The beneficial effects of the present invention are:

[0037] The present invention realizes an efficient retransmission cache system through the UCIE adaptation layer, which is compatible with the transmission and storage of two data Flits of different sizes, 68B and 256B. The introduced buffer write-through function effectively reduces the delay of the storage matrix, reduces the read delay, and improves the data transmission efficiency. At the same time, the structure improves the resource utilization rate and solves the problems of the traditional cache structure being vague, insufficient resource utilization and data transmission delay.

[0038] By using the data receiving module and the token bucket algorithm, the present invention controls the data flow, avoids network congestion, and ensures a reasonable data packet transmission rate. The collaborative work of the mapping module and the pointer management module realizes the precise positioning and efficient management of data. The direct write buffer module further optimizes the data writing process through fast read and write operations, reduces system latency, and improves response speed. The intelligent buffer management algorithm dynamically adjusts buffer resources according to real-time data traffic, optimizes resource allocation, reduces resource waste, and enhances system adaptability and scalability.

[0039] By adaptively adjusting the width and depth of the storage matrix and dynamically updating the pointer management strategy, the cache efficiency is improved and the risk of cache overflow is reduced; the dedicated storage of the header and CRC information of the data Flit by the mapping module speeds up the recognition and processing speed of the data packet and improves the accuracy of data transmission. On the technical level, the present invention solves the challenges of low power consumption and low area implementation, and significantly improves performance in practical applications, providing users with a stable and efficient data transmission experience. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] For better understanding and implementation, the technical solution of the present application is described in detail below with reference to the accompanying drawings.

[0041] Figure 1 A schematic diagram of the structure of a retransmission cache system based on UCIE provided in an embodiment of the present application;

[0042] Figure 2 A schematic diagram of a flow chart of a UCIE-based retransmission cache system provided in an embodiment of the present application, which controls data flow by limiting the transmission rate of data packets through a token bucket algorithm;

[0043] Figure 3 A schematic diagram of a flow chart of a UCIE-based retransmission cache system dynamically adjusting the width and depth of a storage matrix through an adaptive storage matrix adjustment algorithm provided in an embodiment of the present application;

[0044] Figure 4 A schematic diagram of a flow chart of a UCIE-based retransmission cache system processing data writing and adaptively adjusting buffer resources through an intelligent buffer management algorithm provided in an embodiment of the present application. DETAILED DESCRIPTION

[0045] In order to further explain the technical means and effects taken by the present invention to achieve the predetermined invention purpose, exemplary embodiments will be described in detail here, and examples thereof are shown in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application. Instead, they are only examples of methods and systems consistent with some aspects of the present application as detailed in the attached claims.

[0046] The terms used in this application are for the purpose of describing specific embodiments only and are not intended to limit this application. The singular forms of "a", "said" and "the" used in this application and the appended claims are also intended to include plural forms unless the context clearly indicates other meanings. It should also be understood that the term "and / or" used herein refers to and includes any or all possible combinations of one or more associated listed items.

[0047] The specific implementation methods, features and effects of the present invention are described in detail below in conjunction with the accompanying drawings and preferred embodiments.

[0048] See also Figure 1-Figure 4 This embodiment provides a retransmission cache system based on UCIE, which solves the problems of unclear cache structure, insufficient resource utilization and data transmission delay in the prior art by introducing a buffer write-through function through the structure of the data transmission and storage modules compatible with two different formats of the UCIE adaptation layer.

[0049] The present invention provides a retransmission cache system based on UCIE, comprising:

[0050] A data receiving module, used for receiving data from the protocol layer;

[0051] A mapping module, used to convert the write pointer to the corresponding address of the storage matrix according to the current mode, and provide the corresponding data address in the storage matrix when the data can be transmitted;

[0052] A pointer management module, used for storing updated write pointers and read pointers;

[0053] A direct write buffer module, used for allowing data to be written into a buffer when a data Flit arrives for the first time or the storage matrix is ​​empty, the buffer being composed of a storage that can support fast reading and writing, and the direct write buffer module is also used for synchronously updating the pointer management module;

[0054] A data transmission and storage module, used for acquiring data from the storage matrix according to the data address provided by the mapping module, and outputting the data to the protocol layer;

[0055] The storage matrix adopts M×N granularity, the storage width is aligned to 16B or 32B to be compatible with Flit with 68B or 256B data bit width, and the storage depth is aligned to 2 N To facilitate pointer management during retransmission, the pointer can be used cyclically.

[0056] Specifically, the retransmission cache system based on UCIE realizes efficient and flexible data transmission and cache management. The data receiving module is responsible for receiving data from the protocol layer, the mapping module is responsible for correctly mapping the data to the corresponding address of the storage matrix, the pointer management module tracks and manages the position of the read and write pointers, and the direct write buffer module handles the fast writing and synchronous update operations of the data. These modules work together to solve the problem of how to effectively cache and retransmit data in high-speed data transmission, especially for data Flits of different sizes. By dynamically adjusting the width and depth of the storage matrix, the use of storage resources is optimized, the risk of cache overflow is reduced, and the efficiency and reliability of data transmission are improved. This structure is particularly suitable for high-speed communication systems that need to process a large number of data Flits of different sizes, and can significantly improve the overall performance and stability of the system.

[0057] Furthermore, it also includes: a cache management and retransmission mechanism, which is used to use the mapping module and the pointer management module to perform effective read and write management, or retransmit data when necessary.

[0058] Specifically, by integrating cache management and retransmission mechanisms, efficient management of data read and write operations is achieved, and data retransmission can be automatically performed when necessary, thereby ensuring the reliability and integrity of data transmission. This mechanism uses the mapping module to accurately locate the data storage location, and relies on the pointer management module to track the data read and write status, so that the system can intelligently identify errors or losses during data transmission and trigger the retransmission process in a timely manner. Even when network conditions are unstable or data traffic is at a peak, the system can maintain stable performance, reduce the risk of data loss, and improve overall data throughput. In addition, this automatic retransmission capability also reduces the need for manual intervention, reduces delays and potential errors caused by manual retransmission operations, and provides users with a smoother and more reliable data transmission experience.

[0059] Furthermore, when receiving data from the protocol layer, the data receiving module controls the data flow by limiting the transmission rate of the data packet through the token bucket algorithm, and the specific contents include:

[0060] S11, initialize token bucket parameters, and add tokens to the token bucket at each time interval according to the token addition rate;

[0061] S12, when the data packet arrives at the token bucket, check whether there are enough tokens in the token bucket. If there are enough tokens, remove the corresponding number of tokens from the bucket, and then receive and process the data packet;

[0062] S13: If there are insufficient tokens in the token bucket, a signal is sent to the sender to request it to reduce the sending rate;

[0063] S14. At each time interval, the number of tokens in the token bucket is updated, new tokens are added, and tokens are consumed.

[0064] Adding a new token is specifically expressed as: ,

[0065] in, is the updated number of tokens, is the current number of tokens, is the token addition rate, is the capacity of the bucket, Represents each time interval.

[0066] Specifically, by implementing the token bucket algorithm in the data receiving module, the transmission rate of data packets can be accurately controlled and the data flow can be effectively managed. The dynamic adjustment mechanism ensures the rational use of network resources, prevents network congestion, and ensures the stability and efficiency of data transmission. In addition, after each time interval, the system updates the number of tokens in the token bucket. This adaptive process enables the system to flexibly respond to different network conditions and data traffic, improving the performance and reliability of the overall network.

[0067] Furthermore, the depth of the storage matrix is , where the value of N is an integer greater than or equal to 0, and the width of the storage matrix is ​​16B or 32B.

[0068] The storage width is aligned to 16B or 32B in order to minimize the depth of the storage matrix.

[0069] The depth is The storage matrix configuration with a width of 16B or 32B can effectively meet the storage requirements of different data Flit sizes, improve cache utilization, reduce data transmission latency, and simplify pointer management during retransmission, providing a flexible, efficient and scalable cache structure for high-speed data transmission, thereby enhancing the overall performance and stability of the system. This design also allows the system to dynamically adjust storage resources according to real-time data traffic, optimize energy consumption, and ensure the reliability of data transmission.

[0070] Furthermore, the mapping module is further configured to: when the length of the data Flit is 68B, the width of the storage matrix is ​​set to 16B, and the depth of the storage matrix is ​​set to , where N is an integer; when the length of the data Flit is 256B, the width of the storage matrix is ​​set to 32B, and the depth of the storage matrix is ​​set to .

[0071] In the field of computer networks and high-speed communications, Flit describes the smallest data unit transmitted inside a network switch or router, which usually contains header information and a portion of payload data. In high-speed networks, Flit, as a basic unit of data transmission, helps improve the transmission efficiency and processing speed of data packets. By splitting data packets into smaller Flits, more fine-grained flow control and conflict avoidance can be achieved in the network, thereby improving the overall throughput and performance of the network.

[0072] Specifically, through this flexible width and depth setting, the mapping module can adapt to data Flits of different lengths, while optimizing the use of storage space and improving cache efficiency, so that the storage matrix can flexibly process data Flits of different sizes while maintaining efficient data transmission and retransmission capabilities.

[0073] Furthermore, according to the real-time data flow and data load, the width and depth of the storage matrix are dynamically adjusted through an adaptive storage matrix adjustment algorithm, specifically including:

[0074] S21, monitoring the data flow and load of the data receiving module, including key indicators such as data transmission rate and data packet size distribution;

[0075] S22, calculating the required width and depth of the storage matrix according to the monitoring data to ensure that the current amount of data can be effectively processed without causing cache overflow or resource waste;

[0076] S23. When the calculated width and depth do not match the configuration of the current storage matrix, it is necessary to remap the data to a new storage location and update the management strategy of the write pointer and the read pointer.

[0077] After completing these adjustments, the system can continue to efficiently process data streams with the optimal configuration, ensuring the stability and efficiency of data transmission. This adaptive adjustment mechanism enables the storage matrix to flexibly respond to different load conditions, improving the system's robustness and performance.

[0078] Furthermore, the mapping module is also used for: when the length of the data Flit is 68B, the first column of the storage matrix stores the Header information of the data Flit, and the first column is the leftmost column of the storage matrix; when the length of the data Flit is 256B, the first column of the storage matrix stores the Header information of the data Flit, and the second column of the storage matrix stores the CRC information of the data Flit, and the second column is a column adjacent to the first column.

[0079] The Flit Header information refers to the control information in front of each data Flit, including the protocol identifier, stack identifier, reserved bit, sequence number, and confirmation or denial information, which are crucial to ensure the correct transmission and reception of data packets.

[0080] CRC is a cyclic redundancy check, which is an error detection technology used to detect unexpected changes in data transmission or storage. CRC uses a specific polynomial algorithm to treat the data as a large number and calculate the corresponding remainder (check value). This check value is then transmitted or stored with the original data. After receiving the data, the receiver or storage device will recalculate the check value using the same polynomial algorithm and compare it with the received check value to verify the integrity and accuracy of the data.

[0081] Specifically, for 68B data Flit, the Header information is stored in the leftmost column of the storage matrix, which allows for quick access and processing of the header information, which is essential for data packet identification and processing. For 256B data Flit, the Header and CRC information are stored in the first and second columns, respectively, which not only maintains quick access to the header information, but also provides dedicated storage space for the CRC information. In addition, this columnar storage method optimizes the layout of the data, making data retransmission and cache management more efficient, because associated data parts can be stored and accessed continuously, reducing cache line conflicts and improving cache hit rates, thereby reducing data transmission delays and improving overall data transmission efficiency.

[0082] Furthermore, the data receiving module is further used to: receive type identification information of the data Flit sent by the protocol layer; and the mapping module is further used to: determine the length of the data Flit according to the type identification information.

[0083] Specifically, the data receiving module can identify and receive the data Flit type identification information sent by the protocol layer, so that the mapping module can accurately determine the specific length of the data Flit based on this identification information. This intelligent recognition mechanism allows the width and depth of the storage matrix to be dynamically adjusted according to the length of the data Flit, which not only optimizes the use of storage resources and reduces space waste, but also improves the efficiency of data storage and retrieval. Such dynamic adjustment capabilities enable the system to flexibly process data units of different sizes, thereby maintaining high efficiency while also improving the adaptability and scalability of the system. In addition, the adaptive storage strategy based on content length helps to reduce power consumption and increase data processing speed. In high-speed communication systems that need to process a large number of data Flits of different sizes, the effect of this design is particularly significant.

[0084] Furthermore, the storage matrix i The address of a column is represented by , i is a positive integer, the mapping module is further used to: map the write pointer P to the first Columns, where:

[0085] , Represents the floor function.

[0086] Specifically, the storage location of the data in the storage matrix is ​​determined by an efficient and computationally simple method, and the value of the write pointer P is logarithmically calculated using a floor function. The mapping strategy maps the write pointer P to the first Column, where The result of rounding down the logarithm of P with base 2 is equal to P, which realizes a fast and simple data location method. This method not only speeds up the data writing speed and improves the storage efficiency, but also makes the data distribution in the storage matrix more uniform, reduces cache conflicts, and thus improves the overall performance of the cache and the data processing capability of the system. This strategy also has good scalability and can adapt to storage matrices of different sizes, providing an effective cache management mechanism for high-speed data transmission systems.

[0087] Furthermore, the write-through buffer module further includes: processing data writing through an intelligent buffer management algorithm and adaptively adjusting buffer resources, specifically including:

[0088] S31. Using a machine learning model, pre-allocate buffer resources based on historical data traffic and the amount of data predicted by the current trend; the predicted data amount is expressed as: ,in, f represents a machine learning model, P represents the amount of prediction data, H Indicates historical traffic. T Represents time series characteristics;

[0089] S32. According to the prediction results, the data writing strategy is adaptively adjusted to optimize the buffer to ensure fast writing of high-priority data; the writing strategy is expressed as: ,in W Indicates the write priority, D Indicates the data type, P Indicates the amount of prediction data;

[0090] S33, adopting a dynamic pointer management strategy to synchronously update the write pointer and the read pointer according to the real-time data writing situation and the buffer state;

[0091] S34, continuously monitor the usage status of the buffer, and dynamically adjust the buffer resource allocation through an adjustment factor according to the deviation between the actual data flow and the predicted data volume; the adjustment factor is expressed as: ,in A represents the adjustment factor, R Indicates the actual flow rate. Represents the predicted flow rate.

[0092] Specifically, the direct write buffer module effectively handles the rapid writing of data through the intelligent buffer management algorithm, and can adaptively adjust the buffer resources to meet the changing data flow requirements. Specifically, firstly, the machine learning model is used to predict the future data volume based on the historical data flow and time series characteristics, and the buffer resources are pre-allocated accordingly to ensure that the system can efficiently handle the upcoming data load. Then, the data writing strategy is dynamically adjusted according to the prediction results, and the use of the buffer is optimized to ensure that high-priority data can be written quickly, thereby improving the overall data processing speed and system responsiveness. In addition, the dynamic pointer management strategy ensures that the write pointer and the read pointer can be synchronously updated according to the real-time data writing situation and the buffer state to maintain the consistency and accuracy of the data. Finally, the use status of the buffer is continuously monitored, and the buffer resource allocation is dynamically adjusted by adjusting the factor according to the deviation between the actual data flow and the predicted data volume, so as to further optimize the resource utilization. The introduction of this intelligent buffer management algorithm significantly improves the intelligent level of data processing, reduces the need for manual configuration, and improves the adaptive ability of the system. It solves the problem that the cache structure may not be specific enough, the resource utilization may be insufficient, and the data transmission delay may be high in the background technology. The intelligent buffer management algorithm effectively solves these problems through prediction, optimization, dynamic management and adjustment, making the cache structure more efficient, resources more fully utilized and data transmission faster.

[0093] More specifically, the UCIE-based retransmission cache system solves the problems of compatibility and cache efficiency of different Flit Sizes in high-speed data transmission. By adopting an M×N granularity storage matrix, an intelligent mapping module, a pointer management module, and a direct write buffer module, efficient storage and fast access to 68B and 256B data Flits are achieved. In addition, the reliability of data transmission is enhanced through cache management and retransmission mechanisms. The integration of these technologies not only minimizes the waste of storage space, but also reduces data transmission latency, improves the overall performance and resource utilization of the system, thereby optimizing the power consumption and area of ​​the chip while ensuring the accuracy of data transmission, and meeting the dual requirements of modern chip design for high performance and low power consumption.

[0094] In some implementations, the method of a retransmission cache system based on UCIE includes: receiving data from a protocol layer; converting a write pointer to a corresponding address of a storage matrix according to a current mode, and providing a corresponding data address in the storage matrix when data can be transmitted; storing updated write pointers and read pointers; when data Flit arrives for the first time or the storage matrix is ​​empty, allowing data to be written into a buffer, the buffer being composed of a storage that can support fast reading and writing, and synchronously updating the pointer management module; obtaining data from the storage matrix according to the data address provided by the mapping module, and outputting the data to the protocol layer; wherein the storage matrix adopts an M×N granularity, and when the length of the data Flit is 68B, the width of the storage matrix is ​​set to 16B, and the depth of the storage matrix is ​​set to , where N is an integer; when the length of the data Flit is 256B, the width of the storage matrix is ​​set to 32B, and the depth of the storage matrix is ​​set to .

[0095] The above description is only a preferred embodiment of the present invention and does not limit the present invention in any form. Although the present invention has been disclosed as a preferred embodiment as above, it is not used to limit the present invention. Any technical personnel in this field can make some changes or modify the technical contents disclosed above into equivalent embodiments without departing from the scope of the technical solution of the present invention. However, any brief modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention are still within the scope of the technical solution of the present invention.

Claims

1. A retransmission cache system based on UCIE, characterized in that: It includes data receiving module, mapping module, pointer management module, direct write buffer module and data transmission and storage module. The data receiving module is used to receive data from the protocol layer; Among them, when receiving data from the protocol layer, the data receiving module controls the data flow by limiting the transmission rate of the data packet through the token bucket algorithm, and the specific contents include: Initialize token bucket parameters and add tokens to the token bucket at each time interval according to the token addition rate; When a data packet arrives at the token bucket, it checks whether there are tokens in the token bucket. If there are tokens, it removes the corresponding number of tokens from the bucket, and then receives and processes the data packet; If there are not enough tokens in the token bucket, a signal is sent to the sender to request it to reduce the sending rate; At each time interval, the number of tokens in the token bucket is updated, new tokens are added, and tokens are consumed; The mapping module is used to convert the write pointer to the corresponding address of the storage matrix according to the current mode, and provide the corresponding data address in the storage matrix during data transmission; The pointer management module is used to store updated write pointers and read pointers; The direct write buffer module is used to allow data to be written into a buffer when data Flit arrives for the first time or the storage matrix is ​​empty, the buffer is composed of read-write storage, and the direct write buffer module is also used to synchronously update the pointer management module; The data transmission and storage module is used to obtain data from the storage matrix according to the data address provided by the mapping module, and output the data to the protocol layer; The storage matrix adopts M×N granularity.

2. The UCIE-based retransmission cache system according to claim 1, characterized in that: Also includes: The cache management and retransmission mechanism is used to utilize the mapping module and the pointer management module to perform read and write management, or to retransmit data when necessary.

3. The UCIE-based retransmission cache system according to claim 1, characterized in that: The adding of a new token is specifically represented as follows: , in, is the updated number of tokens, is the current number of tokens, is the token addition rate, is the capacity of the bucket, Represents each time interval.

4. The UCIE-based retransmission cache system according to claim 1, characterized in that: The depth of the storage matrix is , where the value of N is an integer greater than or equal to 0, and the width of the storage matrix is ​​16B or 32B.

5. The UCIE-based retransmission cache system according to claim 1, characterized in that: The mapping module is further used to: when the length of the data Flit is 68B, the width of the storage matrix is ​​set to 16B, and the depth of the storage matrix is ​​set to , where N is an integer; when the length of the data Flit is 256B, the width of the storage matrix is ​​set to 32B, and the depth of the storage matrix is ​​set to .

6. The UCIE-based retransmission cache system according to claim 5, characterized in that: According to the real-time data flow and data load, the width and depth of the storage matrix are dynamically adjusted through the adaptive storage matrix adjustment algorithm, including: Monitor the data flow and load of the data receiving module; Calculate the required width and depth of the storage matrix based on the monitoring data; When the calculated width and depth do not match the current storage matrix configuration, the data needs to be remapped to a new storage location and the management strategy of the write pointer and the read pointer needs to be updated.

7. The UCIE-based retransmission cache system according to claim 5, characterized in that: The mapping module is also used for: when the length of the data Flit is 68B, the first column of the storage matrix stores the Header information of the data Flit, and the first column is the leftmost column of the storage matrix; when the length of the data Flit is 256B, the second column of the storage matrix stores the CRC information of the data Flit, and the second column is a column adjacent to the first column.

8. The UCIE-based retransmission cache system according to claim 1, characterized in that: The data receiving module is further used to: receive type identification information of the data Flit sent by the protocol layer; and the mapping module is further used to: determine the length of the data Flit according to the type identification information.

9. The UCIE-based retransmission cache system according to claim 7, characterized in that: The storage matrix i The address of a column is represented by , i is a positive integer, the mapping module is further used to: map the write pointer P to the first Column, where , Represents the floor function.

10. The UCIE-based retransmission cache system according to claim 1, characterized in that: The write-through buffer module also includes: processing data writing through an intelligent buffer management algorithm and adaptively adjusting buffer resources, specifically including: Using a machine learning model, buffer resources are pre-allocated based on historical data traffic and current trend predicted data volume; the predicted data volume is expressed as: ,in, f represents a machine learning model, P represents the amount of prediction data, H Indicates historical traffic. T Represents time series characteristics; According to the prediction results, the data writing strategy is adaptively adjusted to optimize the buffer; the writing strategy is expressed as: ,in W Indicates the write priority, D Indicates the data type, P Indicates the amount of prediction data; Adopt dynamic pointer management strategy to synchronously update write pointer and read pointer according to real-time data writing situation and buffer status; Continuously monitor the usage status of the buffer, and dynamically adjust the buffer resource allocation through the adjustment factor according to the deviation between the actual data flow and the predicted data volume; the adjustment factor is expressed as: , where A represents the adjustment factor, R represents the actual flow rate, Represents the predicted flow rate.

Images