Multi-node server access method and apparatus, computer device and storage medium

Abstract

The application relates to a multi-node server access method and device, computer equipment and a storage medium. The multi-node server access method comprises a backboard, a power supply unit and a plurality of node boards. The node boards comprise a first processor and a second processor, and the second processor is connected with the backboard through a plurality of general-purpose input / output channels. The method comprises the following steps: acquiring in-place information of the plurality of node boards; acquiring configuration information from the first processor, and controlling the second processor to configure the general-purpose input / output pin level corresponding to each node board according to the in-place information and the configuration information; reading the values of the general-purpose input / output pins and storing the values in corresponding registers respectively; and in response to the node board reading the values of a plurality of registers through the plurality of general-purpose input / output channels, determining whether the node board has access permission of the power supply unit according to the in-place information and the values of the plurality of registers. The method can solve the access conflict problem when a plurality of nodes simultaneously access the power supply unit.

Description

Technical Field

[0001] The present application relates to the field of server technology, and in particular to a multi-node server access method, apparatus, computer equipment, and storage medium. Background Art

[0002] Currently, commonly used power management technologies mainly include centralized management and distributed management. Centralized management uses a central controller (such as the master BMC) to manage and allocate PSU (Power Supply Unit) access rights for all node boards. This approach is simple in structure and easy to implement. However, if the central controller fails, the power management of the entire system will be affected. In distributed management, each node board has a BMC and independently manages access rights to the PSU. This method improves system redundancy and reliability, but also increases system complexity. It requires coordinating the work of multiple BMCs, which is prone to conflicts and inconsistencies.

[0003] In the PC-FARM field, since there are multiple nodes sharing one or several PSUs and each node has a BMC, I2C bus conflicts will occur when multiple nodes try to access the PSU at the same time. This also involves the problem of node failure and access by another node. Summary of the Invention

[0004] Based on this, it is necessary to provide a multi-node server access method, device, computer equipment and storage medium that can avoid access conflicts in order to address the above technical problems.

[0005] In one aspect, a method for accessing a multi-node server is provided. The multi-node server includes a backplane, a power supply unit, and multiple node boards. The node boards include a first processor and a second processor. The second processor is connected to the backplane via multiple general-purpose input / output channels, wherein the general-purpose input / output channels correspond one-to-one to the node boards. The method includes:

[0006] Acquiring in-place information of the plurality of node plates;

[0007] Acquire configuration information from the first processor, and control the second processor to configure the general input and output pin levels corresponding to each node board according to the in-position information and the configuration information;

[0008] Reading the values ​​of the general purpose input and output pins and storing them in corresponding registers, wherein the registers correspond to the node boards one by one;

[0009] In response to the node board reading values ​​of multiple registers through the multi-way universal input and output channels, it is determined whether the node board has access rights to the power supply unit according to the presence information and the values ​​of the multiple registers.

[0010] In one embodiment, the backplane includes a plurality of slots, and obtaining the in-place information of the plurality of node boards includes:

[0011] Obtaining, by the second processor, slot numbers and presence signals of the plurality of slots respectively;

[0012] Whether the node plate is in place is determined according to the slot number and the in-place signal, and the position of the node plate is determined.

[0013] In one embodiment, controlling the second processor to configure the general input and output pin levels corresponding to each node board according to the presence information and the configuration information includes:

[0014] In response to the node board being in place, controlling the second processor to set the corresponding general purpose input and output pin to a high level or a low level according to the configuration information;

[0015] In response to the node board being not in place, the second processor is controlled to set the corresponding general purpose input and output pin to a low level.

[0016] In one embodiment, in response to the node board reading the values ​​of multiple registers through the multi-way universal input and output channels, determining whether the node board has access rights to the power supply unit according to the in-position information and the values ​​of the multiple registers includes:

[0017] In response to the second processor reading the values ​​of the multiple registers through the multi-way general input and output channels, transmitting the values ​​of the multiple registers and the in-place information of the multiple node boards to the first processor of each node board;

[0018] Checking a watchdog timer of the first processor to determine whether the first processor is in a normal working state;

[0019] In response to the first processor being in a normal working state, determining in-place node boards and corresponding slot numbers according to the in-place information, and sorting the in-place node boards in ascending order according to the slot numbers;

[0020] Read the values ​​of the registers corresponding to the in-place node boards in sequence according to the sorting results;

[0021] In response to the register value being a first preset value, the in-position node board is used as a target node board, and the access permission of the power supply unit is assigned to the target node board, so that other node boards cannot access the power supply unit;

[0022] In response to the register value being the second preset value, the value of the register corresponding to the next in-place node board is read in sequence according to the sorting result.

[0023] In one embodiment, in response to the register value being a first preset value, taking the in-place node board as a target node board, and assigning the access rights of the power supply unit to the target node board, comprises:

[0024] sending a first enable signal to a target second processor through the target first processor;

[0025] In response to the target second processor receiving the first enable signal, a second enable signal is sent to an integrated circuit bus buffer, so that the target first processor accesses the power supply unit through the integrated circuit bus buffer.

[0026] In one embodiment, the step of sequentially reading the values ​​of the registers corresponding to the in-place node boards according to the sorting results further includes:

[0027] In response to the register value being a second preset value, determining a target node board according to values ​​of other registers, and displaying the slot number of the target node board on the operation and maintenance software;

[0028] The values ​​of the multiple registers are repeatedly obtained until the in-place node board obtains access rights to the power supply unit.

[0029] In one embodiment, the method further comprises:

[0030] In response to a watchdog exception of the target first processor, or the target first processor failing to regularly send a watchdog timer signal to the target second processor, determining that the target first processor is faulty;

[0031] Setting the corresponding general purpose input / output pin to a low level by the target second processor and resetting the second enable signal to release the access rights of the target first processor;

[0032] It is determined whether the next in-place node board has access rights to the power supply unit according to the sorting result.

[0033] In another aspect, a multi-node server access device is provided, the device comprising:

[0034] A first acquisition module is used to acquire the in-place information of the plurality of node plates;

[0035] a configuration module, configured to obtain configuration information from the first processor, and control the second processor to configure the general input and output pin levels corresponding to each node board according to the in-position information and the configuration information;

[0036] A second acquisition module is used to read the value of each general input and output pin and store it in a corresponding register, wherein the register corresponds to the node board one by one;

[0037] The control module is configured to determine whether the node board has access rights to the power supply unit according to the in-position information and the values ​​of the multiple registers in response to the node board reading the values ​​of the multiple registers through the multiple universal input and output channels.

[0038] In another aspect, a computer device is provided, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the computer program, the following steps are implemented:

[0039] Acquiring in-place information of the plurality of node plates;

[0040] Acquire configuration information from the first processor, and control the second processor to configure the general input and output pin levels corresponding to each node board according to the in-position information and the configuration information;

[0041] Reading the values ​​of the general purpose input and output pins and storing them in corresponding registers, wherein the registers correspond to the node boards one by one;

[0042] In response to the node board reading values ​​of multiple registers through the multi-way universal input and output channels, it is determined whether the node board has access rights to the power supply unit according to the presence information and the values ​​of the multiple registers.

[0043] In another aspect, a computer-readable storage medium is provided, on which a computer program is stored, and when the computer program is executed by a processor, the following steps are implemented:

[0044] Acquiring in-place information of the plurality of node plates;

[0045] Acquire configuration information from the first processor, and control the second processor to configure the general input and output pin levels corresponding to each node board according to the in-position information and the configuration information;

[0046] Reading the values ​​of the general purpose input and output pins and storing them in corresponding registers, wherein the registers correspond to the node boards one by one;

[0047] In response to the node board reading values ​​of multiple registers through the multi-way universal input and output channels, it is determined whether the node board has access rights to the power supply unit according to the presence information and the values ​​of the multiple registers.

[0048] The above-mentioned multi-node server access method, device, computer equipment and storage medium integrate multiple GPIO channels as communication and arbitration media in the backplane circuit design. When multiple nodes access the PSU at the same time, by configuring the GPIO and reading the value of the corresponding register, it is possible to identify and specify which channel will play the master role of the I2C bus, thereby obtaining access to the PSU, ensuring that at any given moment, only one node can access one or more PSUs, solving the I2C bus conflict problem that occurs when multiple nodes access the PSU at the same time. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] Figure 1 A schematic diagram of the structure of a multi-node server in one embodiment;

[0050] Figure 2 Schematic diagram of a flow chart of a multi-node server access method in one embodiment;

[0051] Figure 3 A schematic diagram of a flow chart of multi-node server access steps in one embodiment;

[0052] Figure 4 Schematic diagram of the connection between SLOT_ID and PRESENT signals in one embodiment;

[0053] Figure 5 A structural block diagram of a multi-node server access device in one embodiment;

[0054] Figure 6 FIG. 1 is a diagram showing the internal structure of a computer device in one embodiment. DETAILED DESCRIPTION

[0055] In order to make the purpose, technical solutions and advantages of this application more clear, the following further describes this application in detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0056] On server motherboards, a common practice for powering nodes is to use a power supply unit (PSU). The PSU typically outputs +12V to the node, and the node accesses the PSU via I2C signals to read information such as PSU power, voltage, current, and temperature. The node acts as the master device, and the PSU as the slave device. If a direct connection is used between the two, when multiple nodes access the PSU simultaneously, the slave device cannot identify which master device is accessing it, resulting in an access conflict and causing system diagnostic failures.

[0057] This application integrates multiple GPIO (General Purpose Input Output) channels into the backplane circuit design. These channels are specifically used as communication and arbitration media. They can identify and specify which channel will play the master role of the I2C bus, thereby obtaining access to the PSU. This ensures that at any given moment, only one node can access one or more PSUs, solving the I2C bus conflict problem that occurs when multiple nodes attempt to access multiple PSUs simultaneously.

[0058] like Figure 1 As shown, the 4-node design of the PC-FARM 4U chassis is used as an example for explanation. The system is mainly composed of a backplane, a node board and a PSU module. The node board integrates components such as the CPU, memory, BMC (Baseboard Management Controller), CPLD (Complex Programmable Logic Device), hard disk drive and various external interfaces. It should be noted that since some components are not directly related to the design core of the present invention, they are not all shown in the schematic diagram. In short, each node board is essentially equivalent to a compact personal computer. When multiple such node boards are combined together, they form an array, thus forming a complete PC-FARM device.

[0059] In this application, the first processor is the BMC, the second processor is the CPLD, and each node board and PSU module are plugged into the backplane via corresponding connectors. Each node board is connected to four GPIO channels, the SLOT ID signal, and the PRESENT signal via the CPLD. The I2C communication signal is connected to the backplane via the I2C BUFFER (I2C buffer), and the enable control pin EN of the I2C BUFFER is controlled by the CPLD. In addition, the BMC and CPLD are also connected via the I2C0 channel and an indication signal EN_I2C for controlling I2C.

[0060] In one embodiment, Figure 2-4As shown, a multi-node server access method is provided, comprising the following steps:

[0061] Step S1: Acquire the in-place information of the plurality of node plates.

[0062] In an optional embodiment, the backplane includes multiple slots, and obtaining the presence information of the multiple node boards includes: obtaining the slot numbers and presence signals of the multiple slots respectively through the second processor; judging whether the node board is in place based on the slot numbers and the presence signals, and determining the position of the node board.

[0063] The slot ID SLOT_ID identifies each slot and can be represented by two GPIOs, for example, 00, 01, 10, and 11 represent different slot information. The PRESENT signal indicates whether a node board is inserted in a slot and can be represented by a single GPIO. A high level 1 indicates not in place, while a low level 0 indicates in place.

[0064] like Figure 4 As shown, both the slot label SLOT_ID and the presence signal PRESENT can be grounded at different slot pins on the backplane. The signals on the node board are connected to the power supply through pull-up resistors. When the node board is inserted into the slot, these pins will be pulled low. The second processor CPLD determines whether the node board is in place and its slot position by reading the status of these pins, ensuring that the node can accurately identify and locate the position where each node board should be.

[0065] Step S2: acquiring configuration information from the first processor, and controlling the second processor to configure the general input and output pin levels corresponding to each node board according to the presence information and the configuration information.

[0066] In an optional embodiment, controlling the complex programmable logic device to configure the general input and output pin levels corresponding to each node board according to the presence information and the configuration information includes: in response to the node board being in place, controlling the second processor to set the corresponding general input and output pin to a high level or a low level according to the configuration information; in response to the node board not being in place, controlling the second processor to set the corresponding general input and output pin to a low level.

[0067] Specifically, the system predefines configuration information for each node board, including its functions and required GPIO pins. This information is stored in the first processor's BMC. The second processor, the CPLD, reads the SLOT_ID and PRESENT signals and, combined with the configuration information passed by the BMC, configures the corresponding GPIO pin levels. This allows for flexible configuration and management of each node board based on actual needs, adapting to different application scenarios and configuration requirements.

[0068] The CPLD preferably determines the BMC's operating status based on signals received from the BMC, for example, by confirming its functionality through heartbeat monitoring and watchdog mechanisms. When the BMC is operating normally, the CPLD sets the corresponding GPIO bits. This ensures that the system correctly configures the GPIOs based on the BMC's status, preventing a BMC freeze that could result in a node being unable to access the PSU and loss of operational information.

[0069] Step S3, reading the value of each general input and output pin and storing them in the corresponding register, wherein the register corresponds to the node board one by one.

[0070] Specifically, the CPLD of each node reads the corresponding GPIO pin level and stores it in the corresponding register. For example, the register corresponding to node 0 is A0, and the register corresponding to node 1 is A1. The values ​​stored in these registers determine the access priority order of each node.

[0071] Step S4 , in response to the node board reading values ​​of multiple registers through the multi-way universal input and output channels, determining whether the node board has access rights to the power supply unit according to the in-position information and the values ​​of the multiple registers.

[0072] In an optional embodiment, in response to the node board reading the values ​​of multiple registers through the multi-way universal input and output channels, determining whether the node board has access rights to the power supply unit based on the in-place information and the values ​​of the multiple registers includes: in response to the second processor reading the values ​​of the multiple registers through the multi-way universal input and output channels, transmitting the values ​​of the multiple registers and the in-place information of the multiple node boards to the first processor of each node board; checking the watchdog timer of the first processor, and periodically sending a watchdog timer signal to the second processor through the first processor to determine whether the first processor is in in normal working state; in response to the first processor being in normal working state, determining the in-place node board and the corresponding slot number according to the in-place information, and sorting the in-place node boards in ascending order according to the slot number; reading the values ​​of the registers corresponding to the in-place node boards in sequence according to the sorting results; in response to the value of the register being a first preset value, taking the in-place node board as the target node board, and assigning the access rights of the power supply unit to the target node board, so that other node boards cannot access the power supply unit; in response to the value of the register being a second preset value, reading the value of the register corresponding to the next in-place node board in sequence according to the sorting results.

[0073] For example, it is detected that nodes 0-3 are all in place. At this time, register A0 corresponding to node 0 is read first in the order of slot number. If the value of A0 is 1, node 0 preferentially uses the I2C bus to access the PSU; if the value of A0 is 0, register A1 corresponding to node 1 is read in sequence. Similarly, the value of A1 is used to determine whether node 1 has access rights to the PSU. Therefore, permission management and task scheduling can be performed more accurately at the software level.

[0074] Multiple GPIO channels serve both communication and arbitration roles. Each CPLD reads the values ​​of all registers through these channels and transmits them to the BMC via I2C0. The BMC then determines which node is accessing the PSU based on the register values ​​and the corresponding SLOT_ID. This GPIO arbitration mechanism not only ensures that only one node can access the PSU at any given time, but also allows other nodes to monitor and determine which node is currently accessing the PSU, thereby resolving multi-node access conflicts and improving system stability and security.

[0075] In an optional embodiment, the configuration information also includes a priority value, which is used to control the second processor to configure one or more second general input and output pin levels corresponding to each node board, and the values ​​of the one or more second general input and output pin levels are stored in the corresponding second register; in response to the node board reading the values ​​of multiple registers through the multiple general input and output channels, determining whether the node board has access rights to the power supply unit based on the in-place information and the values ​​of the multiple registers, also includes: in response to the second processor reading the values ​​of the multiple second registers through the multiple general input and output channels, transmitting the values ​​of the multiple second registers and the in-place information of the multiple node boards to the first processor of each node board; obtaining the node board with the highest priority among the in-place node boards as the target node board based on the values ​​of the multiple second registers and the in-place information, and assigning the access rights of the power supply unit to the target node board; in response to the value of the second register changing, judging whether to reallocate the access rights based on the changed value.

[0076] In an optional embodiment, in response to the value of the register being a first preset value, the in-place node board is used as the target node board, and the access rights of the power supply unit are assigned to the target node board, including: sending a first enable signal to the target second processor through the target first processor; in response to the target second processor receiving the first enable signal, sending a second enable signal to the integrated circuit bus buffer, so that the target first processor can access the power supply unit through the integrated circuit bus buffer.

[0077] Specifically, for the target BMC that obtains access rights, EN_I2C, the first enable signal, is set to notify the CPLD that it needs to access I2C1. After obtaining the EN_I2C information, the CPLD sets EN, the second enable signal, to enable the I2C BUFFER, allowing the target BMC to access the PSU, thus completing the allocation of PSU access rights.

[0078] In an optional embodiment, the method of sequentially reading the values ​​of the registers corresponding to the in-place node boards according to the sorting results also includes: in response to the value of the register being a second preset value, determining the target node board according to the values ​​of other registers, and displaying the slot number of the target node board on the operation and maintenance software; repeatedly obtaining the values ​​of the multiple registers until the in-place node board obtains access rights to the power supply unit.

[0079] Specifically, when node 0 gains access to the PSU, node 1's BMC detects that register A0 is set to 1 and assumes that node 0's BMC is accessing the PSU. Therefore, node 1 stops accessing the PSU, avoiding conflicts. This GPIO arbitration mechanism allows the BMCs of other nodes that haven't gained access to the PSU to determine which node is accessing the PSU, effectively resolving the common I2C bus access conflict issue in multi-node systems. This information can also be updated to the BMC operation and maintenance software, facilitating device maintenance.

[0080] In an optional embodiment, the method further includes: in response to a watchdog exception of the target first processor, or the target first processor failing to regularly send a watchdog timer signal to the target second processor, determining that the target first processor has failed; setting the corresponding general input and output pin to a low level through the target second processor, and resetting the second enable signal to release access rights to the target first processor; and determining whether the next in-place node board has access rights to the power supply unit based on the sorting result.

[0081] Specifically, by monitoring the BMC working status, it is possible to eliminate the resource occupation of abnormally working BMCs. At the same time, it also ensures that the system can correctly configure GPIO according to the BMC status, prevent the BMC from freezing and causing no nodes to access the PSU, avoid the loss of operation and maintenance information, and enhance the stability of the system.

[0082] It should be understood that although Figure 2-3 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. In addition, Figure 2-3 At least part of the steps may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least part of the sub-steps or stages of other steps.

[0083] In one embodiment, Figure 5 As shown, a multi-node server access device is provided, comprising: a first acquisition module, a configuration module, a second acquisition module and a control module, wherein:

[0084] A first acquisition module is used to acquire the in-place information of the plurality of node plates;

[0085] a configuration module, configured to obtain configuration information from the first processor, and control the second processor to configure the general input and output pin levels corresponding to each node board according to the in-position information and the configuration information;

[0086] A second acquisition module is used to read the value of each general input and output pin and store it in a corresponding register, wherein the register corresponds to the node board one by one;

[0087] The control module is configured to determine whether the node board has access rights to the power supply unit according to the in-position information and the values ​​of the multiple registers in response to the node board reading the values ​​of the multiple registers through the multiple universal input and output channels.

[0088] In one embodiment, the first acquisition module is further used to respectively obtain the slot numbers and in-place signals of the multiple slots through the second processor; determine whether the node board is in place based on the slot numbers and the in-place signals, and determine the position of the node board.

[0089] In one embodiment, the configuration module is further used to control the second processor to set the corresponding general input and output pin to a high level or a low level according to the configuration information in response to the node board being in place; and to control the second processor to set the corresponding general input and output pin to a low level in response to the node board not being in place.

[0090] In one embodiment, the control module is further configured to, in response to the second processor reading the values of the plurality of registers through the multiplexed general-purpose input / output channel, transfer the values of the plurality of registers and the in-place information of the plurality of node boards to the first processor of each node board; check a watchdog timer of the first processor and periodically send a watchdog timer signal to the second processor through the first processor to determine whether the first processor is in a normal working state; in response to the first processor being in the normal working state, determine an in-place node board and a corresponding slot index according to the in-place information, and sort the in-place node boards in ascending order of the slot index; read the values of the registers corresponding to the in-place node boards in sequence according to the sorting result, and determine whether the values of the registers are 1; in response to the values of the registers being 1, take the in-place node board as a target node board, and assign access rights of the power supply unit to the target node board, so that other node boards cannot access the power supply unit; and in response to the values of the registers being 0, read the values of the registers corresponding to the next in-place node board in sequence according to the sorting result.

[0091] In one embodiment, the control module is further configured to send a first enable signal to a target second processor through a target first processor; and in response to the target second processor receiving the first enable signal, send a second enable signal to an integrated circuit bus buffer, so that the target first processor accesses the power supply unit through the integrated circuit bus buffer.

[0092] In one embodiment, the control module is further configured to, in response to the values of the registers being 0, determine a target node board according to the values of other registers, and display a slot index of the target node board on operation and maintenance software; and repeatedly acquire the values of the plurality of registers until the in-place node board obtains the access rights of the power supply unit.

[0093] In one embodiment, the apparatus further comprises a reset module configured to, in response to a watchdog exception of the target first processor or the target first processor not sending a watchdog timer signal to the target second processor, determine that the target first processor is faulty; set a corresponding general-purpose input / output pin to a low level through the target second processor, and reset the second enable signal, so that the target first processor cannot access the power supply unit; and determine whether a next in-place node board has the access rights of the power supply unit according to the sorting result.

[0094] The specific definitions of the multi-node server access device can be found in the definitions of the multi-node server access method above and will not be repeated here. Each module in the multi-node server access device described above can be implemented in whole or in part through software, hardware, or a combination thereof. Each of the modules described above can be embedded in or independent of a processor in a computer device in hardware form, or can be stored in a memory in a computer device in software form, so that the processor can call and execute the corresponding operations of each module.

[0095] In one embodiment, a computer device is provided. The computer device may be a server, and its internal structure diagram may be as follows: Figure 6 As shown. The computer device includes a processor, memory, network interface, and database connected via a system bus. The processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program, and a database. The internal memory provides an environment for the operation of the operating system and computer program in the non-volatile storage medium. The database of the computer device is used to store GPIO register data. The network interface of the computer device is used to communicate with an external terminal via a network connection. When the computer program is executed by the processor, a multi-node server access method is implemented.

[0096] Those skilled in the art will understand that Figure 6 The structure shown in the figure is only a block diagram of a part of the structure related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than shown in the figure, or combine certain components, or have a different component arrangement.

[0097] In one embodiment, a computer device is provided, including a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, the following steps are performed:

[0098] Acquiring in-place information of the plurality of node plates;

[0099] Acquire configuration information from the first processor, and control the second processor to configure the general input and output pin levels corresponding to each node board according to the in-position information and the configuration information;

[0100] Reading the values ​​of the general purpose input and output pins and storing them in corresponding registers, wherein the registers correspond to the node boards one by one;

[0101] In response to the node board reading values ​​of multiple registers through the multi-way universal input and output channels, it is determined whether the node board has access rights to the power supply unit according to the presence information and the values ​​of the multiple registers.

[0102] In one embodiment, when the processor executes the computer program, the following steps are also implemented: the slot numbers and in-place signals of the multiple slots are respectively obtained by the second processor; whether the node board is in place is determined based on the slot numbers and the in-place signals, and the position of the node board is determined.

[0103] In one embodiment, when the processor executes the computer program, the following steps are also implemented: in response to the node board being in place, controlling the second processor to set the corresponding general input and output pin to a high level or a low level according to the configuration information; in response to the node board not being in place, controlling the second processor to set the corresponding general input and output pin to a low level.

[0104] In one embodiment, when executing the computer program, the processor further implements the following steps: in response to the second processor reading the values ​​of the multiple registers through the multiple universal input and output channels, transmitting the values ​​of the multiple registers and the presence information of the multiple node boards to the first processor of each node board; checking the watchdog timer of the first processor, and periodically sending a watchdog timer signal to the second processor through the first processor to determine whether the first processor is in a normal working state; in response to the first processor being in a normal working state, determining the node boards in place and the corresponding slot numbers according to the presence information, and sorting the node boards in place in ascending order according to the slot numbers; reading the values ​​of the registers corresponding to the node boards in place in sequence according to the sorting result, and determining whether the values ​​of the registers are 1; in response to the value of the register being 1, selecting the node board in place as the target node board, and assigning the access rights of the power supply unit to the target node board, so that other node boards cannot access the power supply unit; in response to the value of the register being 0, reading the value of the register corresponding to the next node board in place in sequence according to the sorting result.

[0105] In one embodiment, when the processor executes the computer program, it also implements the following steps: sending a first enable signal to the target second processor through the target first processor; in response to the target second processor receiving the first enable signal, sending a second enable signal to the integrated circuit bus buffer, so that the target first processor accesses the power supply unit through the integrated circuit bus buffer.

[0106] In one embodiment, the processor further implements the following steps when executing the computer program: in response to the value of the register being 0, determining a target node board according to the values of the other registers, and displaying a slot position number of the target node board on the operation and maintenance software; repeatedly acquiring the values of the plurality of registers until the in-place node board obtains the access right of the power supply unit.

[0107] In one embodiment, the processor further implements the following steps when executing the computer program: in response to a watchdog exception of the target first processor, or the target first processor not sending a watchdog timer signal to the target second processor periodically, determining that the target first processor fails; setting a corresponding general input and output pin to low by the target second processor, and resetting the second enable signal to release the access right of the target first processor; determining whether the next in-place node board has the access right of the power supply unit according to the sorting result.

[0108] In one embodiment, a computer readable storage medium is provided, and the computer readable storage medium stores a computer program, and the computer program is executed by a processor to implement the following steps:

[0109] Acquiring in-place information of the plurality of node boards;

[0110] Acquiring configuration information from the first processor, and controlling the second processor to configure the general input and output pins of each node board according to the in-place information and the configuration information;

[0111] Reading values of each general input and output pin and storing the values in corresponding registers respectively, wherein the registers correspond to the node boards one by one;

[0112] In response to the node board reading values of a plurality of registers through the multiplexed general input and output channel, determining whether the node board has the access right of the power supply unit according to the in-place information and the values of the plurality of registers.

[0113] In one embodiment, the computer program is further executed by the processor to implement the following steps: acquiring slot position numbers and in-place signals of the plurality of slots by the second processor respectively; determining whether the node board is in place according to the slot position numbers and the in-place signals, and determining the position of the node board.

[0114] In one embodiment, the computer program is further executed by the processor to implement the following steps: in response to the node board being in place, controlling the second processor to set a corresponding general input and output pin to high or low according to the configuration information; in response to the node board not being in place, controlling the second processor to set a corresponding general input and output pin to low.

[0115] In one embodiment, when the computer program is executed by the processor, the following steps are further implemented: in response to the second processor reading the values ​​of the multiple registers through the multiple general-purpose input and output channels, the values ​​of the multiple registers and the presence information of the multiple node boards are transmitted to the first processor of each node board; the watchdog timer of the first processor is checked, and a watchdog timer signal is periodically sent to the second processor through the first processor to determine whether the first processor is in a normal working state; in response to the first processor being in a normal working state, the node boards and the corresponding slot numbers are determined according to the presence information, and the node boards are sorted in ascending order according to the slot numbers; according to the sorting result, the values ​​of the registers corresponding to the node boards in place are read in sequence, and it is determined whether the values ​​of the registers are 1; in response to the value of the register being 1, the node board in place is used as the target node board, and the access rights of the power supply unit are assigned to the target node board, so that other node boards cannot access the power supply unit; in response to the value of the register being 0, the value of the register corresponding to the next node board in place is read in sequence according to the sorting result.

[0116] In one embodiment, when the computer program is executed by the processor, the following steps are also implemented: sending a first enable signal to the target second processor through the target first processor; in response to the target second processor receiving the first enable signal, sending a second enable signal to the integrated circuit bus buffer, so that the target first processor accesses the power supply unit through the integrated circuit bus buffer.

[0117] In one embodiment, when the computer program is executed by the processor, the following steps are also implemented: in response to the value of the register being 0, determining the target node board based on the values ​​of other registers, and displaying the slot number of the target node board on the operation and maintenance software; repeatedly obtaining the values ​​of the multiple registers until the in-place node board obtains access rights to the power supply unit.

[0118] In one embodiment, when the computer program is executed by the processor, the following steps are also implemented: in response to a watchdog exception of the target first processor, or the target first processor fails to regularly send a watchdog timer signal to the target second processor, determining that the target first processor has a fault; setting the corresponding general input and output pin to a low level through the target second processor, and resetting the second enable signal to release access rights to the target first processor; and determining whether the next in-place node board has access rights to the power supply unit based on the sorting result.

[0119] In one embodiment, a computer product is provided having a computer program stored thereon, which, when executed by a processor, performs the following steps:

[0120] Acquiring in-place information of the plurality of node plates;

[0121] Acquire configuration information from the first processor, and control the second processor to configure the general input and output pin levels corresponding to each node board according to the in-position information and the configuration information;

[0122] Reading the values ​​of the general purpose input and output pins and storing them in corresponding registers, wherein the registers correspond to the node boards one by one;

[0123] In response to the node board reading values ​​of multiple registers through the multi-way universal input and output channels, it is determined whether the node board has access rights to the power supply unit according to the presence information and the values ​​of the multiple registers.

[0124] In one embodiment, when the computer program is executed by the processor, the following steps are also implemented: the slot numbers and in-place signals of the multiple slots are respectively obtained by the second processor; whether the node board is in place is determined based on the slot number and the in-place signal, and the position of the node board is determined.

[0125] In one embodiment, when the computer program is executed by the processor, the following steps are also implemented: in response to the node board being in place, controlling the second processor to set the corresponding general input and output pin to a high level or a low level according to the configuration information; in response to the node board not being in place, controlling the second processor to set the corresponding general input and output pin to a low level.

[0126] In one embodiment, when the computer program is executed by the processor, the following steps are further implemented: in response to the second processor reading the values ​​of the multiple registers through the multiple general-purpose input and output channels, the values ​​of the multiple registers and the presence information of the multiple node boards are transmitted to the first processor of each node board; the watchdog timer of the first processor is checked, and a watchdog timer signal is periodically sent to the second processor through the first processor to determine whether the first processor is in a normal working state; in response to the first processor being in a normal working state, the node boards and the corresponding slot numbers are determined according to the presence information, and the node boards are sorted in ascending order according to the slot numbers; according to the sorting result, the values ​​of the registers corresponding to the node boards in place are read in sequence, and it is determined whether the values ​​of the registers are 1; in response to the value of the register being 1, the node board in place is used as the target node board, and the access rights of the power supply unit are assigned to the target node board, so that other node boards cannot access the power supply unit; in response to the value of the register being 0, the value of the register corresponding to the next node board in place is read in sequence according to the sorting result.

[0127] In one embodiment, when the computer program is executed by the processor, the following steps are also implemented: sending a first enable signal to the target second processor through the target first processor; in response to the target second processor receiving the first enable signal, sending a second enable signal to the integrated circuit bus buffer, so that the target first processor accesses the power supply unit through the integrated circuit bus buffer.

[0128] In one embodiment, when the computer program is executed by the processor, the following steps are also implemented: in response to the value of the register being 0, determining the target node board based on the values ​​of other registers, and displaying the slot number of the target node board on the operation and maintenance software; repeatedly obtaining the values ​​of the multiple registers until the in-place node board obtains access rights to the power supply unit.

[0129] In one embodiment, when the computer program is executed by the processor, the following steps are also implemented: in response to a watchdog exception of the target first processor, or the target first processor fails to regularly send a watchdog timer signal to the target second processor, determining that the target first processor has a fault; setting the corresponding general input and output pin to a low level through the target second processor, and resetting the second enable signal to release access rights to the target first processor; and determining whether the next in-place node board has access rights to the power supply unit based on the sorting result.

[0130] Those skilled in the art will appreciate that all or part of the processes in the above-mentioned embodiments can be implemented by instructing the relevant hardware through a computer program. The computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, storage, database or other media used in the embodiments provided in this application can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM).

[0131] The technical features of the above embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0132] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that a person skilled in the art could make various modifications and improvements without departing from the spirit of the present application, all of which fall within the scope of protection of the present application. Therefore, the scope of protection of the present patent application shall be determined by the appended claims.

Claims

1. A multi-node server access method, characterized in that: The multi-node server includes a backplane, a power supply unit, and a plurality of node boards, wherein the node board includes a first processor and a second processor, and the second processor is connected to the backplane via multiple universal input and output channels, wherein the universal input and output channels correspond one-to-one to the node boards, and the backplane includes a plurality of slots. The method includes: Acquiring in-place information of the plurality of node plates; Acquire configuration information from the first processor, and control the second processor to configure the general input and output pin levels corresponding to each node board according to the in-position information and the configuration information; Reading the values ​​of the general purpose input and output pins and storing them in corresponding registers, wherein the registers correspond to the node boards one by one; In response to the node board reading values ​​of multiple registers through the multi-way universal input and output channel, determining whether the node board has access rights to the power supply unit according to the in-position information and the values ​​of the multiple registers; The step of determining whether the node board has access rights to the power supply unit according to the in-position information and the values ​​of the multiple registers in response to the node board reading the values ​​of the multiple registers through the multi-way universal input and output channels includes: In response to the second processor reading the values ​​of the multiple registers through the multi-way general input and output channels, transmitting the values ​​of the multiple registers and the in-place information of the multiple node boards to the first processor of each node board; checking a watchdog timer of the first processor, and periodically sending a watchdog timer signal to the second processor through the first processor to determine whether the first processor is in a normal working state; In response to the first processor being in a normal working state, determining in-place node boards and corresponding slot numbers according to the in-place information, and sorting the in-place node boards in ascending order according to the slot numbers; Read the values ​​of the registers corresponding to the in-place node boards in sequence according to the sorting results; In response to the register value being a first preset value, the in-position node board is used as a target node board, and the access permission of the power supply unit is assigned to the target node board, so that other node boards cannot access the power supply unit; In response to the register value being the second preset value, the value of the register corresponding to the next in-place node board is read in sequence according to the sorting result.

2. The multi-node server access method according to claim 1, characterized in that: The obtaining of the in-place information of the plurality of node plates includes: Obtaining, by the second processor, slot numbers and presence signals of the plurality of slots respectively; Whether the node plate is in place is determined according to the slot number and the in-place signal, and the position of the node plate is determined.

3. The multi-node server access method according to claim 1 or 2, characterized in that: The controlling the second processor to configure the general input and output pin levels corresponding to each node board according to the in-position information and the configuration information includes: In response to the node board being in place, controlling the second processor to set the corresponding general purpose input and output pin to a high level or a low level according to the configuration information; In response to the node board being not in place, the second processor is controlled to set the corresponding general purpose input and output pin to a low level.

4. The multi-node server access method according to claim 1, wherein: In response to the register value being a first preset value, taking the in-place node board as a target node board, and assigning the access rights of the power supply unit to the target node board, comprises: sending a first enable signal to a target second processor through the target first processor; In response to the target second processor receiving the first enable signal, a second enable signal is sent to an integrated circuit bus buffer, so that the target first processor accesses the power supply unit through the integrated circuit bus buffer.

5. The multi-node server access method according to claim 1, characterized in that: The step of sequentially reading the values ​​of the registers corresponding to the in-place node boards according to the sorting results further includes: In response to the register value being a second preset value, determining a target node board according to values ​​of other registers, and displaying the slot number of the target node board on the operation and maintenance software; The values ​​of the multiple registers are repeatedly obtained until the in-place node board obtains access rights to the power supply unit.

6. The multi-node server access method according to claim 4, characterized in that: The method further comprises: In response to a watchdog exception of the target first processor, or the target first processor failing to periodically send a watchdog timer signal to the target second processor, determining that the target first processor is faulty; Setting the corresponding general purpose input / output pin to a low level by the target second processor and resetting the second enable signal to release the access rights of the target first processor; It is determined whether the next in-place node board has access rights to the power supply unit according to the sorting result.

7. A multi-node server access device, applied to the multi-node server access method according to claim 1, characterized in that: The device comprises: A first acquisition module is used to acquire in-place information of multiple node plates; A configuration module, configured to obtain configuration information from the first processor, and control the second processor to configure the general input and output pin levels corresponding to each node board according to the in-position information and the configuration information; A second acquisition module is used to read the value of each general input and output pin and store it in a corresponding register, wherein the register corresponds to the node board one by one; a control module, configured to, in response to the node board reading values ​​of a plurality of registers through the multi-way general-purpose input and output channels, determine whether the node board has access rights to the power supply unit according to the in-position information and the values ​​of the plurality of registers; Wherein, the control module is specifically used for: In response to the second processor reading the values ​​of the multiple registers through the multi-way general input and output channels, transmitting the values ​​of the multiple registers and the in-place information of the multiple node boards to the first processor of each node board; checking a watchdog timer of the first processor, and periodically sending a watchdog timer signal to the second processor through the first processor to determine whether the first processor is in a normal working state; In response to the first processor being in a normal working state, determining in-place node boards and corresponding slot numbers according to the in-place information, and sorting the in-place node boards in ascending order according to the slot numbers; Read the values ​​of the registers corresponding to the in-place node boards in sequence according to the sorting results; In response to the register value being a first preset value, the in-position node board is used as a target node board, and the access permission of the power supply unit is assigned to the target node board, so that other node boards cannot access the power supply unit; In response to the register value being the second preset value, the value of the register corresponding to the next in-place node board is read in sequence according to the sorting result.

8. A computer device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 6 are implemented.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 6 are implemented.

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