Shift register, gate drive circuit, and display panel

Abstract

Embodiments of the present application disclose a shift register, a gate drive circuit and a display panel. A node voltage control module is configured to control voltages of a first node and a second node according to an input signal, a first output module is configured to output a first gate drive signal according to the voltages of the first node and the second node, a second output module is configured to output a second gate drive signal according to the voltage of the first node and / or the second node, and the first gate drive signal and the second gate drive signal are different. In this way, two different gate drive signals can be output by the same shift register, the driving requirement of a pixel circuit can be met, the frame of the display panel can be reduced, and user experience can be improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a shift register, a gate driving circuit and a display panel. BACKGROUND

[0002] In some display panels, pixel circuits include P-type transistors and N-type transistors, and two kinds of gate driving signals are needed to drive the pixel circuits. If two groups of gate driving circuits are set, the frame area will be increased, which affects the user experience. SUMMARY

[0003] The present application provides a shift register, a gate driving circuit and a display panel, which can output two kinds of gate driving signals through the gate driving circuit, reduce the frame area of the display panel and improve the user experience.

[0004] According to an aspect of the present application, a shift register is provided, which comprises a node voltage control module, a first output module and a second output module, the node voltage control module is connected to a first node and a second node, the first output module is connected to the first node and the second node, and the second output module is connected to the first node and / or the second node.

[0005] The node voltage control module is configured to control the voltage of the first node and the second node according to an input signal; the first output module is configured to output a first gate driving signal through a first output end according to the voltage of the first node and the second node; the second output module is configured to output a second gate driving signal through a second output end according to the voltage of the first node and / or the second node, and the first gate driving signal and the second gate driving signal are different.

[0006] Optionally, one or more of the pulse width, the pulse amplitude and the positive and negative polarity of the pulse amplitude of the first gate driving signal and the second gate driving signal are different.

[0007] And / or, the first gate driving signal and the second gate driving signal are used to drive transistors of different channel types.

[0008] Optionally, the first gate driving signal is used to drive a P-type transistor, and the second gate driving signal is used to drive an N-type transistor.

[0009] The second gate driving signal comprises a first level signal and a second level signal, and the voltage of the first level signal is lower than that of the second level signal; the second output module comprises a P-type transistor, and the second output module is configured to output the first level signal through the P-type transistor.

[0010] Optionally, the second output module comprises a P-type transistor which is a polysilicon transistor; optionally, the first gate drive signal comprises a first level signal and a second level signal; optionally, the pulse of the first gate drive signal overlaps with the pulse of the second gate drive signal; optionally, the duration of the first level signal of the pulse of the first gate drive signal is within the duration of the second level signal of the pulse of the second gate drive signal; optionally, the pulse width of the first gate drive signal is smaller than the pulse width of the second gate drive signal; optionally, the input signal comprises a clock signal and a start signal, the pulse width of the first gate drive signal is equal to the pulse width of the clock signal, and the pulse width of the second gate drive signal is equal to the clock period of the clock signal; optionally, the input signal comprises a first clock signal and a second clock signal, the pulse of the first clock signal overlaps with the pulse of the start signal, and the pulse of the second clock signal overlaps with the pulse of the first gate drive signal; optionally, the rising edge of the pulse of the first gate drive signal is aligned with the rising edge of the pulse of the second clock signal; optionally, the rising edge of the pulse of the second gate drive signal is aligned with the rising edge of the pulse of the first clock signal; optionally, the falling edge of the pulse of the first gate drive signal is aligned with the falling edge of the pulse of the second clock signal; the rising edge of the pulse of the first gate drive signal is aligned with the rising edge of the pulse of the second clock signal; optionally, the rising edge and the falling edge of the pulse of the second gate drive signal are respectively aligned with the falling edges of two adjacent pulses of the first clock signal. Optionally, the first clock signal and the second clock signal have the same frequency and different phases.

[0011] Optionally, the second output module comprises a first output unit and a second output unit,

[0012] The first output unit is connected with the second node and is configured to be turned on or turned off according to the potential of the second node and output a second level signal to the second output end when turned on; or the first output unit is connected with the first node and is configured to be turned on or turned off according to the potential of the first node and output a second level signal to the second output end when turned on;

[0013] The second output unit is connected with the first node and / or the second node and is configured to be turned on or turned off according to the potential of the first node and / or the second node and output a first level signal to the second output end when turned on;

[0014] Optionally, the first output unit comprises a first transistor, the gate potential of the first transistor is positively correlated with the potential of the second node, or the gate potential of the first transistor is negatively correlated with the potential of the first node, or the gate of the first transistor is connected with the second node; the first pole of the first transistor is connected with the second power supply line or inputs the second level signal, and the second pole of the first transistor is connected with the second output end;

[0015] And / or, the second output unit comprises a second transistor, a gate potential of the second transistor is positively related to a potential of the first node, or a gate potential of the first transistor is negatively related to a potential of the second node; a first pole of the second transistor is connected to the first power line or accesses the first level signal, and a second pole of the second transistor is connected to the second output end;

[0016] Optionally, the second transistor is a P-type transistor; and optionally, the first transistor is a P-type transistor.

[0017] Optionally, the second output unit further comprises a first capacitor, a first end of the first capacitor is connected to the gate of the second transistor, and a second end of the first capacitor is connected to the second output end; and optionally, the node voltage control module is configured to control the potential of the first node to jump from a low potential to a high potential, and the potential of the second node to jump from a high potential to a low potential, or the potential of the first node to jump from a high potential to a low potential, and the potential of the second node to jump from a low potential to a high potential; and optionally, the node voltage control module is configured to control the potentials of the first node and the second node to be opposite.

[0018] Optionally, the second output unit further comprises an output control subunit, the output control subunit is connected to the first node and the second node respectively, the output control subunit is connected to the gate of the second transistor at a third node, and the output control subunit is configured to control the potential of the third node according to the potentials of the first node and the second node, so that the potential of the third node is positively related to the potential of the first node; the potential of the third node comprises a third level signal, and a voltage of the third level signal is lower than a voltage of the first power line; optionally, when the potential of the second node jumps from a low potential to a high potential, the potential of the third node jumps from a high potential to a low potential; and optionally, when the potential of the second node jumps from a high potential to a low potential, the potential of the third node jumps from a low potential to a high potential; optionally, the potentials of the second node and the third node are opposite; optionally, the potentials of the first node and the third node jump from a low potential to a high potential at the same time, and / or the potentials of the first node and the third node jump from a high potential to a low potential at the same time; optionally, the potential of the third node further comprises a second level signal, and a voltage of the third level signal is lower than a voltage of the second level signal; and optionally, an absolute value of a voltage difference between the third level signal and the first power line is greater than or equal to an absolute value of a threshold voltage of the second transistor.

[0019] Optionally, the output control subunit comprises a third transistor, a fourth transistor, a fifth transistor and a sixth transistor; a gate of the third transistor is connected with the first node; a first electrode of the third transistor is connected with the second power supply line or inputs the second level signal; a second electrode of the third transistor is connected with a first electrode of the fifth transistor; a second electrode of the fifth transistor is connected with the third power supply line or inputs the third level signal; a gate of the fourth transistor is connected with the second node; a first electrode of the fourth transistor is connected with the second power supply line or inputs the second level signal; a second electrode of the fourth transistor is connected with a first electrode of the sixth transistor; a second electrode of the sixth transistor is connected with the third power supply line or inputs the third level signal; a gate of the fifth transistor is connected with a second electrode of the fourth transistor; a gate of the sixth transistor is connected with a second electrode of the third transistor; optionally, the voltage of the third power supply line is lower than the voltage of the first power supply line; optionally, the third transistor and the fourth transistor are P-type transistors, and the fifth transistor and the sixth transistor are N-type transistors.

[0020] Optionally, the second output unit further comprises an output control subunit; the output control subunit comprises a first inverter; an input end of the first inverter is connected with the second node; an output end of the first inverter is connected with a gate of the second transistor and a third node; a first end of the first inverter is connected with the second power supply line or inputs the second level signal; the output control subunit is used for controlling a potential of the third node according to a potential of the second node; a second end of the first inverter is connected with the third power supply line or inputs the third level signal.

[0021] Alternatively, the output control subunit comprises M first inverters.

[0022] M is an odd number greater than 1; an input end of the first first inverter is connected with the second node; an output end of the i-th first inverter is connected with an input end of the (i+1)-th first inverter; an output end of the M-th first inverter is connected with the gate of the second transistor and the third node; i is an integer greater than or equal to 1 and less than or equal to M; the output control subunit is used for controlling the potential of the third node according to the potential of the second node.

[0023] Alternatively, M is an even number greater than or equal to 2; an input end of the first first inverter is connected with the first node; an output end of the i-th first inverter is connected with an input end of the (i+1)-th first inverter; an output end of the M-th first inverter is connected with the gate of the second transistor and the third node; the output control subunit is used for controlling the potential of the third node according to the potential of the first node.

[0024] The first end of the first inverter is connected with the second power supply line or inputs the second level signal; the second end of the M-th first inverter is connected with the third power supply line or inputs the third level signal.

[0025] Optionally, the second end of the at least one first inverter is connected to a first power line or inputs a first level signal; or, the second end of all the first inverters is connected to a third power line or inputs a third level signal; optionally, the voltage of the third power line is lower than the voltage of the first power line; optionally, the potential of the third node includes the third level signal, and the voltage of the third level signal is lower than the voltage of the first power line; optionally, when the potential of the second node jumps from a low potential to a high potential, the potential of the third node jumps from a high potential to a low potential; when the potential of the second node jumps from a high potential to a low potential, the potential of the third node jumps from a low potential to a high potential; optionally, the potentials of the second node and the third node are opposite to each other; optionally, the potentials of the first node and the third node jump from a low potential to a high potential at the same time, and / or the potentials of the first node and the third node jump from a high potential to a low potential at the same time; optionally, the potential of the third node further includes a second level signal, and the voltage of the third level signal is lower than the voltage of the second level signal; optionally, the absolute value of the voltage difference between the third level signal and the first power line is greater than or equal to the absolute value of the threshold voltage of the second transistor;

[0026] Optionally, the first inverter includes a fifteenth transistor and a sixteenth transistor, the gate of the fifteenth transistor and the gate of the sixteenth transistor are connected to the input end of the first inverter, the first electrode of the fifteenth transistor is connected to the first end of the first inverter, the second electrode of the fifteenth transistor and the first electrode of the sixteenth transistor are connected to the output end of the first inverter, and the second electrode of the sixteenth transistor is connected to the second end of the first inverter; optionally, the fifteenth transistor is an N-type transistor, and the sixteenth transistor is a P-type transistor.

[0027] Optionally, the first output module includes a third output unit and a fourth output unit, the third output unit is connected to the first node and is configured to turn on or turn off according to the potential of the first node and output a second level signal to the first output end when turned on; the fourth output unit is connected to the second node and is configured to turn on or turn off according to the potential of the second node and output a first level signal to the first output end during at least part of the period when turned on;

[0028] Optionally, the effective levels of the first gate drive signal and the second gate drive signal overlap; optionally, the effective level of the first gate drive signal is a first level signal, and the effective level of the second gate drive signal is a second level signal; optionally, the ineffective levels of the first gate drive signal and the second gate drive signal overlap;

[0029] Optionally, the third output unit comprises a seventh transistor, a gate of the seventh transistor is connected with the first node, a first electrode of the seventh transistor is connected with the second power supply line or inputs the second level signal, and a second electrode of the seventh transistor is connected with the first output end; optionally, the fourth output unit comprises an eighth transistor, a gate of the eighth transistor is connected with the second node, a first electrode of the eighth transistor inputs the second clock signal, and a second electrode of the eighth transistor is connected with the first output end; optionally, the fourth output unit further comprises a second capacitor, a first end of the second capacitor is connected with the second node, and a second end of the second capacitor is connected with the first output end.

[0030] Optionally, the input signal comprises a first clock signal, a second clock signal and a start signal; the node voltage control module comprises an input unit and a first control unit, the input unit is used for turning on or turning off according to the first clock signal, and transmitting the start signal to the second node when turned on; the first control unit is used for transmitting the first level signal or the second level signal to the first node according to the potential of the second node; optionally, the node voltage control module further comprises a second control unit, the second control unit is used for transmitting the second level signal to the second node according to the potential of the first node and the second clock signal; optionally, the first control unit comprises a second inverter; optionally, the first clock signal, the second clock signal and the start signal respectively comprise alternately arranged first level pulses and second level pulses, the first level pulse of the start signal overlaps with the first level pulse of the first clock signal, and does not overlap with the first level pulse of the second clock signal; optionally, the first level pulse of the start signal is one or more, and the first level pulse of the first clock signal and the second clock signal is multiple respectively;

[0031] The first output module comprises a third output unit and a fourth output unit, the third output unit comprises a seventh transistor, the gate of the seventh transistor is connected with the first node, the first electrode of the seventh transistor is connected with the second power supply line or inputs the second level signal, and the second electrode of the seventh transistor is connected with the first output end; the fourth output unit comprises an eighth transistor, the gate of the eighth transistor is connected with the second node, the first electrode of the eighth transistor inputs the second clock signal, and the second electrode of the eighth transistor is connected with the first output end; optionally, the input unit comprises a ninth transistor, the gate of the ninth transistor inputs the first clock signal, the first electrode of the ninth transistor inputs the start signal, and the second electrode of the ninth transistor is connected with the second node; optionally, the shift register further comprises a tenth transistor, the second electrode of the ninth transistor is connected with the second node through the tenth transistor, the gate of the tenth transistor is connected with the first power supply line or inputs the first level signal; optionally, the first control unit comprises an eleventh transistor and a twelfth transistor, the gate of the eleventh transistor is connected with the second electrode of the ninth transistor or the second node, the first electrode of the eleventh transistor is connected with the second power supply line or inputs the second level signal, and the second electrode of the eleventh transistor is connected with the first node; the gate of the twelfth transistor is connected with the second electrode of the ninth transistor or the second node, the first electrode of the twelfth transistor is connected with the first power supply line or inputs the first level signal, and the second electrode of the twelfth transistor is connected with the first node; the second control unit comprises a thirteenth transistor and a fourteenth transistor, the first electrode of the thirteenth transistor is connected with the second power supply line or inputs the second level signal, the second electrode of the thirteenth transistor is connected with the first electrode of the fourteenth transistor, the second electrode of the fourteenth transistor is connected with the second electrode of the ninth transistor or the second node, one of the gate of the thirteenth transistor and the gate of the fourteenth transistor is connected with the first node, and the other inputs the second clock signal; optionally, the gate of the thirteenth transistor is connected with the first node, and the gate of the fourteenth transistor inputs the second clock signal; optionally, the eleventh transistor is a P-type transistor, and the twelfth transistor is an N-type transistor.

[0032] According to another aspect of the present application, there is provided a gate drive circuit comprising a plurality of shift registers of any of the embodiments of the present application, the plurality of shift registers being cascaded; the start signal input end of the (n+1)th shift register is connected with the first output end of the nth shift register, wherein n is a positive integer greater than or equal to 1.

[0033] According to another aspect of the present application, there is provided a display panel comprising a pixel circuit and a gate drive circuit of any of the embodiments of the present application, the pixel circuit comprising a plurality of transistors, the first output end and the second output end of the shift register being connected with transistors of different channel types in the pixel circuit.

[0034] Optionally, the pixel circuit comprises a driving transistor, a data writing transistor and a compensation transistor, the data writing transistor is connected between a data line and a first electrode of the driving transistor, and the compensation transistor is connected between a second electrode and a gate electrode of the driving transistor; a gate electrode of the data writing transistor is connected with the first output terminal, and a gate electrode of the compensation transistor is connected with the second output terminal; optionally, a channel type of the data writing transistor is P channel, and a channel type of the compensation transistor is N channel; optionally, the pixel circuit further comprises a first light emitting control transistor and a second light emitting control transistor, the first light emitting control transistor is connected between a fourth power supply line and the first electrode of the driving transistor; the second light emitting control transistor is connected between the second electrode of the driving transistor and a first electrode of the light emitting device, and a second electrode of the light emitting device is connected with a fifth power supply line; a gate electrode of the first light emitting control transistor and a gate electrode of the second light emitting control transistor are connected with a light emitting control signal line; optionally, the pixel circuit further comprises a first initialization transistor, a gate electrode of the first initialization transistor is connected with a first scan line, a first electrode of the first initialization transistor is connected with a first initialization signal line, and a second electrode of the first initialization transistor is connected with the gate electrode or the second electrode of the driving transistor; optionally, the pixel circuit further comprises a second initialization transistor, a gate electrode of the second initialization transistor is connected with a second scan line, a first electrode of the second initialization transistor is connected with a second initialization signal line, and a second electrode of the second initialization transistor is connected with the first electrode of the light emitting device.

[0035] The shift register, the gate drive circuit and the display panel provided by the embodiments of the present application can output two different gate drive signals through the same shift register, can meet the driving requirements of the pixel circuit, and can reduce the frame of the display panel and improve the user experience.

[0036] It should be understood that the description in this section is not intended to identify key or critical features of the embodiments of the present application or to limit the scope of the present application. Other features of the present application will become apparent from the following description. BRIEF DESCRIPTION OF DRAWINGS

[0037] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiments will be briefly introduced as follows. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative effort on the basis of these drawings.

[0038] Figure 1is a structural schematic diagram of a shift register provided by an embodiment of the present application;

[0039] Figure 2 is a structural schematic diagram of another gate drive circuit provided by an embodiment of the present application;

[0040] Figure 3 is a structural schematic diagram of another shift register provided by an embodiment of the present application;

[0041] Figure 4 is a structural schematic diagram of another shift register provided by an embodiment of the present application;

[0042] Figure 5 is a structural schematic diagram of another shift register provided by an embodiment of the present application;

[0043] Figure 6 is a structural schematic diagram of a pixel circuit in the related art;

[0044] Figure 7 is a structural schematic diagram of another shift register provided by an embodiment of the present application;

[0045] Figure 8 is a structural schematic diagram of another shift register provided by an embodiment of the present application;

[0046] Figure 9 is a structural schematic diagram of another shift register provided by an embodiment of the present application;

[0047] Figure 10 is a structural schematic diagram of another shift register provided by an embodiment of the present application;

[0048] Figure 11 is a structural schematic diagram of another shift register provided by an embodiment of the present application;

[0049] Figure 12 is a structural schematic diagram of another shift register provided by an embodiment of the present application;

[0050] Figure 13 is a structural schematic diagram of another shift register provided by an embodiment of the present application;

[0051] Figure 14 is a structural schematic diagram of another shift register provided by an embodiment of the present application,

[0052] Figure 15 is a working timing diagram of a shift register provided by an embodiment of the present application;

[0053] Figure 16 is a structural schematic diagram of a gate drive circuit provided by an embodiment of the present application;

[0054] Figure 17 is a structural schematic diagram of a display panel provided by an embodiment of the present application. DETAILED DESCRIPTION

[0055] In order to enable persons skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by persons skilled in the art without creative efforts should fall within the scope of protection of the present application.

[0056] It should be noted that the terms “first”, “second”, and the like in the specification and claims of the present application and the above-described drawings are used to distinguish similar objects, and do not necessarily indicate a specific order or a chronological sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances, so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein. In addition, the terms “include” and “have” and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product, or device including a series of steps or units does not necessarily have to be limited to only those steps or units clearly listed, but can include other steps or units not clearly listed or inherent to the process, method, product, or device. The connection can include a direct connection or an indirect connection. The connection can include an electrical connection.

[0057] Figure 1 is a structural schematic diagram of a shift register provided by an embodiment of the present application, referring to Figure 1 The shift register includes a node voltage control module 110, a first output module 120, and a second output module 130. The node voltage control module 110 is connected to a first node N1 and a second node N2. The first output module 120 is connected to the first node N1 and the second node N2. The second output module 130 is connected to the first node N1 and / or the second node N2 (exemplarily showing a case where the second output module 130 is connected to the first node N1 and the second node N2). Figure 1 The node voltage control module 110 is configured to control voltages of the first node N1 and the second node N2 according to an input signal. The first output module 120 is configured to output a first gate driving signal through a first output end OUT1 according to the voltages of the first node N1 and the second node N2. The second output module 130 is configured to output a second gate driving signal through a second output end OUT2 according to the voltage of the first node N1 and / or the second node N2. The first gate driving signal and the second gate driving signal are different.

[0058] The node voltage control module 110 is connected to a plurality of input signals, for example, the input signals include but are not limited to a start signal and one or at least two clock signals. The node voltage control module 110 transmits corresponding voltages to the first node N1 and the second node N2 respectively according to the input signals in different working periods of the shift register. The potentials of the first node N1 and the second node N2 are different in at least part of the periods, for example, the potentials are opposite, or the high and low potentials are opposite, or the positive and negative polarities are opposite, etc.

[0059] The first output module 120 is connected to the first node N1 and the second node N2 respectively. The first output module 120 can output a first gate drive signal to a first output end OUT1 of the shift register according to the potentials of the first node N1 and the second node N2, wherein the first gate drive signal includes a first level signal and a second level signal. Specifically, in part of the working periods, the first gate drive signal is the first level signal; in another part of the working periods, the first gate drive signal is the second level signal. The first gate drive signal is used to drive a transistor of a first channel type.

[0060] The second output module 130 is connected to the first node N1 and / or the second node N2. The second output module 130 can output a second gate drive signal to a second output end OUT2 of the shift register according to the potentials of the first node N1 and / or the second node N2, wherein the second gate drive signal includes a first level signal and a second level signal. Specifically, in part of the working periods, the second gate drive signal is the first level signal; in another part of the working periods, the second gate drive signal is the second level signal. The second gate drive signal is used to drive a transistor of a second channel type. The first channel type is a P channel, and the second channel type is an N channel, or the first channel type is an N channel, and the second channel type is a P channel.

[0061] The shift register of the embodiment can output two different gate drive signals through the same shift register, can meet the driving requirements of the pixel circuit, and can reduce the frame of the display panel and improve the user experience, by setting the node voltage control module to control the voltages of the first node and the second node according to the input signals, the first output module to output the first gate drive signal according to the voltages of the first node and the second node, and the second output module to output the second gate drive signal according to the voltages of the first node and / or the second node, and the first gate drive signal and the second gate drive signal being different.

[0062] Optionally, one or more of the pulse width, the pulse amplitude, and the positive and negative polarity of the pulse amplitude of the first gate drive signal and the second gate drive signal are different; and / or, the first gate drive signal and the second gate drive signal are used to drive transistors of different channel types. In this way, the first gate drive signal and the second gate drive signal can drive different transistors, for example, transistors turned on in different working stages in a pixel circuit of a display panel, and / or transistors of different channel types, to meet the driving requirements of the pixel circuit while reducing the frame of the display panel.

[0063] As described in the above embodiment, the first gate drive signal includes a first level signal and a second level signal, and the second gate drive signal includes a first level signal and a second level signal. In some optional embodiments of the present application, the first gate drive signal is used to drive a P-type transistor, and the second gate drive signal is used to drive an N-type transistor; the voltage of the first level signal is lower than the voltage of the second level signal; and the second output module 130 includes a P-type transistor, and the second output module 130 is used to output the first level signal through the P-type transistor.

[0064] Specifically, in the related art, the first level signal in the second gate drive signal is output through an N-type oxide transistor. Since the mobility of the oxide transistor is low, when the transistor characteristics fluctuate due to stress, the output waveform stability of the second gate drive signal is poor, reducing the reliability of the gate drive circuit. In the present embodiment, the second output module 130 is configured to include a P-type transistor, and the first level signal is output through the P-type transistor. The P-type transistor can be a polysilicon transistor, such as a low-temperature polysilicon transistor. Compared with the N-type oxide transistor, the P-type transistor has higher mobility, which can improve the output stability of the second gate drive signal and improve the reliability of the gate drive circuit.

[0065] Figure 2 is another structural schematic diagram of a gate drive circuit provided by an embodiment of the present application, referring to Figure 2 Optionally, in the gate drive circuit, the second output module 130 includes a first output unit 131 and a second output unit 132.

[0066] The first output unit 131 is connected with the second node N2, and the first output unit 131 is configured to control the potential of the second output end OUT2 according to the potential of the second node N2, for example, the first output unit 131 is configured to turn on or turn off according to the potential of the second node N2, and output the second level signal VGH to the second output end OUT2 when turned on. Alternatively, the first output unit 131 is connected with the first node N1, and the first output unit 131 is configured to control the potential of the second output end OUT2 according to the potential of the first node N1, for example, the first output unit 131 is configured to turn on or turn off according to the potential of the first node N1, and output the second level signal VGH to the second output end OUT2 when turned on.

[0067] The second output unit 132 is connected with the first node N1 and / or the second node N2, and the second output unit 132 is configured to control the potential of the second output end OUT2 according to the potential of the first node N1 and / or the second node N2, for example, the second output unit 132 is configured to turn on or turn off according to at least the potential of the first node N1, and output the first level signal VGL to the second output end OUT2 when turned on.

[0068] Specifically, in the second output module 130, the first output unit 131 can control whether the voltage of the second power line and / or the second level signal VGH is output to the second output end OUT2, and the second output unit 132 can control whether the voltage of the first power line and / or the first level signal VGL is output to the second output end OUT2. For example, the turn-on period of the first output unit 131 and the turn-on period of the second output unit 132 are at least partially different. For example, the first output unit 131 and the second output unit 132 are time-divisionally turned on. Optionally, the node voltage control module 110 is configured to control the potentials of the first node N1 and the second node N2 to be opposite, that is, when the first node N1 is at a high potential, the second node N2 is at a low potential; when the first node N1 is at a low potential, the second node N2 is at a high potential. Specifically, the node voltage control module 110 is configured to control the potential of the first node N1 to jump from a low potential to a high potential, and the potential of the second node N2 to jump from a high potential to a low potential; and the potential of the first node N1 to jump from a high potential to a low potential, and the potential of the second node N2 to jump from a low potential to a high potential. The first output unit 131 and the second output unit 132 each include at least one switching element, which can be a transistor. The first output unit 131 is connected with the second node N2, and the node voltage control module 110 controls the turn-on state of the first output unit 131 by controlling the potential of the second node N2, thereby controlling whether the second level signal VGH is output to the second output end OUT2. The first output unit 131 can be configured to control the potential of the second output end OUT2 according to the potential of the second node N2.

[0069] Optionally, the first output unit 131 comprises a first transistor T1, a gate potential of the first transistor T1 is positively related to a potential of the second node N2. That is, the gate potential of the first transistor T1 and the potential of the second node N2 are simultaneously high or low. And / or, that is, the gate potential of the first transistor T1 and the potential of the second node N2 are simultaneously changed from low to high or from high to low. For example, the gate of the first transistor T1 is connected with the second node N2. The first electrode of the first transistor T1 is connected with the second power line and / or the second level signal VGH, and the second electrode of the first transistor T1 is connected with the second output terminal OUT2.

[0070] The second output unit 132 is connected with the first node N1 and / or the second node N2, and is used to turn on or turn off according to the potential of the first node N1 and / or the second node N2. When turned on, the second output unit 132 transmits the first level signal VGL to the second output terminal OUT2. For example, the second output unit 132 is connected with the first node N1, and is used to turn on or turn off according to the potential of the first node N1. When turned on, the second output unit 132 transmits the first level signal VGL to the second output terminal OUT2. For example, the second output unit 132 is connected with the second node N2, and is used to turn on or turn off according to the potential of the second node N2. When turned on, the second output unit 132 transmits the first level signal VGL to the second output terminal OUT2. The second output unit 132 is connected with the first node N1 and the second node N2, and is used to turn on or turn off according to the potential of the first node N1 and the second node N2. When turned on, the second output unit 132 transmits the first level signal VGL to the second output terminal OUT2. The second output unit 132 is connected with at least the first node N1. In some embodiments, the second output unit 132 is connected with the first node N1 and turns on or turns off according to the potential of the first node N1. In other embodiments, the second output unit 132 is connected with the first node N1 and the second node N2 respectively, and turns on or turns off according to the potential of the first node N1 and the second node N2. When turned on, the second output unit 132 transmits the first level signal VGL to the second output terminal OUT2. The second output unit 132 can be used to control the potential of the second output terminal OUT2 according to the potential of the first node N1 and the second node N2.

[0071] Figure 2The second output unit 132 is connected to the first node N1 and not connected to the second node N2 in the example shown in FIG. 2. Optionally, the second output unit 132 includes a second transistor T2, and the gate potential of the second transistor T2 is positively correlated with the potential of the first node N1. That is, the gate potential of the second transistor T2 is high at the same time as the potential of the first node N1 is high, and is low at the same time as the potential of the first node N1 is low. And / or, that is, the gate potential of the second transistor T2 jumps from low to high at the same time as the potential of the first node N1 jumps from high to low, and jumps from high to low at the same time as the potential of the first node N1 jumps from low to high.

[0072] In other embodiments, the gate potential of the second transistor T2 is inversely correlated with the potential of the second node N2, for example, the potentials are opposite. That is, the gate potential of the second transistor T2 is high when the potential of the second node N2 is low, and is low when the potential of the second node N2 is high. And / or, that is, the gate potential of the second transistor T2 jumps from low to high at the same time as the potential of the second node N2 jumps from high to low, and jumps from high to low at the same time as the potential of the second node N2 jumps from low to high. Jumping from low to high can be a rising edge. Jumping from high to low can be a falling edge.

[0073] The first electrode of the second transistor T2 is connected to the first power supply line and / or accesses the first level signal VGL, and the second electrode of the second transistor T2 is connected to the second output terminal OUT2. As shown in FIG. 2, in some embodiments, the gate of the second transistor T2 is connected to the first node N1. Optionally, the second transistor T2 is a P-type transistor, so as to ensure that the second output module 130 outputs the first level signal VGL through the P-type transistor, ensure the stability of the first level signal VGL in the second gate drive signal output by the shift register, and facilitate improving the display effect. Figure 2

[0074] In some optional embodiments of the present application, the first transistor T1 is a P-type transistor, so as to ensure that the second output module 130 outputs the second level signal VGH through the P-type transistor, ensure the stability of the second level signal VGH in the second gate drive signal output by the shift register, and facilitate improving the display effect.

[0075] Optionally, the second output unit 132 further includes a first capacitor C1, the first end of the first capacitor C1 is connected to the gate of the second transistor T2, and the second end of the first capacitor C1 is connected to the second output terminal OUT2.

[0076] Figure 3 FIG. 3 is a structural schematic diagram of another shift register provided by an embodiment of the present application, which is similar to FIG. 2, and the same parts are not described here. Figure 3 ​In some embodiments, the second output unit 132 further comprises an output control sub-unit 133 connected with the first node N1 and the second node N2 respectively, and the output control sub-unit 133 is connected with the gate of the second transistor T2 and the third node N3, for controlling the potential of the third node N3 according to the potentials of the first node N1 and the second node N2, so that the potential of the third node N3 is positively correlated with the potential of the first node N1, and when the potential of the first node N1 is the first level signal VGL, the potential of the third node N3 is the third level signal VGL2, and the voltage of the third level signal VGL2 is lower than the voltage of the first level signal VGL. The potential of the third node N3 is positively correlated with the potential of the first node N1, that is, the potential of the third node N3 and the potential of the first node N1 are high at the same time, are low at the same time, and / or the potential of the third node N3 and the potential of the first node N1 jump from low to high at the same time, jump from high to low at the same time.

[0077] Optionally, when the potential of the second node N2 jumps from low to high, the potential of the third node N3 jumps from high to low; when the potential of the second node N2 jumps from high to low, the potential of the third node N3 jumps from low to high. Optionally, the potentials of the second node N2 and the third node N3 are opposite.

[0078] In this embodiment, the gate of the second transistor T2 is not directly connected with the first node N1, the first node N1 and the second node N2 are connected through the output control subunit 133, and the output control subunit 133 controls the potential of the third node N3 according to the potentials of the first node N1 and the second node N2. Optionally, when the first node N1 is the first level signal VGL and the second node N2 is the second level signal VGH, the output control subunit 133 outputs the third level signal VGL2 to the third node N3 according to the first level signal VGL of the first node N1 and the second level signal VGH of the second node N2; when the first node N1 is the second level signal VGH and the second node N2 is the first level signal VGL, the output control subunit 133 outputs the second level signal VGH to the third node N3 according to the second level signal VGH of the first node N1 and the first level signal VGL of the second node N2. Since the voltage of the third level signal VGL2 is lower than the voltage of the first level signal VGL, when the third node N3 is the third level signal VGL2, the absolute value of the voltage difference between the gate and the first electrode of the second transistor T2 is large, so that the on state of the second transistor T2 is better, and it is ensured that the first level signal VGL input to the first electrode of the second transistor T2 can be transmitted to the second output end OUT2 with the same amplitude, thereby ensuring that the on or off state of the transistor driven by the second gate drive signal is better, which is beneficial to improving the display effect. For example, when the transistor driven by the second gate drive signal is an N-type transistor, the first level signal VGL is a low-level signal, and the second level signal VGH is a high-level signal, the N-type transistor driven by the second gate drive signal can be completely turned off under the action of the first level signal VGL in the second gate drive signal.

[0079] Optionally, the potential of the third node N3 further includes a second level signal, and the voltage of the third level signal is lower than the voltage of the second level signal.

[0080] In some optional embodiments of the present application, the absolute value of the voltage difference between the third level signal VGL2 and the first level signal VGL is greater than or equal to the absolute value of the threshold voltage of the second transistor T2. In this way, it can be ensured that when the potential of the third node N3 is the third level signal VGL2, the second transistor T2 can be completely turned on, and it is further ensured that when the second transistor T2 is turned on, the first level signal VGL can be transmitted to the second output end OUT2 with the same amplitude, thereby improving the display effect.

[0081] For example, the absolute value of the voltage difference between the third level signal VGL2 and the first power line (which can transmit the first level signal VGL) is greater than or equal to the absolute value of the threshold voltage of the second transistor T2.

[0082] Continuing to refer to Figure 3Optionally, the output control subunit 133 comprises a third transistor T3, a fourth transistor T4, a fifth transistor T5 and a sixth transistor T6; the gate of the third transistor T3 is connected with the first node N1, the first electrode of the third transistor T3 is connected with the second power supply line and / or inputs the second level signal VGH, the second electrode of the third transistor T3 is connected with the first electrode of the fifth transistor T5, the second electrode of the fifth transistor T5 is connected with the third power supply line and / or inputs the third level signal VGL2; the gate of the fourth transistor T4 is connected with the second node N2, the first electrode of the fourth transistor T4 is connected with the second power supply line and / or inputs the second level signal VGH, the second electrode of the fourth transistor T4 is connected with the first electrode of the sixth transistor T6, the second electrode of the sixth transistor T6 is connected with the third power supply line and / or inputs the third level signal VGL2; the gate of the fifth transistor T5 is connected with the second electrode of the fourth transistor T4, the gate of the sixth transistor T6 is connected with the second electrode of the third transistor T3. In this connection mode, when the fifth transistor T5 is turned off, the gate of the fifth transistor can transmit the third level signal VGL2 by the sixth transistor T6, the source of the fifth transistor T5 is also the third level signal VGL2, the potential of the gate and the source of the fifth transistor T5 is equal, so that the leakage current of the fifth transistor T5 is small when the fifth transistor T5 is turned off, and the power consumption of the gate drive circuit is reduced. The same is true for the sixth transistor T6 in the output control subunit 133. When the output control subunit 133 is set as an inverter structure, when the N-type transistor in the inverter is turned off, the gate is the first level signal VGL1, the source is the third level signal VGL3, the leakage current of the N-type transistor is large, and the power consumption is also large. That is, the structure of the output control subunit 133 in this embodiment can reduce the leakage current of the N-type transistor and reduce the power consumption of the gate drive circuit compared with the structure of the inverter.

[0083] Optionally, the voltage of the third power supply line is lower than the voltage of the first power supply line.

[0084] Optionally, the third transistor T3 is a P-type transistor, and / or the fourth transistor T4 is a P-type transistor, and / or the fifth transistor T5 is an N-type transistor, and / or the sixth transistor T6 is an N-type transistor.

[0085] Taking the first level signal VGL as a low level signal and the second level signal VGH as a high level signal as an example. When the first node N1 is the first level signal VGL and the second node N2 is the second level signal VGH, the third transistor T3 is turned on, the fourth transistor T4 is turned off, the second level signal VGH is transmitted to the gate of the sixth transistor T6 through the third transistor T3, so that the sixth transistor T6 is turned on, the third level signal VGL2 is transmitted to the third node N3, and the fifth transistor T5 is turned off according to the third level signal VGL2. When the first node N1 is the second level signal VGH and the second node N2 is the first level signal VGL, the third transistor T3 is turned off, the fourth transistor T4 is turned on, the second level signal VGH is transmitted to the gate of the fifth transistor T5 and the third node N3 through the fourth transistor T4, the fifth transistor T5 is turned on according to the second level signal VGH of the gate, the third level signal VGL2 is transmitted to the gate of the sixth transistor T6 through the fifth transistor T5, and the sixth transistor T6 is turned off. In this way, the potential of the third node N3 is positively correlated with the potential of the first node N1, and when the potential of the first node N1 is the first level signal VGL, the potential of the third node N3 is the third level signal VGL2.

[0086] Figure 4 is another structure diagram of a shift register provided by the embodiment of the present application, referring to Figure 4 Optionally, the second electrode of the sixth transistor T6 is connected to the third power supply line and / or accesses the third level signal VGL2; and the second electrode of the fifth transistor T5 is connected to the first power supply line and / or accesses the first level signal VGL.

[0087] Compared with the second electrode of the fifth transistor T5 being connected to the first power supply line and / or accessing the first level signal VGL (the gate-source voltage difference of the sixth transistor T6 when turned off is the difference between the first level signal VGL and the third level signal VGL2, that is, greater than 0), the second electrode of the fifth transistor T5 is connected to the third power supply line and / or accesses the third level signal VGL2 (the gate-source voltage difference of the sixth transistor T6 when turned off is the difference between the third level signal VGL2 and the third level signal VGL2, that is, 0), which can reduce the leakage current when the sixth transistor T6 is turned off.

[0088] Figure 5 is another structure diagram of a shift register provided by the embodiment of the present application, referring to Figure 5Optionally, the first output module 120 comprises a third output unit 121 and a fourth output unit 122, the third output unit 121 is connected with the first node N1, and the third output unit 121 is configured to control the potential of the first output end OUT1 according to the potential of the first node N1, for example, the third output unit 121 is configured to turn on or turn off according to the potential of the first node N1, and output the second level signal VGH to the first output end OUT1 when turned on; the fourth output unit 122 is connected with the second node N2, and the fourth output unit 122 is configured to control the potential of the first output end OUT1 according to the potential of the second node N2, for example, the fourth output unit 122 is configured to turn on or turn off according to the potential of the second node N2, and output the first level signal VGL to the first output end OUT1 during at least part of the time period when turned on.

[0089] Optionally, the third output unit 121 and the fourth output unit 122 each comprise at least one switching device, which can be a transistor. By providing that the first output module 120 comprises the third output unit 121 and the fourth output unit 122, the third output unit 121 and the fourth output unit 122 can be turned on at different times, and when the third output unit 121 is turned on, the third output unit 121 outputs the second level signal VGH to the first output end OUT1; and during at least part of the time period when the fourth output unit 122 is turned on, the fourth output unit 122 outputs the first level signal VGL to the first output end OUT1.

[0090] Optionally, the third output unit 121 comprises a seventh transistor T7, the gate of the seventh transistor T7 is connected with the first node N1, the first pole of the seventh transistor T7 is connected with the second power supply line and / or inputs the second level signal VGH, and the second pole of the seventh transistor T7 is connected with the first output end OUT1.

[0091] In some embodiments, the fourth output unit 122 comprises an eighth transistor T8, the gate of the eighth transistor T8 is connected with the second node N2, the signal inputted to the first pole of the eighth transistor T8 comprises the first level signal VGL, and in some embodiments, the first pole of the eighth transistor T8 inputs a periodic clock signal comprising the first level signal VGL and the second level signal VGH (as shown in the eighth transistor T8 in the middle of the figure). Figure 4 In some embodiments, the first pole of the eighth transistor T8 inputs the second clock signal CK2 (as shown in the eighth transistor T8 in the middle of the figure), and the second pole of the eighth transistor T8 is connected with the first output end OUT1.

[0092] Optionally, the fourth output unit 122 further comprises a second capacitor C2, the first end of the second capacitor C2 is connected with the second node N2, and the second end of the second capacitor C2 is connected with the first output end OUT1.

[0093] Optionally, the effective levels of the first gate drive signal and the second gate drive signal overlap.

[0094] The effective level of the first gate drive signal is a level that can turn on the transistor to be driven, and the ineffective level of the first gate drive signal is a level that can turn off the transistor to be driven. The effective level of the second gate drive signal is a level that can turn on the transistor to be driven, and the ineffective level of the second gate drive signal is a level that can turn off the transistor to be driven.

[0095] Optionally, the effective level of the first gate drive signal is a first level signal, and the effective level of the second gate drive signal is a second level signal. In some optional embodiments, the ineffective levels of the first gate drive signal and the second gate drive signal overlap.

[0096] The one of the first level signal VGL and the second level signal VGH is a high level signal, and the other is a low level signal. In the case where the first gate drive signal is used to drive a P-type transistor and the second gate drive signal is used to drive an N-type transistor, the first level signal VGL is a low level signal, and the second level signal VGH is a high level signal; in the case where the first gate drive signal is used to drive an N-type transistor and the second gate drive signal is used to drive a P-type transistor, the first level signal VGL is a high level signal, and the second level signal VGH is a low level signal.

[0097] The first gate drive signal and the second gate drive signal output by the shift register can be used to drive different transistors in the pixel circuit. Figure 6 is a structural schematic diagram of a pixel circuit in the related art, referring to Figure 6 The pixel circuit includes a drive transistor DT, a data writing transistor M1, and a compensation transistor M2. The data writing transistor M1 is connected between a data line Data and a first electrode of the drive transistor DT, and the compensation transistor M2 is connected between a second electrode and a gate electrode of the drive transistor DT. A first output end OUT1 of the shift register can be connected to the data writing transistor M1 in the pixel circuit, a second output end OUT2 can be connected to the compensation transistor M2 in the pixel circuit, an effective level of the first gate drive signal Scan1 is a level that can turn on the data writing transistor M1, and an effective level of the second gate drive signal Scan2 is a level that can turn on the compensation transistor M2. By setting the effective level of the first gate drive signal and the effective level of the second gate drive signal output by the shift register to overlap, the data writing transistor M1 and the compensation transistor M2 can be turned on at the same time during the overlapping period of the effective level of the first gate drive signal and the effective level of the second gate drive signal, and then the writing of the data voltage on the data line to the gate electrode of the drive transistor DT is completed.

[0098] In some embodiments, the data writing transistor M1 is a P-type transistor, and the compensation transistor M2 is an N-type transistor. That is, the channel type of the data writing transistor M1 is a P-channel, and the channel type of the compensation transistor M2 is an N-channel. Optionally, the P-type transistor in the pixel circuit is a polysilicon transistor, for example, a low-temperature polysilicon transistor, and the N-type transistor is an oxide transistor. Correspondingly, the display panel is a low-temperature polysilicon oxide (LTPO) process display panel. In some embodiments, the P-type transistor in the shift register is a polysilicon transistor, for example, a low-temperature polysilicon transistor, and the N-type transistor is an oxide transistor. That is, the shift register of the present embodiment can be used for driving the LTPO process display panel, which is conducive to ensuring a higher smoothness and lower power consumption of the display panel.

[0099] Optionally, the pixel circuit further comprises a first light-emitting control transistor M3 and a second light-emitting control transistor M4, the first light-emitting control transistor M3 is connected between the fourth power supply line VDD and the first electrode of the driving transistor DT; the second light-emitting control transistor M4 is connected between the second electrode of the driving transistor DT and the first electrode of the light-emitting device D1, the second electrode of the light-emitting device D1 is connected to the fifth power supply line VSS; the gate of the first light-emitting control transistor M3 and the gate of the second light-emitting control transistor M4 are connected to the light-emitting control signal line EM.

[0100] Optionally, the pixel circuit further comprises a first initialization transistor M5, the gate of the first initialization transistor M5 is connected to the first scan line Sn1, the first electrode of the first initialization transistor M5 is connected to the first initialization signal line Vref1, and the second electrode of the first initialization transistor M5 is connected to the gate or the second electrode of the driving transistor DT.

[0101] Optionally, the pixel circuit further comprises a second initialization transistor M6, the gate of the second initialization transistor M6 is connected to the second scan line Sn2, the first electrode of the second initialization transistor M6 is connected to the second initialization signal line Vref2, and the second electrode of the second initialization transistor M6 is connected to the first electrode of the light-emitting device D1.

[0102] Optionally, the pixel circuit further comprises a storage capacitor Cst, the first end of the storage capacitor Cst is connected to the gate of the driving transistor DT, and the second end of the storage capacitor Cst is connected to the fourth power supply line VDD.

[0103] Figure 7 is another structure diagram of a shift register provided by an embodiment of the present application, referring to Figure 7Optionally, the input signals include a first clock signal CK1, a second clock signal CK2 and a start signal SIN; the node voltage control module 110 includes some or all of an input unit 111, a first control unit 112 and a second control unit 113, the input unit 111 is configured to control transmission of the start signal SIN to the second node N2 according to the first clock signal CK1, for example, the input unit 111 is configured to turn on or turn off according to the first clock signal CK1, and transmit the start signal SIN to the second node N2 when turned on; the first control unit 112 is configured to output the potential of the second node N2 to the first node inversely, for example, the first control unit 112 is configured to transmit the first level signal VGL or the second level signal VGH to the first node N1 according to the potential of the second node N2; the second control unit 113 is configured to transmit the second level signal VGH to the second node N2 according to the potential of the first node N1 and the second clock signal CK2.

[0104] The first clock signal CK1, the second clock signal CK2 and the start signal SIN each include first level pulses and second level pulses arranged alternately, the first clock signal CK1 and the second clock signal CK2 are periodic signals, the periods of the first clock signal CK1 and the second clock signal CK2 are equal, the first clock signal CK1 and the second clock signal CK2 each include a plurality of first level pulses and second level pulses, the first level pulse of the first clock signal CK1 overlaps the second level pulse of the second clock signal CK2, and the second level pulse of the first clock signal CK1 overlaps the first level pulse of the second clock signal CK2.

[0105] The gate drive circuit in the display panel includes a plurality of shift registers, and the plurality of shift registers are cascaded. For a first stage shift register, a start signal SIN is provided by an external circuit structure. For a second stage to a last stage shift register, the start signal SIN can be a first gate drive signal output by an upper stage shift register, that is, in adjacent two stages of registers, a first output end OUT1 of a lower stage shift register is connected with a first output end OUT1 of an upper stage shift register. Optionally, the first level pulse of the start signal SIN is one or more, the first level pulse of the start signal SIN overlaps the first level pulse of the first clock signal CK1, and does not overlap the first level pulse of the second clock signal CK2.

[0106] Specifically, when the first clock signal CK1 is the first level signal VGL, the input unit 111 is turned on. When the second node N2 is the first level signal VGL, the first control unit 112 transmits the second level signal VGH to the first node N1; when the second node N2 is the second level signal VGH, the first control unit 112 transmits the first level signal VGL to the first node N1. When the first node N1 is the first level signal VGL and the second clock signal CK2 is the first level signal VGL, the second control unit 113 transmits the second level signal VGH to the second node N2.

[0107] In some embodiments, the first output module 120 comprises a third output unit 121 and a fourth output unit 122. The third output unit 121 comprises a seventh transistor T7, the gate of the seventh transistor T7 is connected with the first node N1, the first electrode of the seventh transistor T7 is connected with the second power supply line and / or inputs the second level signal VGH, and the second electrode of the seventh transistor T7 is connected with the first output end OUT1. The fourth output unit 122 comprises an eighth transistor T8, the gate of the eighth transistor T8 is connected with the second node N2, the first electrode of the eighth transistor T8 inputs the second clock signal CK2, and the second electrode of the eighth transistor T8 is connected with the first output end OUT1.

[0108] Figure 8 is another structure diagram of a shift register provided by the embodiment of the present application, referring to Figure 8 Optionally, the input unit 111 comprises a ninth transistor T9, the gate of the ninth transistor T9 inputs the first clock signal CK1, the first electrode of the ninth transistor T9 inputs the start signal SIN, and the second electrode of the ninth transistor T9 is connected with the second node N2.

[0109] In some embodiments, the shift register further comprises a tenth transistor T10, the second electrode of the ninth transistor T9 is connected with the second node N2 through the tenth transistor T10, or the second electrode of the ninth transistor T9 is connected with the gate of the eighth transistor T8 through the tenth transistor T10; the gate of the tenth transistor T10 is connected with the first power supply line and / or inputs the first level signal VGL. Taking the tenth transistor T10 as a P-type transistor as an example, the tenth transistor T10 is arranged to prevent the second node N2 from being coupled to an extremely low level, so that the extremely low level is blocked by the tenth transistor T10 and cannot be transmitted to the common end (i.e., the fourth node N4) of the tenth transistor T10 and the ninth transistor T9, thereby protecting the ninth transistor T9 and the transistor in the second control unit 113 connected with the tenth transistor T10 from being damaged due to excessive voltage difference, and improving the reliability of the shift register.

[0110] Figure 9 is another structure diagram of a shift register provided by the embodiment of the present application, referring toFigure 9 Optionally, the first control unit 112 comprises a second inverter, and in some embodiments, the first control unit 112 comprises an eleventh transistor T11 and a twelfth transistor T12, a gate of the eleventh transistor T11 is connected with a second electrode of the ninth transistor T9 or the second node N2, a first electrode of the eleventh transistor T11 is connected with the second power line and / or accesses the second level signal VGH, a second electrode of the eleventh transistor T11 is connected with the first node N1; a gate of the twelfth transistor T12 is connected with the second electrode of the ninth transistor T9 or the second node N2, a first electrode of the twelfth transistor T12 is connected with the first power line and / or accesses the first level signal VGL, a second electrode of the twelfth transistor T12 is connected with the first node N1. Optionally, the eleventh transistor T11 is a P-type transistor, and the twelfth transistor T12 is an N-type transistor. By setting the shift register to simultaneously comprise a P-type transistor and an N-type transistor, the number of transistor devices included in the shift register can be reduced, which is conducive to reducing the frame and improving the user experience. Optionally, the P-type transistor is a polysilicon transistor, and the N-type transistor is an oxide transistor. For example, the second inverter comprises the eleventh transistor T11 and the twelfth transistor T12.

[0111] Specifically, in the case where the ninth transistor T9 is directly connected with the second output unit 132 at the second node N2, the gate of the eleventh transistor T11 is directly connected with the second node N2. In the case where the ninth transistor T9 is connected with the second output unit 132 through the tenth transistor T10, the gate of the eleventh transistor T11 is connected with the second electrode (the fourth node N4) of the ninth transistor T9. The same applies to the twelfth transistor T12, which will not be described here. The eleventh transistor T11 is turned on when the second node N2 is the first level signal VGL or the second electrode (the fourth node N4) of the ninth transistor T9 is the first level signal VGL, and transmits the second level signal VGH to the first node N1. The twelfth transistor T12 is turned on when the second node N2 is the second level signal VGH or the second electrode (the fourth node N4) of the ninth transistor T9 is the second level signal VGH, and transmits the first level signal VGL to the first node N1.

[0112] Continuing to refer to Figure 9 In some embodiments, the second control unit 113 comprises a thirteenth transistor T13 and a fourteenth transistor T14, a first electrode of the thirteenth transistor T13 accesses the second level signal VGH, a second electrode of the thirteenth transistor T13 is connected with a first electrode of the fourteenth transistor T14, a second electrode of the fourteenth transistor T14 is connected with the second electrode (the fourth node N4) of the ninth transistor T9 or the second node N2, one of a gate of the thirteenth transistor T13 and a gate of the fourteenth transistor T14 is connected with the first node N1, and the other accesses the second clock signal CK2.

[0113] Optionally, the gate of the thirteenth transistor T13 is connected with the first node N1, and the gate of the fourteenth transistor T14 is connected with the second clock signal CK2.

[0114] Specifically, when the first node N1 is the first level signal VGL, the thirteenth transistor T13 is turned on, and the second level signal VGH is transmitted from the first electrode of the thirteenth transistor T13 to the first electrode of the fourteenth transistor T14. When the second clock signal CK2 is the first level signal VGL, the fourteenth transistor T14 is turned on, and the signal at the first electrode of the fourteenth transistor T14 is transmitted to the second electrode (the fourth node N4) of the ninth transistor T9 or the second node N2. When the first node N1 is the first level signal VGL, and the second clock signal CK2 at the gate of the fourteenth transistor T14 is the first level signal VGL, the second level signal VGH is transmitted to the second electrode (the fourth node N4) of the ninth transistor T9 or the second node N2 through the thirteenth transistor T13 and the fourteenth transistor T14.

[0115] Figure 10 is another structure diagram of a shift register provided by an embodiment of the present application, referring to Figure 10 Optionally, the connecting node (i.e., the fourth node N4) of the tenth transistor T10 and the ninth transistor T9 can be used as the second node N2, and the fourth output unit 122 includes the tenth transistor T10. The gate of the fourth transistor can be connected with the fourth node N4. The fourth node N4 and the second node are the same node.

[0116] Figure 11 is another structure diagram of a shift register provided by an embodiment of the present application, referring to Figure 11Optionally, the gate potential of the first transistor T1 is inversely related to the potential of the first node N1, and the potentials are opposite in high and low. That is, one of the gate potential of the first transistor T1 and the potential of the first node N1 is high, and the other is low. And / or, that is, when the gate potential of the first transistor T1 jumps from low to high, the potential of the first node N1 jumps from high to low. When the gate potential of the first transistor T1 jumps from high to low, the potential of the first node N1 jumps from low to high. For example, the first node N1 is connected to the gate of the first transistor T1 through the third inverter 1311. Optionally, the first output unit 131 further includes the third inverter 1311, the input end of the third inverter 1311 is connected to the first node N1, and the output end of the third inverter 1311 is connected to the gate of the first transistor T1. Wherein, the third inverter 1311 can invert the potential of the first node N1 and output to the gate of the first transistor T1. The gate of the second transistor T2 is the third node N3, and the third node N3 is connected to the first node N1, or the third node N3 is the same node as the first node N1. In this case, the second output module 130 can output the second gate drive signal through the second output end OUT2 according to the voltage of the first node N1. The third inverter 1311 has the same or similar structure as the first inverter 1331 or the second inverter, which will not be described here.

[0117] For example Figure 10 The first node N1 in the first node N1 is connected to the gate of the first transistor T1 through the third inverter 1311, instead of directly connecting the second node to the gate of the first transistor T1. The working principle is the same or similar, which will not be described here.

[0118] Figure 12 is another structure diagram of a shift register provided by an embodiment of the application, referring to Figure 12 Optionally, the second output unit 132 further includes an output control subunit 133, and the output control subunit 133 includes a first inverter 1331, the input end of the first inverter 1331 is connected to the second node N2, and the output end of the first inverter 1331 is connected to the gate of the second transistor T2 at the third node N3; the first end of the first inverter 1331 is connected to the second power line or accesses the second level signal VGH, and the output control subunit 133 is used for controlling the potential of the third node N3 according to the potential of the second node N2; the second end of the first inverter 1331 is connected to the third power line or accesses the third level signal VGL2.

[0119] Specifically, the first inverter 1331 can invert the potential of the second node N2, so that when the potential of the second node N2 is the first level signal VGL, the potential of the third node N3 is the second level signal VGH; when the potential of the second node N2 is the second level signal VGH, the potential of the third node N3 is the third level signal VGL2 or the voltage on the third power supply line.

[0120] In some optional embodiments, the output control subunit 133 includes M first inverters 1331; optionally, M is an odd number greater than 1, the input end of the first first inverter 1331 is connected with the second node N2, the output end of the i-th first inverter 1331 is connected with the input end of the (i+1)-th first inverter 1331, and the output end of the M-th first inverter 1331 is connected with the gate of the second transistor T2 at the third node N3; i is an integer greater than or equal to 1 and less than or equal to M; the output control subunit 133 is configured to control the potential of the third node N3 according to the potential of the second node N2.

[0121] Figure 13 is another structure diagram of a shift register provided by an embodiment of the present application, and in other optional embodiments, M is an even number greater than or equal to 2; the input end of the first first inverter 1331 is connected with the first node, the output end of the i-th first inverter 1331 is connected with the input end of the (i+1)-th first inverter 1331, and the output end of the M-th first inverter 1331 is connected with the gate of the second transistor T2 at the third node N3; the output control subunit 133 is configured to control the potential of the third node N3 according to the potential of the first node; the first end of the first inverter 1331 is connected with the second power supply line or inputs the second level signal VGH, and the second end of the M-th first inverter 1331 is connected with the third power supply line or inputs the third level signal VGL2.

[0122] Optionally, when the potential of the second node N2 jumps from a low potential to a high potential, the potential of the third node N3 jumps from a high potential to a low potential; when the potential of the second node N2 jumps from a high potential to a low potential, the potential of the third node N3 jumps from a low potential to a high potential. Optionally, the potentials of the second node N2 and the third node N3 are opposite in high and low. Optionally, the potentials of the first node N1 and the third node N3 simultaneously jump from a low potential to a high potential, and / or the potentials of the first node N1 and the third node N3 simultaneously jump from a high potential to a low potential.

[0123] Optionally, the first inverter 1331 comprises a fifteenth transistor T15 and a sixteenth transistor T16, the gate of the fifteenth transistor T15 and the gate of the sixteenth transistor T16 are connected with the input end of the first inverter 1331, the first electrode of the fifteenth transistor T15 is connected with the first end of the first inverter 1331, the second electrode of the fifteenth transistor T15 and the first electrode of the sixteenth transistor T16 are connected with the output end of the first inverter 1331, and the second electrode of the sixteenth transistor T16 is connected with the second end of the first inverter 1331; optionally, the fifteenth transistor T15 is an N-type transistor, and the sixteenth transistor T16 is a P-type transistor.

[0124] Reference Figure 12 When M is an odd number, when the potential of the second node N2 is low, the fifteenth transistor T15 is turned on to transmit the second level signal VGH to the third node N3. When the potential of the second node N2 is high, the sixteenth transistor T16 is turned on to transmit the third level signal VGL2 to the third node N3.

[0125] Reference Figure 13 When M is an even number, when the potential of the first node N1 is low, in the first inverter 1331 at an odd position, the fifteenth transistor T15 is turned on to transmit the second level signal VGH to the input end of the first inverter 1331 at an even position, so that the sixteenth transistor T16 in the first inverter 1331 at the even position is turned on to transmit the third level signal VGL2 backward, and finally the potential of the third node is the third level signal VGL2. When the potential of the first node N1 is high, in the first inverter 1331 at an odd position, the sixteenth transistor T16 is turned on to transmit the third level signal VGL2 to the input end of the first inverter 1331 at an even position, so that the fifteenth transistor T15 in the first inverter 1331 at the even position is turned on to transmit the second level signal VGH backward, and finally the potential of the third node is the second level signal VGH.

[0126] Figure 14 is another structure diagram of a shift register provided by an embodiment of the application, referring to Figure 14 Optionally, the second end of at least one first inverter 1331 is connected with a first power supply line or inputs a first level signal; or, referring to Figure 12 and Figure 13 The second end of all the first inverters 1331 is connected with a third power supply line or inputs a third level signal VGL2.

[0127] Optionally, the potential of the third node N3 comprises a third level signal VGL2, and the voltage of the third level signal VGL2 is lower than the voltage of the first power supply line; optionally, the voltage of the third power supply line is lower than the voltage of the first power supply line.

[0128] Optionally, the potential of the third node N3 further comprises a second level signal VGH, and a voltage of the third level signal VGL2 is lower than a voltage of the second level signal VGH.

[0129] Optionally, an absolute value of a voltage difference between the third level signal VGL2 and the voltage of the first power line is greater than or equal to an absolute value of a threshold voltage of the second transistor T2.

[0130] Figure 15 is a working timing diagram of a shift register provided by an embodiment of the present application, for reference Figure 9 and Figure 15 , taking the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9, the tenth transistor T10, the eleventh transistor T11, the thirteenth transistor T13 and the fourteenth transistor T14 as P-type transistors, and taking the fifth transistor T5, the sixth transistor T6 and the twelfth transistor T12 as N-type transistors as examples, taking a low level signal as the first level signal VGL and taking a high level signal as the second level signal VGH as examples for description, the working timing of the shift register comprises the following stages.

[0131] In the first stage t1, the start signal SIN is a high level signal, the first clock signal CK1 is a low level signal, and the second clock signal CK2 is a high level signal. The ninth transistor T9 is turned on in response to the first clock signal CK1, the high level signal of the start signal SIN is transmitted to the second node N2 through the ninth transistor T9 and the tenth transistor T10, and the eighth transistor T8 is turned off. The twelfth transistor T12 is turned on according to the high level signal of the fourth node N4, and the first level signal VGL (low level signal) is transmitted to the first node N1, the seventh transistor T7 is turned on according to the low level signal of the first node N1, and the second level signal VGH (high level signal) is output to the first output end OUT1 through the seventh transistor T7. The third transistor T3 is turned on according to the low level signal of the first node N1, and the second level signal VGH (high level signal) is transmitted to the gate of the sixth transistor T6, the sixth transistor T6 is turned on, the third level signal VGL2 is transmitted to the third node N3, so that the second transistor T2 is turned on, and the first level signal VGL is transmitted to the second output end OUT2. Moreover, the voltage of the third level signal VGL2 is lower than the voltage of the first level signal VGL, so that the on state of the second transistor T2 is good, and the influence of the threshold voltage of the second transistor T2 on the output of the first level signal VGL is reduced. The first transistor T1 is turned off according to the high level signal of the second node N2.

[0132] In the second stage t2, the start signal SIN is a high level signal, the first clock signal CK1 is a high level signal, and the second clock signal CK2 is a low level signal. The ninth transistor T9 is turned off in response to the first clock signal CK1, and no signal is transmitted to the fourth node N4. The fourth node N4 keeps the high level of the previous stage, and accordingly, the second node N2 keeps the high level of the previous stage, and the eighth transistor T8 is turned off. The twelfth transistor T12 keeps being turned on, and accordingly, the seventh transistor T7 keeps being turned on. The second level signal VGH is transmitted to the first output end OUT1 through the seventh transistor T7. Because the potentials of the first node N1 and the second node N2 are the same as the state of the first stage t1, in the second stage t2, the second transistor T2 is turned on, the first transistor T1 is turned off, and the first level signal VGL is transmitted to the second output end OUT2 through the second transistor T2. The thirteenth transistor T13 and the fourteenth transistor T14 are turned on, and the second level signal VGH is transmitted to the second node N2 through the thirteenth transistor T13 and the fourteenth transistor T14.

[0133] In the third stage t3, the start signal SIN is a low level signal, the first clock signal CK1 is a low level signal, and the second clock signal CK2 is a high level signal. The ninth transistor T9 is turned on in response to the first clock signal CK1, and the low level signal of the start signal SIN is transmitted to the second node N2 through the ninth transistor T9 and the tenth transistor T10. The eighth transistor T8 is turned on according to the low level signal of the second node N2, and the high level second clock signal CK2 is transmitted to the first output end OUT1. The eleventh transistor T11 is turned on according to the low level signal of the fourth node N4, and the second level signal VGH (high level signal) is transmitted to the first node N1. The seventh transistor T7 is turned off according to the high level signal of the first node N1. The first transistor T1 is turned on according to the low level signal of the second node N2, and the second level signal VGH (high level signal) is transmitted to the second output end OUT2. The fourth transistor T4 is turned on according to the low level signal of the second node N2, and the second level signal VGH (high level signal) is transmitted to the gate of the fifth transistor T5 and the third node N3, so that the fifth transistor T5 is turned on, the third level signal VGL2 is transmitted to the gate of the sixth transistor T6, and the sixth transistor T6 is turned off. The second transistor T2 is turned off according to the high level of the third node N3.

[0134] In the fourth stage t4, the start signal SIN is a high level signal, the first clock signal CK1 is a high level signal, and the second clock signal CK2 is a low level signal. The ninth transistor T9 is turned off in response to the first clock signal CK1, and no signal is transmitted to the fourth node N4. The fourth node N4 keeps the low level of the previous stage, and the second node N2 keeps the low level of the previous stage. The eighth transistor T8 is turned on to transmit the low level second clock signal CK2 to the first output terminal OUT1. The eleventh transistor T11 keeps being turned on, the first node N1 is a high level signal, and the seventh transistor T7 keeps being turned off. Because the potentials of the first node N1 and the second node N2 are the same as the state of the first stage t1, in the second stage t2, the first transistor T1 is turned on, the second transistor T2 is turned off, and the second level signal VGH is transmitted to the second output terminal OUT2 through the first transistor T1.

[0135] In the fifth stage t5, the start signal SIN is a high level signal, the first clock signal CK1 is a low level signal, and the second clock signal CK2 is a high level signal. The ninth transistor T9 is turned on in response to the first clock signal CK1, and the high level signal of the start signal SIN is transmitted to the second node N2 through the ninth transistor T9 and the tenth transistor T10. The eighth transistor T8 is turned off. The twelfth transistor T12 is turned on according to the high level signal of the fourth node N4 to transmit the first level signal VGL (low level signal) to the first node N1. The seventh transistor T7 is turned on according to the low level signal of the first node N1 to output the second level signal VGH (high level signal) to the first output terminal OUT1 through the seventh transistor T7. The third transistor T3 is turned on according to the low level signal of the first node N1 to transmit the second level signal VGH (high level signal) to the gate of the sixth transistor T6. The sixth transistor T6 is turned on to transmit the third level signal VGL2 to the third node N3, so that the second transistor T2 is turned on to transmit the first level signal VGL to the second output terminal OUT2. Moreover, the voltage of the third level signal VGL2 is lower than the voltage of the first level signal VGL, so that the second transistor T2 is in a good turned-on state, and the threshold voltage of the second transistor T2 reduces the influence on the output of the first level signal VGL. The first transistor T1 is turned off according to the high level signal of the second node N2.

[0136] In the sixth stage t6, the start signal SIN is a high level signal, the first clock signal CK1 is a high level signal, and the second clock signal CK2 is a low level signal. The ninth transistor T9 is turned off in response to the first clock signal CK1, and no signal is transmitted to the fourth node N4. The fourth node N4 keeps the high level of the previous stage, and the second node N2 keeps the high level of the previous stage correspondingly. The eighth transistor T8 is turned off. The twelfth transistor T12 keeps conducting, and the seventh transistor T7 keeps conducting correspondingly. The second level signal VGH is transmitted to the first output end OUT1 through the seventh transistor T7. Because the potentials of the first node N1 and the second node N2 are the same as the state of the first stage t1, in the sixth stage t6, the second transistor T2 is turned on, the first transistor T1 is turned off, and the first level signal VGL is transmitted to the second output end OUT2 through the second transistor T2. The thirteenth transistor T13 and the fourteenth transistor T14 are turned on, and the second level signal VGH is transmitted to the second node N2 through the thirteenth transistor T13 and the fourteenth transistor T14.

[0137] In the subsequent process, the fifth stage t5 and the sixth stage t6 are alternately repeated in the same timing.

[0138] The first stage t1 and the second stage t2, the second stage t2 and the third stage t3, the third stage t3 and the fourth stage t4, the fourth stage t4 and the fifth stage t5, and the fifth stage t5 and the sixth stage t6 each include an intermediate state stage. In each intermediate state stage, the potentials of the first node N1, the second node N2, the third node N3, and the fourth node N4 in the shift register are the same as the potentials of the first node N1, the second node N2, the third node N3, and the fourth node N4 in the previous stage corresponding to the intermediate state stage.

[0139] For example, in the first intermediate state stage between the first stage t1 and the second stage t2, the start signal SIN is a high level signal, the first clock signal CK1 is a high level signal, and the second clock signal CK2 is a high level signal. The ninth transistor T9 is turned off according to the first clock signal CK1 in the shift register, the fourth node N4 and the second node N2 maintain the high level of the first stage t1, the twelfth transistor T12 keeps conducting, and the first node N1 is still at a low level. Because the potential states of the first node N1 and the second node N2 are the same as those of the first stage t1, the potential state of the third node N3 is determined by the potentials of the first node N1 and the second node N2, and thus the potential state of the third node N3 is also the same as that of the first stage t1. Therefore, in the first intermediate state stage, the first output end OUT1 is still the second level signal VGH output by the seventh transistor T7, and the second output end OUT2 is still the first level signal VGL output by the second transistor T2.

[0140] In the second intermediate state stage between the second stage t2 and the third stage t3, the start signal SIN is a high level signal for a period of time and a low level signal for a period of time, the first clock signal CK1 is a high level signal, the second clock signal CK2 is a high level signal, the ninth transistor T9 in the shift register is turned off according to the first clock signal CK1, the fourth node N4 and the second node N2 maintain the high level of the second stage t2, so that the twelfth transistor T12 remains turned on, and the first node N1 is still a low level. Since the potential states of the first node N1 and the second node N2 are the same as those in the second stage t2, the potential state of the third node N3 is determined by the potentials of the first node N1 and the second node N2, and therefore the potential state of the third node N3 is also the same as that in the second stage t2. Correspondingly, the third node N3 is a low level signal, and therefore in the second intermediate state stage, the first output end OUT1 is still the second level signal VGH output by the seventh transistor T7, and the second output end OUT2 is still the first level signal VGL output by the second transistor T2.

[0141] In the third intermediate state stage between the third stage t3 and the fourth stage t4, the start signal SIN is a low level signal for a period of time and a high level signal for a period of time, the first clock signal CK1 is a high level signal, and the second clock signal CK2 is a high level signal. The ninth transistor T9 in the shift register is turned off according to the first clock signal CK1, the fourth node N4 and the second node N2 maintain the low level of the third stage t3, the eighth transistor T8 is turned on according to the low level of the second node N2, and the high level second clock signal CK2 is transmitted to the first output end OUT1. The eleventh transistor T11 is turned on according to the low level of the fourth node N4, the second level signal VGH (high level signal) is transmitted to the first node N1, so that the seventh transistor T7 is turned off. Since the potential states of the first node N1 and the second node N2 are the same as those in the third stage t3, the potential state of the third node N3 is determined by the potentials of the first node N1 and the second node N2, and therefore the potential state of the third node N3 is also the same as that in the third stage t3. Correspondingly, the third node N3 is a high level signal, and therefore in the third intermediate state stage, the first output end OUT1 is still the high level second clock signal CK2 output by the eighth transistor T8, and the second output end OUT2 is still the second level signal VGH output by the first transistor T1.

[0142] In the fourth intermediate state stage between the fourth stage t4 and the fifth stage t5, the start signal SIN is a high level signal, the first clock signal CK1 is a high level signal, and the second clock signal CK2 is a high level signal. The ninth transistor T9 in the shift register is turned off according to the first clock signal CK1, the fourth node N4 and the second node N2 maintain the high level of the fifth stage t5, so that the twelfth transistor T12 remains turned on, and the first node N1 remains a low level. Because the potential state of the first node N1 and the second node N2 is the same as that of the first stage t1, the potential state of the third node N3 is determined by the potentials of the first node N1 and the second node N2, so the potential state of the third node N3 is also the same as that of the fifth stage t5. Therefore, in the fifth intermediate state stage, the first output terminal OUT1 remains the second level signal VGH output by the seventh transistor T7, and the second output terminal OUT2 remains the first level signal VGL output by the second transistor T2.

[0143] In the fourth intermediate state stage between the fourth stage t4 and the fifth stage t5, the start signal SIN is a high level signal, the first clock signal CK1 is a high level signal, and the second clock signal CK2 is a high level signal. The ninth transistor T9 in the shift register is turned off according to the first clock signal CK1, the fourth node N4 and the second node N2 maintain the high level of the fifth stage t5, so that the twelfth transistor T12 remains turned on, and the first node N1 remains a low level. Because the potential state of the first node N1 and the second node N2 is the same as that of the first stage t1, the potential state of the third node N3 is determined by the potentials of the first node N1 and the second node N2, so the potential state of the third node N3 is also the same as that of the fifth stage t5. Therefore, in the fifth intermediate state stage, the first output terminal OUT1 remains the second level signal VGH output by the seventh transistor T7, and the second output terminal OUT2 remains the first level signal VGL output by the second transistor T2.

[0144] Reference Figure 15 Optionally, the pulse of the first gate driving signal overlaps with the pulse of the second gate driving signal.

[0145] Optionally, the pulse of the first gate driving signal overlaps with the pulse of the second gate driving signal.

[0146] In some embodiments, the duration of the first level signal of the pulse of the first gate drive signal is within the duration of the second level signal of the pulse of the second gate drive signal.

[0147] Optionally, the pulse width of the first gate drive signal is smaller than the pulse width of the second gate drive signal.

[0148] Optionally, the input signal comprises a clock signal and a start signal SIN, the pulse width of the first gate drive signal is equal to the pulse width of the clock signal, and the pulse width of the second gate drive signal is equal to the clock period of the clock signal.

[0149] Optionally, the input signal comprises a first clock signal CK1 and a second clock signal CK2, the pulse of the first clock signal CK1 overlaps the pulse of the start signal SIN, and the pulse of the second clock signal CK2 overlaps the pulse of the first gate drive signal.

[0150] Optionally, the rising edge of the pulse of the first gate drive signal is aligned with the rising edge of the pulse of the second clock signal CK2.

[0151] Optionally, the falling edge of the pulse of the second gate drive signal is aligned with the falling edge of the pulse of the first clock signal CK1.

[0152] Optionally, the falling edge of the pulse of the first gate drive signal is aligned with the falling edge of the pulse of the second clock signal CK2, and the rising edge of the pulse of the first gate drive signal is aligned with the rising edge of the pulse of the second clock signal CK2.

[0153] Optionally, the rising edge and the falling edge of the pulse of the second gate drive signal are respectively aligned with the falling edges of two adjacent pulses of the first clock signal CK1.

[0154] Optionally, the first clock signal CK1 and the second clock signal CK2 have the same frequency and different phases, for example, opposite phases. The active potential pulse of the first clock signal CK1 and the active potential pulse of the second clock signal CK2 do not overlap, for example, there is a time interval. The active potential of the active potential pulse of the first clock signal CK1 and the active potential pulse of the second clock signal CK2 is the first level signal, for example, a low potential.

[0155] The embodiment of the present application also provides a gate drive circuit, Figure 16 is a structural schematic diagram of the gate drive circuit provided by the embodiment of the present application, referring to Figure 16The gate drive circuit comprises a plurality of shift registers 10, wherein the shift register 10 is the shift register 10 of any of the above embodiments of the present application, the plurality of shift registers 10 are cascaded, and optionally, a start signal input end of an n+1th shift register (which can be connected to the start signal SIN) is connected with a first output end OUT1 of an nth shift register, wherein n is a positive integer greater than or equal to 1, that is, the first output end OUT1 of the nth shift register outputs the first gate drive signal as the start signal of the n+1th shift register. The start signal of the first shift register is inputted from outside.

[0156] The gate drive circuit of the embodiment comprises the shift register of any of the above embodiments of the present application, and has the beneficial effects of the shift register of any of the above embodiments of the present application, which will not be repeated here.

[0157] The gate drive circuit can be connected with a first clock line and a second clock line. The first clock line can be used to provide the first clock signal to the odd-numbered shift register, and the second clock line can be used to provide the second clock signal to the odd-numbered shift register. The first clock line can be used to provide the second clock signal to the even-numbered shift register, and the second clock line can be used to provide the first clock signal to the even-numbered shift register.

[0158] The embodiment of the present application further provides a display panel, Figure 17 which is a structural schematic diagram of the display panel provided by the embodiment of the present application, referring to Figure 6 and Figure 17 The display panel comprises a pixel circuit 2 and the gate drive circuit 1 of any of the embodiments of the present application, the pixel circuit 2 comprises a plurality of transistors, and the first output end and the second output end of the shift register 10 are connected with transistors of different channel types in the pixel circuit 2.

[0159] Optionally, the pixel circuit 2 comprises a driving transistor DT, a data writing transistor M1 and a compensation transistor M2, the data writing transistor M1 is connected with a data line Data and a first electrode of the driving transistor DT respectively, and the compensation transistor M2 is connected between a second electrode and a gate electrode of the driving transistor DT; a gate electrode of the data writing transistor M1 is connected with the first output end OUT1, the gate electrode of the data writing transistor M1 is connected with the first gate drive signal Scan1, and a gate electrode of the compensation transistor M2 is connected with the second output end OUT2, the gate electrode of the compensation transistor M2 is connected with the second gate drive signal Scan2.

[0160] Optionally, the channel type of the data writing transistor M1 is P channel, and the channel type of the compensation transistor M2 is N channel.

[0161] Optionally, the pixel circuit 2 further comprises a first light emitting control transistor M3 and a second light emitting control transistor M4, the first light emitting control transistor M3 is connected between the fourth power supply line VDD and the first electrode of the driving transistor DT; the second light emitting control transistor M4 is connected between the second electrode of the driving transistor DT and the first electrode of the light emitting device D1, the second electrode of the light emitting device D1 is connected to the fifth power supply line VSS; the gate of the first light emitting control transistor M3 and the gate of the second light emitting control transistor M4 are connected to the light emitting control signal line EM.

[0162] Optionally, the pixel circuit further comprises a first initialization transistor M5, the gate of the first initialization transistor M5 is connected to the first scan line Sn1, the first electrode of the first initialization transistor M5 is connected to the first initialization signal line Vref1, and the second electrode of the first initialization transistor M5 is connected to the gate or the second electrode of the driving transistor DT.

[0163] Optionally, the pixel circuit further comprises a second initialization transistor M6, the gate of the second initialization transistor M6 is connected to the second scan line Sn2, the first electrode of the second initialization transistor M6 is connected to the second initialization signal line Vref2, and the second electrode of the second initialization transistor M6 is connected to the first electrode of the light emitting device D1.

[0164] Optionally, the pixel circuit further comprises a storage capacitor Cst, the first end of the storage capacitor Cst is connected to the gate of the driving transistor DT, and the second end of the storage capacitor Cst is connected to the fourth power supply line VDD.

[0165] It should be understood that the various forms of flow shown above can be used to reorder, add or delete steps. For example, the steps described in the present application can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solutions of the present application can be achieved, which are not limited herein.

[0166] The above detailed description does not constitute a limitation on the protection scope of the present application. Those skilled in the art should understand that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modifications, equivalent replacements and improvements made within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. A shift register, characterized by, The node voltage control module is connected to the first node and the second node, the first output module is connected to the first node and the second node, and the second output module is connected to the first node and / or the second node. The node voltage control module is configured to control voltages of the first node and the second node according to an input signal. The first output module is configured to output a first gate drive signal through a first output end according to the voltages of the first node and the second node, and the second output module is configured to output a second gate drive signal through a second output end according to the voltages of the first node and / or the second node, wherein the first gate drive signal and the second gate drive signal are different. The second output module includes a first output unit and a second output unit, the first output unit is connected to the second node and is configured to turn on or turn off according to a potential of the second node, and output a second level signal to the second output end when turned on. Alternatively, the first output unit is connected to the first node and is configured to turn on or turn off according to a potential of the first node, and output a second level signal to the second output end when turned on. The second output unit is connected to the first node and the second node and is configured to turn on or turn off according to potentials of the first node and the second node, and output a first level signal to the second output end when turned on.

2. The shift register of claim 1, wherein One or more of pulse width, pulse amplitude, and polarity of the first gate drive signal and the second gate drive signal are different. And / or, the first gate drive signal and the second gate drive signal are configured to drive transistors of different channel types.

3. The shift register of claim 2, wherein, The first gate drive signal is configured to drive a P-type transistor, and the second gate drive signal is configured to drive an N-type transistor. The second gate drive signal includes a first level signal and a second level signal, and a voltage of the first level signal is lower than a voltage of the second level signal.

4. The shift register of claim 3, wherein, The P-type transistor included in the second output module is a polysilicon transistor.

5. The shift register of claim 2, wherein, The first gate drive signal includes the first level signal and the second level signal, and the second gate drive signal includes a first level signal and a second level signal, and a voltage of the first level signal is lower than a voltage of the second level signal.

6. The shift register of claim 2, wherein, Pulses of the first gate drive signal overlap pulses of the second gate drive signal.

7. The shift register of claim 2, wherein, The first gate drive signal includes the first level signal and the second level signal, and the second gate drive signal includes a first level signal and a second level signal, and a duration of the first level signal of a pulse of the first gate drive signal is within a duration of the second level signal of a pulse of the second gate drive signal.

8. The shift register of claim 2, wherein, The pulse width of the first gate driving signal is smaller than the pulse width of the second gate driving signal.

9. The shift register of claim 2, wherein, The input signal comprises a clock signal and a start signal, the pulse width of the first gate driving signal is equal to the pulse width of the clock signal, and the pulse width of the second gate driving signal is equal to the clock period of the clock signal.

10. The shift register of claim 9, wherein, The input signal comprises a first clock signal and a second clock signal, the pulse of the first clock signal overlaps with the pulse of the start signal, and the pulse of the second clock signal overlaps with the pulse of the first gate driving signal.

11. The shift register of claim 10, wherein, The rising edge of the pulse of the first gate driving signal is aligned with the rising edge of the pulse of the second clock signal.

12. The shift register of claim 10, wherein, The rising edge of the pulse of the second gate driving signal is aligned with the rising edge of the pulse of the first clock signal.

13. The shift register of claim 10, wherein, The falling edge of the pulse of the first gate driving signal is aligned with the falling edge of the pulse of the second clock signal, and the rising edge of the pulse of the first gate driving signal is aligned with the rising edge of the pulse of the second clock signal.

14. The shift register of claim 10, wherein, The rising edge and the falling edge of the pulse of the second gate driving signal are respectively aligned with the falling edges of two adjacent pulses of the first clock signal.

15. The shift register of claim 10, wherein, The first clock signal and the second clock signal have the same frequency and different phases.

16. The shift register according to any one of claims 1 to 15, wherein The first output unit comprises a first transistor, the gate potential of the first transistor is positively correlated with the potential of the second node, or the gate potential of the first transistor is negatively correlated with the potential of the first node, or the gate of the first transistor is connected with the second node; the first pole of the first transistor is connected with a second power supply line or accesses the second level signal, and the second pole of the first transistor is connected with the second output end. And / or, the second output unit comprises a second transistor, the gate potential of the second transistor is positively correlated with the potential of the first node, or the gate potential of the second transistor is negatively correlated with the potential of the second node. The first pole of the second transistor is connected with a first power supply line or accesses the first level signal, and the second pole of the second transistor is connected with the second output end.

17. The shift register of claim 16, wherein, The second transistor is a P-type transistor.

18. The shift register of claim 16, wherein, The first transistor is a P-type transistor.

19. The shift register of claim 16, wherein, The second output unit further comprises a first capacitor, the first end of the first capacitor is connected with the gate of the second transistor, and the second end of the first capacitor is connected with the second output end.

20. The shift register of claim 1, wherein, The node voltage control module is configured to control the potential of the first node to jump from a low potential to a high potential, and the potential of the second node to jump from a high potential to a low potential, and control the potential of the first node to jump from a high potential to a low potential, and the potential of the second node to jump from a low potential to a high potential.

21. The shift register of claim 1, wherein, The node voltage control module is configured to control the potentials of the first node and the second node to be opposite.

22. The shift register of claim 16, wherein, The second output unit comprises a second transistor; the second output unit further comprises an output control subunit, the output control subunit is connected with the first node and the second node respectively, the gate of the output control subunit and the gate of the second transistor are connected with a third node, the output control subunit is used for controlling the potential of the third node according to the potentials of the first node and the second node, so that the potential of the third node is positively correlated with the potential of the first node, and the potential of the third node comprises a third level signal, and the voltage of the third level signal is lower than the voltage of the first power line.

23. The shift register of claim 22, wherein, When the potential of the second node jumps from a low potential to a high potential, the potential of the third node jumps from a high potential to a low potential; when the potential of the second node jumps from a high potential to a low potential, the potential of the third node jumps from a low potential to a high potential.

24. The shift register of claim 22, wherein, The potentials of the second node and the third node are opposite in high and low.

25. The shift register of claim 22, wherein, The potentials of the first node and the third node jump from a low potential to a high potential at the same time, and / or the potentials of the first node and the third node jump from a high potential to a low potential at the same time.

26. The shift register of claim 22, wherein, The potential of the third node further comprises a second level signal, and the voltage of the third level signal is lower than the voltage of the second level signal.

27. The shift register of claim 22, wherein, The second output unit comprises a second transistor; the voltage difference between the voltage of the third level signal and the voltage of the first power line is greater than or equal to the absolute value of the threshold voltage of the second transistor.

28. The shift register of claim 22, wherein, The output control subunit comprises a third transistor, a fourth transistor, a fifth transistor and a sixth transistor; The gate of the third transistor is connected with the first node, the first pole of the third transistor is connected with a second power line or accesses the second level signal, the second pole of the third transistor is connected with the first pole of the fifth transistor, the second pole of the fifth transistor is connected with a third power line or accesses the third level signal; the gate of the fourth transistor is connected with the second node, the first pole of the fourth transistor is connected with a second power line or accesses the second level signal, the second pole of the fourth transistor is connected with the first pole of the sixth transistor, the second pole of the sixth transistor is connected with a third power line or accesses the third level signal; the gate of the fifth transistor is connected with the second pole of the fourth transistor, and the gate of the sixth transistor is connected with the second pole of the third transistor.

29. The shift register of claim 28, wherein The voltage of the third power line is lower than the voltage of the first power line.

30. The shift register of claim 28, wherein The third transistor and the fourth transistor are P-type transistors, and the fifth transistor and the sixth transistor are N-type transistors.

31. The shift register of claim 1, wherein, The first output module comprises a third output unit and a fourth output unit, the third output unit is connected with the first node, used for turning on or turning off according to the potential of the first node, and outputting a second level signal to the first output end when turned on; The fourth output unit is connected with the second node, used for turning on or turning off according to the potential of the second node, and outputting a first level signal to the first output end at least in part of the period when turned on.

32. The shift register of claim 31, wherein, The active level of the first gate drive signal and the second gate drive signal overlap.

33. The shift register of claim 31, wherein, The active level of the first gate drive signal is a first level signal, and the active level of the second gate drive signal is a second level signal.

34. The shift register of claim 31, wherein, The inactive level of the first gate drive signal and the second gate drive signal overlap.

35. The shift register of claim 31, wherein, The third output unit includes a seventh transistor, a gate of the seventh transistor is connected with the first node, a first electrode of the seventh transistor is connected with a second power supply line or inputs a second level signal, and a second electrode of the seventh transistor is connected with the first output end.

36. The shift register of claim 31, wherein, The fourth output unit includes an eighth transistor, a gate of the eighth transistor is connected with the second node, a first electrode of the eighth transistor inputs a second clock signal, and a second electrode of the eighth transistor is connected with the first output end.

37. The shift register of claim 31, wherein, The fourth output unit further includes a second capacitor, a first end of the second capacitor is connected with the second node, and a second end of the second capacitor is connected with the first output end.

38. The shift register of claim 1, wherein, The input signal includes a first clock signal, a second clock signal and a start signal; the node voltage control module includes an input unit and a first control unit, the input unit is used for turning on or turning off according to the first clock signal, and transmitting the start signal to the second node when turned on; The first control unit is used for transmitting a first level signal or a second level signal to the first node according to the potential of the second node.

39. The shift register of claim 38, wherein, The node voltage control module further includes a second control unit, the second control unit is used for transmitting the second level signal to the second node according to the potential of the first node and the second clock signal.

40. The shift register of claim 38, wherein, The first control unit includes a second inverter.

41. The shift register of claim 38, wherein, The first clock signal, the second clock signal and the start signal respectively include alternately arranged first level pulses and second level pulses, the first level pulse of the start signal overlaps with the first level pulse of the first clock signal, and does not overlap with the first level pulse of the second clock signal.

42. The shift register of claim 38, wherein, The first level pulse of the start signal is one or more, and the first level pulses of the first clock signal and the second clock signal are respectively multiple; The first output module includes a third output unit and a fourth output unit, the third output unit includes a seventh transistor, a gate of the seventh transistor is connected with the first node, a first electrode of the seventh transistor is connected with a second power supply line or inputs a second level signal, and a second electrode of the seventh transistor is connected with the first output end; the fourth output unit includes an eighth transistor, a gate of the eighth transistor is connected with the second node, a first electrode of the eighth transistor inputs a second clock signal, and a second electrode of the eighth transistor is connected with the first output end.

43. The shift register of claim 39, wherein, The input unit includes a ninth transistor, a gate of the ninth transistor inputs a first clock signal, a first electrode of the ninth transistor inputs a start signal, and a second electrode of the ninth transistor is connected with a second node.

44. The shift register of claim 43, wherein, The shift register further comprises a tenth transistor, a second electrode of the ninth transistor being connected to the second node through the tenth transistor; a gate electrode of the tenth transistor being connected to a first power supply line or inputting a first level signal.

45. The shift register of claim 43, wherein, The first control unit comprises an eleventh transistor and a twelfth transistor, a gate electrode of the eleventh transistor being connected to the second electrode of the ninth transistor or the second node, a first electrode of the eleventh transistor being connected to a second power supply line or inputting a second level signal, and a second electrode of the eleventh transistor being connected to the first node; a gate electrode of the twelfth transistor being connected to the second electrode of the ninth transistor or the second node, a first electrode of the twelfth transistor being connected to the first power supply line or inputting the first level signal, and a second electrode of the twelfth transistor being connected to the first node; The second control unit comprises a thirteenth transistor and a fourteenth transistor, a first electrode of the thirteenth transistor being connected to the second power supply line or inputting the second level signal, a second electrode of the thirteenth transistor being connected to a first electrode of the fourteenth transistor, a second electrode of the fourteenth transistor being connected to the second electrode of the ninth transistor or the second node, and one of a gate electrode of the thirteenth transistor and a gate electrode of the fourteenth transistor being connected to the first node, and the other being inputted with a second clock signal.

46. The shift register of claim 45, wherein, The gate electrode of the thirteenth transistor is connected to the first node, and the gate electrode of the fourteenth transistor is inputted with the second clock signal.

47. The shift register of claim 45, wherein, The eleventh transistor is a P-type transistor, and the twelfth transistor is an N-type transistor.

48. A shift register, comprising: The node voltage control module is configured to control voltages of the first node and the second node according to an input signal. The first output module is configured to output a first gate drive signal through a first output end according to the voltages of the first node and the second node, and the second output module is configured to output a second gate drive signal through a second output end according to the voltage of the first node and / or the voltage of the second node, the first gate drive signal being different from the second gate drive signal. The second output module comprises a first output unit and a second output unit, the first output unit being connected to the second node and configured to be turned on or turned off according to a potential of the second node, and outputting a second level signal to the second output end when turned on. Alternatively, the first output unit is connected to the first node and configured to be turned on or turned off according to a potential of the first node, and outputting a second level signal to the second output end when turned on. The second output unit comprises a second transistor. The second output unit is connected to the first node or the second node and configured to be turned on or turned off according to a potential of the first node or the second node, and outputting a first level signal to the second output end when turned on. ​ The second output unit further comprises an output control subunit, The output control subunit comprises a first inverter, an input end of the first inverter being connected with the second node, an output end of the first inverter being connected with a gate of the second transistor to a third node; a first end of the first inverter being connected with a second power supply line or being connected with the second level signal, the output control subunit being used for controlling a potential of the third node according to a potential of the second node; a second end of the first inverter being connected with a third power supply line or being connected with a third level signal; Alternatively, the output control subunit comprises M first inverters; M is an odd number greater than 1, an input end of the first first inverter being connected with the second node, an output end of the i-th first inverter being connected with an input end of the (i+1)-th first inverter, an output end of the M-th first inverter being connected with the gate of the second transistor to the third node; i is an integer greater than or equal to 1 and less than or equal to M; The output control subunit is used for controlling the potential of the third node according to the potential of the second node; Alternatively, M is an even number greater than or equal to 2; an input end of the first first inverter being connected with the first node, an output end of the i-th first inverter being connected with an input end of the (i+1)-th first inverter, an output end of the M-th first inverter being connected with the gate of the second transistor to the third node; the output control subunit being used for controlling the potential of the third node according to the potential of the first node; The first end of the first inverter is connected with the second power supply line or the second level signal, and the second end of the M-th first inverter is connected with the third power supply line or the third level signal.

49. The shift register of claim 48, wherein, The second end of at least one of the first inverters is connected with the first power supply line or the first level signal; or, the second end of all the first inverters is connected with the third power supply line or the third level signal.

50. The shift register of claim 49, wherein, The voltage of the third power supply line is lower than the voltage of the first power supply line.

51. The shift register of claim 49, wherein, The potential of the third node comprises a third level signal, and the voltage of the third level signal is lower than the voltage of the first power supply line.

52. The shift register of claim 48, wherein, When the potential of the second node jumps from a low potential to a high potential, the potential of the third node jumps from a high potential to a low potential; when the potential of the second node jumps from a high potential to a low potential, the potential of the third node jumps from a low potential to a high potential.

53. The shift register of claim 48, wherein, The potentials of the second node and the third node are opposite to each other.

54. The shift register of claim 48, wherein, The potentials of the first node and the third node jump from a low potential to a high potential at the same time, and / or the potentials of the first node and the third node jump from a high potential to a low potential at the same time.

55. The shift register of claim 48, wherein, The potential of the third node further comprises a second level signal, and the voltage of the third level signal is lower than the voltage of the first level signal.

56. The shift register of claim 49, wherein, The absolute value of the voltage difference between the third level signal and the voltage of the first power supply line is greater than or equal to the absolute value of the threshold voltage of the second transistor.

57. The shift register of claim 48, wherein, The first inverter comprises a fifteenth transistor and a sixteenth transistor, a gate of the fifteenth transistor and a gate of the sixteenth transistor are connected with an input end of the first inverter, a first pole of the fifteenth transistor is connected with a first end of the first inverter, a second pole of the fifteenth transistor and a first pole of the sixteenth transistor are connected with an output end of the first inverter, and a second pole of the sixteenth transistor is connected with a second end of the first inverter.

58. The shift register of claim 57, wherein, The fifteenth transistor is an N-type transistor, and the sixteenth transistor is a P-type transistor.

59. The shift register of claim 48, wherein, One or more of a pulse width, a pulse amplitude, and a positive or negative polarity of the pulse amplitude of the first gate drive signal and the second gate drive signal are different. And / or, the first gate drive signal and the second gate drive signal are used to drive transistors of different channel types.

60. The shift register of claim 48, wherein, The input signal comprises a first clock signal, a second clock signal, and a start signal; the node voltage control module comprises an input unit and a first control unit, the input unit is used to turn on or turn off according to the first clock signal, and transmit the start signal to the second node when turned on; The first control unit is used to transmit a first level signal or a second level signal to the first node according to a potential of the second node.

61. The shift register of claim 60, wherein, The node voltage control module further comprises a second control unit, and the second control unit is used to transmit the second level signal to the second node according to a potential of the first node and the second clock signal.

62. The shift register of claim 60, wherein, The first control unit comprises a second inverter.

63. The shift register of claim 60, wherein, The first clock signal, the second clock signal, and the start signal respectively comprise first level pulses and second level pulses arranged alternately, the first level pulse of the start signal overlaps with the first level pulse of the first clock signal, and does not overlap with the first level pulse of the second clock signal.

64. The shift register of claim 60, wherein, The first level pulse of the start signal is one or more, and the first level pulses of the first clock signal and the second clock signal are respectively multiple; The first output module comprises a third output unit and a fourth output unit, the third output unit comprises a seventh transistor, a gate of the seventh transistor is connected with the first node, a first pole of the seventh transistor is connected with a second power supply line or accesses a second level signal, and a second pole of the seventh transistor is connected with the first output end; the fourth output unit comprises an eighth transistor, a gate of the eighth transistor is connected with the second node, a first pole of the eighth transistor accesses a second clock signal, and a second pole of the eighth transistor is connected with the first output end.

65. A gate drive circuit, comprising: A plurality of shift registers according to any one of claims 1-64 are cascaded; A start signal input end of an (n+1)th shift register is connected with a first output end of an nth shift register, wherein n is a positive integer greater than or equal to 1.

66. A display panel comprising: The gate drive circuit comprises a pixel circuit and the gate drive circuit of claim 65, The pixel circuit comprises a plurality of transistors, and the first output end and the second output end of the shift register are connected with transistors of different channel types in the pixel circuit.

67. The display panel of claim 66, wherein, The pixel circuit comprises a driving transistor, a data writing transistor and a compensation transistor, the data writing transistor is connected between a data line and a first electrode of the driving transistor, and the compensation transistor is connected between a second electrode and a gate electrode of the driving transistor; a gate electrode of the data writing transistor is connected with the first output end, and a gate electrode of the compensation transistor is connected with the second output end.

68. The display panel of claim 67, wherein, The channel type of the data writing transistor is P channel, and the channel type of the compensation transistor is N channel.

69. The display panel of claim 67, wherein, The pixel circuit further comprises a first light emitting control transistor and a second light emitting control transistor, the first light emitting control transistor is connected between a fourth power supply line and the first electrode of the driving transistor; the second light emitting control transistor is connected between the second electrode of the driving transistor and a first electrode of a light emitting device, and a second electrode of the light emitting device is connected with a fifth power supply line. Gate electrodes of the first light emitting control transistor and the second light emitting control transistor are connected with a light emitting control signal line.

70. The display panel of claim 67, wherein, The pixel circuit further comprises a first initialization transistor, a gate electrode of the first initialization transistor is connected with a first scanning line, a first electrode of the first initialization transistor is connected with a first initialization signal line, and a second electrode of the first initialization transistor is connected with a gate electrode or a second electrode of the driving transistor.

71. The display panel of claim 69, wherein, The pixel circuit further comprises a second initialization transistor, a gate electrode of the second initialization transistor is connected with a second scanning line, a first electrode of the second initialization transistor is connected with a second initialization signal line, and a second electrode of the second initialization transistor is connected with a first electrode of the light emitting device.

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