drive circuit

Abstract

This application relates to a driving circuit, which includes a control module, a first output module, and a second output module. The second output module includes a first output submodule and a first control submodule. The control module is connected to both the first output module and the first output submodule, and is also connected to the first control submodule. The first control submodule is also connected to the first output submodule. The control module is used to control the first output module to output a first signal under the control of a first input signal, a clock signal, and a first control signal, and to control the second output module to output a second signal under the control of the first input signal, the clock signal, the first control signal, and the second control signal, together with the first control submodule. The first signal and the second signal have different frequencies. The driving circuit provided by this application can simultaneously output two signals of different frequencies without adding an additional signal, thereby increasing the size of the bezel.

Description

Technical Field

[0001] This application relates to the field of circuit technology, and in particular to a driving circuit. Background Technology

[0002] OLED (Organic Light Emitting Diode) displays can reduce power consumption in low-frequency displays. In OLED display processes, the display module is typically divided into write frames and hold frames. Write frames are used for data writing and storage, while hold frames do not write data; instead, they control light emission through stored signals. Therefore, in hold frames, some signals are converted from AC clock signals to DC clock signals.

[0003] To ensure proper display, additional control or clock signals are required. Traditionally, this is achieved by adding extra signal generation circuitry, which increases the size of the display panel bezel. Summary of the Invention

[0004] Therefore, it is necessary to provide a driving circuit to address the aforementioned technical problems.

[0005] In a first aspect, one embodiment of this application provides a driving circuit, including: a control module, a first output module and a second output module, wherein the second output module includes a first output submodule and a first control submodule; the control module is connected to both the first output module and the first output submodule, and is also connected to the first control submodule, wherein the first control submodule is also connected to the first output submodule;

[0006] The control module is used to control the first output module to output a first signal under the control of the first input signal, the clock signal, and the first control signal, and to control the second output module to output a second signal under the control of the first input signal, the clock signal, the first control signal, and the second control signal, together with the first control submodule; the first signal and the second signal have different frequencies.

[0007] Secondly, one embodiment of this application provides a driving circuit, including a control module, a first output module, and a second output module. The second output module includes a fifth output unit and a sixth output unit. The control module is connected to both the first output module and the fifth output unit, the first output module is connected to the sixth output unit, and the fifth output unit is connected to the sixth output unit.

[0008] The control module is used to control the first output module to output a first signal and the second output module to output a second signal under the control of the first input signal, the second input signal, the first control signal and the clock signal. The first signal and the second signal have different frequencies.

[0009] Thirdly, one embodiment of this application provides a driving circuit, including: a control module, a first output module, and a second output module, wherein the second output module includes a second output submodule and a third control submodule; the control module is connected to both the first output module and the second output submodule, and the second output submodule is also connected to both the first output module and the third control submodule;

[0010] The control module is used to control the first output module to output a first signal under the control of the first input signal, the clock signal and the first control signal, and to control the second output module to output a second signal under the control of the first input signal, the first control signal and the clock signal, together with the third control submodule; the first signal and the second signal have different frequencies.

[0011] Fourthly, one embodiment of this application provides a scanning driving circuit, including multiple cascaded driving circuits of any one of the driving circuits provided in the first aspect, the second aspect, and the third aspect; the output signal of the first output module of the preceding driving circuit is the input signal of the following driving circuit.

[0012] This application provides a driving circuit including a control module, a first output module, and a second output module. The second output module includes a first output submodule and a first control submodule. The control module is connected to both the first output module and the first output submodule, and is also connected to the first control submodule. The first control submodule is also connected to the first output submodule. The control module is used to control the first output module to output a first signal under the control of a first input signal, a clock signal, and a first control signal, and to control the second output module to output a second signal under the control of the first input signal, the clock signal, the first control signal, and the second control signal, together with the first subcontrol module. The first signal and the second signal have different frequencies. The driving circuit provided in this embodiment includes two output modules (a first output module and a second output module). Under the control of the first input signal, the clock signal, the first control signal, and the second control signal, the control module can control the two output modules to output a first signal and a second signal with different frequencies, respectively. This allows for resetting the transistor source potential in the low-frequency pixel circuit without adding an additional signal generation circuit to generate additional control signals or clock signals, thereby improving the low-frequency display effect. Furthermore, it does not increase the size of the display panel bezel. Attached Figure Description

[0013] Figure 1 A schematic diagram of a display circuit provided for one embodiment;

[0014] Figure 2 A schematic diagram of the output current provided for one embodiment;

[0015] Figure 3 A schematic diagram of a display circuit provided for another embodiment;

[0016] Figure 4 A schematic diagram of the output current provided for another embodiment;

[0017] Figure 5 A schematic diagram of the drive circuit provided in one embodiment;

[0018] Figure 6 A schematic diagram of the drive circuit provided for another embodiment;

[0019] Figure 7 A schematic diagram of the drive circuit provided for another embodiment;

[0020] Figure 8 A timing diagram of a driving circuit provided for one embodiment;

[0021] Figure 9 A waveform diagram of the output signal of a drive circuit provided in one embodiment;

[0022] Figure 10 A schematic diagram of the drive circuit provided for another embodiment;

[0023] Figure 11 A timing diagram of the drive circuit provided for another embodiment;

[0024] Figure 12 A schematic diagram of the drive circuit provided for another embodiment;

[0025] Figure 13 A timing diagram of the drive circuit provided for another embodiment;

[0026] Figure 14 A waveform diagram of the output signal of the drive circuit provided in another embodiment;

[0027] Figure 15 A schematic diagram of a scan drive circuit provided for one embodiment;

[0028] Figure 16 A schematic diagram of a scan drive circuit provided for another embodiment;

[0029] Figure 17 A schematic diagram of a pixel circuit provided for one embodiment;

[0030] Figure 18 A timing diagram of a pixel circuit provided for one embodiment;

[0031] Figure 19A schematic diagram of the layout of a drive circuit provided for one embodiment;

[0032] Figure 20 A schematic diagram of the layout of the drive circuit provided for another embodiment;

[0033] Figure 21 A timing diagram of the drive circuit provided for another embodiment;

[0034] Figure 22 A schematic diagram of the drive circuit provided for another embodiment;

[0035] Figure 23 A timing diagram of the drive circuit provided for another embodiment;

[0036] Figure 24 A schematic diagram of a scan drive circuit provided for another embodiment.

[0037] Explanation of reference numerals in the attached figures:

[0038] 10. Drive circuit; 20. Drive circuit; 30. Drive circuit; 100. Control module; 200. First output module; 300. Second output module; 310. First output submodule; 320. First control submodule; 311. First output unit; 312. Second output unit; 210. Third output unit; 220. Fourth output unit; 110. Input submodule; 120. Second control submodule; 330. Fifth output unit; 340. Sixth output unit; 350. Second output submodule; 360. Third control submodule. Detailed Implementation

[0039] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0040] The serial numbers assigned to components in this article, such as "first" and "second", are used only to distinguish the objects being described and have no sequential or technical meaning.

[0041] First, before introducing the technical solutions of the embodiments disclosed in this application, the background technology or technological evolution on which the embodiments of this application are based will be introduced. In the OLED (Organic Light Emitting Diode) display industry, the pursuit of image quality has never stopped, and screen refresh rates have repeatedly broken new records. In addition, screen power consumption reduction is also ongoing, with breakthroughs in low-frequency displays and continuous reductions in screen logic power consumption. In the OLED display process, the display module is typically divided into write frames and hold frames. Write frames are used for data writing and storage, while in hold frames, no data is written; the stored signals control the pixel units to emit light. Therefore, in hold frames, some signals are converted from AC clock signals to DC signals, reducing the power consumption of the control chip (IC) and the screen. Conventionally, as... Figure 1 The 7T1C display circuit shown exhibits a brightness variation, i.e., screen flickering, during low-frequency display when the output transistor is subjected to prolonged differential pressure. This difference in output current between the write and hold frames causes variations in brightness. Figure 2 As shown. The low-frequency display circuit 8T1C is as follows. Figure 3 As shown, or other circuits with transistor source reset functionality, offer better display performance at low frequencies. By continuously resetting the potential of the output transistor source, the output current of the write frame and the hold frame are kept consistent, such as... Figure 4 As shown. Since the timing of the low-frequency pixel circuit is divided into write frames and hold frames, additional control signals or clock signals are needed to reset the source voltage of the transistors. This is to prevent differences in current output between write frames and hold frames under long-term low-frequency stress, which could lead to brightness differences between different frames. However, the operating states of the control signals and clock signals for write frames and hold frames are inconsistent. For example, during a write frame, all clock signals of the pixel circuit are AC signals; during a hold frame, the clock signal controlling the data writing of the pixel circuit is changed to a continuous high-potential DC signal. The additional clock signal still needs to output an AC signal to reset the transistor stress state, which means the additional control signal clock signal cannot be shared with the original signal. Traditional technology adds an additional driving circuit to output the new clock signal or control signal. However, this increases the bezel size of the display panel, which is not conducive to the trend of narrow bezels, causing insufficient space or compressing the line width and spacing, increasing impedance and power consumption. To address this, this application provides a driving circuit.

[0042] The technical solution of this application and how the technical solution of this application solves the technical problem are described in detail below with specific embodiments.

[0043] In one embodiment, such as Figure 5As shown, a driving circuit 10 is provided, including a control module 100, a first output module 200, and a second output module 300; the second output module 300 includes a first output submodule 310 and a first control submodule 320; the control module 100 is connected to both the first output module 200 and the first output submodule 310, and is also connected to the first control submodule 320, which is also connected to the first output submodule 310.

[0044] The control module 100 is used to control the first output module 200 to output a first signal under the control of the first input signal, the clock signal, and the first control signal, and to control the second output module 300 to output a second signal under the control of the first input signal, the clock signal, the first control signal, and the second control signal, together with the first control submodule 320; the first signal and the second signal have different frequencies.

[0045] The control module 100 includes a first terminal, a second terminal, and a third terminal. The first output submodule 310 includes two control terminals, and the first control submodule 320 includes a first terminal and a second terminal. The first terminal of the control module 100 is connected to the first output module 200. The second terminal of the control module 100 is connected to one control terminal of the first output submodule 310. The third terminal of the control module 100 is connected to the first terminal of the first control submodule 320. The other control terminal of the first output submodule 310 is connected to the second terminal of the first control submodule 320.

[0046] The first input signal, clock signal, first control signal, and second control signal can all be periodic pulse signals. Multiple clock signals can be input to the control module 100. After inputting the first input signal, clock signal, and first control signal into the control module 100, the control module 100 controls the first output module 200 to output the first signal (out1), and simultaneously inputs the second control signal to the first control submodule 320, so that the control module 100 and the first control submodule 320 simultaneously control the second output module 300 to output the second signal (out2). That is, the drive circuit 10 includes two output terminals, which respectively output the first signal and the second signal. Through the control of the control module 100 and the first control submodule 320, the frequencies of the output first signal and the second signal are different. This embodiment does not limit the specific structure of the control module 100, the first output module 200, the first output submodule 310, and the first control submodule 320, as long as their functions can be achieved.

[0047] In other words, during the write frame, the control module 100 controls the first output module 200 to input a first signal to the pixel circuit via the input first input signal, clock signal, and first control signal. During the hold frame, the control module 100 and the first control submodule 320 control the second output module 300 to input a second signal to the pixel circuit via the input first input signal, clock signal, first control signal, and second control signal, thus enabling the write frame and hold frame to output signals of different frequencies.

[0048] The driving circuit 10 provided in this embodiment includes a control module 100, a first output module 200, and a second output module 300. The second output module 300 includes a first output submodule 310 and a first control submodule 320. The control module 100 is connected to both the first output module 200 and the first output submodule 310, and is also connected to the first control submodule 320. The first control submodule 320 is also connected to the first output submodule 310. The control module 100 is used to control the first output module 200 to output a first signal under the control of a first input signal, a clock signal, and a first control signal, and to control the second output module 300 to output a second signal under the control of the first input signal, the clock signal, the first control signal, and the second control signal, together with the first control submodule 320. The first signal and the second signal have different frequencies. The driving circuit 10 provided in this embodiment includes two output modules (a first output module 200 and a second output module 300). Under the control of a first input signal, a clock signal, a first control signal, and a second control signal, the control module 100 can control the two output modules to output first and second signals with different frequencies respectively. This allows for the resetting of the transistor source potential in the low-frequency pixel circuit without adding an additional signal generation circuit to generate additional control or clock signals, thus improving the low-frequency display effect. Furthermore, it does not increase the size of the display panel bezel.

[0049] In one embodiment, such as Figure 6 As shown, the first output submodule 310 includes a first output unit 311 and a second output unit 312; the first end of the first output unit 311 is connected to the control module 100, the second end of the first output unit 311 is used to input a high potential, the first end of the second output unit 312 is connected to the first control submodule 320, the second end of the second output unit 312 is used to input a first clock signal, and the third end of the first output unit 311 is connected to the third end of the second output unit 312.

[0050] The first output unit 311 includes a first terminal, a second terminal, and a third terminal, and the second output unit 312 also includes a first terminal, a second terminal, and a third terminal. The first terminal of the first output unit 311 serves as a control terminal of the first output submodule 310 and is connected to the control module 100. The second terminal of the first output unit 311 is used to input a high potential VGH, and the third terminal of the first output unit 311 is connected to the third terminal of the second output unit 312. The first terminal of the second output unit 312 serves as another control terminal of the first output submodule 310 and is connected to the first control submodule 320, and the second terminal of the second output unit 312 is used to input a first clock signal.

[0051] Under the control of the first input signal, the first clock signal, the first control signal, and the second control signal, the control module 100 and the first control submodule 320 control the first output unit 311 and the second output unit 312 to jointly output the second signal. This embodiment does not limit the specific structure of the first output unit 311 and the second output unit 312, as long as their functions can be achieved.

[0052] In this embodiment, the first output submodule 310 includes a first output unit 311 and a second output unit 312, and the structure of such a first output submodule 310 is simple.

[0053] Please continue reading Figure 6 In one embodiment, the first output unit 311 includes a first transistor T1, and the second output unit 312 includes a first capacitor C1 and a second transistor T2.

[0054] The first terminal of the first transistor T1 is connected to the control module 100, the second terminal of the first transistor T1 is used to input a high potential VGH, and the third terminal of the first transistor T1 is connected to the third terminal of the second output unit 312.

[0055] The first terminal of the first capacitor C1 is connected to the first control submodule 320, the second terminal of the first capacitor C1 is connected to the third terminal of the second output unit 312, the first terminal of the second transistor T2 is connected to the first terminal of the first capacitor C1, the second terminal of the second transistor T2 is used to input the first clock signal SCK1, and the third terminal of the second transistor T2 is connected to the second terminal of the first capacitor C1.

[0056] The first terminal (control terminal) of the first transistor T1 is connected to the control module 100 as the first terminal of the first output unit 311. The second terminal of the first transistor T1 is used to input a high potential VGH. The third terminal of the first transistor T1 is connected to the third terminal of the second output unit 312 as the third terminal of the first output unit 311.

[0057] The first terminal of the first capacitor C1 is connected to the first control submodule 320 as the first terminal of the second output unit 312. The second terminal of the first capacitor C1 is connected to the third terminal of the second output unit 312, that is, it is also connected to the third terminal of the first output unit 311. The first terminal of the second transistor T2 is connected to the first terminal of the first capacitor C1, that is, it is also connected to the first control submodule 320. The second terminal of the second transistor T2 is used to input the first clock signal SCK1. The third terminal of the second transistor T2 is connected to the second terminal of the first capacitor C1, that is, it is also connected to the third terminal of the first output unit 311. The first capacitor C1 is used to store signals and discharges to provide signals to the second transistor T2 when the first control submodule 320 is open-circuited.

[0058] In this embodiment, the first output unit 311 includes a first transistor T1, and the second output unit 312 includes a first capacitor C2 and a second transistor T1. The structure of such a first output unit 311 and second output unit 312 is simple, and the capacitor and transistor are readily available, resulting in low cost and improved practicality of the drive circuit 10.

[0059] Please continue reading Figure 6 In one embodiment, the first control submodule 320 includes: a third transistor T3; the first terminal of the third transistor T3 is used to input the second control signal SW2, the second terminal of the third transistor T3 is connected to the control module 100, and the third terminal of the third transistor T3 is connected to the first output submodule 310.

[0060] The second terminal of the third transistor T3 is connected to the control module 100 as the first terminal of the first control submodule 320, and the third terminal of the third transistor T3 is connected to the first output submodule 310 as the second terminal of the first control submodule 320. The third transistor T3 is turned on or off under the control of the second control signal SW2, and together with the control module 100, controls the first output submodule 310 to output the second signal.

[0061] In this embodiment, the first control submodule 320 includes a third transistor T3. The first control submodule 320 has a simple structure, and the third transistor T3 is readily available and inexpensive, making the drive circuit 10 more practical.

[0062] Please continue reading Figure 6In one embodiment, the first output module 200 includes a third output unit 210 and a fourth output unit 220; the first terminal of the third output unit 210 is connected to the control module 100, the second terminal of the third output unit 210 is used to input a high potential VGH, the first terminal of the fourth output unit 220 is connected to the control module 100, the second terminal of the fourth output unit 220 is used to input a first clock signal SCK1, and the third terminal of the fourth output unit 220 is connected to the third terminal of the third output unit 210.

[0063] The first terminals of the third output unit 210 and the fourth output unit 220 are both connected to the control module 100 to receive control signals transmitted by the control module 100. The second terminal of the third output unit 210 is used to input a high potential VGH, and the second terminal of the fourth output unit 220 is used to input a first clock signal. The third terminals of the third output unit 210 and the fourth output unit 220 are connected, meaning that the third terminals of the third output unit 210 and the fourth output unit 220 serve as output terminals of the first output module 200, outputting a first signal. This embodiment does not limit the specific structure of the third output unit 210 and the fourth output unit 220, as long as their functions can be achieved.

[0064] In this embodiment, the first output module 200 includes a third output unit 210 and a fourth output unit 220. The first output module 200 has a simple structure and is easy to implement.

[0065] Please continue reading Figure 6 The third output unit 210 includes a second capacitor C2 and a fourth transistor T4, and the fourth output unit 220 includes a third capacitor C3 and a fifth transistor T5.

[0066] The first terminal of the second capacitor C2 is connected to the control module 100, the second terminal of the second capacitor C2 is used to input a high potential VGH, the first terminal of the fourth transistor T4 is connected to the first terminal of the second capacitor C2, the second terminal of the fourth transistor T4 is used to input a high potential VGH, and the third terminal of the fourth transistor T4 is connected to the third terminal of the fourth output unit 220.

[0067] The first terminal of the third capacitor C3 is connected to the control module 100, the second terminal of the third capacitor C3 is connected to the third terminal of the third output unit 210, the first terminal of the fifth transistor T5 is connected to the first terminal of the third capacitor C3, the second terminal of the fifth transistor T5 is used to input the first clock signal SCK1, and the third terminal of the fifth transistor T5 is connected to the second terminal of the third capacitor C3.

[0068] The first terminal of the second capacitor C2 is connected to the control module 100 as the first terminal of the third output unit 210. The second terminal of the second capacitor C2 is used as the second terminal of the third output unit 210 for inputting a high potential VGH and is also connected to the second terminal of the fourth transistor T4, meaning the second terminal of the fourth transistor T4 is also used for inputting a high potential VGH. The first terminal (control terminal) of the fourth transistor T4 is connected to the first terminal of the second capacitor C2, i.e., connected to the control module 100. The control signal input by the control module 100 to the fourth transistor T4 can control the on / off state of the fourth transistor T4. The third terminal of the fourth transistor T4 is connected to the third terminal of the fourth output unit 220 as the third terminal of the third output unit 210. The second capacitor C2 is used to store signals so that it can discharge to provide signals to the fourth transistor T4 when the control module 100 does not input control signals to the fourth transistor T4.

[0069] The first terminal of the third capacitor C3 is connected to the control module 100 as the first terminal of the fourth output unit 220, and the second terminal of the third capacitor C3 is connected to the third terminal of the third output unit 210 as the third terminal of the fourth output unit 220. The first terminal (control terminal) of the fifth transistor T5 is connected to the first terminal of the third capacitor C3, that is, it is also connected to the control module 100. The control signal input by the control module 100 to the fifth transistor T5 can control the on / off state of the fifth transistor T5. The second terminal of the fifth transistor T5 is used to input the first clock signal SCK1. When the fifth transistor T5 is turned on, the first clock signal SCK1 can be output through the fifth transistor T5. The third terminal of the fifth transistor T5 is connected to the second terminal of the third capacitor C3, that is, it is also connected to the third terminal of the third output unit 210. The third capacitor C3 is used to store signals so that it can discharge to provide signals to the fifth transistor T5 when the control module 100 does not input control signals to the fifth transistor T5.

[0070] In this embodiment, the third output unit 210 includes a second capacitor C2 and a fourth transistor T2, and the fourth output unit 220 includes a third capacitor C3 and a fifth transistor T5. Such third output units 210 and fourth output units 220 have simple structures, and the capacitors and transistors are readily available, resulting in low cost and improved practicality of the drive circuit 10.

[0071] In one embodiment, such as Figure 7 As shown, the control module 100 includes an input submodule 110 and a second control submodule 120. The first terminal of the input submodule 110 is used to input the second clock signal SCK2, the second terminal of the input submodule 110 is used to input the first input signal SIN1, and the third terminal of the input submodule 110 is connected to the input terminal of the second control submodule 120.

[0072] The control terminal of the second control submodule 120 is used to input the first clock signal SCK1, the second clock signal SCK2, the first control signal SW1 and the high potential VGH. The output terminal of the second control submodule 120 is connected to the first output module 200, the first output submodule 310 and the first control submodule 320.

[0073] The input submodule 110 includes a first terminal, a second terminal, and a third terminal, and the second control submodule 120 includes an input terminal, a control terminal, and an output terminal. The first terminal of the input submodule 110 is used to input the second clock signal SCK2, the second terminal is used to input the first input signal SIN1, and the third terminal is connected to the input terminal of the second control submodule 120. The control terminal of the second control submodule 120 is used to input the first clock signal SCK1, the second clock signal SCK2, the first control signal SW1, and the high potential VGH required for control. The output terminal of the second control submodule 120 is connected to the first output module 200, the first output submodule 310, and the first control submodule 320.

[0074] The second control submodule 120, under the control of the first clock signal SCK1, the second clock signal SCK2, the first control signal SW1, the second control signal SW2, the high potential VGH, and the first input signal SIN1 input through the input submodule 110, jointly controls the first output module 200 to output the first signal and the second output module 300 to output the second signal, together with the first control submodule 320. This embodiment does not limit the specific structure of the input submodule 110 and the second control submodule 120, as long as their functions can be achieved.

[0075] In this embodiment, the control module 100 includes an input submodule 110 and a second control submodule 120. That is, through the joint control of the input submodule 110 and the second control submodule 120, the first output module 200 and the second output module 300 respectively output a first signal and a second signal. Such a control module 100 has a simple structure and is easy to implement, making the drive circuit 10 highly practical.

[0076] Please continue reading Figure 7 In one embodiment, the input submodule 110 includes at least one sixth transistor T6, the first terminal of the sixth transistor T6 is used to input a second clock signal SCK2, the second terminal of the sixth transistor T6 is used to input a first input signal SIN1, and the third terminal of the sixth transistor T6 is connected to the first terminal of the second control submodule 120.

[0077] The input submodule 110 may include one sixth transistor T6, or multiple sixth transistors T6. When the input submodule 110 includes one sixth transistor T6, the first terminal of the sixth transistor T6 serves as the first terminal of the input submodule 110 for inputting the second clock signal SCK2, the second terminal of the sixth transistor T6 serves as the second terminal of the input submodule 110 for inputting the first input signal SIN1, and the third terminal of the sixth transistor T6 serves as the third terminal of the input submodule 110 connected to the first terminal of the second control submodule 120.

[0078] When the input submodule 110 includes multiple sixth transistors T6, the first terminals of the multiple sixth transistors T6 are all used to input the second clock signal SCK2. The multiple sixth transistors T6 are cascaded, that is, the second terminal of the first sixth transistor T6 is used to input the first input signal SIN1, the third terminal of the first sixth transistor T6 is connected to the second terminal of the second sixth transistor T6, the third terminal of the second sixth transistor T6 is connected to the second terminal of the third sixth transistor T6, and so on, and the third terminal of the last sixth transistor T6 is connected as the third terminal of the input submodule 110 to the first terminal of the second control submodule 120.

[0079] In this embodiment, the input submodule 110 includes at least one sixth transistor T6. The input submodule 110 has a simple structure, and the transistors are readily available and inexpensive, which makes the driving circuit 10 more practical.

[0080] Please continue reading Figure 7 The second control submodule 120 includes: a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, and an eleventh transistor T11; the first terminal of the seventh transistor T7 is connected to the third terminal of the input submodule 110, the second terminal of the seventh transistor T7 is used to input the first clock signal SCK1, and the third terminal of the seventh transistor T7 is connected to the first terminal of the eighth transistor T8.

[0081] The second terminal of the eighth transistor T8 is used to input a high potential VGH. The third terminal of the eighth transistor T8 is connected to the first terminal of the ninth transistor T9. The second terminal of the ninth transistor T9 is used to input the second clock signal SCK2. The third terminal of the ninth transistor T9 is connected to the first terminal of the tenth transistor T10. The second terminal of the tenth transistor T10 is used to input the first control signal SW1. The third terminal of the tenth transistor T10 is connected to the first output module 200.

[0082] The first terminal of the eleventh transistor T11 is connected to the third terminal of the eighth transistor T8. The second terminal of the eleventh transistor T11 is used to input the second clock signal SCK2, and the third terminal of the eleventh transistor T11 is used to input the low potential VGL.

[0083] The second control submodule 120 includes multiple transistors, namely, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, and an eleventh transistor T11. The second control submodule 120 controls the on / off state of each transistor through a first input signal, a first clock signal, a second clock signal, and a first control signal, so that each transistor inputs a control signal to the first output module 200 and the second output module 300, causing the first output module 200 and the second output module 300 to output a first signal and a second signal, respectively.

[0084] In this embodiment, the second control submodule 120 includes multiple transistors, which have a simple structure and are easy to obtain and have low cost, thereby improving the practicality of the drive circuit 10.

[0085] In one embodiment, a driving method applied to the driving circuit 10 described above is provided, the method comprising:

[0086] Under the control of the first input signal, the first clock signal, the second clock signal, the first control signal, and the second control signal, the first output module is controlled to output the first signal and the second output module is controlled to output the second signal; the first signal and the second signal have different frequencies.

[0087] In this system, the low-level pulse signal in each cycle of the first input signal corresponds to the low-level pulse signal in the second clock signal, and the low-level pulse signal in each cycle of the first input signal corresponds to the high-level pulse signal in the first clock signal; the first control signal is a low-level signal, and the second control signal changes from low level to high level when the low-level pulse signal is triggered in the second cycle of the first input signal.

[0088] The timing diagram of the first input signal, the first clock signal, the second clock signal, the first control signal, the second control signal, the first signal output by the first output module, and the second signal output by the second output module is as follows: Figure 8 As shown. Figure 8The diagram shows the pulse waveforms of the first clock signal, the second clock signal, the first control signal, and the second control signal during two cycles of the first input signal. During the first cycle of the first input signal (i.e., the write frame of the display module), both the first and second control signals are low-level pulse signals. The low-level pulse signal of the first input signal corresponds to the low-level pulse signal of the second clock signal and the high-level pulse signal of the first clock signal. During the second cycle of the first input signal (i.e., the hold frame of the display module), the first control signal is a low-level pulse signal. The second control signal changes from low to high when the first input signal triggers a low-level pulse signal and remains high. The low-level pulse signal of the first input signal corresponds to the low-level pulse signal of the second clock signal and the high-level pulse signal of the first clock signal.

[0089] In such Figure 8 As shown in the timing diagram, Figure 7 The operation of the drive circuit 10 shown is as follows:

[0090] In stage ①, the first input signal is low, the second clock signal is low, the first clock signal is high, and both the first and second control signals are low. At this time, the sixth transistor T6 is on, the seventh transistor T7 is off, the eighth transistor T8 is on, the ninth transistor T9 is on, the tenth transistor T10 is on, the eleventh transistor T11 is on, the fourth transistor T4 is on, and the fifth transistor T5 is on. The first output module outputs the first signal, which is VGH and the first clock signal SCK1. In the second output module, the first transistor T1 is on, the second transistor T2 is on, and the third transistor T3 is on. The second output module outputs the second signal, which is VGH and the first clock signal SCK1.

[0091] In stage ②, the first input signal is high, the second clock signal is high, the first clock signal is low, and both the first and second control signals are low. At this time, the sixth transistor T6 is off, the seventh transistor T7 is on, the eighth transistor T8 is on, the ninth transistor T9 is off, the tenth transistor T10 is on, the eleventh transistor T11 is off, the fourth transistor T4 is off, and the first transistor T1 is off. In the first output module, the potential of capacitor C3 is maintained, causing the fifth transistor T5 to conduct, and the first output module outputs the first signal, which is the first clock signal. In the second output module, the potential of capacitor C1 is maintained, causing the second transistor T2 to conduct, and the second output module outputs the second signal, which is the first clock signal.

[0092] In stage ③, the first input signal is low, the second clock signal is low, the first clock signal is high, the first control signal is low, and the second control signal is high. At this time, the sixth transistor T6 is turned on, the seventh transistor T7 is turned off, the eighth transistor T8 is turned on, the ninth transistor T9 is turned on, the tenth transistor T10 is turned on, the eleventh transistor T11 is turned on, and the fourth transistor T4 and the fifth transistor T5 are both turned on. The first output module outputs the first signal, which is VGH and the first clock signal SCK1. In the second output module, the first transistor T1 is turned on, the potential of capacitor C1 is maintained, the second transistor T2 is turned on, and the second output module outputs the second signal, which is VGH and the first clock signal SCK1.

[0093] In stage ④, the first input signal is high, the second clock signal is high, the first clock signal is low, the first control signal is low, and the second control signal is high. At this time, the sixth transistor T6 is off, the seventh transistor T7 is on, the eighth transistor T8 is on, the ninth transistor T9 is off, the tenth transistor T10 is on, the eleventh transistor T11 is off, and the fourth transistor T4 and the first transistor T1 are off. In the first output module, the potential of capacitor C3 is maintained, causing the fifth transistor T5 to conduct. The first output module outputs the first signal, which is the first clock signal. The second output module outputs the second signal, which is low.

[0094] The driving method provided in this embodiment is applied to the driving circuit 10 provided in the above embodiment. Therefore, the driving method has all the beneficial effects of the driving circuit 10, which will not be repeated here.

[0095] In an optional embodiment, the waveform of the signal output by the drive circuit 10 during the write frame and hold frame is as follows: Figure 9 As shown. Figure 9 The first four waveforms are the waveforms of the first signal output by the first output module, and the last four waveforms are the waveforms of the second signal output by the second output module.

[0096] In one embodiment, such as Figure 10 As shown, a driving circuit 20 is provided, including a control module 100, a first output module 200 and a second output module 300. The second output module 300 includes a fifth output unit 330 and a sixth output unit 340. The control module 100 is connected to both the first output module 200 and the fifth output unit 330. The first output module 200 is connected to the sixth output unit 340, and the fifth output unit 330 is connected to the sixth output unit 340.

[0097] The control module 100 is used to control the first output module 200 to output a first signal and the second output module 300 to output a second signal under the control of the first input signal, the second input signal, the first control signal and the clock signal. The first signal and the second signal have different frequencies.

[0098] The descriptions of the control module 100 and the first output module 200 can be found in the specific descriptions in the above embodiments, and will not be repeated here.

[0099] The second output module 300 includes two output units: a fifth output unit 330 and a sixth output unit 340. The fifth output unit 330 includes a first terminal, a second terminal, and a third terminal, as does the sixth output unit 340. The first terminal (control terminal) of the fifth output unit 330 is connected to the control module 100, the second terminal of the fifth output unit 330 is used to input a high potential, and the third terminal of the fifth output unit 330 is connected to the third terminal of the sixth output unit 340. The first terminal of the sixth output unit 340 is used to input a second input signal, and the second terminal of the sixth output unit 340 is connected to the first output module 200.

[0100] The first input signal, the second input signal, the first control signal, and the clock signal can all be periodic pulse signals. Multiple clock signals can be input to the control module 100. When the first input signal, the clock signal, and the first control signal are input to the control module 100, and the second output signal is input to the sixth output unit 340, the control module 100 controls the first output module 200 to output the first signal, and the second output module 300 to output the second signal. The first signal and the second signal have different frequencies. This embodiment does not limit the specific structure of the fifth output unit 330 and the sixth output unit 340, as long as their functions can be achieved.

[0101] In other words, the control module 100 can control the first output module 200 and the second output module 300 to output signals of different frequencies, so that different clock signals or control signals can be provided to the pixel circuit during the write frame and the hold frame, respectively.

[0102] The driving circuit 20 provided in this embodiment includes a control module 100, a first output module 200, and a second output module 300. The second output module 300 includes a fifth output unit 330 and a sixth output unit 340. The control module 100 is connected to both the first output module 200 and the fifth output unit 330. The first output module 200 is also connected to both the fifth output unit 330 and the sixth output unit 340. The fifth output unit 330 and the sixth output unit 340 are connected. The control module 100 is used to control the first output module 200 to output a first signal and the second output module 300 to output a second signal under the control of a first input signal, a second input signal, a first control signal, and a clock signal. The first signal and the second signal have different frequencies. The driving circuit 20 provided in this embodiment includes two output modules, namely a first output module 200 and a second output module 300. Under the control of the first input signal, the second input signal, the clock signal, and the first control signal, the control module 100 can control the two output modules to output a first signal and a second signal with different frequencies, respectively. This allows for resetting the transistor source potential in the low-frequency pixel circuit without adding an additional signal generation circuit to generate additional control or clock signals, thus improving the low-frequency display effect. Furthermore, it does not increase the size of the display panel bezel.

[0103] Please continue reading Figure 10 In one embodiment, the fifth output unit 330 includes a twelfth transistor T12, and the sixth output unit 340 includes a thirteenth transistor T13.

[0104] The first terminal of the twelfth transistor T12 is used to input a high potential, the second terminal of the twelfth transistor T12 is connected to the control module 100, and the third terminal of the twelfth transistor T12 is connected to the first terminal of the thirteenth transistor T13.

[0105] The second terminal of the thirteenth transistor T13 is used to input the second input signal SIN2, and the third terminal of the thirteenth transistor T13 is connected to the first output module 200.

[0106] The fifth output unit 330 includes a twelfth transistor T12. The first terminal of the twelfth transistor T12 serves as the second terminal of the fifth output unit 330 for inputting a high potential. The second terminal of the twelfth transistor T12 serves as the first terminal of the fifth output unit 330 and is connected to the control module 100. The third terminal of the twelfth transistor T12 serves as the third terminal of the fifth output unit 330 and is connected to the third terminal of the sixth output unit 340.

[0107] The sixth output unit 340 includes a thirteenth transistor T13. The first terminal of the thirteenth transistor T13 is connected to the fifth output unit 330 as the third terminal of the sixth output unit 340. The second terminal of the thirteenth transistor T13 is used as the first terminal of the sixth output unit 340 for inputting the second input signal SIN2. The third terminal of the thirteenth transistor T13 is connected to the first output module 200 as the second terminal of the sixth output unit 340.

[0108] In this embodiment, the fifth output unit 330 includes a twelfth transistor T12, and the sixth output unit 340 includes a thirteenth transistor T13. The fifth output unit 330 and the sixth output unit 340 have simple structures, readily available transistors, and low cost, making the driving circuit 20 more practical.

[0109] In one embodiment, a driving method applied to the driving circuit 20 described above is provided, the method comprising:

[0110] Under the control of the first input signal, the second input signal, the first control signal, the first clock signal, and the second clock signal, the first output module is controlled to output the first signal, and the second output module is controlled to output the second signal; the first signal and the second signal have different frequencies.

[0111] In this circuit, the low-level pulse signal in each cycle of the first input signal corresponds to the low-level pulse signal in the second clock signal, the low-level pulse signal in each cycle of the first input signal corresponds to the high-level pulse signal in the first clock signal, and the high-level pulse signal in the second input signal corresponds to the second cycle of the first input signal.

[0112] The timing diagrams for the first input signal, the second input signal, the first clock signal, and the second clock signal are as follows: Figure 11 As shown (the first control signal is always a low-level pulse signal, not shown in the figure). Figure 11 The diagram shows the pulse waveforms of the first clock signal, the second clock signal, and the second input signal during two cycles of the first input signal. In the first cycle of the first input signal (i.e., the write frame of the display module), the second input signal is low; the low-level pulse signal of the first input signal corresponds to the low-level pulse signal of the second clock signal, and the high-level pulse signal of the first clock signal corresponds to the high-level pulse signal of the first clock signal. In the second cycle of the first input signal (i.e., the hold frame of the display module), the second input signal becomes high; the low-level pulse signal of the first input signal corresponds to the low-level pulse signal of the second clock signal, and the high-level pulse signal of the first clock signal corresponds to the high-level pulse signal of the first clock signal.

[0113] In such Figure 11 As shown in the timing diagram, Figure 10The operation of the driving circuit 20 shown is as follows:

[0114] In stage ①, the first input signal is low, the second clock signal SCK2 is low, the first clock signal SCK1 is high, the second input signal SIN2 is low, and the first control signal SW1 is low. At this time, the sixth transistor T6 is turned on, the seventh transistor T7 is turned off, the ninth transistor T9 is turned on, the eighth transistor T8 is turned on, the tenth transistor T10 is turned on, the eleventh transistor T11 is turned on, the fourth transistor T4 and the fifth transistor T5 are both turned on, and the twelfth transistor T12 and the thirteenth transistor T3 are also both turned on. Then, the first output module outputs the first signal, which is VGH and the first clock signal SCK1, and the second output module outputs the second signal, which is VGH and the first clock signal SCK1.

[0115] In stage ②, the first input signal is high, the second clock signal SCK2 is high, the first clock signal SCK1 is high, the second input signal SIN2 is low, and the first control signal SW1 is low. At this time, the potentials of capacitors C3 and C2 are maintained, the fourth transistor T4 and the fifth transistor T5 are turned on, the first output module outputs the first signal, which is VGH and the first clock signal SCK1, the twelfth transistor T12 and the thirteenth transistor T13 are turned on, and the second output module outputs the second signal, which is two VGH signals and the first clock signal SCK1.

[0116] In stage ③, the first input signal is high, the second clock signal SCK2 is high, the first clock signal SCK1 is low, the second input signal SIN2 is low, and SW1 is low. At this time, the sixth transistor T6 is off, the seventh transistor T7 is on, the eighth transistor T8 is on, the ninth transistor T9 is off, the tenth transistor T10 is on, the eleventh transistor T11 is off, the fourth transistor T4 and the fifth transistor T5 are off, the first output module outputs the first signal, which is low, the twelfth transistor T12 and the thirteenth transistor are off, and the second output module outputs the second signal, which is low.

[0117] In stage ④, the first input signal is low, the second clock signal SCK2 is low, the first clock signal SCK1 is high, the second input signal SIN2 is high, and the first control signal SW1 is low. At this time, the sixth transistor T6 is turned on, the seventh transistor T7 is turned off, the ninth transistor T9 is turned on, the eighth transistor T8 is turned on, the tenth transistor T10 is turned on, the eleventh transistor T11 is turned on, the fourth transistor T4 and the fifth transistor T5 are both turned on, and the twelfth transistor T12 and the thirteenth transistor T3 are also both turned on. Then the first output module outputs the first signal, which is VGH and the first clock signal SCK1, and the second output module outputs the second signal, which is VGH.

[0118] In stage ⑤, the first input signal is high, the second clock signal SCK2 is high, the first clock signal SCK1 is high, the second input signal SIN2 is high, and the first control signal SW1 is low. At this time, the potentials of capacitors C3 and C2 are maintained, the fourth transistor T4 and the fifth transistor T5 are turned on, the first output module outputs the first signal, which is VGH and the first clock signal SCK1, the twelfth transistor T12 and the thirteenth transistor T13 are turned on, and the second output module outputs the second signal, which is two VGH signals.

[0119] The driving method provided in this embodiment is applied to the driving circuit provided in the above embodiment. Therefore, the driving method has all the beneficial effects of the driving circuit, which will not be repeated here.

[0120] In one embodiment, such as Figure 12 As shown, a driving circuit 30 is provided, including: a control module 100, a first output module 200 and a second output module 300. The second output module 300 includes a second output submodule 350 and a third control submodule 360. The control module 100 is connected to both the first output module 200 and the second output submodule 350, and the second output submodule 350 is also connected to both the first output module 200 and the third control submodule 360.

[0121] The control module 100 is used to control the first output module 200 to output a first signal under the control of the first input signal, the clock signal and the first control signal, and to control the second output module 300 to output a second signal under the control of the first input signal, the clock signal and the first control signal, together with the third control submodule 360; the first signal and the second signal have different frequencies.

[0122] The descriptions of the control module 100 and the first output module 200 can be found in the specific descriptions in the above embodiments, and will not be repeated here.

[0123] The second output module 300 includes a second output submodule 350 and a third control submodule 360. The second output submodule 350 includes a first terminal, a second terminal, and a third terminal, as does the third control submodule 360. The first terminal of the second output submodule 350 is connected to the control module 100, the second terminal of the second output submodule 350 is connected to the first output module 200, and the third terminal of the second output submodule 350 is connected to the third terminal of the third control submodule 360. The first terminal of the third control submodule 360 ​​is used to connect to a low potential, and the second terminal of the third control submodule 360 ​​is used to input a clock signal.

[0124] The first input signal, clock signal, and first control signal can all be periodic pulse signals. The first input signal, clock signal, and first control signal are input to the control module 100, and the clock signal is input to the third control submodule 360, so that the control module 100 controls the first output module 200 to output the first signal, and the control module 100 and the third control submodule 360 ​​control the second output submodule 350 to output the second signal. In other words, the control module 100 and the third control submodule 360 ​​can control the first output module 200 and the second output module 300 to output signals of different frequencies, so that different clock signals or control signals can be provided to the pixel circuit during the write frame and the hold frame, respectively.

[0125] The driving circuit 30 provided in this embodiment includes a control module 100, a first output module 200, and a second output module 300. The second output module 300 includes a second output submodule 350 and a third control submodule 360. The control module 100 is connected to both the first output module 200 and the second output submodule 350, and the second output submodule 350 is also connected to both the first output module 200 and the third control submodule 360. The control module 100 is used to control the first output module 200 to output a first signal under the control of a first input signal, a clock signal, and a first control signal, and to control the second output module 300 to output a second signal under the control of the first input signal, the first control signal, and the clock signal, together with the third control submodule 360. The first signal and the second signal have different frequencies. The driving circuit 30 provided in this embodiment includes two output modules, namely a first output module 200 and a second output module 300. Under the control of the first input signal, the clock signal, and the first control signal, the control module 100 can control the two output modules to output a first signal and a second signal with different frequencies, respectively. This allows for resetting the transistor source potential in the low-frequency pixel circuit without adding an additional signal generation circuit to generate additional control or clock signals, thus improving the low-frequency display effect. Furthermore, it does not increase the size of the display panel bezel.

[0126] Please continue reading Figure 12In one embodiment, the third control submodule 360 ​​includes: a fourteenth transistor T14 and a fifteenth transistor T15, the first terminal of the fourteenth transistor T14 is used to input a first clock signal SCK1, the second terminal of the fourteenth transistor T14 is used to input a low potential, and the third terminal of the fourteenth transistor T14 is connected to the first terminal of the fifteenth transistor T15.

[0127] The second terminal of the fifteenth transistor T15 is used to input the third clock signal SCK3, and the third terminal of the fifteenth transistor T15 is connected to the second output submodule 350.

[0128] The first terminal of the fourteenth transistor T14 serves as the second terminal of the third control submodule 360 ​​for inputting the first clock signal. The second terminal of the fourteenth transistor T14 serves as the first terminal of the third control submodule 360 ​​for inputting a low potential. The third terminal of the fourteenth transistor T14 is connected to the first terminal of the fifteenth transistor T15.

[0129] The second terminal of the fifteenth transistor T15 serves as the second terminal of the third control submodule 360 ​​for inputting the third clock signal SCK3, and the third terminal of the fifteenth transistor T15 serves as the third terminal of the third control submodule 360 ​​and is connected to the second output submodule 350.

[0130] In this embodiment, the third control submodule 360 ​​includes a fourteenth transistor T14 and a fifteenth transistor T15. This third control submodule 360 ​​has a simple structure, readily available transistors, and low cost, making the drive circuit 30 more practical.

[0131] Please continue reading Figure 12 In one embodiment, the second output submodule 350 includes a sixteenth transistor T16 and a seventeenth transistor T17; the first terminal of the sixteenth transistor T16 is connected to the first output module 200, the second terminal of the sixteenth transistor T16 is connected to the control module 100, and the third terminal of the sixteenth transistor T16 is connected to the first terminal of the seventeenth transistor T17.

[0132] The second terminal of the seventeenth transistor T17 is connected to the control module 100, and the third terminal of the seventeenth transistor T17 is connected to the third control submodule 360.

[0133] The first terminal of the sixteenth transistor T16 is connected to the first output module 200 as the second terminal of the second output submodule 350. The second terminal of the sixteenth transistor T16 is connected to the control module 100 as the first terminal of the second output submodule 350. The third terminal of the sixteenth transistor T16 is connected to the first terminal of the seventeenth transistor T17. The second terminal of the seventeenth transistor T17 is connected to the control module 100 as the second terminal of the second output submodule 350. The third terminal of the seventeenth transistor T17 is connected to the third control submodule 360 ​​as the third terminal of the second output submodule 350.

[0134] In this embodiment, the second output submodule 350 includes a sixteenth transistor T16 and a seventeenth transistor T17. This second output submodule 350 has a simple structure, and the transistors are readily available and inexpensive, making the drive circuit 30 more practical.

[0135] In one embodiment, a driving method is provided for the driving circuit 30 as provided in the above embodiment, the driving method comprising:

[0136] Under the control of the input signal, the first clock signal, the second clock signal, the third clock signal, and the first control signal, the first output module is controlled to output a first signal and the second output module is controlled to output a second signal; the first signal and the second signal have different frequencies.

[0137] Wherein, the low-level pulse signal in the first cycle of the first input signal corresponds to the high-level pulse signal in the second clock signal, the low-level pulse signal in each cycle of the first input signal corresponds to the low-level pulse signal of the first clock signal, and the low level in each cycle of the first input signal corresponds to the low-level pulse signal of the third clock signal.

[0138] The high-level pulse signal in the third clock signal corresponds to the second cycle in the first input signal.

[0139] The timing diagrams for the first input signal, the first clock signal, the second clock signal, and the third clock signal are as follows: Figure 13 As shown (the first control signal is always a low-level pulse signal, not shown in the figure). Figure 13The diagram illustrates the pulse waveforms of the first, second, and third clock signals within two cycles of the first input signal. In the first cycle of the first input signal (i.e., the write frame of the display module), a low-level pulse signal of the first input signal corresponds to a high-level pulse signal of the second clock signal, and vice versa. In the second cycle of the first input signal (i.e., the hold frame of the display module), a low-level pulse signal of the first input signal corresponds to a high-level pulse signal of the second clock signal, and vice versa; the third clock signal is a continuous high-level pulse signal.

[0140] In an optional embodiment, the waveform of the signal output by the drive circuit 10 during the write frame and hold frame is as follows: Figure 14 As shown. Figure 14 The first four waveforms are the waveforms of the first signal output by the first output module, and the last four waveforms are the waveforms of the second signal output by the second output module.

[0141] One embodiment of this application provides a scan driving circuit, including multiple cascaded circuits as described above. Figure 5 , Figure 6 and Figure 7 The driving circuit 10 shown is as described above. Figure 9 The driving circuit 20 shown above and the driving circuit as described above Figure 11 Any of the driving circuits 30 shown; the output signal of the first output module of the preceding driving circuit in the plurality of driving circuits is the input signal of the following driving circuit.

[0142] When the scan driving circuit includes the driving circuit 10 or driving circuit 20 provided in the above embodiments, a schematic diagram of the scan driving circuit is shown below. Figure 15 As shown, the scanning driving circuit includes multiple driving circuits 10 or driving circuits 20. The output signal of the first output module of the previous driving circuit is used as the input signal of the next driving circuit. Pixel represents the pixel circuit and EM represents the driving circuit.

[0143] When the scan driving circuit includes the driving circuit 30 provided in the above embodiments, a schematic diagram of the scan driving circuit is shown below. Figure 16 As shown, the scanning drive circuit includes multiple cascaded drive circuits 30.

[0144] The scanning drive circuit provided in this embodiment includes any one of the drive circuits 10, 20 and 30 provided in the above embodiments. The scanning drive circuit has all the beneficial effects of the drive circuits 10, 20 or 30, which will not be repeated here.

[0145] One embodiment of this application provides a display device that includes the scanning drive circuit provided in the above embodiment.

[0146] The display device also includes a pixel circuit, where the output signal of the scan drive circuit serves as a control signal or clock signal for the pixel circuit. Optionally, the pixel circuit, such as... Figure 17 As shown in the diagram. S1, S2, and S3 are all input terminals of the pixel circuit. S1 and S2 input high-frequency signals, and S3 inputs low-frequency signals. The waveform diagram of the pixel circuit is shown below. Figure 18 As shown.

[0147] The display device provided in this application includes a scanning drive circuit, and the display device has all the beneficial effects of the scanning drive circuit, which will not be described in detail here.

[0148] In conventional technology, different frequencies can be provided to the entire area of ​​a display device using a scan driving circuit and an emission (EM) driving circuit. In an optional embodiment, the scan driving circuit provided in this embodiment can be used to connect pixel circuits in different areas of the display device, thereby allowing different areas of the display device to have different frequencies. The layout of the scan driving circuit and the EM driving circuit in the display device can be as follows: Figure 19 As shown, Figure 19 The black rectangle indicates the setting position of the EM driver circuit, and the gray rectangle indicates the setting position of the Scan driver circuit. From... Figure 19 As can be seen, the Scan drive circuit can be located at the display bezel or in the center of the display device. The Scan drive circuit can provide signals of different frequencies to the pixel circuits of the two connected areas, thus making the display frequencies of these two areas different. Optionally, such as... Figure 20 As shown, different frequencies can be displayed in the areas on the left and right sides of the Scan drive circuit. Similarly, different frequencies can also be displayed in the upper and lower areas on the left side of the Scan drive circuit, and different frequencies can be displayed in the three areas on the right side of the Scan drive circuit. When different frequencies are displayed in the upper and lower areas on the left side of the Scan drive circuit, the timing diagram of the drive circuit 10 is as follows: Figure 21 As shown.

[0149] In one embodiment, a method such as Figure 22 The driving circuit shown has the following timing diagram: Figure 23 As shown. The scan drive circuit includes multiple cascaded... Figure 22In the driving circuit shown, the clock signal waveform input to one end of the nineteenth transistor T19 in the first driving circuit is SCK3, and the clock signal waveform input to one end of the nineteenth transistor T19 in the second driving circuit is SCK4. That is, clock signals SCK3 and SCK4 are connected alternately, and so on. A schematic diagram of the scanning driving circuit is shown below. Figure 24 As shown.

[0150] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0151] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A driving circuit, characterized in that, include: The system includes a control module, a first output module, and a second output module. The second output module includes a first output submodule and a first control submodule. The control module is connected to both the first output module and the first output submodule, and is also connected to the first control submodule. The first control submodule is also connected to the first output submodule. The control module is configured to control the first output module to output a first signal under the control of a first input signal, a clock signal, and a first control signal, and to control the second output module to output a second signal under the control of the first input signal, the clock signal, the first control signal, and the second control signal, together with the first control submodule; the first signal and the second signal have different frequencies. The control module includes an input submodule and a second control submodule. The first terminal of the input submodule is used to input a second clock signal, the second terminal of the input submodule is used to input the first input signal, and the third terminal of the input submodule is connected to the input terminal of the second control submodule. The control terminal of the second control submodule is used to input the first clock signal, the second clock signal, the first control signal, and a high potential. The output terminal of the second control submodule is connected to the first output module, the first output submodule, and the first control submodule. The second control submodule includes: a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, and an eleventh transistor; The first terminal of the seventh transistor is connected to the third terminal of the input submodule, the second terminal of the seventh transistor is used to input the first clock signal, and the third terminal of the seventh transistor is connected to the first terminal of the eighth transistor. The second terminal of the eighth transistor is used to input the high potential, the third terminal of the eighth transistor is connected to the first terminal of the ninth transistor, the second terminal of the ninth transistor is used to input the second clock signal, and the third terminal of the ninth transistor is connected to the first terminal of the tenth transistor; the second terminal of the tenth transistor is used to input the first control signal, and the third terminal of the tenth transistor is connected to the first output module; the first terminal of the eleventh transistor is connected to the third terminal of the eighth transistor, the second terminal of the eleventh transistor is used to input the second clock signal, and the third terminal of the eleventh transistor is used to input a low potential.

2. The driving circuit according to claim 1, characterized in that, The first output submodule includes: a first output unit and a second output unit; a first terminal of the first output unit is connected to the control module, a second terminal of the first output unit is used to input a high potential, a first terminal of the second output unit is connected to the first control submodule, a second terminal of the second output unit is used to input a first clock signal, and a third terminal of the first output unit is connected to the third terminal of the second output unit.

3. The driving circuit according to claim 2, characterized in that, The first output unit includes a first transistor, and the second output unit includes a first capacitor and a second transistor; Wherein, the first terminal of the first transistor is connected to the control module, the second terminal of the first transistor is used to input the high potential, and the third terminal of the first transistor is connected to the third terminal of the second output unit; The first terminal of the first capacitor is connected to the first control submodule, the second terminal of the first capacitor is connected to the third terminal of the second output unit, the first terminal of the second transistor is connected to the first terminal of the first capacitor, the second terminal of the second transistor is used to input the first clock signal, and the third terminal of the second transistor is connected to the second terminal of the first capacitor.

4. The driving circuit according to claim 1, characterized in that, The first control submodule includes: a third transistor; the first terminal of the third transistor is used to input the second control signal, the second terminal of the third transistor is connected to the control module, and the third terminal of the third transistor is connected to the first output submodule.

5. The driving circuit according to claim 1, characterized in that, The first output module includes a third output unit and a fourth output unit; the first end of the third output unit is connected to the control module, the second end of the third output unit is used to input a high potential, the first end of the fourth output unit is connected to the control module, the second end of the fourth output unit is used to input a first clock signal, and the third end of the fourth output unit is connected to the third end of the third output unit.

6. The driving circuit according to claim 5, characterized in that, The third output unit includes a second capacitor and a fourth transistor, and the fourth output unit includes a third capacitor and a fifth transistor. Wherein, the first terminal of the second capacitor is connected to the control module, the second terminal of the second capacitor is used to input the high potential, the first terminal of the fourth transistor is connected to the first terminal of the second capacitor, the second terminal of the fourth transistor is used to input the high potential, and the third terminal of the fourth transistor is connected to the third terminal of the fourth output unit. The first terminal of the third capacitor is connected to the control module, the second terminal of the third capacitor is connected to the third terminal of the third output unit, the first terminal of the fifth transistor is connected to the first terminal of the third capacitor, the second terminal of the fifth transistor is used to input the first clock signal, and the third terminal of the fifth transistor is connected to the second terminal of the third capacitor.

7. The driving circuit according to claim 1, characterized in that, The input submodule includes: at least one sixth transistor, the first terminal of the sixth transistor being used to input the second clock signal, the second terminal of the sixth transistor being used to input the first input signal, and the third terminal of the sixth transistor being connected to the first terminal of the second control submodule.

8. A driving circuit, characterized in that, It includes a control module, a first output module, and a second output module. The second output module includes a fifth output unit and a sixth output unit. The control module is connected to both the first output module and the fifth output unit. The first output module is connected to the sixth output unit, and the fifth output unit is connected to the sixth output unit. The control module is used to control the first output module to output a first signal and control the second output module to output a second signal under the control of the first input signal, the second input signal, the first control signal and the clock signal, wherein the first signal and the second signal have different frequencies; The control module includes an input submodule and a second control submodule. The first terminal of the input submodule is used to input a second clock signal, the second terminal of the input submodule is used to input the first input signal, and the third terminal of the input submodule is connected to the input terminal of the second control submodule. The control terminal of the second control submodule is used to input the first clock signal, the second clock signal, the first control signal, and a high potential. The output terminal of the second control submodule is connected to both the first output module and the fifth output unit. The second control submodule includes: a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, and an eleventh transistor; The first terminal of the seventh transistor is connected to the third terminal of the input submodule, the second terminal of the seventh transistor is used to input the first clock signal, and the third terminal of the seventh transistor is connected to the first terminal of the eighth transistor. The second terminal of the eighth transistor is used to input the high potential, the third terminal of the eighth transistor is connected to the first terminal of the ninth transistor, the second terminal of the ninth transistor is used to input the second clock signal, and the third terminal of the ninth transistor is connected to the first terminal of the tenth transistor; the second terminal of the tenth transistor is used to input the first control signal, and the third terminal of the tenth transistor is connected to the first output module; the first terminal of the eleventh transistor is connected to the third terminal of the eighth transistor, the second terminal of the eleventh transistor is used to input the second clock signal, and the third terminal of the eleventh transistor is used to input a low potential.

9. The driving circuit according to claim 8, characterized in that, The fifth output unit includes a twelfth transistor, and the sixth output unit includes a thirteenth transistor; The first terminal of the twelfth transistor is used to input a high potential, the second terminal of the twelfth transistor is connected to the control module, and the third terminal of the twelfth transistor is connected to the first terminal of the thirteenth transistor. The second terminal of the thirteenth transistor is used to input the second input signal, and the third terminal of the thirteenth transistor is connected to the first output module.

10. A driving circuit, characterized in that, include: The system includes a control module, a first output module, and a second output module. The second output module includes a second output submodule and a third control submodule. The control module is connected to both the first output module and the second output submodule, and the second output submodule is also connected to both the first output module and the third control module. The control module is configured to control the first output module to output a first signal under the control of a first input signal, a clock signal, and a first control signal, and to control the second output module to output a second signal under the control of the first input signal, the first control signal, and the clock signal, together with the third control submodule; the first signal and the second signal have different frequencies. The control module includes an input submodule and a second control submodule. The first terminal of the input submodule is used to input a second clock signal, the second terminal of the input submodule is used to input the first input signal, and the third terminal of the input submodule is connected to the input terminal of the second control submodule. The control terminal of the second control submodule is used to input the first clock signal, the second clock signal, the first control signal, and a high potential. The output terminal of the second control submodule is connected to both the first output module and the second output submodule. The second control submodule includes: a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, and an eleventh transistor; The first terminal of the seventh transistor is connected to the third terminal of the input submodule, the second terminal of the seventh transistor is used to input the first clock signal, and the third terminal of the seventh transistor is connected to the first terminal of the eighth transistor. The second terminal of the eighth transistor is used to input the high potential, the third terminal of the eighth transistor is connected to the first terminal of the ninth transistor, the second terminal of the ninth transistor is used to input the second clock signal, and the third terminal of the ninth transistor is connected to the first terminal of the tenth transistor; the second terminal of the tenth transistor is used to input the first control signal, and the third terminal of the tenth transistor is connected to the first output module; the first terminal of the eleventh transistor is connected to the third terminal of the eighth transistor, the second terminal of the eleventh transistor is used to input the second clock signal, and the third terminal of the eleventh transistor is used to input a low potential.

11. The driving circuit according to claim 10, characterized in that, The third control submodule includes a fourteenth transistor and a fifteenth transistor. The first terminal of the fourteenth transistor is used to input a first clock signal, the second terminal of the fourteenth transistor is used to input a low potential, and the third terminal of the fourteenth transistor is connected to the first terminal of the fifteenth transistor. The second terminal of the fifteenth transistor is used to input the third clock signal, and the third terminal of the fifteenth transistor is connected to the second output submodule.

12. The driving circuit according to claim 10, characterized in that, The second output submodule includes a sixteenth transistor and a seventeenth transistor; the first terminal of the sixteenth transistor is connected to the first output module, the second terminal of the sixteenth transistor is connected to the control module, and the third terminal of the sixteenth transistor is connected to the first terminal of the seventeenth transistor. The second terminal of the seventeenth transistor is connected to the control module, and the third terminal of the seventeenth transistor is connected to the third control submodule.

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