Partition display driving circuit, display panel and display device

Abstract

The invention discloses a partition display driving circuit, a display panel and a display device, the partition display driving circuit is used for driving a pixel array, the partition display driving circuit comprises a plurality of data lines, a plurality of gating modules and a control module, and one data line is used for connecting one column of pixel circuits; the first end of the gating module is used for receiving a data signal, and the second end of the gating module is connected with at least one data line; wherein the gating module is used for being switched on or switched off according to a received data signal under the condition that a periodic trigger signal is received, and the pixel circuit is used for configuring the refresh rate according to the duty ratio of the received data signal. By controlling on and off of the gating modules, the duty ratio of the data signals output to the pixel circuits by the gating modules can be changed, so that the refresh rate of the pixel circuits corresponding to a whole column is changed, the data signals of a plurality of data lines are configured through cooperation of a plurality of adjacent gating modules or through one gating module, and the refresh rate of the pixel circuits corresponding to the whole column is changed. Partition display of the pixel array can be realized.

Description

Technical Field

[0001] The present application belongs to the technical field of display devices, and in particular relates to a partitioned display driving circuit, a display panel, and a display device. Background Art

[0002] Currently, organic light emitting diodes (OLEDs) and flat panel display devices based on technologies such as light emitting diodes (LEDs) are widely used due to their advantages such as high image quality, power saving, thin body and wide range of applications, becoming the mainstream display devices. Summary of the Invention

[0003] The purpose of this application is to provide a partitioned display driving circuit, a display panel and a display device to solve the problems existing in the prior art.

[0004] A first aspect of an embodiment of the present application provides a partitioned display driving circuit for driving a pixel array, wherein the pixel array includes a plurality of pixel circuits, and the plurality of pixel circuits are arranged in an array. The partitioned display driving circuit includes: a plurality of data lines, wherein one data line is used to connect a column of the pixel circuits; a plurality of gating modules, wherein a first end of the gating module is used to receive a data signal, and a second end of the gating module is connected to at least one of the data lines; and a control module, connected to the first end of each of the gating modules, for outputting the data signal; wherein the gating module is used to turn on or off according to the received data signal when a periodic trigger signal is received, and the pixel circuit is used to configure a refresh rate according to the duty cycle of the received data signal.

[0005] In one embodiment, the data signal includes periodic selection control data bits, and the selection control data bits correspond one-to-one to the trigger signal. The selection module is used to identify the level of the selection control data bits when receiving the trigger signal, and remain on or off in the next cycle according to the level of the selection control data bits; preferably, the data signals output by the control module are all high level except for the selection control data bits.

[0006] In one embodiment, the selection module includes a logic operation unit, a storage unit and a switch unit; the logic operation unit is connected to the first end of the storage unit, and the logic operation unit is used to send a corresponding control signal to the storage unit according to the level of the selection control data bit when receiving the trigger signal, and control the storage unit to store the control signal; the second end of the storage unit is connected to the control end of the switch unit, and is used to provide the stored control signal to the switch unit; the first end of the switch unit is connected to the control module, and the second end of the switch unit is connected to at least one of the data lines, and the switch unit is used to turn on or off according to the control signal.

[0007] In one embodiment, the logic operation unit includes a first switching device and a second switching device, the storage unit includes a first inverter and a second inverter, and the switching unit includes a third switching device; a first end of the first switching device is connected to the control module, a second end of the first switching device is connected to the input end of the first inverter, and a control end of the first switching device is used to receive the trigger signal; a first end of the second switching device is connected to the input end of the first inverter, a second end of the second switching device is connected to the output end of the second inverter, and the control end of the second switching device is used to receive the trigger signal; the output end of the first inverter is connected to the input end of the second inverter and the control end of the third switching device, a first end of the third switching device is connected to the control module, and a second end of the third switching device is connected to at least one of the data lines; the conduction logic of the first switching device and the third switching device is the same, and the conduction logic of the first switching device and the third switching device is opposite to the conduction logic of the second switching device; preferably, the first switching device and the third switching device are configured to be turned on at a low level, and the second switching device is configured to be turned on at a high level.

[0008] In one embodiment, the switching unit further includes a fourth switching device, a first end of the fourth switching device being connected to the first end of the third switching device, a second end of the fourth switching device being connected to the second end of the third switching device, and a control end of the fourth switching device being connected to the second end of the second switching device; the conduction logic of the third switching device is opposite to the conduction logic of the fourth switching device; preferably, the fourth switching device is configured to be turned on at a high level.

[0009] In one embodiment, the trigger signal is a low-level signal, and the selection module is used to, when receiving the trigger signal, continuously turn on in the next cycle if the selection control data bit is a high level, and continuously turn off in the next cycle if the selection control data bit is a low level.

[0010] In one embodiment, a plurality of scanning circuits are further included, wherein one scanning circuit is used to connect to a row of pixel circuits, and the scanning circuit is used to transmit a scanning signal, and the scanning signal is used to configure the maximum refresh rate of each pixel circuit; the refresh rate of a pixel circuit is equal to the product of the corresponding maximum refresh rate and the duty cycle of the corresponding data signal.

[0011] In one embodiment, the frequency of the trigger signal received by the selection module is the same as the frequency of the scanning signal; preferably, the pixel array includes N rows of pixel circuits, the partitioned display driving circuit includes N+1 rows of scanning circuits, the scanning circuits in the 1st to Nth rows correspond one-to-one to the pixel circuits in N rows, and the scanning circuit in the N+1th row is used to provide the trigger signal; preferably, the control module is also used to provide the trigger signal.

[0012] A second aspect of the embodiments of the present application provides a display panel, including a pixel array and the above-mentioned partitioned display driving circuit, wherein the partitioned display driving circuit is connected to the pixel array.

[0013] A third aspect of the embodiments of the present application provides a display device, comprising the display panel as described above.

[0014] Compared with the prior art, the embodiments of the present application have the following advantages: by controlling the on and off of the gating module, the duty cycle of the data signal output by the gating module to the pixel circuit can be changed, thereby changing the refresh rate of the pixel circuit corresponding to an entire column; by cooperating with multiple adjacent gating modules or configuring the data signals of multiple data lines through one gating module, partitioned display of the pixel array can be achieved. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 A schematic diagram of a partition display driving circuit provided in one embodiment of the present application;

[0016] Figure 2 A circuit diagram of a gating module provided in one embodiment of the present application;

[0017] Figure 3 Another circuit diagram of a gating module provided in one embodiment of the present application;

[0018] Figure 4 A schematic diagram of a pixel array provided in one embodiment of the present application;

[0019] Figure 5 Waveform diagrams of trigger signals, data signals, and scan signals provided in one embodiment of the present application;

[0020] Figure 6Another waveform diagram of the trigger signal, data signal and scan signal provided in one embodiment of the present application;

[0021] Figure 7 Waveform diagram of data signals from columns 1 to 4 provided in one embodiment of the present application;

[0022] Figure 8 Another waveform diagram of the data signals of columns 1 to 4 provided in one embodiment of the present application;

[0023] Figure 9 Another waveform diagram of the data signals of columns 1 to 4 provided in one embodiment of the present application;

[0024] Figure 10 A schematic diagram of a display panel provided in one embodiment of the present application;

[0025] Figure 11 A schematic diagram of a display device provided in one embodiment of the present application.

[0026] Explanation of the accompanying drawings: 10, partition display driving circuit; 20, pixel array; 30, display panel; 40, display device; 100, pixel circuit; 200, selection module; 210, logic operation unit; 220, storage unit; 221, first inverter; 222, second inverter; 230, switch unit; 300, control module. DETAILED DESCRIPTION

[0027] In order to make the technical problems, technical solutions and beneficial effects to be solved by this application more clearly understood, this application is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0028] It should be noted that when an element is referred to as being “fixed on” or “disposed on” another element, it may be directly on the other element or indirectly on the other element. When an element is referred to as being “connected to” another element, it may be directly connected to the other element or indirectly connected to the other element.

[0029] It should be understood that the terms "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on this application.

[0030] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. Throughout the description of this application, "plurality" means two or more, unless otherwise specifically defined.

[0031] In the prior art, a common pixel array usually outputs multiple scanning signals through a gate in panel (GIP), and frequency modulation is performed in units of a row of pixels.

[0032] By controlling the scan signal output by the GIP, it is possible to determine whether the thin film transistor (TFT) of the corresponding row is turned on, and further determine whether data is written to the pixels of the corresponding row, ultimately achieving control of the refresh rate of a row of pixels.

[0033] By controlling the refresh rates of multiple adjacent rows of pixels simultaneously, a certain pixel array partition display can be achieved.

[0034] Figure 1 A schematic diagram of a partitioned display driving circuit provided in an embodiment of the present application is shown. For ease of explanation, only the portion related to this embodiment is shown, which is described in detail as follows:

[0035] A partitioned display driving circuit 10 is used to drive a pixel array 20. The pixel array 20 includes a plurality of pixel circuits 100 arranged in an array. The partitioned display driving circuit 10 includes: a plurality of data lines, a plurality of strobe modules 200 and a control module 300.

[0036] A data line is used to connect a column of pixel circuits 100. The first end of the gating module 200 is used to receive a data signal, and the second end of the gating module 200 is connected to at least one data line. The control module 300 is connected to the first end of each gating module 200 and is used to output a data signal.

[0037] The gating module 200 is used to turn on or off according to the received data signal when receiving a periodic trigger signal, and the pixel circuit 100 is used to configure the refresh rate according to the duty cycle of the received data signal.

[0038] It should be noted that the pixel array 20 also includes multiple light-emitting signals, and a pixel circuit 100 can be connected to one or more light-emitting chips to control the brightness of each light-emitting chip. The control module 300 may include a control chip. Due to the limitations of the control chip model and function, it is difficult for a single control module 300 to individually adjust each data signal according to actual needs, and it is impossible to adjust the refresh rate of the pixel circuits 100 in the pixel array 20 on a column-by-column basis.

[0039] When the second end of the gating module 200 is connected to only one data line, this embodiment can change the duty cycle of the data signal output by the gating module 200 to the pixel circuit 100 by controlling the conduction and shutdown of the gating module 200, thereby changing the refresh rate of the pixel circuit 100 corresponding to an entire column. By coordinating multiple adjacent gating modules 200 or configuring the data signals of multiple data lines through a single gating module 200, a partitioned display of the pixel array 20 can be achieved. Compared to existing technical solutions, this embodiment only requires adjusting the data bit corresponding to the trigger signal in the data signal to achieve column-by-column adjustment of the refresh rate of the pixel array 20.

[0040] In one embodiment, the data signal includes periodic strobe control data bits, which correspond one-to-one to the trigger signal. The strobe module 200 is used to identify the level of the strobe control data bit when receiving the trigger signal, and remain on or off in the next cycle according to the level of the strobe control data bit.

[0041] It should be noted that the data signal can be considered as consisting of multiple level signals, and a strobe control data bit can correspond to one of the levels. A trigger signal can specifically be a pulse signal, for example, the trigger signal can be a low-level pulse signal.

[0042] In some embodiments, a trigger signal may specifically be a transition edge received by the strobe module 200 , and the strobe module 200 is configured to identify the data signal while detecting the transition edge of the signal.

[0043] When the selection module 200 receives a trigger signal (for example, when the trigger signal is a low-level pulse signal and the level of the terminal of the selection module 200 for receiving the trigger signal is a low level), the selection module 200 can identify the level of the selection control data bit of the data signal received simultaneously with the trigger signal, and before receiving the next trigger signal, the selection module 200 can be controlled to be turned on according to the level of the selection control data bit.

[0044] Preferably, the data signals output by the control module 300 are all high level except for the strobe control data bit.

[0045] It can be understood that when the selection module 200 is turned off, the corresponding pixel circuit 100 cannot receive the data signal, and thus cannot change the light-emitting parameters of the corresponding light-emitting chip (i.e., the corresponding pixel circuit 100 stops refreshing). However, when the selection module 200 is turned on, the corresponding pixel circuit 100 can change the light-emitting parameters of the corresponding light-emitting chip according to the data signal (i.e., the corresponding pixel circuit 100 can be continuously refreshed). Therefore, after changing the conduction state of the selection module 200, the refresh rate of the pixel circuit 100 can be adjusted. The longer the conduction time of a selection module 200, the greater the duty cycle of the data signal provided to the pixel circuit 100, and the higher the refresh rate of the corresponding column of pixel circuits 100.

[0046] In one embodiment, if Figure 2 As shown, the gating module 200 includes a logic operation unit 210, a storage unit 220, and a switch unit 230. The logic operation unit 210 is connected to a first terminal of the storage unit 220. Upon receiving a trigger signal SCAN, the logic operation unit 210 is configured to send a corresponding control signal to the storage unit 220 based on the level of the gating control data bit, and to control the storage unit 220 to store the control signal. The second terminal of the storage unit 220 is connected to a control terminal of the switch unit 230, and is configured to provide the stored control signal to the switch unit 230. The first terminal of the switch unit 230 is connected to the control module 300, and the second terminal of the switch unit 230 is connected to at least one data line. The switch unit 230 is configured to be turned on or off according to the control signal.

[0047] When the logic operation unit 210 receives the trigger signal SCAN, the logic operation unit 210 will identify the level of the data signal DATA-IC (selection control data bit) and output the corresponding control signal. Before receiving the next trigger signal SCAN (that is, in the next adjacent cycle), the storage unit 220 will save the control signal and continue to output it to the switch unit 230, thereby controlling the conduction and shutdown of the switch unit 230, and ultimately achieving the effect of changing the duty cycle of the data signal DATA-AA provided to the pixel circuit 100.

[0048] In one embodiment, if Figure 2As shown, the logic operation unit 210 includes a first switch device Q1 and a second switch device Q2, the storage unit 220 includes a first inverter 221 and a second inverter, and the switch unit 230 includes a third switch device Q3. A first terminal of the first switch device Q1 is connected to the control module 300, a second terminal of the first switch device Q1 is connected to the input terminal of the first inverter 221, and a control terminal of the first switch device Q1 is configured to receive a trigger signal SCAN. A first terminal of the second switch device Q2 is connected to the input terminal of the first inverter 221, a second terminal of the second switch device Q2 is connected to the output terminal of the second inverter 222, and a control terminal of the second switch device Q2 is configured to receive a trigger signal SCAN. The output terminal of the first inverter 221 is connected to the input terminal of the second inverter 222 and to the control terminal of the third switch device Q3. A first terminal of the third switch device Q3 is connected to the control module 300, and a second terminal of the third switch device Q3 is connected to at least one data line. The turn-on logic of the first switching device Q1 and the third switching device Q3 is the same, and the turn-on logic of the first switching device Q1 and the third switching device Q3 is opposite to the turn-on logic of the second switching device Q2.

[0049] Preferably, the first switching device Q1 and the third switching device Q3 are configured to be turned on at a low level, and the second switching device Q2 is configured to be turned on at a high level.

[0050] When the logic operation unit 210 receives the trigger signal SCAN, the trigger signal SCAN can turn on the first switch device Q1 and turn off the second switch device Q2. The logic operation unit 210 can output a corresponding control signal according to the level of the selection control data bit of the data signal DATA-IC output by the control module 300. After passing through the first inverter 221, the control signal is provided to the third switch device Q3 to control the conduction and shutdown of the third switch device Q3.

[0051] When the level of the selected control data bit is high, the control signal after inversion by the first inverter 221 can control the third switch device Q3 to turn on, and the data signal DATA-AA can be transmitted to the corresponding pixel circuit 100 through the third switch device Q3, so that the light-emitting parameters of the light-emitting chip corresponding to the pixel circuit 100 are continuously refreshed.

[0052] When the level of the selected control data bit is low, the control signal after inversion by the first inverter 221 can control the third switch device Q3 to be turned off, and the data signal DATA-AA cannot be transmitted to the pixel circuit 100, so that the light-emitting parameters of the light-emitting chip corresponding to the pixel circuit 100 stop being refreshed.

[0053] Therefore, by properly configuring the levels of the strobe control data bits of different data signals DATA-IC, the refresh rates of the pixel circuits 100 in different columns can be made different.

[0054] In the next cycle (before the next trigger signal SCAN arrives), the first switch device Q1 is turned off and the second switch device Q2 is turned on. The control signal provided to the third switch device Q3 will be transmitted to the input end of the first inverter 221 through the second inverter 222, thereby achieving the effect of saving the control signal and keeping the switching state of the third control signal unchanged.

[0055] In one embodiment, if Figure 3 As shown, the switch unit 230 further includes a fourth switch device Q4. A first terminal of the fourth switch device Q4 is connected to the first terminal of the third switch device Q3, a second terminal of the fourth switch device Q4 is connected to the second terminal of the third switch device Q3, and a control terminal of the fourth switch device Q4 is connected to the second terminal of the second switch device Q2. The conduction logic of the third switch device Q3 is opposite to the conduction logic of the fourth switch device Q4. Preferably, the fourth switch device Q4 is configured to be turned on at a high level.

[0056] Since the conduction logic of the third switching device Q3 is opposite to the conduction logic of the fourth switching device Q4, and the control signal provided to the fourth switching device Q4 is inverted by the second inverter 222, when the third switching device Q3 is turned on, the fourth switching device Q4 will also be turned on, thereby increasing the current passing through the switching unit 230 and improving the charging effect of the data line.

[0057] In one embodiment, the trigger signal SCAN is a low-level signal. The selection module 200 is used to, when receiving the trigger signal SCAN, continuously turn on in the next cycle if the selection control data bit is a high level, and continuously turn off in the next cycle if the selection control data bit is a low level.

[0058] Specifically, in some embodiments, the first switching device Q1 and the third switching device Q3 can both be low-level conduction switching devices, and the second switching device Q2 and the fourth switching device Q4 can both be high-level conduction switching devices. The first switching device Q1, the second switching device Q2, the third switching device Q3, and the fourth switching device Q4 can specifically be metal-oxide semiconductor field effect transistors (MOS) or insulated-gate bipolar transistors (IGBT). The specific device types of the first switching device Q1, the second switching device Q2, the third switching device Q3, and the fourth switching device Q4 can be set according to actual needs and are not limited in this embodiment.

[0059] Therefore, when the trigger signal SCAN is received, the first switch device Q1 is turned on and the second switch device Q2 is turned off. When the trigger signal SCAN is not received, the first switch device Q1 is turned off and the second switch device Q2 is turned on.

[0060] When the strobe control data bit is high, the third switching device Q3 and the fourth switching device Q4 are turned on in the period, and when the strobe control data bit is low, the third switching device Q3 and the fourth switching device Q4 are turned off in the period.

[0061] In one embodiment, the partitioned display driver circuit 10 further includes multiple scan circuits. One scan circuit is connected to a row of pixel circuits 100. The scan circuit is configured to transmit scan signals, which are used to configure the maximum refresh rate of each pixel circuit 100. The actual refresh rate of a pixel circuit 100 is equal to the product of the corresponding maximum refresh rate and the duty cycle of the corresponding data signal DATA-AA.

[0062] It is understood that the scan signal can determine the maximum refresh rate of each pixel circuit 100. When all the gating modules 200 are turned on, the refresh rate of each pixel circuit 100 is the maximum refresh rate. However, when some gating modules 200 are turned off for some time periods, the refresh rate of the corresponding pixel circuit 100 will decrease as the duty cycle of the data signal DATA-AA decreases.

[0063] For example, in some embodiments, Figure 4 As shown, the pixel array 20 includes a first area, a second area, a third area, ..., and a ninth area, each of which includes a plurality of pixel circuits 100. The first area, the second area, the third area, ..., and the ninth area are arranged in the same row from left to right, the fourth area, the fifth area, and the sixth area are arranged in the same row from left to right, and the seventh area, the eighth area, and the ninth area are arranged in the same row from left to right.

[0064] When the fifth zone is required to be a high refresh zone and the other zones are low refresh zones, the maximum refresh rate of the pixel circuits 100 in the fourth, fifth and sixth zones can be set to 120Hz by configuring each scanning signal, and the maximum refresh rate of the pixel circuits 100 in the first, second, third, seventh, eighth and ninth zones can be set to 60Hz. On this basis, by keeping the gating module 200 corresponding to the fifth zone turned on, the conduction time of the gating modules 200 corresponding to the fourth and sixth zones is halved (that is, the duty cycle of the data signal DATA-AA output by the gating modules 200 corresponding to the fourth and sixth zones is 50%). Finally, the refresh rate of the fifth zone is set to 120Hz, and the refresh rates of the other zones are all set to 60Hz.

[0065] In one embodiment, if Figure 5 、 Figure 6 As shown, the frequency of the trigger signal received by the gating module 200 is the same as the frequency of the scanning signal. Figure 5 、 Figure 6 The scan signals shown in include a third-to-last row scan signal, a second-to-last row scan signal, and a last row scan signal. Figure 5 The middle strobe control data bit is high level, Figure 6 In some embodiments, when the strobe control data bit is at a high level, the corresponding strobe module 200 may be controlled to be turned on, and when the strobe control data bit is at a low level, the corresponding strobe module 200 may be controlled to be turned off.

[0066] It can be understood that the frequency of the scanning signal specifically refers to the frequency of the pulse used for scanning of any row of the scanning signal. The trigger signal can be set according to the scanning signal so that the selection module 200 has sufficient switching frequency, so that the minimum refresh rate of the pixel circuit 100 can be 1Hz.

[0067] For example, in some embodiments, taking 4 columns of data signals corresponding to 4 data lines as an example, Figure 7 The waveform diagram of the data signals in columns 1 to 4 is shown. The data signals in columns 1 to 4 are respectively provided to the pixel circuits 100 in columns 1 to 4 in the pixel array 20. The duty cycle of the data signals in columns 1 to 4 is 100%. When the maximum refresh rate is 120 Hz, the refresh rate of the pixel circuits 100 in columns 1 to 4 is 120 Hz.

[0068] For example, in some embodiments, taking 4 columns of data signals corresponding to 4 data lines as an example, Figure 8 The waveform diagram of the data signals for columns 1 to 4 is shown. The data signals for columns 1 to 4 are respectively provided to the pixel circuits 100 for columns 1 to 4 in the pixel array 20. The duty cycle of the data signals for columns 1 and 4 is 50%, and the duty cycle of the data signals for columns 2 and 3 is 100%. When the maximum refresh rate is 120 Hz, the refresh rate of the pixel circuits 100 for columns 1 and 4 is 60 Hz, and the refresh rate of the pixel circuits 100 for columns 2 and 3 is 120 Hz.

[0069] For example, in some embodiments, taking 4 columns of data signals corresponding to 4 data lines as an example, Figure 9The waveform diagram of the data signals for columns 1 to 4 is shown. The data signals for columns 1 to 4 are respectively provided to the pixel circuits 100 for columns 1 to 4 in the pixel array 20. The duty cycle of the data signals for columns 1 and 4 is 8.3%, and the duty cycle of the data signals for columns 2 and 3 is 100%. When the maximum refresh rate is 120 Hz, the refresh rate of the pixel circuits 100 for columns 1 and 4 is 1 Hz, and the refresh rate of the pixel circuits 100 for columns 2 and 3 is 120 Hz.

[0070] Specifically, the phase of the signal may be changed based on the tail scan signal, thereby obtaining a periodic trigger signal.

[0071] In some embodiments, the pixel array 20 includes N rows of pixel circuits 100, the partitioned display driving circuit 10 includes N+1 rows of scanning circuits, the 1st to Nth rows of scanning circuits correspond one-to-one to the N rows of pixel circuits 100, and the N+1th row of scanning circuits is used to provide the trigger signal.

[0072] It should be noted that a scanning signal usually includes a periodic pulse signal. Therefore, when a trigger signal is a pulse signal and the pulse signal parameters of the trigger signal are the same as those of the scanning signal, when the frequency of the trigger signal received by the selection module 200 is the same as the frequency of the scanning signal, a signal composed of a periodic trigger signal can be generated based on the waveform of the last row scanning signal (the scanning signal corresponding to the Nth row scanning circuit).

[0073] In some embodiments, the control module 300 is also used to output a trigger signal to each selection module 200. It can be understood that the control module 300 can be configured so that one port of the control module 300 outputs the required trigger signal, and the trigger signal can be adjusted according to actual needs.

[0074] Figure 10 A schematic diagram of a display panel provided in an embodiment of the present application is shown. For ease of explanation, only the portion related to this embodiment is shown, which is described in detail as follows:

[0075] A display panel 30 includes a pixel array 20 and a partitioned display driving circuit 10 according to any one of the above embodiments. The partitioned display driving circuit 10 is connected to the pixel array 20 .

[0076] Since the display panel 30 includes the partitioned display driving circuit 10 of any of the above embodiments, the display panel 30 has the beneficial effects of the partitioned display driving circuit 10 of any of the above embodiments, which will not be described in detail here.

[0077] Figure 11A schematic diagram of a display device provided in an embodiment of the present application is shown. For ease of explanation, only the portion related to this embodiment is shown, which is described in detail as follows:

[0078] A display device 40 includes the partitioned display driving circuit 10 according to any one of the above embodiments, or the display panel 30 according to any one of the above embodiments.

[0079] Since the display device 40 includes the display panel 30 of any of the above embodiments, the display device 40 has the beneficial effects of the display panel 30 of any of the above embodiments, which will not be described in detail here.

[0080] The display device 40 in the embodiment of the present application includes but is not limited to mobile phones, personal digital assistants (PDAs), tablet computers, e-books, televisions, access control systems, smart landline phones, consoles, and other devices with display functions.

[0081] Those skilled in the art can clearly understand that, for the convenience and brevity of description, only the division of the above-mentioned functional units and modules is used as an example for illustration. In actual applications, the above-mentioned functions can be distributed and completed by different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiment can be integrated into one processing unit, or each unit can exist physically alone, or two or more units can be integrated into one unit. The above-mentioned integrated unit can be implemented in the form of hardware or in the form of software functional units. In addition, the specific names of the functional units and modules are only for the convenience of distinguishing each other, and are not used to limit the scope of protection of this application. The specific working process of the units and modules in the above-mentioned system can refer to the corresponding process in the aforementioned method embodiment, and will not be repeated here.

[0082] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant description of other embodiments.

[0083] The above-described embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present application, and should all be included in the scope of protection of the present application.

Claims

1. A partition display driving circuit (10), characterized in that: Used to drive a pixel array (20), the pixel array (20) comprising a plurality of pixel circuits (100), the plurality of pixel circuits (100) being arranged in an array, the partition display driving circuit (10) comprising: A plurality of data lines, one of the data lines being used to connect a column of the pixel circuits (100); A plurality of gating modules (200), wherein a first end of the gating module (200) is used to receive a data signal, and a second end of the gating module (200) is connected to at least one of the data lines; A control module (300) connected to the first end of each of the gating modules (200) and configured to output the data signal; The gating module (200) is used to switch on or off according to a received data signal when a periodic trigger signal is received, and the pixel circuit (100) is used to configure a refresh rate according to a duty cycle of the received data signal.

2. The partition display driving circuit (10) according to claim 1, characterized in that: The data signal comprises a periodic gating control data bit, the gating control data bit corresponds to the trigger signal one by one, and the gating module (200) is used to identify the level of the gating control data bit when receiving the trigger signal, and keep on or off in the next cycle according to the level of the gating control data bit; Preferably, the data signals output by the control module (300) are all at high level except for the selection control data bit.

3. The partition display driving circuit (10) according to claim 2, characterized in that: The gating module (200) comprises a logic operation unit (210), a storage unit (220) and a switch unit (230); The logic operation unit (210) is connected to a first end of the storage unit (220), and the logic operation unit (210) is used to send a corresponding control signal to the storage unit (220) according to the level of the selection control data bit when receiving the trigger signal, and control the storage unit (220) to store the control signal; The second end of the storage unit (220) is connected to the control end of the switch unit (230) and is used to provide the stored control signal to the switch unit (230); The first end of the switch unit (230) is connected to the control module (300), the second end of the switch unit (230) is connected to at least one of the data lines, and the switch unit (230) is used to switch on or off according to the control signal.

4. The partition display driving circuit (10) according to claim 3, characterized in that: The logic operation unit (210) includes a first switch device and a second switch device, the storage unit (220) includes a first inverter (221) and a second inverter, and the switch unit (230) includes a third switch device; The first end of the first switch device is connected to the control module (300), the second end of the first switch device is connected to the input end of the first inverter (221), and the control end of the first switch device is used to receive the trigger signal; The first end of the second switch device is connected to the input end of the first inverter (221), the second end of the second switch device is connected to the output end of the second inverter (222), and the control end of the second switch device is used to receive the trigger signal; The output end of the first inverter (221) is connected to the input end of the second inverter (222) and the control end of the third switch device, the first end of the third switch device is connected to the control module (300), and the second end of the third switch device is connected to at least one of the data lines; The first switch device and the third switch device have the same conduction logic, and the conduction logic of the first switch device and the third switch device is opposite to the conduction logic of the second switch device; Preferably, the first switching device and the third switching device are configured to be turned on at a low level, and the second switching device is configured to be turned on at a high level.

5. The partition display driving circuit (10) according to claim 4, characterized in that: The switch unit (230) further comprises a fourth switch device, wherein a first end of the fourth switch device is connected to a first end of the third switch device, a second end of the fourth switch device is connected to a second end of the third switch device, and a control end of the fourth switch device is connected to a second end of the second switch device; The conduction logic of the third switch device is opposite to the conduction logic of the fourth switch device; Preferably, the fourth switch device is configured to be turned on at a high level.

6. The partition display driving circuit (10) according to claim 1, characterized in that: The trigger signal is a low-level signal, and the gating module (200) is used to, upon receiving the trigger signal, continuously conduct in the next cycle if the gating control data bit is a high level, and continuously shut down in the next cycle if the gating control data bit is a low level.

7. The partition display driving circuit (10) according to claim 1, characterized in that: It also includes a plurality of scanning circuits, one of the scanning circuits is used to connect to a row of the pixel circuits, the scanning circuit is used to transmit a scanning signal, and the scanning signal is used to configure the maximum refresh rate of each of the pixel circuits; The refresh rate of one pixel circuit (100) is equal to the product of the corresponding maximum refresh rate and the duty cycle of the corresponding data signal.

8. The partition display driving circuit (10) according to claim 1, characterized in that: The frequency of the trigger signal received by the gating module (200) is the same as the frequency of the scanning signal; Preferably, the pixel array (20) comprises N rows of pixel circuits (100), the partitioned display driving circuit (10) comprises N+1 rows of scanning circuits, the scanning circuits in the 1st to Nth rows correspond one to one to the pixel circuits (100) in the Nth row, and the scanning circuit in the N+1th row is used to provide the trigger signal; Preferably, the control module (300) is also used to provide the trigger signal.

9. A display panel (30), characterized in that: It comprises a pixel array (20) and a partition display driving circuit (10) according to any one of claims 1 to 8, wherein the partition display driving circuit (10) is connected to the pixel array (20).

10. A display device (40), characterized in that: Comprising the display panel (30) as claimed in claim 9.

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