Use-based interference alert signaling

Abstract

Apparatuses and techniques for implementing use-based interference alert signaling are described. The techniques allow for use-based interference UBD alerts to be communicated from the memory device to the outside without a dedicated external interface. In particular, UBD alarms are combined with memory error / alarm signals and communicated over a shared alarm related interface. UBD tracking occurs at a bank level using a corresponding independent UBD alert signal. These signals are efficiently combined to produce an overall UBD alert. When an overall UBD alert is transmitted, a temporary backoff signal is generated. The backoff signal ensures that necessary external timing parameters are satisfied while allowing individual banks to generate persistent UBD alerts.

Description

[0001] CROSS REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of U.S. Provisional Patent Application Serial No. 63 / 583,477, filed on September 18, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to usage-based interference alert signaling. Background Art

[0004] Computers, smartphones, and other electronic devices rely on processors and memory. The processor executes code based on data to run applications and provide features to users. The processor obtains the code and data from the memory. The memory in an electronic device may include volatile memory, such as random access memory (RAM), and non-volatile memory, such as flash memory. Like the power of the processor, the power of the memory may affect the performance of the electronic device. This performance impact may increase as processors that execute code faster are developed and as applications operate on larger and larger data sets requiring larger and larger memory. Summary of the invention

[0005] On the one hand, the present disclosure provides a device comprising: a plurality of memory-level usage-based interference alarm circuit systems, which are configured to generate corresponding memory-level usage-based interference alarm signals; a die-level usage-based interference alarm circuit system, which is coupled to the outputs of the plurality of memory-level usage-based interference alarm circuit systems and is configured to generate a die-level usage-based interference alarm signal based on the memory-level usage-based interference alarm signal; an error detection circuit system, which is configured to generate an error detection signal; an alarm lead; and an alarm circuit system, which is coupled to the output of the die-level usage-based interference alarm circuit system, the output of the error detection circuit system and the alarm lead, the alarm circuit system being configured to output an alarm signal based on the die-level usage-based interference alarm signal and the error detection signal via the alarm lead.

[0006] On the other hand, the present disclosure provides a method comprising: transmitting an alarm signal having a first pulse indicating detection of a memory cell-level alarm event associated with usage-based interference on a lead of a bare die of a memory device, the first pulse having a first pulse length; and transmitting the alarm signal having a second pulse indicating detection of an error event different from the memory cell-level alarm event on the lead, the second pulse having a second pulse length different from the first pulse length.

[0007] On the other hand, the present disclosure provides a method, which includes: generating a die-level usage-based interference alarm signal having an alarm state or a non-alarm state, the alarm state indicating that a usage-based interference alarm event is detected in at least one storage body of a die of a memory device; monitoring a backoff signal having a blocking state or an alarm transmission state; generating a usage-based interference alarm signal based on the die-level usage-based interference alarm signal and the backoff signal, the usage-based interference alarm signal having the alarm state in response to the die-level usage-based interference alarm signal having the alarm state and the backoff signal having the alarm transmission state; and inducing the backoff state of the backoff signal within a period of time in response to the usage-based interference alarm signal transitioning from the non-alarm state to the alarm state. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The apparatus and techniques for implementing usage-based interference alert signaling are described with reference to the following figure. The same numbers are used throughout the figures to refer to similar features and components:

[0009] Figure 1A An example device is described in which aspects of usage-based interference (UBD) alert signaling may be implemented;

[0010] Figure 1B illustrating example operation of a memory device in performing aspects of UBD alert signaling;

[0011] Figure 2 An example computing system is illustrated in which aspects of UBD alert signaling may be implemented within a memory device;

[0012] Figure 3 illustrating an example memory device in which aspects of UBD alert signaling may be implemented;

[0013] Figure 4A Describes example circuitry that may implement UBD alert signaling;

[0014] Figure 4B Describe the instance bank-level UBD warning signal and the instance die-level UBD warning signal;

[0015] Figure 5A describes example circuitry for UBD alert signaling including examples of alert circuitry including combined alert circuitry;

[0016] Figures 5B to 5D Examples of input and output signals of the combined alarm circuit system are described in various timing scenarios;

[0017] Fig. 6A describes example circuitry for UBD alert signaling including examples of alert circuitry including sequential alert circuitry;

[0018] Figures 6B to 6D Examples of input and output signals of sequential alarm circuit systems are described in various timing scenarios;

[0019] Figure 7 An example die-level UBD alarm circuit system including UBD alarm signal generation circuit system, backoff circuit system, and comparison circuit system is described;

[0020] Figure 8 A first example of UBD signal timing including backoff signal timing is described;

[0021] Fig. 9 A second example of UBD signal timing including backoff signal timing is described;

[0022] Fig.10 A first example method for implementing aspects of UBD alert signaling is described;

[0023] Fig.11 A second example method for implementing aspects of UBD alert signaling is described; and

[0024] Fig.12 A third example method for implementing aspects of UBD alert signaling is described. DETAILED DESCRIPTION

[0025] Overview

[0026] Processors and memory work together to provide features to users of computers and other electronic devices. As processors and memory operate faster together in a complementary manner, electronic devices can provide enhanced features, such as high-resolution graphics and artificial intelligence (AI) analysis. Some applications, such as applications for financial services, medical devices, and advanced driver assistance systems (ADAS), also require more reliable memory. These applications use increasingly reliable memory to limit errors in financial transactions, medical decisions, and object recognition. However, in some implementations, more reliable memory sacrifices bit density, power efficiency, and simplicity.

[0027] In order to meet the demand for physically smaller memories, memory devices may be designed with higher chip density. However, increasing chip density increases electromagnetic coupling (e.g., capacitive coupling) between adjacent or proximate rows of memory cells, at least in part due to the reduced distance between these rows. Due to this undesirable coupling, activating (or charging) a first row of memory cells sometimes negatively affects nearby second row of memory cells. In particular, activating a first row may produce interference or crosstalk that causes the second row to experience voltage fluctuations. In some examples, this voltage fluctuation may cause the state (or value) of the memory cell in the second row to be incorrectly determined by the sense amplifier. Consider an example in which the state of the memory cell in the second row is "1". In this example, the voltage fluctuation may cause the sense amplifier to incorrectly determine the state of the memory cell as "0" instead of "1". If not curbed, this interference may lead to memory errors or data loss within the memory device.

[0028] In some cases, memory cells of a particular row are repeatedly activated in an unintentional or intentional (sometimes malicious) manner. For example, consider a memory cell in row R that is subjected to repeated activation, which causes one or more memory cells in neighboring rows (e.g., within row R+1, row R+2, row R-1, and / or row R-2) to change state. This effect is known as usage-based disturbance (UBD). The occurrence of UBD can cause the contents within the affected row of memory to be corrupted or altered.

[0029] Some memory devices utilize circuits that can detect UBD and mitigate its effects. However, these circuits increase the complexity and cost of the memory device. In addition, these circuits increase the overall footprint and power consumption of the memory device, which can make integration into space-constrained devices, including portable devices, challenging.

[0030] To address this and other issues regarding UBD, this document describes aspects of UBD alert signaling. This technique allows UBD alerts to be communicated externally from a memory device without the need for a dedicated external interface. Specifically, UBD alerts are combined with memory error signals and communicated on a shared alert-related interface. UBD detection and mitigation occur at the bank level using corresponding independent UBD alert signals. These signals are efficiently combined to generate die-level UBD alerts. In some implementations, additional backoff logic ensures that necessary external timing parameters are met at the external interface while allowing individual banks to generate persistent UBD alerts.

[0031] Instance operating environment

[0032] Figure 1AAn example operating environment including an apparatus 102 that may implement UBD alert signaling is generally illustrated at 100. The apparatus 102 may include various types of electronic devices, including an Internet of Things (IoT) device 102-1, a tablet device 102-2, a smartphone 102-3, a laptop computer 102-4, a passenger car 102-5, a server computer 102-6, and a server cluster 102-7 that may be part of a cloud computing infrastructure, a data center, or a portion thereof (e.g., a printed circuit board (PCB)). Other examples of the apparatus 102 include a wearable device (e.g., a smart watch or smart glasses), an entertainment device (e.g., a set-top box, a video dongle, a smart TV, a gaming device), a desktop computer, a motherboard, a blade server, a consumer appliance, a vehicle, a drone, an industrial equipment, a security device, or a sensor or electronic components thereof. Each type of apparatus may include one or more components for providing computing functionality or features.

[0033] In an example implementation, the apparatus 102 may include at least one host device 104, at least one interconnect 106, and at least one memory device 108. The host device 104 may include at least one processor 110, at least one cache memory 112, and a memory controller 114. The memory device 108 (which may also be implemented with a memory module) may include, for example, a dynamic random access memory (DRAM) die or module (e.g., a low power double data rate synchronous DRAM (LPDDR SDRAM)). The DRAM die or module may include a three-dimensional (3D) stacked DRAM device, which may be a high bandwidth memory (HBM) device or a hybrid memory cube (HMC) device. The memory device 108 may operate as a main memory of the apparatus 102. Although not illustrated, the apparatus 102 may also include a storage memory. The storage memory may include, for example, a storage class memory device (e.g., a flash memory, a hard disk drive, a solid state drive, a phase change memory (PCM), or a 3D XPoint TM of memory).

[0034] Processor 110 is operably coupled to cache memory 112, which is operably coupled to memory controller 114. Processor 110 is also directly or indirectly coupled to memory controller 114. Host device 104 may include other components to form, for example, a single chip system (SoC). Processor 110 may include a general purpose processor, a central processing unit, a graphics processing unit (GPU), a neural network engine or accelerator, an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) integrated circuit (IC), or a communication processor (e.g., a modem or baseband processor).

[0035] In operation, the memory controller 114 may provide a high-level or logical interface between the processor 110 and at least one memory, such as an external memory. The memory controller 114 may be implemented with any of a variety of suitable memory controllers, such as a double data rate (DDR) memory controller that can process requests for data stored on the memory device 108. Although not shown, the host device 104 may include a physical interface (PHY) that transmits data between the memory controller 114 and the memory device 108 through the interconnect 106. For example, the physical interface may be an interface compatible with the DDR PHY interface (DFI) group interface protocol. The memory controller 114 may, for example, receive memory requests from the processor 110 and provide the memory requests to the external memory with appropriate formatting, timing, and reordering. The memory controller 114 may also forward responses to memory requests received from the external memory to the processor 110.

[0036] The memory controller 114 may also receive an alert signal from the memory device 108 via the interconnect 106. For example, the alert signal may indicate that the memory device 108 has detected a UBD condition and / or a memory request error, such as a cyclic redundancy check (CRC) error in read or write data. The memory controller 114 may pass such alerts to the processor 110 or may handle such alerts directly.

[0037] The host device 104 is operably coupled to the memory device 108 via the interconnect 106. In some examples, the memory device 108 is connected to the host device 104 via the interconnect 106 with an intervening buffer or cache. The memory device 108 is operably coupled to a storage memory (not shown). The host device 104 may also be coupled to the memory device 108 and the storage memory directly or indirectly via the interconnect 106. The interconnect 106 and other interconnects (not illustrated in FIG. 1 ) may transfer data between two or more components of the apparatus 102. Examples of the interconnect 106 include a bus (e.g., a unidirectional or bidirectional bus), a switch fabric, or one or more conductors carrying voltage or current signals. The interconnect 106 may propagate one or more communications 116 between the host device 104 and the memory device 108. For example, the host device 104 may transmit a memory request to the memory device 108 via the interconnect 106. The memory device 108 may also transmit a corresponding memory response to the host device 104 via the interconnect 106.

[0038] The illustrated components of the device 102 represent an example architecture with a hierarchical memory system. The hierarchical memory system may include memory at different levels, where each level has memory with different speeds or capacities. As illustrated, cache memory 112 logically couples the processor 110 to the memory device 108. In the illustrated implementation, the cache memory 112 is at a higher level than the memory device 108. The storage memory, in turn, may be at a lower level than the main memory (e.g., the memory device 108). The memory at a lower hierarchical level may have a reduced speed but increased capacity relative to the memory at a higher hierarchical level.

[0039] The apparatus 102 may be implemented in various ways with more, fewer, or different components. For example, the host device 104 may include multiple cache memories (e.g., including multiple levels of cache memories) or no cache memories. In other embodiments, the host device 104 may omit the processor 110 or the memory controller 114. A memory (e.g., the memory device 108) may have an "internal" or "local" cache memory. As another example, the apparatus 102 may include a cache memory between the interconnect 106 and the memory device 108. Computer engineers may also include any of the illustrated components in a distributed or shared memory system.

[0040] Computer engineers can implement host device 104 and various memories in a variety of ways. In some cases, host device 104 and memory device 108 can be disposed on or physically supported by a printed circuit board (e.g., a rigid or flexible motherboard). Host device 104 and memory device 108 can additionally be integrated together on an integrated circuit or fabricated on separate integrated circuits and packaged together. Memory device 108 can also be coupled to multiple host devices 104 via one or more interconnects 106 and can respond to memory requests from two or more host devices 104. Each host device 104 can include a respective memory controller 114, or multiple host devices 104 can share a memory controller 114. This file references Figure 1A An example computing system architecture is described having at least one host device 104 coupled to a memory device 108 .

[0041] Two or more memory components (e.g., modules, dies, banks, or groups of banks) may share an electrical path or coupling of the interconnect 106. The interconnect 106 may include at least one command and address bus (CA bus) and at least one data bus (DQ bus). The command and address bus may transmit addresses and commands from the memory controller 114 of the host device 104 to the memory device 108, which may exclude propagating data. The data bus may propagate data between the memory controller 114 and the memory device 108. The memory device 108 may also be implemented as any suitable memory, including, but not limited to, DRAM, SDRAM, 3D stacked DRAM, DDR memory, or LPDDR memory (e.g., LPDDR DRAM or LPDDR SDRAM).

[0042] Memory device 108 may form at least part of the main memory of apparatus 102. However, memory device 108 may form at least part of cache memory, storage memory, or a single-chip system of apparatus 102. Memory device 108 includes UBD circuitry 118, error detection circuitry 120, alarm circuitry 122, and alarm leads 124, which may be implemented as part of interconnect 106. UBD circuitry 118, error detection circuitry 120, and alarm circuitry 122 may be implemented using software, firmware, hardware, fixed logic circuitry, or a combination thereof. These circuitry and alarm leads 124 enable memory device 108 to report different types of alarms to memory controller 114.

[0043] Throughout this disclosure, the terms "alarm" and "error" are both used to generally refer to the detection of an undesirable event or condition. For purposes of explanation, the term "alarm" is used to indicate an event associated with UBD mitigation, and the term "error" is used to indicate an event associated with other non-UBD related operations of the memory device 108 (e.g., operations not related to UBD mitigation).

[0044] The UBD circuitry 118 mitigates UBD of one or more memory banks associated with the memory device 108. The UBD circuitry 118 may include at least one counter circuit for detecting UBD, at least one queue for managing refresh operations to mitigate UBD, and / or at least one error correction code (ECC) circuit for detecting and / or correcting bit errors associated with UBD. The UBD circuitry 118 also includes components for detecting and reporting alarms associated with UBD.

[0045] Error detection circuitry 120 detects another type of error that is unrelated to UBD or the process of mitigating UBD. In some cases, this error is associated with normal data read from or written to memory device 108. Example errors may include cyclic redundancy check (CRC) errors in read or written data. In general, errors detected by error detection circuitry 120 may indicate to memory controller 114 that there is a problem with the operation of memory device 108 involving normal data.

[0046] Rather than having separate leads for communicating different alarms from the UBD circuitry 118 and the error detection circuitry 120, the alarm lead 124 handles both. The alarm lead 124 may be a pad that is operable in a high voltage default state and is placed in a low voltage state to output a signal indicative of an alarm. Because the alarm lead 124 is used to communicate multiple alarms reported by different components of the memory device 108, the alarm lead 124 may be referred to as a restricted interface. Furthermore, because the alarms detected by these components may occur independently of one another, conflicts may arise when multiple alarms / errors are reported during the same time interval.

[0047] To address this issue, memory device 108 includes alarm circuitry 122 that manages the communication of these alarms via alarm lead 124. Alarm circuitry 122 serves as an interface between two or more alarm generating components (e.g., UBD circuitry 118 and error detection circuitry 120) and alarm lead 124. These circuits are related to Figure 1B Further description.

[0048] Figure 1B An example memory device 108 is illustrated. In the depicted configuration, the outputs of the UBD circuitry 118 and the error detection circuitry 120 are coupled to different inputs of the alarm circuitry 122. An alarm lead 124 is coupled to the output of the alarm circuitry 122. The UBD circuitry 118 includes components distributed at the bank level and the die level, as described with respect to FIG. Figure 3 Further described. UBD circuitry 118 may optionally include backoff circuitry 126 . Backoff circuitry 126 prevents subsequent generation of UBD alert signal 128 from affecting timing parameters associated with alert lead 124 .

[0049] During operation of the memory device 108, the UBD circuitry 118 performs an array counter update procedure that monitors how often rows of memory cells are activated. If the activation count of an activated row meets or exceeds a threshold, then the adjacent rows including one or more neighboring rows may face an increased risk of data corruption due to repeated activation of accessed rows and usage-based disturb effects. To manage this risk for affected rows, the UBD circuitry 118 adds this aggressor row to a queue and refreshes one or more victim rows associated with the queued aggressor row through the queue.

[0050] The UBD circuit system 118 may be designed to report one or more UBD-related alarm events to the memory controller 114 via the alarm circuit system 122 and the alarm lead 124. A first example UBD-related alarm event involves the UBD circuit system 118 determining that an activation row has an activation count that exceeds a first threshold. A second example UBD-related alarm event involves the UBD circuit system 118 determining that the number of times the activation row exceeds the first threshold is greater than a second threshold. A third example UBD-related alarm event involves the UBD circuit system 118 detecting a parity error associated with the activation count. A fourth example UBD-related alarm event involves the UBD circuit system 118 determining that a queue is full. In general, the UBD circuit system 118 generates a UBD alarm signal 128 to indicate the detection of any type of event (or condition) associated with UBD or UBD mitigation. The UBD alarm signal 128 may also be referred to as a die-level UBD alarm signal, such as with respect to Figure 4A To B for further description.

[0051] Error detection circuitry 120 monitors for other errors associated with normal operation of memory device 108 (e.g., associated with reading or writing data). In some cases, error detection circuitry 120 detects an error and communicates this error to alarm circuitry 122 using error detection signal 130. Error detection circuitry 120 may perform various memory-related error detection techniques. For example, error detection circuitry 120 may generate a CRC checksum for transmission with outgoing read data. Error detection circuitry 120 may check the received CRC checksum against incoming write data, in which case error detection circuitry 120 may generate a CRC error detection signal after a CRC failure. As another example, error detection circuitry 120 may perform a parity check or other data-related error check and generate a corresponding error detection signal.

[0052] Alarm circuitry 122 provides an alarm signal 132 to alarm lead 124 . Alarm signal 132 is based on UBD alarm signal 128 generated by UBD circuitry 118 and error detection signal 130 generated by error detection circuitry 120 .

[0053] During a first time interval, the alarm circuit system 122 outputs a first alarm signal 132 based on the UBD alarm signal 128 via the alarm lead 124. During a second time interval, the alarm circuit system 122 outputs a second alarm signal 132 based on the error detection signal 130 received from the error detection circuit system 120 via the alarm lead 124. During a third time interval, the alarm circuit system 122 outputs a third alarm signal 132 based on some combination of the UBD alarm signal 128 and the error detection signal 130 via the alarm lead 124. In some examples, the first, second, and / or third alarm signals 132 have different pulse lengths, wherein a first pulse length (i.e., of the first alarm signal) indicates a UBD alarm event, a second pulse length (i.e., of the second alarm signal) indicates an error-associated event, and a third pulse length (i.e., of the third alarm signal) indicates both the UBD alarm signal 128 and the error detection signal 130. Different implementations of the alarm circuit system 122 may treat concurrent receipt of the UBD alarm signal 128 and the error detection signal 130 in various ways. Figure 5A 6A to D and 6A to D respectively illustrate the combination and sequence examples of the alarm circuit system 122. The memory device 108 is related to Figure 2 Further description.

[0054] Figure 2 An example computing system 200 is illustrated in which aspects of UBD alert signaling may be implemented. In some implementations, the computing system 200 includes at least one memory device 108, at least one interconnect 106, and at least one processor 202. The memory device 108 may include or be associated with at least one memory array 204, at least one interface 206, and a central circuit system 208 (or peripheral circuit system) operably coupled to the memory array 204. The memory array 204 may include an array of memory cells, including, but not limited to, memory cells of DRAM, SDRAM, 3D stacked DRAM, DDR memory, LPDDR SDRAM, etc. The memory array 204 may be organized into one or more bank-level groupings, such as banks, sub-banks, or groups of banks. The memory array 204 and the central circuit system 208 may be components on a single semiconductor die or separate semiconductor dies. The memory array 204 and / or the central circuit system 208 may also be distributed across multiple dies. The central circuit system 208 may manage traffic on a bus separate from the interconnect 106.

[0055] The central circuitry 208 may include various components that the memory device 108 may use to perform various operations. These operations may include communicating with other devices, managing memory performance, performing refresh operations (e.g., self-refresh operations or auto-refresh operations), and performing memory read or write operations. For example, the central circuitry 208 may include array control logic 210, clock circuitry 212, registers 214, at least a portion of the UBD circuitry 118, error detection circuitry 120, and at least one instance of the alarm circuitry 122.

[0056] Array control logic 210 may include circuitry that provides command decoding, address decoding, input / output functions, amplification circuitry, power supply management, power control modes, and other functions. Clock circuitry 212 may utilize one or more external clock signals (including command and address clocks or data clocks) provided via interconnect 106 to synchronize various memory components. Clock circuitry 212 may also use internal clock signals to synchronize memory components and may provide timer functionality. Registers 214 may store various configuration and state data. For example, registers 214 may store timing parameters, configuration information that activates or deactivates specific functionality, or various state data.

[0057] The illustrated example of the UBD circuit system 118 includes a die-level UBD alarm circuit system 218 and a bank-level UBD alarm circuit system 220. The bank-level UBD alarm circuit system 220 detects alarms associated with mitigating UBD at the bank level. In contrast, the die-level UBD alarm circuit system 218 detects alarms at the die level based on alarms received from the bank-level UBD alarm circuit system 220. The die-level UBD alarm circuit system 218 may be implemented within the central circuit system 208. Another example of the UBD circuit system 118, including the die-level UBD alarm circuit system 218 and the bank-level UBD alarm circuit system 220, is related to Figure 3 Give a description.

[0058] Central circuitry 208 also includes error detection circuitry 120. In various implementations, error detection circuitry 120 may store information about error detection operations in registers in registers 214. For example, error detection circuitry 120 may set a flag bit at a predefined error status address in registers 214 after detecting an error.

[0059] The interface 206 may couple the central circuitry 208 or the memory array 204 directly or indirectly to the interconnect 106. In some implementations, the UBD circuitry 118, the error detection circuitry 120, the alarm circuitry 122, the array control logic 210, and the clock circuitry 212 may be parts of a single component, such as the central circuitry 208. In other implementations, one or more of the UBD circuitry 118, the error detection circuitry 120, the alarm circuitry 122, the array control logic 210, or the clock circuitry 212 may be implemented as separate components that may be provided on a single semiconductor die or disposed across multiple semiconductor dies. For example, Figure 3 An example is illustrated in which the UBD circuitry 118 includes die-level UBD alert circuitry 218 and bank-level UBD alert circuitry 220. These components may be coupled to the interconnect 106 via the interface 206, either individually or jointly.

[0060] The interconnect 106 may use one or more of a variety of interconnects that communicatively couple the various components together and enable commands, addresses, or other information and data to be transferred between two or more components (e.g., between the memory device 108 and the processor 202). Figure 2 Although illustrated with a single line in FIG. 1 , the interconnect 106 may include at least one bus, at least one switching fabric, one or more wires or traces carrying voltage or current signals, at least one switch, one or more buffers, etc. Furthermore, the interconnect 106 may be separated into at least a command and address bus and a data bus.

[0061] In some aspects, the memory device 108 may be relative to ( Figure 1A The memory device 108 may be a "separate" component of any of the host device 104 or the processor 202 (or any of the host devices 104 or the processor 202). The separate components may include a printed circuit board, a memory card, a memory stick, and a memory module (e.g., a single in-line memory module (SIMM) or a dual in-line memory module (DIMM)). Thus, the separate physical components may be located together within the same housing of an electronic device or may be distributed across a server rack, a data center, and the like. Alternatively, the memory device 108 may be integrated with other physical components including the host device 104 or the processor 202 by being combined on a printed circuit board or in a single package or single chip system.

[0062] like Figure 21, processor 202 may include a computer processor 202-1, a baseband processor 202-2, and an application processor 202-3 coupled to memory device 108 via interconnect 106. Processor 202 may include or form part of a central processing unit, a graphics processing unit, a single chip system, an application specific integrated circuit, or a field programmable gate array. In some cases, a single processor may include multiple processing resources each dedicated to a different function (e.g., modem management, applications, graphics, central processing). In some implementations, baseband processor 202-2 may include or be coupled to a modem ( Figure 2 Modem or baseband processor 202-2 may be implemented via, for example, cellular, Near field or another technology or protocol for wireless communication to wirelessly couple to the network.

[0063] In some implementations, processors 202 may be directly connected to memory devices 108 (e.g., via interconnect 106). In other implementations, one or more of processors 202 may be indirectly connected to memory devices 108 (e.g., via a network connection or through one or more other devices). Memory devices 108 (including UBD circuitry 118) may be connected to memory devices 108 (e.g., via a network connection or through one or more other devices). Figure 3 Further description.

[0064] Example Technology and Hardware

[0065] Figure 3 An example memory device 108 is illustrated in which aspects of UBD alert signaling may be implemented. The memory device 108 includes a memory module 302, which may include a plurality of dies 304. As illustrated, the memory module 302 includes a first die 304-1, a second die 304-2, a third die 304-3, and a D-th die 304-D, where D represents a positive integer.

[0066] The memory module 302 may be a SIMM or a DIMM. As another example, the memory module 302 may be interconnected via a bus (e.g., a peripheral component interconnect fast bus) to connect to other components. Figure 1A and 2 The memory device 108 illustrated in may, for example, correspond to a plurality of dies 304-1 through 304-D or a memory module 302 having two or more dies 304. As shown, the memory module 302 may include one or more electrical contacts 306 (eg, pins) to interface the memory module 302 to other components.

[0067] Memory module 302 can be implemented in various ways. For example, memory module 302 can include a printed circuit board, and multiple dies 304-1 to 304-D can be mounted or otherwise attached to the printed circuit board. Dies 304 (e.g., memory dies) can be arranged in rows or arranged along two or more dimensions (e.g., forming a grid or array). Dies 304 can have similar sizes or can have different sizes. Each die 304 can be similar to another die 304 or different in size, shape, data capacity, or control circuitry. Dies 304 can also be positioned on a single side or multiple sides of memory module 302.

[0068] One or more of the dies 304-1 to 304-D may include UBD circuitry 118. In this example, each die 304-1 to 304-D includes N memory banks 308-1, 308-2 to 308-N (referred to as memory banks 308 or memory banks 308-i), where N represents a positive integer. Each memory bank 308-i includes an independently addressable or accessible array of memory cells organized into rows. In various examples, each memory bank 308-i includes dedicated memory bank-level circuitry, such as sense amplifiers, precharge circuits, column address circuitry, buffers, or routing circuitry. The memory banks 308-1 to 308-N further include corresponding examples of memory bank-level UBD alert circuitry 220-1, 220-2, ..., 220-N (referred to as circuitry 220 or circuitry 220-i).

[0069] Each bank-level UBD alert circuitry 220-i detects the occurrence of a UBD alert condition on its respective bank 308-i. In some implementations, each bank-level UBD alert circuitry 220-i generates a respective bank-level UBD alert signal in response to the detected UBD alert condition. For example, the bank-level UBD alert circuitry 220 may generate a respective bank-level UBD alert signal when the corresponding queue is full. This condition may be resolved by different actions or events that clear the bank-level UBD alert signal.

[0070] In some embodiments, the bank-level UBD alert circuitry 220 may include circuitry that is shared between multiple memory banks 308 (e.g., groups of memory banks). In some embodiments, the bank-level UBD alert circuitry 220 may include multiple instances within a given memory bank 308. For example, there may be an instance of the bank-level UBD alert circuitry 220-i for each sub-bank of each memory bank 308. The bank-level UBD alert circuitry 220 is communicatively coupled to the die-level UBD alert circuitry 218.

[0071] The die-level UBD alert circuitry 218 detects the die-level UBD condition in response to the presence of the bank-level UBD condition. In some embodiments, the die-level UBD alert circuitry 218 may generate a die-level UBD alert signal in response to detecting the presence of the bank-level UBD condition. Figure 4A and 4B Further description.

[0072] Figure 4A Example circuitry that implements aspects of UBD alert signaling is described. For example, the described circuitry can be a component of a memory model, such as a Figure 3 Memory module 302 is depicted. Example circuitry includes banks 308-1 through 308-N, UBD circuitry 118, error detection circuitry 120, alert circuitry 122, and alert leads 124. UBD circuitry 118 includes die-level UBD alert circuitry 218 and bank-level UBD alert circuitry 220-1 through 220-N.

[0073] In the depicted configuration, die-level UBD alert circuitry 218 includes a common signal bus 402 and an output 404. Die-level UBD alert circuitry 218 may include driver circuitry for driving a voltage of common signal bus 402. Bank-level UBD alert circuitry 220-1 through 220-N include respective outputs 406-1 through 406-N (collectively, bank-level UBD alert circuitry 220 has output 406; individually, bank-level UBD alert circuitry 220-i has output 406-i). Error detection circuitry 120 includes output 408.

[0074] A common signal bus 402 couples the outputs 406-1 through 406-N of the bank-level UBD alert circuitry 220 to the output 404 of the die-level UBD alert circuitry 218. In some implementations, the common signal bus 402 may be connected to ground, and each output 406-i includes circuitry that may drive the common signal bus 402 to a signal voltage. Other implementations are also possible in which the die-level UBD alert circuitry 218 is implemented as a multiplexer and the outputs 406 of the bank-level UBD alert circuitry 220 are directly coupled to the inputs of the alert circuitry 122.

[0075] As illustrated, the alarm circuitry 122 is coupled to the output 404 of the die-level UBD alarm circuitry 218, the output 408 of the error detection circuitry 120, and the alarm lead 124. As discussed above, different circuitry implementations of the alarm circuitry 122 may combine the UBD alarm signal 128 and the error detection signal 130 in different ways to generate the alarm signal 132.

[0076] During operation, each bank-level UBD alert circuitry 220-i may detect a UBD alert event within its respective bank 308-i and generate a respective bank-level UBD alert signal 410-1 through 410-N (referred to as a bank-level UBD alert signal 410 or a bank-level UBD alert signal 410-i). The bank-level UBD alert signal 410-i (or more specifically, the state of the bank-level UBD alert signal 410-i) may indicate the detection of a UBD alert event. The UBD alert events detected by the bank-level UBD alert circuitry 220 are independent of each other. Thus, any two of the bank-level UBD alert circuitry 220 may detect UBD alert events in different time intervals or during the same time interval.

[0077] The die-level UBD alert circuitry 218 generates a die-level UBD alert signal 412 based on the bank-level UBD alert signals 410. In this example, the die-level UBD alert signal 412 represents a combination (e.g., a logical OR) or a summation of the bank-level UBD alert signals 410. In general, the die-level UBD alert signal 412 indicates the detection of a UBD alert event within at least one of the banks 308 to which the die-level UBD alert circuitry 218 is connected. The die-level UBD alert circuitry 218 outputs the die-level UBD alert signal 412 as the UBD alert signal 128.

[0078] In addition, the die-level UBD alert signal 412 can meet various constraints or characteristics. For example, the die-level UBD alert signal 412 can be synchronized to a clock signal, have a length that indicates an alert event type, or meet various timing parameters, such as a maximum alert signal length or an alert backoff timing requirement. Another example of the die-level UBD alert circuitry 218 is related to Figure 7 The example states of the bank-level UBD alert signal 410 and the die-level UBD alert signal 412 are as follows: Figure 4B Further description.

[0079] Figure 4BExample bank-level UBD alert signals 410-i and 410-j and die-level UBD alert signal 412 are illustrated. In this example, bank-level UBD alert signals 410-i and 410-j and die-level UBD alert signal 412 may have voltages representing an alert state 414 or a non-alert state 416, which may also be referred to as a default state. Alert state 414 and non-alert state 416 may represent different aspects of UBD alert signaling, as further described below.

[0080] In an example embodiment, the alarm state 414 of the bank-level UBD alarm signal 410-i or 410-j indicates that an alarm event is detected by the corresponding bank-level UBD alarm circuitry 220-i or 220-j. In contrast, the non-alarm state 416 of the bank-level UBD alarm signal 410-i or 410-j indicates that an alarm event is not detected by the corresponding bank-level UBD alarm circuitry 220-i or 220-j.

[0081] The alarm state 414 of the die-level UBD alarm signal 412 indicates that at least one of the bank-level UBD alarm signals 410-i and 410-j is in the alarm state 414. The non-alarm state 416 of the die-level UBD alarm signal 412 indicates that all bank-level UBD alarm signals 410-i and 410-j are in the non-alarm state 416.

[0082] exist Figure 4B In the example shown in , the alarm state 414 represents a high voltage (e.g., supply voltage), and the non-alarm state 416 represents a low voltage (e.g., ground). Other examples may utilize other signaling voltage states (e.g., low voltage indicates the alarm state 414 and high voltage indicates the non-alarm state 416) or may utilize other signaling techniques.

[0083] Consider the example signals shown at 418. Prior to time t1, the bank-level UBD alert circuitry 220-i and 220-j did not detect a UBD alert event. Thus, the bank-level UBD alert circuitry 220-i and 220-j generates bank-level UBD alert signals 410-i and 410-j having a non-alert state 416. The die-level UBD alert signal 412 is also in the non-alert state 416 based on the bank-level UBD alert signals 410-i and 410-j being in the non-alert state 416.

[0084] At time t1, the bank-level UBD alert circuitry 220-j detects a UBD alert event and generates a bank-level UBD alert signal 410-j having an alert state 414. In other words, the output 406-j of the bank-level UBD alert circuitry 220-j induces the alert state 414 at time t1. The bank-level UBD alert circuitry 220-i does not detect a UBD alert event. Thus, the bank-level UBD alert signal 410-i remains in a non-alert state 416. Because the bank-level UBD alert signal 410-j is in the alert state 414, the state of the die-level UBD alert signal 412 changes from the non-alert state 416 to the alert state 414.

[0085] At time t2, the bank-level UBD alert circuitry 220-i detects the UBD alert event and generates the bank-level UBD alert signal 410-i having the alert state 414. In other words, the output 406-i of the bank-level UBD alert circuitry 220-i induces the alert state 414 at time t2. The die-level UBD alert signal 412 remains in the alert state 414.

[0086] At time t3, the UBD alert event detected by the bank-level UBD alert circuitry 220-j is cleared. As a result, the bank-level UBD alert circuitry 220-j generates a bank-level UBD alert signal 410-j having a non-alert state 416. In other words, the bank-level UBD alert circuitry 220-j stops inducing the alert state 414, thereby allowing its output 406-j to return to the non-alert state 416. Because the bank-level UBD alert signal 410-i is still in the alert state 414, the die-level UBD alert signal 412 remains in the alert state 414.

[0087] Alert circuitry 122 may be implemented in a variety of different ways to communicate the information provided by die-level UBD alert signal 412 to alert lead 124 . Figure 5A 6A to D and 6A to D illustrate a combination example and a sequential example of the alarm circuit system 122, respectively.

[0088] Figure 5A Example circuitry for UBD alert signaling is illustrated including an example of alert circuitry 122 implemented as combined alert circuitry 502 . Figures 5B to 5D Examples of input and output signals of the combined alarm circuit system 502 in various timing scenarios 500-1, 500-2, and 500-3 are described respectively. Figure 5A, combined alarm circuitry 502 is coupled to output 404 of UBD circuitry 118 and output 408 of error detection circuitry 120. Combined alarm circuitry 502 receives UBD alarm signal 128 from UBD circuitry 118 and error detection signal 130 from error detection circuitry 120. In some cases, combined alarm circuitry 502 receives UBD alarm signal 128 by, for example, monitoring a voltage at output 404 via a signal line connecting output 404 to combined alarm circuitry 502. In some implementations, UBD alarm signal 128 indicates information about an error. Figure 4A B. The combined alarm circuitry 502 may also receive the error detection signal 130 by monitoring the voltage at the output 408 , for example, via a signal line connecting the output 408 to the combined alarm circuitry 502 .

[0089] The UBD alarm signal 128, the error detection signal 130, and the alarm signal 132 may be voltage modulated signals having different voltages to indicate an alarm state 414 and a non-alarm state 416 (e.g., a default state). For example, the UBD alarm signal 128 and the error detection signal may use a high voltage (e.g., a supply voltage) to indicate the alarm state 414 and a low voltage (e.g., a ground voltage) to indicate the non-alarm state 416. In other embodiments, the voltage states may be reversed, with the low voltage indicating the alarm state 414. The alarm state 414 of the UBD alarm signal 128 may be referred to as a UBD alarm state, while the alarm state 414 of the error detection signal 130 may be referred to as an error detection state.

[0090] In the example example, the pulse length and timing of the alarm state 414 within the UBD alarm signal 128 (e.g., the pulse length is equal to t4-t2 at 500-1, equal to t4-t1 at 500-2, and equal to t4-t3 at 500-3) are controlled by the UBD circuitry 118. The UBD circuitry 118 can establish the pulse length and synchronize the UBD alarm signal 128 to the internal clock signal provided by the clock circuitry 212. This example of the UBD circuitry 118 is related to Figure 7 Similar to UBD circuitry 118 , error detection circuitry 120 establishes the pulse length and timing of alarm state 414 within error detection signal 130 .

[0091] The combined alarm circuitry 502 combines the UBD alarm signal 128 with the error detection signal 130 to generate the alarm signal 132. The combined alarm circuitry 502 may include one or more logic gates configured to generate the alarm signal 132. The combined alarm circuitry 502 may include other circuitry configured to perform additional operations to generate the alarm signal 132. In this example, the combined alarm circuitry 502 includes a logic gate configured to perform a digital 'NOR' operation on the received signals 128 and 132. The combined alarm circuitry 502 also includes inversion circuitry to cause the alarm signal 132 to have a low voltage (e.g., ground voltage) to indicate the alarm state 414 and a high voltage (e.g., supply voltage) to indicate the non-alarm state 416.

[0092] The alarm lead 124 may be at a high voltage during normal operation when no alarm is present. For example, the alarm lead 124 may include circuitry, such as a pull-up resistor, to connect the voltage on the alarm lead 124 to a supply voltage during normal operation. The combined alarm circuitry 502 includes circuitry, such as a driver circuitry, for inducing the alarm state 414 at the alarm lead 124. For example, the combined alarm circuitry 502 may include a driver circuitry to drive the alarm lead 124 to a ground voltage to induce the alarm state 414. Example timing and states of the UBD alarm signal 128, the error detection signal 130, and the alarm signal 132 (generated by the combined alarm circuitry 502) with respect to Figure 5B To D for further description.

[0093] Figure 5B A first example timing diagram 500-1 is illustrated in which the alarm states 414 of the UBD alarm signal 128 and the error detection signal 130 partially overlap during a common time interval. As illustrated, the error detection signal 130 is received with pulses from time t1 until t3, and the UBD alarm signal 128 is received with pulses from time t2 until t4. The pulses within the UBD alarm signal 128 and the error detection signal 130 represent periods in which the UBD circuitry 118 and the error detection circuitry 120 detect an alarm / error event and communicate the alarm state 414.

[0094] In this example, during a common time interval from t2 until t3, the pulse length of the error detection signal 130 partially overlaps with the pulse length of the UBD alert signal 128. The combined alert circuitry 502 generates an alert signal 132 having an alert state 414 from t1' until t4' based on the error detection signal 130 and the UBD alert signal 128, where the prime indicates that the output time may be the same as the input time (i.e., within the same clock cycle) or may be delayed from the input time (e.g., delayed by several clock cycles or a few nanoseconds). The alert signal 132 has a pulse length equal to the non-overlapping alert state 414 of the UBD alert signal 128 plus the overlapping alert state 414 of the error detection signal 130 (i.e., pulse length = (t2 - t1) + (t3 - t2) + (t4 - t3)). The resulting alert signal 132 is in the alert state 414 for a period of time longer than either of the input signals 128 or 130.

[0095] In some examples (e.g., embodiments where both the UBD alert signal 128 and the error detection signal 130 have fixed pulse lengths), the longer pulse length of the alert signal 132 may indicate the presence of both a UBD-related alert event and an error-related event. In other examples (e.g., embodiments where the pulse length of the UBD alert signal 128 indicates the count of UBD-related alert events), the longer pulse length may indicate the presence of at least one UBD-related alert event and a possible error-related event. In this case, a component that detects the alert lead 124 (e.g., the memory controller 114) may further interact with the memory device 108 to determine which alerts are present. For example, the memory controller 114 may read a register 214 that stores the error detection status to determine whether the memory device 108 is experiencing an error-related event.

[0096] Figure 5C Illustrate a second example timing diagram 500-2 where the alert states 414 of the UBD alert signal 128 and the error detection signal 130 completely overlap during a common time interval. As illustrated, the UBD alert signal 128 is in the alert state 414 from time t1 until time t4. The error detection signal 130 is in the alert state 414 from time t2 until time t3, where t1 < t2 and t3 < t4. Thus, the pulse of the error detection signal 130 is completely overlapped by the pulse of the UBD alert signal 128. The resulting alert signal 132 is in the alert state 414 from t1' until t4' and has a pulse length equal to the pulse length of the UBD alert signal 128. In this case, the error detection signal 130 is masked by the UBD alert signal 128. Thus, the alert signal 132 indicates a UBD-related alert event and a possible error-related event. As discussed above, the memory controller 114 may further communicate with the memory device 108 to determine whether there is also an error-related event in addition to the UBD-related alert event.

[0097] Figure 5D A third example timing diagram 500-3 is illustrated in which the alarm states 414 of the UBD alarm signal 128 and the error detection signal 130 occur during non-overlapping time intervals. When the UBD alarm signal 128 and the error detection signal 130 are sequentially in the alarm state 414 in a sequential manner, the combined alarm circuit system 502 generates an alarm signal 132 having the alarm state 414 in the same sequence. In the illustrated example, the error detection signal 130 is in the alarm state 414 from time t1 until time t2. Subsequently, the UBD alarm signal 128 is in the alarm state 414 from time t3 until time t4. The resulting alarm signal 132 includes a first pulse based on the pulse of the error detection signal 130 and a second pulse based on the pulse of the UBD alarm signal 128. Similarly, if the UBD alarm signal 128 is received before the error detection signal 130 and there is no overlap, the alarm signal 128 has a first pulse based on the pulse of the UBD alarm signal 128 and a second pulse based on the pulse of the error detection signal 130.

[0098] In some examples, the inactivity period between the first and second pulses of the alarm signal 132 may provide an indication of multiple alarm conditions without requiring the memory controller 114 to evaluate the register 214. In other examples, the time between the first and second pulses of the alarm signal 132 may be too short and result in a glitching. Although the combined alarm circuit system 502 may be relatively simple to implement, the ambiguity in the alarm signal 132 in examples 500-1 and 500-2 and the possible glitches in example 500-3 may be explained using the information about the alarm condition. Fig. 6A Another type of implementation scheme further described in D is addressed.

[0099] Fig. 6A Example circuitry for UBD alert signaling is illustrated including an example of alert circuitry 122 implemented as sequential alert circuitry 602 . Figures 6B to 6D Examples of input and output signals of the sequence alarm circuit system 602 in various timing scenarios 600-1, 600-2, and 600-3 are illustrated. Figure 5A Compared with the combined alarm circuit system 502, Fig. 6AThe sequential alarm circuitry 602 has additional logic to arbitrate conflicts and reduce the probability of glitches. For example, the sequential alarm circuitry 602 may include delay circuitry that ensures that alarms / errors indicated during overlapping time intervals are reported in a sequential manner with inactive periods between reports. More specifically, the sequential alarm circuitry 602 outputs multiple signal pulses indicating detection of multiple alarm / error events and separates these pulses with inactive periods to avoid glitches. Thus, when both the UBD alarm signal 128 and the error detection signal 130 are in the alarm state 414 during a common time interval, the alarm signal 132 provides indications of the two alarm states 414 during different time intervals.

[0100] like Fig. 6A , the sequence alarm circuit system 602 is coupled to the output 404 of the UBD circuit system 118 and the output 408 of the error detection circuit system 120. The sequence alarm circuit system 602 can be connected to the output 404 of the UBD circuit system 118 and the output 408 of the error detection circuit system 120. Figure 5A The combined alarm circuitry 502 receives the UBD alarm signal 128 from the UBD circuitry 118 and the error detection signal 130 from the error detection circuitry 120 in a manner similar to that described above. Fig. 6A The UBD alarm signal 128 and the error detection signal 130 depicted in FIG. 1 may have the same state, such as with respect to FIG. Figure 5A To D description.

[0101] The sequential alarm circuitry 602 combines the UBD alarm signal 128 with the error detection signal 130 to generate the alarm signal 132. The sequential alarm circuitry 602 may include circuitry such as logic gates, buffers, delay circuitry, or edge-triggered flip-flops. The sequential alarm circuitry 602 is configured to output a sequence of signal pulses based on receiving a plurality of errors / alarms during an arbitration period 604. The arbitration period 604 defines a period in which the UBD alarm signal 128 and the error detection signal 130 may be in the alarm state 414 and the alarm signal 132 may be generated as a plurality of output pulses. Signals received simultaneously outside of the arbitration period 604 may be masked.

[0102] In some implementations, the arbitration period 604 and / or the delay period d may be programmable parameters, such as parameters stored in registers 214 and programmable by the memory controller 114. For example, the arbitration period 604 may be defined as twice the pulse length of the error detection signal 130. In other implementations, these parameters may be predefined.

[0103] Other timing parameters may be set to accommodate sequential pulse transmissions. For example, the memory device 108 may have a parameterized timing setting that defines the maximum allowed time (e.g., t_CRC) in which the error detection signal 130 will be sent after an error is detected. In this example, t_CRC may include the arbitration period 604, the delay period d, and the period for performing error detection. In some implementations, the UBD alert signal 128 may have similar timing requirements that may be set to include potential delays caused by previous error / alert signals.

[0104] The sequential alarm circuit system 602 may perform other operations on the incoming signal to generate an outgoing signal. In an example embodiment, the sequential alarm circuit system 602 includes an inversion circuit system that causes the resulting alarm signal 132 to have a low voltage (e.g., ground voltage) to indicate the alarm state 414 and a high voltage to indicate the non-alarm state 416. The alarm lead 124 may be at a high voltage during normal operation when no alarm is present. For example, the alarm lead 124 may include a circuit system that connects the voltage on the alarm lead 124 to a supply voltage during normal operation, such as a pull-up resistor. The sequential alarm circuit system 602 includes a circuit system for inducing the alarm state 414 at the alarm lead 124, such as a driver circuit system. For example, the sequential alarm circuit system 602 may include a driver circuit system to drive the alarm lead 124 to a ground voltage to induce the alarm state 414. Example timing and states of the UBD alarm signal 128, the error detection signal 130, and the alarm signal 132 (generated by the sequential alarm circuit system 602) with respect to Figure 6B To D for further description.

[0105] Figure 6B A first example timing diagram 600-1 is illustrated, which has Figure 5B The input signal timing is similar to that of 500-1. Figure 6B , the UBD alarm signal 128 and the error detection signal 130 are in the alarm state 414 in a partially overlapping manner within the arbitration period 604. As illustrated, the arbitration period 604 is defined as being shorter than the pulse length of the UBD alarm signal 128. The sequential alarm circuitry 602 generates the alarm signal 132 with two signal pulses 606-1 and 606-2 separated by a delay period d. The two signal pulses 606-1 and 606-2 represent two examples in which the alarm signal 132 is in the alarm state 414. This is different from the alarm signal 132 including a single pulse generated by the combined alarm circuitry 502 at 500-1.

[0106] To further explain, the UBD alarm signal 128 has a pulse indicating the alarm state 414 from time t2 until t4, and the error detection signal 130 has a pulse indicating the alarm state 414 from time t1 until t3. In this example, a portion of the pulses of the UBD alarm signal 128 and the error detection signal 130 are received concurrently such that the pulse length of the error detection signal 130 overlaps the pulse length of the UBD alarm signal 128 during a common time interval from t2 until t3. The resulting alarm signal 132 includes a first pulse 606-1 from t1' until t3' and a second pulse 606-2 from t3'+d until t3'+d+(t4-t2). In other words, the second pulse 606-2 begins a delay time d after the end of the first pulse 606-1 and lasts for the pulse length of the UBD alarm signal 128. The prime sign indicates that the output time may be the same as the input time (i.e., within the same clock cycle) or may be delayed from the input time (e.g., delayed by a number of clock cycles or nanoseconds). Using two separate pulses 606-1 and 606-2, the alarm signal 132 can indicate the occurrence of both a UBD-related alarm event and an error-related event to the memory controller 114. Furthermore, because the second pulse 606-2 is delayed a sufficient amount from the first pulse 606-1, the sequential alarm circuitry 602 reduces the probability of a glitch occurring.

[0107] Figure 6C A second example timing diagram 600-2 is illustrated, which has Figure 5C The signal input timing is similar to that of 500-2. Figure 6C In the example, the UBD alarm signal 128 and the error detection signal 130 are in the alarm state 414 in a completely overlapping manner during the arbitration period 604. The combined alarm circuit system 502 masks one signal within the other (e.g., Figure 5C 500-2), the sequential alarm circuit system 602 outputs two signal pulses 606-1 and 606-2 separated by a delay time d. Therefore, the memory controller 114 receiving the alarm signal 132 can recognize the occurrence of two alarm conditions without reading the register 214.

[0108] As illustrated, the UBD alert signal 128 is in the alert state 414 from time t1 until time t4. The error detection signal 130 is in the alert state 414 within the arbitration period 604 from time t2 until time t3, where t1 < t2 and t3 < t4, such that the alert state 414 of the error detection signal 130 is completely overlapped in time by the alert state 414 of the UBD alert signal 128. The resulting alert signal 132 includes a pulse 606-1 from t1' until t4' and a pulse 606-2 from t4'+d until t4'+d+(t3-t2). In this way, the pulse 606-2 starts after the end of the pulse 606-1 by a delay time d and lasts for the pulse length of the error detection signal 130. Thus, the alert signal 132 indicates both a UBD-related alert event and an error-related event.

[0109] Fig.6D Illustrate a third example timing diagram 600-3. The UBD alert signal 128 and the error detection signal 130 are in the alert state 414 during a common time interval that extends beyond the arbitration period 604. In this case, the alert state 414 of the error detection signal 130 is masked within the alert signal 132 by the alert state 414 of the UBD alert signal 128. As illustrated, the UBD alert signal 128 is in the alert state 414 from time t1 until time t4. The error detection signal 130 is in the alert state 414 from time t2 until time t3 after the end of the arbitration period 604, where t1 < t2 and t3 < t4, such that the alert state 414 of the error detection signal 130 is completely overlapped by the alert state 414 of the UBD alert signal 128. The resulting alert signal 132 includes a pulse 606 that lasts from t1' to t4' and has a pulse length equal to the pulse length of the UBD alert signal 128.

[0110] In this example, the alert state 414 of the error detection signal 130 is masked by the alert state 414 of the UBD alert signal 128. Thus, the alert signal 132 indicates both a UBD-related alert event and a possible error-related event. As discussed above, the memory controller 114 may further communicate with the memory device 108 to determine whether there is also an error-related event in addition to the UBD event. Other embodiments may avoid this by setting the arbitration period 604 to be as long as the longest alert pulse length (e.g., the pulse length of the alert state 414 of the UBD alert signal 128), such that the corresponding outgoing signal pulses within the alert signal 132 are sent sequentially in response to any concurrent receipt of alerts / errors.

[0111] In some implementations, the UBD alert signal 128 provided via the alert lead 124 may follow a backoff timing parameter. For example, this may prevent a persistent die-level UBD alert signal 412 from appearing on the alert lead 124 when a persistent bank-level UBD alert signal 410 is present. Example implementations of the UBD circuit system 118 including the backoff circuit system 126 Figure 7 Further description.

[0112] Figure 7 An example die-level UBD alert circuitry 218 is illustrated that includes a UBD alert signal generation circuitry 702, a backoff circuitry 126, and a comparison circuitry 704. As illustrated, the backoff circuitry 126 is communicatively coupled to the UBD alert signal generation circuitry 702, the comparison circuitry 704, the array control logic 210, and / or the clock circuitry 212. The backoff circuitry 126 enables the UBD alert signal generation circuitry 702 to generate the UBD alert signal 128 in response to the bank-level UBD alert signal 410 while satisfying the timing parameters associated with the alert pin 124 (or external interface). The UBD alert signal generation circuitry 702 is coupled to the common signal bus 402 via the comparison circuitry 704.

[0113] As about Figure 4A As described in detail in FIG. 1B , the common signal bus 402 combines the bank-level UBD alert signals 410 from multiple banks 308. In some cases, the bank-level UBD alert signal 410 may continue to be in the alert state 414 for longer than the duration allowed on the alert lead 124. In other cases, multiple bank-level UBD alert signals 410 may be in the alert state 414 and cause the die-level UBD alert signal 412 on the common signal bus 402 to be in the alert state 414 for longer than the duration allowed on the alert lead. To address this issue, the backoff circuitry 126 limits the duration of the alert state 414 within the UBD alert signal 128.

[0114] In general, the backoff circuitry 126 generates a backoff signal 706. The backoff signal 706 has different states to indicate whether the UBD alarm signal 128 can be used to indicate an alarm event or whether the UBD alarm signal 128 is backed off based on indicating an alarm event. The backoff circuitry 126 can determine the amount of time in which the backoff process occurs. In some embodiments, the backoff circuitry 126 manages the duration of the alarm backoff process with reference to the clock signal 708 provided by the clock circuitry 212.

[0115] The comparison circuitry 704 uses the backoff signal 706 to limit the duration of the alarm state 414 within the die-level UBD alarm signal 412 provided by the common signal bus 402. The comparison circuitry 704 outputs the comparison signal 712 based on the backoff signal 706 and the die-level UBD alarm signal 412. The comparison signal 712 represents a combination of the backoff signal 706 and the die-level UBD alarm signal 412. The comparison circuitry 704 may be implemented using a logic 'AND' or 'NAND' gate configured to mask the die-level UBD alarm signal 412 with the backoff signal 706.

[0116] The UBD alarm signal generation circuitry 702 generates the UBD alarm signal 128 based on the comparison signal 712. In some implementations, the UBD alarm signal generation circuitry 702 may generate the UBD alarm signal 128 for a time indicative of a number of UBD-related alarm events. For example, the UBD alarm signal generation circuitry 702 may retrieve the number of ongoing UBD-related alarm events stored in the register 214 and use this value to modify the pulse length of the UBD alarm signal 128 while satisfying the timing parameters associated with the alarm lead 124.

[0117] Consider a situation in which the UBD alarm signal generation circuitry 702 generates the UBD alarm signal 128 having the alarm state 414. At this point, the UBD alarm signal generation circuitry 702 also generates a backoff trigger 710, which is provided to the backoff circuitry 126. The backoff trigger 710 causes the backoff circuitry 126 to activate a backoff process. The resulting backoff signal 706 causes the comparison circuitry 704 to induce a non-alarm state within the comparison signal 712, regardless of whether the die-level UBD alarm signal 412 is in the alarm state 414. After a predetermined amount of time has passed, the backoff circuitry 126 stops the backoff process and enables subsequent alarm events to be reported to the UBD alarm signal generation circuitry 702 by the die-level UBD alarm signal 412. Backoff signal 706, comparison signal 712, and UBD alarm signal 128 are related to Figure 8 and 9 Further description.

[0118] Figure 8 and 9 Two example signal timing diagrams 800 and 900 are illustrated according to various implementations. In these examples, the comparison circuitry 704 performs a logical 'AND' operation on the backoff signal 706 and the die-level UBD alert signal 412. In these examples, the backoff signal 706 is in an alert passing state 802 (e.g., a default state) at a high voltage and in a backoff state 804 at a low voltage or ground voltage. Other examples may utilize other voltages to convey these states.

[0119] At 800, the die-level UBD alarm signal 412 is in the alarm state 414 starting at time t1. This may illustrate a situation where there are multiple ongoing UBD-related alarm events on different memory banks 308. Also, at time t1, the backoff signal 706 is in the alarm delivery state 802. The backoff signal 706 and the die-level UBD alarm signal 412 cause the comparison signal 712 to be in the alarm state 414 at time t1. The comparison signal 712 causes the UBD alarm signal 128 to be in the alarm state 414 at time t1′.

[0120] The UBD alarm signal 128 transitions from the non-alarm state 416 to the alarm state 414 at time t1′ causing the UBD alarm signal generation circuitry 702 to generate a backoff trigger 710. Using the backoff trigger 710, the backoff circuitry 126 activates the backoff process. This causes the backoff circuitry 126 to generate a backoff signal 706 having a backoff state 804 at t1+x, where x indicates the minimum period that the comparison signal 712 is in the alarm state 414. For example, x may be one or more clock cycles or may be short enough so that t1 and t1+x occur in a single clock cycle. After t1+x, the backoff signal 706 is in the backoff state 804 and the comparison signal 712 is in the non-alarm state 416. Therefore, the alarm state 414 of the die-level UBD alarm signal 412 is masked by the backoff state 804.

[0121] As illustrated, the UBD alarm signal 128 is in the alarm state 414 until a mitigation event 806 occurs. For example, the mitigation event 806 may be a threshold number of mitigation commands, such as row activation, occurring. As another example, the event 806 may be a signal received from the array control logic 210. The UBD alarm signal 128 persists for a period 808 after the mitigation event 806. For example, the period 808 may be a minimum recovery time, which may be a programmable or preconfigured parameter. After the elapse of the period 808, the UBD alarm signal 128 transitions to the non-alarm state 416. In other examples, the period 808 may not exist and the non-alarm state 416 may be entered immediately after the mitigation event 806. The backoff circuit system 126 waits for the backoff period 810 after the alarm state 414 in the UBD alarm signal 128 ends. Therefore, the comparison signal 712 remains in the non-alarm state 416 during the backoff period 810. After the backoff period 810, the backoff signal 706 returns to the alarm delivery state 802 at t2. At t2, the alarm delivery state 802 of the backoff signal 706 causes the UBD alarm signal generation circuitry 702 to generate the UBD alarm signal 128 having a second pulse at t2'. Other embodiments of the die-level UBD alarm circuitry 218 may generate the UBD alarm signal 128 in another manner, such as with respect to Fig. 9 Further description.

[0122] exist Fig. 9 In the timing diagram 900 of FIG. 1 , the timing of the die-level UBD alarm signal 412, the backoff signal 706, and the comparison signal 712 is similar to Figure 8 The timing shown at 800 in FIG. However, Fig. 9 The UBD alarm signal 128 is Figure 8 The UBD alarm signal 128 shown in FIG. 1 is generated in different ways.

[0123] As illustrated, the UBD alarm signal 128 is in the alarm state 414 for a period 902 indicating a count of UBD-related alarm events. The time between the minimum pulse length 904 and the maximum pulse length 906 may be mapped to a number of potential UBD alarm events that the memory device 108 may experience and enable the UBD alarm signal 128 to satisfy the timing parameters associated with the alarm lead 124. The backoff circuitry 126 waits for the period 908 after the UBD alarm signal 128 begins. For example, the period 908 may be set according to a recovery period after the maximum possible pulse length 906. In some implementations, the backoff circuitry 126 may wait for the earlier of a threshold number of mitigation events or the period 908.

[0124] The backoff circuitry 126 further waits for a delay time 910 after the transition trigger occurs (e.g., time period 908). Therefore, the comparison signal 712 remains in the non-alarm state 416 during the delay time 910. After the delay time 910, the backoff signal 706 returns to the alarm passing state 802 at t2, which causes the comparison signal 712 to return to the alarm state 414 because the die-level UBD alarm signal 412 is in the alarm state 414. Therefore, the UBD alarm signal generation circuitry 702 causes the UBD alarm signal 128 to transition from the non-alarm state 416 to the alarm state 414 at t2', which triggers the generation of the second pulse.

[0125] Instance Methods

[0126] This chapter describes reference Figures 10 to 12 Flowchart of an example method for implementing UBD alert signaling. By way of example only, these descriptions may also refer to Figures 1A to 9 The components, entities and other aspects depicted in the description are not necessarily limited to operations performed by one entity or multiple entities on one device.

[0127] Fig.10 An example flowchart 1000 including operations 1002 through 1008 is illustrated. In one aspect, the operations of the method 1000 are performed by or with reference to Figures 1A to 9At 1002, a bank-level UBD alarm signal is generated. For example, the bank-level UBD alarm circuitry 220 may each be configured to detect a UBD-related alarm event and generate a corresponding bank-level UBD alarm signal 410 indicating the detection of the UBD-related alarm event in a manner such as Figure 4A Displayed in.

[0128] At 1004, a die-level UBD alert signal is generated based on the bank-level UBD alert signal. For example, the die-level UBD alert circuitry 218 combines the bank-level UBD alert signal 410 to generate the die-level UBD alert signal 412, such as Figure 4A The die-level UBD alarm circuit system 218 may use the common signal bus 402 or multiplexer to generate a die-level UBD alarm signal 412 based on the memory bank-level UBD alarm signal 410. In some examples, the alarm state 414 of the die-level UBD alarm signal 412 may be masked with a backoff signal 706, such as Figures 7 to 9 Displayed in.

[0129] At 1006, an error detection signal is generated. For example, the error detection circuit system 120 generates the error detection signal 130, such as Figure 1B and 4A . Error detection circuitry 120 may include CRC error detection circuitry that performs a cyclic redundancy check on a data input or a data output. In this example, error detection circuitry 120 generates an error detection signal 130 in a manner that indicates detection of a cyclic redundancy check failure.

[0130] At 1008, an alarm signal is output via an alarm pin based on the die-level UBD alarm signal and the error detection signal. For example, the alarm circuit system 122 may output the alarm signal 132 based on the die-level UBD alarm signal 412 (or more generally, the UBD alarm signal 128) and the error detection signal, such as Figure 1B and 4A The alarm circuitry 122 may be implemented using the combined alarm circuitry 502 described in FIG. 5 or the sequential alarm circuitry 602 described with respect to FIG.

[0131] Fig.11 An example flowchart 1100 including operations 1102 through 1104 is illustrated. In one aspect, the operations of the method 1100 are performed by or with reference to Figures 1A to 9 The alarm circuit system 122 and alarm lead 124 are described as being implemented.

[0132] At 1102, an alarm signal is transmitted on a lead of a die of a memory device. The first alarm signal has a first pulse indicating detection of a bank-level alarm event associated with a UBD. The first pulse has a first pulse length. For example, the alarm circuitry 122 transmits the alarm signal 132 on the alarm lead 124 of the die 304, such as Figure 1B . The alarm signal 132 has a first pulse indicating the detection of a bank-level alarm event associated with UBD. The first pulse represents a first example of an alarm state 414 of the alarm signal 132. The alarm state 414 may be associated with a high voltage or a low voltage, depending on the implementation. In this example, the alarm signal 132 indicates the presence of a UBD-related alarm event on at least one of the banks 308 within the die 304. The length of the first pulse may indicate the number of UBD-related alarm events, such as Fig. 9 Displayed in.

[0133] At 1104, an alarm signal having a second pulse indicating detection of an error event different from the bank-level alarm event is transmitted on the lead. The second pulse has a second pulse length different from the first pulse length. For example, the alarm circuit system 122 transmits the alarm signal 132 on the alarm lead 124 of the die 304, such as Figure 1B The alarm signal 132 has a second pulse indicating an error event not related to UBD. For example, the error event may indicate a cyclic redundancy check failure.

[0134] If the UBD-related alarm event and the error event occur at different times in a non-overlapping manner, the first pulse and the second pulse may be separated in time. However, if another UBD-related alarm event and another error event occur in an at least partially overlapping manner, the alarm circuit system 122 may generate a single pulse or separate pulses depending on the implementation, such as with respect to Figures 5A to 6D describe.

[0135] Fig.12 An example flowchart 1200 including operations 1202 through 1210 is illustrated. In one aspect, the operations of the method 1200 are performed by or with reference to Figure 1B and 7 At 1202, a die-level usage-based disturbance alarm signal having an alarm state or a non-alarm state is generated. The alarm state indicates that a usage-based disturbance alarm event is detected in at least one memory bank of a die of a memory device. For example, the die-level UBD alarm circuitry 218 generates a die-level UBD alarm signal 412 having an alarm state 414 or a non-alarm state 416, as shown in FIG. Figure 4A and 4BThe alarm state 414 of the die-level UBD alarm signal 412 indicates that a UBD-related alarm event is detected by at least one of the bank-level UBD alarm circuitry 220. In this way, the alarm state 414 indicates that a UBD alarm event is detected within at least one bank 308 of a die 304 of a memory device 108.

[0136] At 1204, the backoff signal is monitored for a blocking state or an alarm passing state. For example, the die-level UBD alarm circuitry 218 monitors the state of the backoff signal 706, such as Figure 7 The backoff signal 706 may have a backoff state 804 or an alert delivery state 802, such as Figure 8 and 9 Displayed in.

[0137] At 1208, a UBD alarm signal is generated based on the die-level usage-based interference alarm signal and the backoff signal. The UBD alarm signal has an alarm state in response to the die-level usage-based interference alarm signal having an alarm state and the backoff signal having an alarm delivery state. For example, the die-level UBD alarm circuitry 218 generates the UBD alarm signal 128 based on the die-level UBD alarm signal 412 and the backoff signal 706, as shown in FIG. Figure 7 The UBD alarm signal 128 has an alarm state 414 in response to the die-level UBD alarm signal 412 having an alarm state 414 and the backoff signal 706 having an alarm delivery state 802, such as Figure 8 and 9 Displayed in.

[0138] At 1210, a backoff state of the backoff signal is induced for a period of time in response to the UBD alarm signal transitioning from the non-alarm state to the alarm state. For example, the die-level UBD alarm circuitry 218 induces the backoff state 804 of the backoff signal 706 for a period of time in response to the UBD alarm signal 128 transitioning from the non-alarm state 416 to the alarm state 414.

[0139] With respect to the above figures, the order in which the operations are shown and / or described is not intended to be construed as limiting. Any number or combination of described process operations may be combined or rearranged in any order to implement a given method or an alternative method. Operations may also be omitted from or added to the described methods. In addition, the described operations may be implemented in a completely or partially overlapping manner.

[0140] Aspects of these methods may be implemented in, for example, hardware (eg, fixed logic circuitry or a processor in conjunction with memory), firmware, software, or some combination thereof. Figures 1A to 9The methods are implemented by one or more of the devices or components shown in the drawings, wherein the components may be further divided, combined, rearranged, etc. The devices and components of these figures generally represent: hardware, such as electronic devices, packaged modules, IC chips, or circuits; firmware or its actions; software; or a combination thereof. Therefore, these figures illustrate some of the many possible systems or devices capable of implementing the described methods.

[0141] Computer-readable media includes both non-transitory computer storage media and communication media, including any media that facilitates the transfer of computer programs (such as applications) or data from one entity to another. Non-transitory computer storage media can be any available media that can be accessed by a computer, such as RAM, ROM, flash, EEPROM, optical media, and magnetic media.

[0142] In the following, various examples for implementing aspects of UBD alert signaling are described:

[0143] Example 1: A device comprising:

[0144] a plurality of memory bank-level usage-based disturb alert circuitry configured to generate respective memory bank-level usage-based disturb alert signals;

[0145] a die-level usage-based disturber alarm circuitry coupled to the outputs of the plurality of bank-level usage-based disturber alarm circuitry and configured to generate a die-level usage-based disturber alarm signal based on the bank-level usage-based disturber alarm signal;

[0146] an error detection circuit system configured to generate an error detection signal;

[0147] alarm leads; and

[0148] An alarm circuit system is coupled to the output of the die-level usage-based interference alarm circuit system, the output of the error detection circuit system and the alarm lead, and the alarm circuit system is configured to output an alarm signal based on the die-level usage-based interference alarm signal and the error detection signal via the alarm lead.

[0149] Example 2: The apparatus of example 1 or any other example, wherein:

[0150] the plurality of memory bank-level usage-based disturbance alarm circuitry each configured to detect a usage-based disturbance-related alarm event and to generate the respective memory bank-level usage-based disturbance alarm signal in a manner indicative of the detection of the usage-based disturbance-related alarm event;

[0151] The die-level usage-based interference circuitry includes a common signal bus coupled to the outputs of the plurality of bank-level usage-based interference circuitry; and

[0152] The die-level usage-based interference circuit system is configured to use the common signal bus to generate the die-level usage-based interference alarm signal in a manner that indicates that the usage-based interference-related alarm event is detected in response to one or more of the memory body-level usage-based interference alarm signals indicating the detection of the usage-based interference-related alarm event.

[0153] Example 3: An apparatus according to Example 1 or any other example, wherein the alarm circuit system is configured to generate the alarm signal in a manner that indicates the alarm state in response to at least one of the die-level interference alarm signal based on use having the alarm state or the error detection signal having the alarm state.

[0154] Example 4: The apparatus of example 3 or any other example, wherein the alarm circuitry comprises a logic gate configured to perform a NOR operation on the die-level usage-based jammer alarm signal and the error detection signal to generate the alarm signal.

[0155] Example 5: An apparatus according to example 1 or any other example, wherein the alarm circuit system is configured to generate the alarm signal with sequential pulses in response to the die-level based interference alarm signal and the error detection signal having an alarm state within an arbitration delay time of each other.

[0156] Example 6: The apparatus of example 5 or any other example, wherein the alarm circuitry is configured such that the sequential pulses are separated in time by a predetermined delay time.

[0157] Example 7: The apparatus of example 1 or any other example, wherein:

[0158] The memory bank level is in an alarm state for a first duration indicative of one or more alarms based on a combination of one or more of the used disturbance alarm signals; and

[0159] The die-level usage-based jammer alert circuitry is configured to limit a duration for which the die-level usage-based jammer alert signal is in the alarm state such that the die-level usage-based jammer alert signal is in the alarm state for a second duration that is shorter than the first duration.

[0160] Example 8: The apparatus of example 7 or any other example, wherein:

[0161] The die-level usage-based disturb alert circuitry is configured to suppress the one or more alarms associated with the one or more memory bank-level usage-based disturb alert signals for a predefined amount of time.

[0162] Example 9: The apparatus of example 1 or any other example, wherein:

[0163] The error detection circuitry is configured to:

[0164] Detecting cyclic redundancy check failures; and

[0165] The error detection signal is generated in a manner indicating that the cyclic redundancy check fails.

[0166] Example 10: A method comprising:

[0167] transmitting an alarm signal having a first pulse indicating detection of a bank-level alarm event associated with usage-based disturbance on a lead of a die of a memory device, the first pulse having a first pulse length; and

[0168] The alert signal is transmitted on the lead having a second pulse indicating detection of an error event different from the bank level alert event, the second pulse having a second pulse length different from the first pulse length.

[0169] Example 11: The method of example 10 or any other example, wherein the error event is associated with data read from or written to the memory device.

[0170] Example 12: The method of example 10 or any other example, further comprising:

[0171] The alarm signal having a third pulse indicating detection of a second memory bank level alarm event and a second error event associated with the usage-based interference is transmitted on the lead, the third pulse having a third pulse length equal to the sum of an overlapping duration and a non-overlapping duration of the second memory bank level alarm event and the second error event.

[0172] Example 13: The method of example 10 or any other example, further comprising:

[0173] first detecting one of a second memory bank level alarm event or a second error event;

[0174] subsequently detecting the other of said second bank level alarm event or said second alarm event, said subsequent detection of said other event occurring during a time of said first detected event; and

[0175] The alarm signal is transmitted having a third pulse for indicating the first detected event and a fourth pulse for indicating the subsequent detection of the another event, the third and fourth pulses being separated in time by a predetermined amount.

[0176] Example 14: The method of example 13 or any other example, wherein:

[0177] The subsequent detection occurs within an arbitration time of the first detection event; and

[0178] The arbitration time has a duration between a duration of the third pulse and a duration of the fourth pulse.

[0179] Example 15: The method of example 10 or any other example, further comprising:

[0180] Detecting memory bank level usage-based alarm conditions in the first instance;

[0181] inducing a blocking state of a backoff signal in response to detecting a usage-based alarm state of the memory bank level during the blocking period;

[0182] transmitting said first pulse of said alarm signal in response to detecting a usage-based alarm condition of said memory bank level;

[0183] detecting, at a second time, a usage-based alarm state at the memory bank level; and

[0184] A third pulse of the alarm signal is transmitted in response to detecting a usage-based alarm state of the memory bank level at the second time and in response to detecting that the blocking state is not present.

[0185] Example 16: A method comprising:

[0186] generating a die-level usage-based disturbance alarm signal having an alarm state or a non-alarm state, the alarm state indicating that a usage-based disturbance alarm event was detected within at least one memory bank of a die of a memory device;

[0187] Monitoring of fallback signals with blocking status or alarm delivery status;

[0188] generating a usage-based interference alarm signal based on the die-level usage-based interference alarm signal and the backoff signal, the usage-based interference alarm signal having the alarm state in response to the die-level usage-based interference alarm signal having the alarm state and the backoff signal having the alarm delivery state; and

[0189] A backoff state of the backoff signal is induced for a period of time in response to the usage-based jammer alert signal transitioning from the non-alarm state to the alert state.

[0190] Example 17: The method of example 16 or any other example, further comprising:

[0191] transmitting the usage-based interference alert signal from the memory device to a memory controller using an alert lead,

[0192] wherein the generating of the usage-based jammer alert signal comprises causing the usage-based jammer alert signal to have a pulse having a pulse length limited by the induced backoff state, the pulse length satisfying timing parameters associated with an interface between the memory device and the memory controller.

[0193] Example 18: The method of example 17 or any other example, further comprising:

[0194] generating a false detection signal indicative of detection of a non-usage based interference related event; and

[0195] The error detection signal is transmitted from the memory device to the memory controller using the alert lead.

[0196] Example 19: The method of example 16 or any other example, wherein the generating of the usage-based jammer alert signal comprises combining the die-level usage-based jammer alert signal with the backoff signal using a logical AND operation.

[0197] Example 20: The method of Example 16 or any other example, wherein the generating of the usage-based interference alarm signal comprises causing the alarm state of the usage-based interference alarm signal to occur for a shorter duration than the alarm state of the die-level usage-based interference alarm signal.

[0198] Unless the context dictates otherwise, the word "or" as used herein may be considered to use an "inclusive or" or a term that permits inclusion or application of one or more items connected by the word "or" (e.g., the phrase "A or B" may be interpreted as permitting only "A", only "B", or both "A" and "B"). Moreover, as used herein, a phrase referring to "at least one of" a list of items refers to any combination of the items, including a single member. For example, "at least one of a, b, or c" may encompass a, b, c, ab, ac, bc, and abc, as well as any combination with multiple identical elements (e.g., aa, aaa, aab, aac, abb, acc, bb, bbb, bbc, cc, and ccc, or any other ordering of a, b, and c). Furthermore, the items represented in the figures and terms discussed herein may indicate one or more items or terms, and thus may refer interchangeably to the singular or plural forms of the items and terms in this written description.

[0199] Summarize

[0200] Although aspects implementing UBD alert signaling have been described in language specific to certain features and / or methods, the subject matter of the appended claims is not necessarily limited to the specific features or methods described. Rather, the specific features and aspects are disclosed as various example implementations implementing UBD alert signaling.

Claims

1. A device comprising: a plurality of memory bank-level usage-based disturb alert circuitry configured to generate respective memory bank-level usage-based disturb alert signals; a die-level usage-based disturber alarm circuitry coupled to the outputs of the plurality of bank-level usage-based disturber alarm circuitry and configured to generate a die-level usage-based disturber alarm signal based on the bank-level usage-based disturber alarm signal; an error detection circuit system configured to generate an error detection signal; Alarm leads; and An alarm circuit system is coupled to the output of the die-level usage-based interference alarm circuit system, the output of the error detection circuit system and the alarm lead, and the alarm circuit system is configured to output an alarm signal based on the die-level usage-based interference alarm signal and the error detection signal via the alarm lead.

2. The apparatus according to claim 1, wherein: the plurality of bank-level usage-based disturber alert circuitry each configured to detect a usage-based disturber-related alarm event and to generate one of the bank-level usage-based disturber alert signals in a manner indicative of the detection of the usage-based disturber-related alarm event; The die-level usage-based interference circuitry includes a common signal bus coupled to the outputs of the plurality of bank-level usage-based interference circuitry; and The die-level usage-based interference circuit system is configured to use the common signal bus to generate the die-level usage-based interference alarm signal in a manner that indicates that the usage-based interference-related alarm event is detected in response to one or more of the memory body-level usage-based interference alarm signals indicating the detection of the usage-based interference-related alarm event.

3. The apparatus of claim 1 , wherein the alarm circuit system is configured to generate the alarm signal in a manner that indicates the alarm state in response to at least one of the die-level usage-based interference alarm signal having an alarm state or the error detection signal having the alarm state. 4 . The apparatus of claim 3 , wherein the alarm circuitry comprises a logic gate configured to perform a NOR operation on the die-level usage-based jammer alarm signal and the error detection signal to generate the alarm signal.

5. The apparatus of claim 1, wherein the alarm circuitry is configured to generate the alarm signal having sequential pulses in response to the die-level based usage interference alarm signal and the error detection signal having alarm states within an arbitration delay time of each other.

6. The apparatus of claim 5, wherein the alarm circuitry is configured such that the sequential pulses are spaced apart in time by a predetermined delay time.

7. The apparatus of claim 1, wherein: The memory bank level is in an alarm state for a first duration indicative of one or more alarms based on a combination of one or more of the used disturbance alarm signals; and The die-level usage-based jammer alert circuitry is configured to limit a duration for which the die-level usage-based jammer alert signal is in the alarm state such that the die-level usage-based jammer alert signal is in the alarm state for a second duration that is shorter than the first duration.

8. The apparatus of claim 7, wherein: The die-level usage-based disturb alert circuitry is configured to suppress the one or more alarms associated with the one or more memory bank-level usage-based disturb alert signals for a predefined amount of time.

9. The apparatus of claim 1, wherein: The error detection circuitry is configured to: Detecting cyclic redundancy check failures; and The error detection signal is generated in a manner indicating that the cyclic redundancy check fails.

10. A method comprising: transmitting an alarm signal having a first pulse indicating detection of a bank-level alarm event associated with usage-based disturbance on a lead of a die of a memory device, the first pulse having a first pulse length; and The alert signal is transmitted on the lead having a second pulse indicating detection of an error event different from the bank level alert event, the second pulse having a second pulse length different from the first pulse length.

11. The method of claim 10, wherein the error event is associated with data read from or written to the memory device.

12. The method according to claim 10, further comprising: The alarm signal having a third pulse indicating detection of a second memory bank level alarm event and a second error event associated with the usage-based interference is transmitted on the lead, the third pulse having a third pulse length equal to the sum of an overlapping duration and a non-overlapping duration of the second memory bank level alarm event and the second error event.

13. The method according to claim 10, further comprising: first detecting one of a second memory bank level alarm event or a second error event; subsequently detecting the other of said second bank level alarm event or said second alarm event, said subsequent detection of said other event occurring during a time of said first detected event; and The alarm signal is transmitted having a third pulse for indicating the first detected event and a fourth pulse for indicating the subsequent detection of the another event, the third and fourth pulses being separated in time by a predetermined amount.

14. The method according to claim 13, wherein: The subsequent detection occurs within an arbitration time of the first detection event; and The arbitration time has a duration between a duration of the third pulse and a duration of the fourth pulse.

15. The method according to claim 10, further comprising: Detecting memory bank level usage-based alarm conditions in the first instance; inducing a blocking state of a backoff signal in response to detecting a usage-based alarm state of the memory bank level during the blocking period; transmitting said first pulse of said alarm signal in response to detecting a usage-based alarm condition of said memory bank level; detecting a usage-based alarm state of the memory bank level at a second time; and A third pulse of the alarm signal is transmitted in response to detecting a usage-based alarm state of the memory bank level at the second time and in response to detecting that the blocking state is not present.

16. A method comprising: generating a die-level usage-based disturbance alarm signal having an alarm state or a non-alarm state, the alarm state indicating that a usage-based disturbance alarm event was detected within at least one memory bank of a die of a memory device; Monitoring of fallback signals with blocking status or alarm delivery status; generating a usage-based interference alarm signal based on the die-level usage-based interference alarm signal and the backoff signal, the usage-based interference alarm signal having the alarm state responsive to the die-level usage-based interference alarm signal having the alarm state and the backoff signal having the alarm delivery state; and A backoff state of the backoff signal is induced for a period of time in response to the usage-based jammer alert signal transitioning from the non-alarm state to the alert state.

17. The method according to claim 16, further comprising: transmitting the usage-based interference alert signal from the memory device to a memory controller using an alert lead, wherein the generating of the usage-based jammer alert signal comprises causing the usage-based jammer alert signal to have a pulse having a pulse length limited by the induced backoff state, the pulse length satisfying timing parameters associated with an interface between the memory device and the memory controller.

18. The method according to claim 17, further comprising: generating a false detection signal indicative of detection of a non-usage-based interference-related event; and The error detection signal is transmitted from the memory device to the memory controller using the alert lead.

19. The method of claim 16, wherein the generating of the usage-based jammer alert signal comprises combining the die-level usage-based jammer alert signal with the backoff signal using a logical AND operation.

20. The method of claim 16, wherein the generating of the usage-based jammer alert signal comprises causing the alarm state of the usage-based jammer alert signal to occur for a shorter duration than the alarm state of the die-level usage-based jammer alert signal.

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