A Method for Improving the Performance of 3D Wafer Stacking and a Semiconductor Structure

Abstract

The present invention belongs to the field of semiconductor processing technology, and particularly relates to a method for improving the efficiency of 3D wafer stacking and a semiconductor structure. A metal interconnect structure is provided in a wafer oxide layer, a through hole is opened in the oxide layer from the bonding surface side, the through hole communicates with the metal interconnect structure and is filled with a conductor layer; the bonding surfaces of one wafer and another wafer face each other, and the conductor layers of the two wafers are communicated; a TSV through hole is opened in the direction of the metal interconnect structure from the bottom surface of any one of the wafers, and the TSV through hole communicates with the metal interconnect structure; an oxidation deposition layer is deposited in the TSV through hole, and the oxidation deposition layer covers the side wall and the bottom of the TSV through hole; ions are implanted into the oxidation deposition layer on the side wall of the TSV through hole; a photolithography step is performed to remove the oxidation deposition layer at the bottom of the TSV through hole, exposing the metal interconnect structure at the bottom of the TSV through hole; a TSV through hole conductor layer is deposited in the TSV through hole, and the TSV through hole conductor layer communicates with the metal interconnect structure.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor processing, and particularly relates to a method for improving the performance of 3D wafer stacking. Background Art

[0002] With the rapid development of semiconductor manufacturing technology, in order for semiconductor devices to achieve faster computing speeds, larger data storage capacities, and more functions, semiconductor chips are developing towards higher integration levels. The higher the integration level of semiconductor chips, the smaller the critical dimension of semiconductor devices.

[0003] 3D wafer stacking technology is an advanced semiconductor manufacturing process that realizes higher integration and performance by vertically stacking multiple wafers. 3D wafer stacking technology stacks multiple wafers vertically and uses technologies such as through-silicon vias (TSVs) to achieve interlayer interconnection.

[0004] The through-silicon via (TSV) process can connect the circuits fabricated on the upper surface of a silicon wafer to the back of the silicon wafer through the metal filled in the through-silicon vias. Combining with three-dimensional packaging technology, the IC layout has evolved from the traditional two-dimensional side-by-side arrangement to a more advanced three-dimensional stacking, so that the component packaging is more compact and the chip lead distance is shorter, thereby greatly improving the frequency characteristics and power characteristics of the circuit. The existing through-silicon via process includes: etching vias on the wafer surface using plasma etching; forming an insulating layer on the via surface using chemical vapor deposition; metallizing the through-silicon vias, filling the vias using copper electroplating, and removing the excess copper electroplating layer using CMP; performing wafer back grinding to expose the copper conductor layer and complete the through-silicon via structure.

[0005] As a connection structure between multi-layer circuit structures, through-silicon vias play the role of electrically connecting circuit devices between multiple layers. In the known prior art, there are various reasons for leakage to occur at the through-silicon vias, for example: there may be defects or contamination at the interface between the TSV and the silicon substrate, the thermal expansion coefficients of the TSV and the silicon substrate are different, and the thermal stress generated during manufacturing and use may cause microcracks or defects; if there are pinholes, cracks, or uneven thickness in the insulating dielectric layer around the TSV; if the etching, deposition, and other steps during the manufacturing process are not properly controlled, etc.

[0006] If leakage occurs at the through-silicon vias, it will affect the connection performance of circuit devices and the stability of the electronic device structure. Summary of the Invention

[0007] The purpose of the present invention is to solve one of the above technical problems, and propose a method for solving the leakage problem at the through-silicon vias in a 3D wafer stacking structure, and improving the stacking performance of 3D wafers.

[0008] To achieve the above object, in some embodiments of the present invention, the following technical solutions are provided:

[0009] The first aspect of the present invention provides a method for improving the leakage current of 3D wafer stacking, including:

[0010] A method for improving the performance of 3D wafer stacking, including:

[0011] Providing wafers, where the wafers include a base layer and an oxide layer, one side of the oxide layer is a bonding surface, and one side of the base layer is a bottom surface; a metal interconnect structure is provided in the oxide layer, and a through hole is opened in the oxide layer from the bonding surface side, and the through hole communicates with the metal interconnect structure and is filled with a conductor layer;

[0012] The bonding surfaces of one wafer and another wafer face each other, and the conductor layers of the two wafers are connected;

[0013] Opening TSV through holes in the direction from the bottom surface of any wafer to the metal interconnect structure, and the TSV through holes communicate with the metal interconnect structure;

[0014] Depositing an oxidation deposition layer in the TSV through holes, and the oxidation deposition layer covers the side wall and the bottom of the TSV through holes;

[0015] Injecting ions into the oxidation deposition layer on the side wall of the TSV through hole;

[0016] Performing a lithography step to remove the oxidation deposition layer at the bottom of the TSV through hole, exposing the metal interconnect structure at the bottom of the TSV through hole;

[0017] Depositing a TSV through hole conductor layer in the TSV through hole, and the TSV through hole conductor layer communicates with the metal interconnect structure.

[0018] Combined with the first aspect of the present invention, in some embodiments of the present invention, the step of injecting ions includes: depositing a photoresist layer, the photoresist layer covers the oxidation deposition layer at the bottom of the TSV through hole, and the oxidation deposition layer on the side wall of the TSV through hole remains exposed; injecting ions into the oxidation deposition layer on the side wall of the TSV through hole.

[0019] Combined with the first aspect of the present invention, in some embodiments of the present invention, the types of injected ions include but are not limited to: B, BF2, Si, Al, Phosp, AS.

[0020] Combined with the first aspect of the present invention, in some embodiments of the present invention, the energy of the injected ions is controlled at 2KeV - 50KeV.

[0021] Combined with the first aspect of the present invention, in some embodiments of the present invention, the dose of the injected ions is controlled at 1e 12 / cm 2-1e 15 / cm 2 。

[0022] In combination with the first aspect of the present invention, in some embodiments of the present invention, the thickness of the oxidation deposition layer is 。

[0023] In combination with the first aspect of the present invention, in some embodiments of the present invention, before the step of opening TSV vias on the bottom surface of any wafer, it further includes:

[0024] Deposit a passivation layer on the bottom surface of the wafer where TSV vias need to be opened, and open TSV vias along the direction of the passivation layer towards the metal interconnect structure; the passivation layer includes a combination of an oxide layer and a silicon layer.

[0025] In combination with the first aspect of the present invention, in some embodiments of the present invention, the oxidation deposition layer covers the surface of the passivation layer, and ions are implanted into the oxidation deposition layer on the surface of the passivation layer during the ion implantation step.

[0026] The second aspect of the present invention provides a semiconductor structure constructed by using the method provided in the first aspect of the present invention, including:

[0027] The first wafer: includes a base layer and an oxide layer, one side of the oxide layer is a bonding surface, and one side of the base layer is a bottom surface; a metal interconnect structure is provided in the oxide layer, and a via is opened in the oxide layer from the bonding surface side, and the via communicates with the metal interconnect structure and is filled with a conductor layer;

[0028] The second wafer: includes a base layer and an oxide layer, one side of the oxide layer is a bonding surface, and one side of the base layer is a bottom surface; a metal interconnect structure is provided in the oxide layer, and a via is opened in the oxide layer from the bonding surface side, and the via communicates with the metal interconnect structure and is filled with a conductor layer;

[0029] The bonding surfaces of the first wafer and the second wafer face each other, and the conductor layer of the first wafer is connected to the conductor layer of the second wafer;

[0030] TSV vias are opened on the bottom surface of the first wafer in the direction of the metal interconnect structure, and the TSV vias communicate with the metal interconnect structure of the first wafer;

[0031] An oxide deposition layer is deposited on the sidewall of the TSV via, and ion implantation is performed inside the oxide deposition layer on the side of the TSV via;

[0032] The TSV via is filled with a TSV via conductor layer, and the TSV via conductor layer communicates with the metal interconnect structure of the first wafer.

[0033] In some embodiments of the present invention, a passivation layer is provided on the bottom surface of the first wafer, and the oxide deposition layer covers the passivation layer.

[0034] Compared with the prior art, the beneficial effects of the technical solution of the present invention are as follows:

[0035] Deposit an oxide deposition layer inside the TSV via hole. By means of ion implantation etching, remove the oxide deposition layer at the bottom of the TSV via hole. Due to the difference in etching rate, over-damage to the oxide deposition layer on the sidewall of the TSV via hole can be prevented. Deposit a TSV via hole conductor layer outside the oxide deposition layer to form a 3D stacked interconnection structure. The oxide deposition layer on the sidewall of the TSV via hole plays a role in insulation and preventing leakage. The present invention solves the problem of TSV via hole leakage through a simple process and can improve the reliability of the interconnection structure of semiconductor devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0037] Figure 1 Schematic diagram of the wafer structure provided by the present invention.

[0038] Figure 2 Schematic diagram of the bonding structure of the first wafer and the second wafer of the present invention.

[0039] Figure 3a Schematic diagram of the bonding structure of the present invention without a passivation layer.

[0040] Figure 3b Schematic diagram of the bonding structure of the present invention with a passivation layer.

[0041] Figure 4 Schematic diagram of the step structure of opening a TSV via hole and depositing an oxide deposition layer of the present invention.

[0042] Figure 5 Schematic diagram of the ion implantation step structure of the present invention.

[0043] Figure 6 Schematic diagram of the step structure of etching the oxide deposition layer.

[0044] Figure 7 Schematic diagram of the structure of filling the TSV via hole conductor layer.

[0045] In the above figures:

[0046] 1 - base layer;

[0047] 2 - oxide layer;

[0048] 3 - Metal interconnect structure;

[0049] 4 - Through - hole;

[0050] 5 - Conductor layer;

[0051] 601 - Bonding surface, 602 - Bottom surface;

[0052] 7 - TSV through - hole;

[0053] 8 - Oxide deposition layer;

[0054] 9 - TSV through - hole conductor layer;

[0055] 10 - Photoresist layer;

[0056] 11 - Passivation layer. Detailed implementation manners

[0057] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present invention more clear and understandable, the present invention will be further described in detail below with reference to the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0058] Obviously, the drawings in the following description are only some examples or embodiments of the present application. For those of ordinary skill in the art, without creative efforts, the present application can also be applied to other similar scenarios based on these drawings. In addition, it can also be understood that although the efforts made in this development process may be complex and lengthy, for those of ordinary skill in the art related to the content disclosed in the present application, some design, manufacturing or production changes based on the technical content disclosed in the present application are only conventional technical means and should not be understood that the content disclosed in the present application is insufficient.

[0059] 3D wafer stacking technology stacks multiple wafers in the vertical direction and uses technologies such as through - silicon vias (TSV) to achieve inter - layer interconnection. The connection form of through - silicon vias (TSV) can shorten the interconnection length, reduce latency and power consumption. However, TSV leakage is an important reliability issue that may affect chip performance and yield.

[0060] Through - silicon vias (TSV) need to be etched. Due to reasons such as etching process and semiconductor structure defects, it is easy to cause leakage in through - silicon vias (TSV).

[0061] In the known prior art, TSV leakage is usually caused by the following factors:

[0062] Insulation layer defects: The insulation layer of the TSV (such as SiO2) may have cracks, holes, or uneven thickness; Thermal stress: The high-temperature processes during TSV manufacturing or the thermal stress generated during chip operation may cause the insulation layer to crack or interface delamination; Electromigration: Under high current density, the metal filling material (such as copper) may undergo electromigration, resulting in damage to the insulation layer; Process defects: Defects in process steps such as etching, deposition, or chemical mechanical polishing (CMP) may lead to an incomplete TSV structure; Interface problems: Defects may exist at the interface between the TSV and the surrounding silicon substrate or metal interconnects, triggering leakage paths.

[0063] TSV leakage will increase the power consumption of the device, resulting in an increase in static power consumption and affecting energy efficiency; It causes signal attenuation or noise, affects circuit performance, and causes a decrease in signal integrity; Long-term leakage may lead to local overheating, accelerating device aging or even failure, and reducing device reliability; At the same time, TSV leakage is one of the main reasons for the yield loss of 3D stacked chips.

[0064] In the known prior art, the problem of leakage is solved by improving and optimizing the insulation layer structure. For example, a uniform insulation material (such as a high-k dielectric) is used, and the thickness of the insulation layer is increased; The problem of leakage can also be solved by improving the TSV process. For example, the etching and deposition processes are optimized to reduce insulation layer defects, and a low-temperature process is used to reduce the impact of thermal stress on the insulation layer. With the development of technology, leakage repair techniques have also emerged, such as laser repair or local re-deposition to repair defects.

[0065] The existing methods for dealing with leakage structures in the prior art have defects such as complex process technology and high technical requirements. To solve this problem, the present invention proposes a method for improving the leakage of 3D wafer stacking, and based on this method, a new semiconductor structure is proposed.

[0066] In the first aspect of the present invention, a method for improving the leakage of 3D wafer stacking is provided, and the method includes the following steps.

[0067] S1: Prepare a wafer.

[0068] Provide a wafer, which includes a base layer 1 and an oxide layer 2. One side of the oxide layer is a bonding surface 601, and one side of the base layer is a bottom surface 602; A metal interconnect structure 3 is provided in the oxide layer. A through hole is opened in the oxide layer from the bonding surface side, and the through hole 4 communicates with the metal interconnect structure 3 and is filled with a conductor layer 5.

[0069] Reference Figure 1 , a schematic diagram of a wafer structure is provided for the present invention.

[0070] The wafer base layer 1 can be a silicon substrate, a silicon carbide substrate, a silicon nitride substrate, etc. In this embodiment, a silicon nitride matrix is used. A multi-layer semiconductor structure is deposited on the base layer 1, and the multi-layer semiconductor structure includes an oxide layer 2. The oxide layer is mainly used for insulation, protection, and the construction of device structures. The oxide layer can be made of silicon dioxide, high-k materials. During the deposition of the oxide layer 2, a metal interconnect structure 3 is designed inside the oxide layer 2. The metal interconnect structure 3 is usually a copper block disposed inside the oxide layer 2, and the copper block is mainly used for the interconnect layer in the wafer to achieve electrical connection of the devices.

[0071] Etch a through hole 4 from the surface on one side of the oxide layer 2 towards the base layer 1. The through hole 4 needs to have a certain depth so that after etching, the metal interconnect structure 3 can be exposed. Fill the through hole 4 with a conductor layer 5. The conductor layer 5 has conductivity and can be connected to the metal interconnect structure 3.

[0072] Use the same method to process multiple wafer structures.

[0073] S2: Wafer bonding.

[0074] Refer to Figure 2 , provide the wafers processed by step S1, defined as the first wafer and the second wafer. The bonding surfaces 601 of the first wafer and the second wafer are opposite, and the positions where the conductor layers 5 of the two wafers are located are opposite. The conductor layers 5 are connected, thereby realizing the connection of the circuit structures between the two wafers. In this embodiment, the wafer located above the illustrated position is defined as the first wafer, and the one below is the second wafer.

[0075] S3: TSV via processing step.

[0076] Refer to Figure 3a and Figure 3b , open a TSV via 7 from one side of the bottom surface 602 of any wafer towards the metal interconnect structure 3. The TSV via 7 is connected to the metal interconnect structure 3. The line width of the TSV via 7 is , which can be selected according to actual processing requirements.

[0077] Deposit an oxide deposition layer 8 in the TSV via 7. The oxide deposition layer 8 covers the side wall and the bottom of the TSV via 7;

[0078] Inject ions into the oxide deposition layer on the side wall of the TSV via 7. The types of injected ions include but are not limited to: B, BF2, Si, Al, Phosp, AS, and any other ions that can achieve ion implantation lithography. During the ion implantation process, the energy of the injected ions is controlled at 2 KeV - 50 KeV, and the dose of the injected ions is controlled at 1e 12 / cm 2 -1e 15 / cm2 The control of the ion implantation energy and the selection of the dose can be designed according to actual requirements.

[0079] After the ion implantation is completed, a photolithography step is performed to remove the oxide deposition layer 8 at the bottom of the TSV via 7, exposing the metal interconnect structure 3 at the bottom of the TSV via 7. In this step, at least a part or all of the oxide deposition layer 8 at the bottom of the TSV via 7 needs to be removed so that the metal interconnect structure 3 can be exposed. In some embodiments, it is also possible to choose to remove the oxide deposition layer 8 in the middle of the bottom of the TSV via 7 and retain the oxide deposition layer 8 adjacent to the side wall of the TSV via 7.

[0080] Subsequently, a TSV via conductor layer 9 is deposited into the TSV via 7. The TSV via conductor layer 9 can also be made of copper, and the TSV via conductor layer 9 connects the metal interconnect structure 3.

[0081] In this embodiment, steps S2 and S3 are performed on the first wafer. It should be understood that, for the circuit structure layout of semiconductor devices, in some embodiments, steps S2 and S3 can also be performed on both the first wafer and the second wafer, that is, the TSV via 7 structures are processed on the bottom surfaces 602 of both wafers.

[0082] The oxide deposition layer 8 on the side wall of the TSV via 7 is used to protect the TSV via 7, reduce the damage to the side wall oxide layer, and prevent leakage in the TSV via 7. In the present invention, an etching step is performed after ion implantation. The ion implantation improves the damage to the oxide deposition layer 8 on the side wall caused during the etching process of the oxide deposition layer 8 at the bottom of the TSV via 7, and thus the leakage between the TSV vias 7 and the leakage between the TSV via 7 and other device connection structures can be avoided.

[0083] Combined with the first aspect of the present invention, in some embodiments of the present invention, the thickness of the oxide deposition layer 8 is , which can be selected and designed according to actual processing requirements. In some implementation structures, the thickness of the oxide deposition layer 8 at the bottom of the TSV via 7 is greater than the thickness of the oxide deposition layer 8 on the side wall of the TSV via 7.

[0084] Reference Figures 5 to 7 , combined with the first aspect of the present invention, in some embodiments of the present invention, the ion implantation etching technology is used to remove the oxide deposition layer 8 at the bottom of the TSV via 7. The step of removing the oxide deposition layer 8 at the bottom of the TSV via 7 includes: depositing a photoresist layer 10, the photoresist layer 10 covering the oxide deposition layer 8 at the bottom of the TSV via 7, and the oxide deposition layer on the side wall of the TSV via 7 remaining exposed; injecting ions into the oxide deposition layer 8 on the side wall of the TSV via 7. The photoresist layer 10 serves as a protective layer to cover the areas that do not need to be implanted, ensuring that the ions are only implanted into the oxide deposition layer 8 on the side wall of the TSV via 7.

[0085] After the ion implantation is completed, an etching step is performed. The oxide deposition layer 8 on the sidewall of the TSV via 7 is not etched away due to the implanted ions, and thus can play a role in insulating from other electrical connection structures and preventing leakage.

[0086] Protecting the oxide deposition layer 8 on the sidewall of the TSV via 7 by using the lithography technology of the oxide layer on the sidewall of the TSV via 7 can solve the problem that the etching of the oxide layer at the bottom of the TSV causes damage and thus leads to leakage between the TSVs, affecting the performance.

[0087] The present invention is also applicable to the passivation layer technology.

[0088] Combined with the first aspect of the present invention, in some embodiments of the present invention, before the step of opening the TSV via 7 on the bottom surface of any wafer, it further includes:

[0089] Deposit a passivation layer 11 on the bottom surface 602 of the wafer where the TSV via 7 needs to be opened, and open the TSV via 7 along the direction of the passivation layer 11 towards the metal interconnect structure 3. The semiconductor passivation layer 11 is a key step in semiconductor device manufacturing, mainly used to protect the device surface from the influence of the external environment (such as moisture, pollutants, mechanical damage, etc.), and at the same time improve the reliability and stability of the device.

[0090] Combined with the first aspect of the present invention, in some embodiments of the present invention, deposit a passivation layer 11 on the bottom surface 602 of the first wafer. The passivation layer 11 includes a combination of an oxide layer and a silicon layer, and may simultaneously include a plurality of spaced oxide layers and a plurality of silicon layers.

[0091] Combined with the first aspect of the present invention, in some embodiments of the present invention, the oxide deposition layer 8 covers the surface of the passivation layer 11.

[0092] In the ion implantation step, ions are also implanted into the oxide deposition layer 8 on the surface of the passivation layer 11.

[0093] Except for the structure of the passivation layer 11, the other implementation steps are the same as the foregoing implementation manners and will not be elaborated.

[0094] Adopting the 3D stacking method provided by the first aspect of the present invention, through the oxide deposition layer 8 on the sidewall of the TSV via 7, the oxide deposition layer 8 plays an insulating role and can improve the problem of leakage of the TSV via 7.

[0095] The second aspect of the present invention provides a semiconductor structure constructed by using the method provided by the first aspect of the present invention. The semiconductor structure is specifically a semiconductor bonding structure based on 3D stacking.

[0096] The semiconductor structure includes a first wafer and a second wafer bonded together.

[0097] The first wafer: includes a base layer 1 and an oxide layer 2. One side of the oxide layer 2 is a bonding surface 601, and one side of the base layer is a bottom surface 602. A metal interconnect structure 3 is provided in the oxide layer 2. A through hole is formed in the oxide layer 2 from the bonding surface 601 side. The through hole 4 communicates with the metal interconnect structure 3 and is filled with a conductor layer 5.

[0098] The second wafer: includes a base layer 1 and an oxide layer 2. One side of the oxide layer 2 is a bonding surface 601, and one side of the base layer is a bottom surface 602. A metal interconnect structure 3 is provided in the oxide layer 2. A through hole is formed in the oxide layer 2 from the bonding surface 601 side. The through hole 4 communicates with the metal interconnect structure 3 and is filled with a conductor layer 5.

[0099] The bonding surfaces of the first wafer and the second wafer face each other, and the conductor layer 5 of the first wafer is connected to the conductor layer 5 of the second wafer.

[0100] A TSV through hole 7 is formed on the bottom surface of the first wafer in the direction of the metal interconnect structure 3. The TSV through hole 7 communicates with the metal interconnect structure 3 of the first wafer.

[0101] An oxide deposition layer 8 is deposited on the side surface of the TSV through hole 7. The oxide deposition layer 8 covers the side surface of the TSV through hole 7 and exposes the metal interconnect structure 3 at the bottom of the TSV through hole 7. Ion implantation is performed inside the oxide deposition layer on the side surface of the TSV through hole 7. The types of implanted ions include, but are not limited to: B, BF2, Si, Al, Phosp, AS.

[0102] The TSV through hole 7 is filled with a TSV through hole conductor layer 9, and the TSV through hole conductor layer 9 communicates with the metal interconnect structure 3 of the first wafer.

[0103] In some embodiments of the present invention, a passivation layer 11 is provided on the bottom surface of the first wafer, and the oxide deposition layer 8 covers the passivation layer 11.

[0104] The above are only the preferred embodiments of the present invention and are not intended to limit the present invention. It should be noted that for those of ordinary skill in the art, any modifications, equivalent replacements, and improvements made within the spirit and principle of the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the patent application of the present invention shall be subject to the protection scope of the appended claims.

Claims

1. A method for improving 3D wafer stacking performance, characterized in that: include: Providing a wafer, the wafer comprising a base layer and an oxide layer, one side of the oxide layer being a bonding surface, and one side of the base layer being a bottom surface; A metal interconnection structure is arranged in the oxide layer, and a through hole is opened in the oxide layer from the bonding surface side, wherein the through hole is connected to the metal interconnection structure and filled with the conductor layer; The bonding surfaces of one wafer and another wafer are opposite, and the conductor layers of the two wafers are connected; Opening a TSV through hole on the bottom surface of any wafer in the direction of the metal interconnection structure, wherein the TSV through hole is connected to the metal interconnection structure; Depositing an oxide deposition layer in the TSV through hole, wherein the oxide deposition layer covers the sidewalls and the bottom of the TSV through hole; Depositing a photoresist layer, wherein the photoresist layer covers the oxide deposition layer at the bottom of the TSV through hole, and the oxide deposition layer on the side wall of the TSV through hole is still exposed; and injecting ions into the oxide deposition layer on the side wall of the TSV through hole; Performing a photolithography step to partially remove the oxide deposition layer at the bottom of the TSV through hole, exposing the metal interconnection structure at the bottom of the TSV through hole, so that the oxide deposition layer covers the sidewall of the TSV through hole and a portion of the bottom area adjacent to the sidewall of the TSV through hole; A TSV through hole conductor layer is deposited into the TSV through hole, wherein the TSV through hole conductor layer is connected to the metal interconnection structure.

2. The method for improving 3D wafer stacking performance as claimed in claim 1, wherein: The types of implanted ions include but are not limited to: B, BF2, Si, Al, Phosp, AS.

3. The method for improving 3D wafer stacking performance as claimed in claim 1, wherein: The energy of the implanted ions is controlled at 2KeV-50KeV.

4. The method for improving 3D wafer stacking performance as claimed in claim 1, wherein: The dose of implanted ions is controlled at 1e 12 / cm 2 -1e 15 / cm 2 .

5. The method for improving 3D wafer stacking performance as claimed in claim 1, wherein: The thickness of the oxide deposition layer is .

6. The method for improving 3D wafer stacking performance as claimed in claim 1, wherein: Before any TSV through-hole step is performed on the bottom surface of the wafer, the method further includes: A passivation layer is deposited on the bottom surface of the wafer where TSV through holes are required to be opened, and TSV through holes are opened along the passivation layer toward the metal interconnection structure; the passivation layer includes a combination of an oxide layer and a silicon layer.

7. The method for improving 3D wafer stacking performance as claimed in claim 6, wherein: The oxide deposition layer covers the surface of the passivation layer, and in the ion implantation step, ions are implanted into the oxide deposition layer on the surface of the passivation layer.

8. A semiconductor structure, characterized in that: The method according to any one of claims 1 to 7 is used to construct the device, comprising: The first wafer comprises a base layer and an oxide layer, wherein one side of the oxide layer is a bonding surface, and one side of the base layer is a bottom surface; a metal interconnection structure is arranged in the oxide layer, and a through hole is opened in the oxide layer from the bonding surface side, wherein the through hole is connected to the metal interconnection structure and filled with a conductor layer; The second wafer comprises a base layer and an oxide layer, wherein one side of the oxide layer is a bonding surface, and one side of the base layer is a bottom surface; a metal interconnection structure is arranged in the oxide layer, and a through hole is opened in the oxide layer from the bonding surface side, wherein the through hole is connected to the metal interconnection structure and filled with a conductor layer; The bonding surfaces of the first wafer and the second wafer are opposite to each other, and the conductor layer of the first wafer is connected to the conductor layer of the second wafer; A TSV through hole is opened on the bottom surface of the first wafer in the direction of the metal interconnection structure, wherein the TSV through hole is connected to the metal interconnection structure of the first wafer; Depositing an oxide deposition layer on the side wall of the TSV through hole, and implanting ions inside the oxide deposition layer on the side of the TSV through hole; The TSV through hole fills a TSV through hole conductor layer, and the TSV through hole conductor layer is connected to the metal interconnection structure of the first wafer.

9. The semiconductor structure according to claim 8, characterized in that A passivation layer is disposed on the bottom surface of the first wafer, and the oxide deposition layer covers the passivation layer.

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