A power module package structure integrated with a protection circuit

Abstract

This invention discloses a power module packaging structure with integrated protection circuitry, relating to the field of semiconductor packaging technology. The packaging structure includes a support substrate and a first DBC substrate and a second DBC substrate disposed on the support substrate. At least one power chip is disposed on the first DBC substrate. The second DBC substrate includes a capacitor integration region, within which at least one capacitor module is disposed. The capacitor module includes a first insulating dielectric layer fabricated on the capacitor integration region and a first conductive layer fabricated on the first insulating dielectric layer. A protection capacitor is formed based on the capacitor integration region, the first insulating dielectric layer, and the first conductive layer, and is electrically connected between a first electrode and a second electrode of the power chip. This invention integrates the protection circuitry within the packaging structure, and the protection capacitor in the protection circuitry is formed by stacking the first insulating dielectric layer and the first conductive layer, simplifying the fabrication process and saving fabrication costs.

Description

Technical Field

[0001] This invention relates to the field of semiconductor packaging technology, and in particular to a power module packaging structure with integrated protection circuitry. Background Technology

[0002] A power module is a module formed by combining power electronic devices according to certain functions and then encapsulating them. IGBT (Insulated Gate Bipolar Transistor) power modules are widely used in frequency converters, electric vehicles, and switching power supplies due to their advantages such as high voltage withstand, high current, and low loss. However, IGBTs are prone to voltage spikes when turned off, which can damage the devices. Therefore, IGBT power modules usually need to be used in conjunction with protection circuits.

[0003] Currently, traditional power module packaging layouts are compact, making it difficult to incorporate additional protection circuitry within the original package structure. Furthermore, protection circuitry typically includes capacitors, which are not easily soldered onto the DBC substrate using conventional methods. They require reflow soldering using tooling fixtures, resulting in cumbersome fabrication and increased manufacturing costs. Summary of the Invention

[0004] To address the aforementioned problems and technical requirements, the inventors have proposed a power module packaging structure integrating protection circuitry. The technical solution of this invention is as follows:

[0005] A power module packaging structure with integrated protection circuitry includes a support substrate and a first DBC substrate and a second DBC substrate disposed on the support substrate.

[0006] At least one power chip is disposed on the first DBC substrate;

[0007] The second DBC substrate includes a capacitor integration area, in which at least one capacitor module is disposed;

[0008] The capacitor module includes a first insulating dielectric layer fabricated on the capacitor integration region, and a first conductive layer fabricated on the first insulating dielectric layer.

[0009] A protective capacitor is formed based on the capacitor integration area, the first insulating dielectric layer, and the first conductive layer, and the protective capacitor is electrically connected between the first electrode and the second electrode of the power chip.

[0010] A further technical solution is that a third DBC substrate is also provided on the supporting substrate, and the third DBC substrate includes a resistor integration area;

[0011] The first DBC substrate includes an electrical connection area, the power chip is disposed in the electrical connection area, and at least one protective resistor is disposed in the resistor integration area;

[0012] The second electrode of the power chip is electrically connected to the electrical connection area, the electrical connection area is electrically connected to one end of the protection resistor, the other end of the protection resistor is electrically connected to the first conductive layer, and the capacitor integration area is electrically connected to the first electrode of the power chip.

[0013] A further technical solution is that the second DBC substrate further includes a grounding area, which is electrically connected to the capacitor integration area;

[0014] The grounding area is provided with a grounding through hole, which penetrates the second DBC substrate and the supporting substrate. The grounding through hole is filled with a grounding post, and the grounding area is grounded through the grounding post.

[0015] A further technical solution is that the first DBC substrate further includes an electrode lead-out area, which is electrically connected to the first electrode of the power chip.

[0016] A further technical solution includes a first electrode terminal, a second electrode terminal, and a grounding terminal. The first electrode terminal is electrically connected to the electrode lead-out area, the second electrode terminal is electrically connected to the electrical connection area, and the grounding terminal is electrically connected to the grounding area.

[0017] A further technical solution is that the power chip is an IGBT chip or a SiC MOSFET chip.

[0018] A further technical solution is that, when the power chip is an IGBT chip, at least one diode chip is also disposed on the first DBC substrate, the anode of the diode chip is electrically connected to the first electrode of the power chip, and the cathode of the diode chip is electrically connected to the second electrode of the power chip.

[0019] A further technical solution is that the first DBC substrate includes a plurality of first electrode leads and a plurality of third electrode leads;

[0020] The first electrode lead is electrically connected to the first electrode of the power chip, and the third electrode lead is electrically connected to the third electrode of the power chip.

[0021] A further technical solution is that a second insulating dielectric layer is disposed above the first DBC substrate, and a conductive layer group is disposed on the second insulating dielectric layer;

[0022] The second insulating dielectric layer is disposed above the first electrode lead and the third electrode lead, and the power chip is disposed above the conductive layer group, which includes a second conductive layer and a third conductive layer.

[0023] The second insulating dielectric layer is provided with a plurality of first conductive pillars and a plurality of second conductive pillars, the first conductive pillars and the second conductive pillars penetrating the second insulating dielectric layer;

[0024] One end of the first conductive post is in contact with the first electrode lead, and the other end of the first conductive post is in contact with one side of the second conductive layer. The other side of the second conductive layer is in contact with the first electrode of the power chip.

[0025] One end of the second conductive post is in contact with the third electrode lead, and the other end of the second conductive post is in contact with one side of the third conductive layer. The other side of the third conductive layer is in contact with the third electrode of the power chip.

[0026] A further technical solution is that the materials of the first conductive layer, the second conductive layer, and the third conductive layer include copper.

[0027] The beneficial technical effects of this invention are:

[0028] This invention incorporates a second DBC substrate within the packaging structure, and a capacitor integration region is formed on the second DBC substrate. A protective capacitor is constructed between the first electrode and the second electrode of the power chip using the capacitor integration region, a first insulating dielectric layer fabricated on the capacitor integration region, and a first conductive layer fabricated on the first insulating dielectric layer. This invention integrates a protection circuit within the original packaging structure, effectively suppressing voltage spikes and improving the module's current carrying capacity and stability. Furthermore, the protective capacitor in the protection circuit is formed by stacked insulating dielectric and conductive layers, and can be fabricated using existing module manufacturing processes, eliminating the need for reflow soldering, thus simplifying the manufacturing process and saving costs. Attached Figure Description

[0029] Figure 1 This is a top view schematic diagram of the power module packaging structure in Embodiment 1 of the present invention.

[0030] Figure 2 This is a cross-sectional schematic diagram of the power module packaging structure in Embodiment 1 of the present invention.

[0031] Figure 3 This is a schematic cross-sectional view of the second DBC substrate at the grounding via in Embodiment 1 of the present invention.

[0032] Figure 4 This is a top view schematic diagram of the first DBC substrate in Embodiment 2 of the present invention.

[0033] Figure 5 This is a side view schematic diagram of the first DBC substrate in Embodiment 2 of the present invention.

[0034] Figure label:

[0035] 1-Supporting substrate, 2-First electrode terminal, 3-Second electrode terminal, 4-Grounding terminal;

[0036] 10-First DBC substrate, 11-Electrical connection layer, 12-Power chip, 13-Diode chip, 14-Electrode lead area, 15-First electrode lead, 16-Third electrode lead, 17-Second insulating dielectric layer, 18-First conductive pillar, 19-Second conductive pillar, 201-Second conductive layer, 202-Third conductive layer;

[0037] 20-Second DBC substrate, 21-Capacitor integration area, 22-First insulating dielectric layer, 23-First conductive layer, 24-Grounding area, 25-Grounding post, 26-Grounding via;

[0038] 30 - Third DBC substrate, 31 - Resistor integration area, 32 - Protection resistor. Detailed Implementation

[0039] The specific embodiments of the present invention will be further described below with reference to the accompanying drawings.

[0040] The present invention provides a power module packaging structure with integrated protection circuit, including a support substrate 1 and a first DBC substrate 10 and a second DBC substrate 20 disposed on the support substrate 1.

[0041] At least one power chip 12 is disposed on the first DBC substrate 10;

[0042] The second DBC substrate 20 includes a capacitor integration area 21, in which at least one capacitor module is disposed;

[0043] The capacitor module includes a first insulating dielectric layer 22 fabricated on the capacitor integration region 21, and a first conductive layer 23 fabricated on the first insulating dielectric layer 22.

[0044] A protective capacitor is formed based on the capacitor integration area 21, the first insulating dielectric layer 22 and the first conductive layer 23, and the protective capacitor is electrically connected between the first electrode and the second electrode of the power chip 12.

[0045] Specifically, the first and second DBC (Direct Bonded Copper) substrates are in the same form as in the prior art. A typical DBC substrate includes a top copper layer, a ceramic layer, and a bottom copper layer stacked sequentially from top to bottom. The top copper layer is patterned and divided into multiple different conductive regions, and the bottom copper layer is soldered to the support substrate 1. The capacitor integration area 21 is the conductive region formed after the top copper layer of the second DBC substrate 20 is patterned.

[0046] Figure 1 and Figure 2 A schematic diagram of the power module packaging structure in Embodiment 1 of the present invention is shown. The integrated protection circuit includes at least one protection capacitor. The present invention uses the capacitor integration area 21 and the first conductive layer 23 as the electrode plate of the protection capacitor and the first insulating dielectric layer 22 as the dielectric layer of the protection capacitor to form a protection capacitor. The protection capacitor is electrically connected between the first electrode and the second electrode of the power chip 12, which can suppress the voltage spike generated when the power chip 21 is turned off and improve the overall stability of the power module.

[0047] The first conductive layer 23 can be made of copper, and the first insulating dielectric layer 22 is made of the same material as the ceramic layer in the DBC substrate. That is, both the first insulating dielectric layer 22 and the first conductive layer 23 in the capacitor module can be made using the same materials as the DBC substrate. The protection capacitor can be fabricated using the existing fabrication process and fixtures for the power module, eliminating the need for additional reflow soldering or other process steps and fixtures. This simplifies the fabrication process and saves on fabrication costs while integrating the protection circuit within the power module. The specific method by which the protection capacitor is electrically connected between the first and second electrodes of the power chip 12 can be referred to the following description. Multiple capacitor modules can be disposed on the capacitor integration area 21 to form multiple protection capacitors. In specific implementation, the number of capacitor modules and the connection relationship between the multiple protection capacitors can be determined according to the circuit topology of the required protection circuit.

[0048] Furthermore, a third DBC substrate 30 is also provided on the support substrate 1, and the third DBC substrate 30 includes a resistor integration region 31;

[0049] The first DBC substrate 10 includes an electrical connection area 11, the power chip 12 is disposed in the electrical connection area 11, and at least one protection resistor 32 is disposed in the resistor integration area 31.

[0050] The second electrode of the power chip 12 is electrically connected to the electrical connection area 11, the electrical connection area 11 is electrically connected to one end of the protection resistor 32, the other end of the protection resistor 32 is electrically connected to the first conductive layer 23, and the capacitor integration area 21 is electrically connected to the first electrode of the power chip 12.

[0051] Specifically, the electrical connection area 11 is a conductive area formed by patterning the top copper layer of the first DBC substrate 10, and the resistor integration area 31 is a conductive area formed by patterning the third DBC substrate 30. The protection resistor 32 can be a vertical resistor. In the first embodiment, the protection circuit includes a protection resistor 32 and a protection capacitor formed based on the above-mentioned capacitor module. One end of the protection resistor 32, i.e., the first pin, is soldered to the resistor integration area 31. The resistor integration area 31 is electrically connected to the electrical connection area 11 through a bonding wire. The electrical connection area 11 is electrically connected to the second electrode of the power chip 12. The other end of the protection resistor 32, i.e., the second pin, is electrically connected to the first conductive layer 23 through a bonding wire. The capacitor integration area 21 is electrically connected to the first electrode of the power chip 12, so that the first electrode of the power chip 12 is connected to the second electrode of the power chip 12 in sequence through the protection capacitor and the protection resistor 32, so as to integrate the protection circuit into the power module. In specific implementation, multiple protective resistors 32 can be set on the resistor integration area 31. The number of protective resistors 32 and the connection relationship of the multiple protective resistors 32 can be determined according to the circuit topology of the required protection circuit.

[0052] The power chip 12 is an IGBT chip or a SiC MOSFET chip. For an IGBT chip, the first electrode is the emitter, and the second electrode is the collector. The IGBT chip also includes a gate. The IGBT / SiC MOSFET chip includes a front side and a corresponding back side. Generally, the front side of an IGBT chip has a gate and an emitter, and the back side has a collector. The front side of a SiC MOSFET chip has a gate and a source, and the back side has a drain.

[0053] When the power chip 12 is an IGBT chip, at least one diode chip 13 for freewheeling is also disposed on the electrical connection area 11 of the first DBC substrate 10. The diode chip 13 is connected in reverse parallel with the IGBT chip, that is, the anode of the diode chip 13 is electrically connected to the first electrode (emitter) of the IGBT chip, and the cathode of the diode chip 13 is electrically connected to the second electrode (collector) of the IGBT chip. Specifically, the diode chip 13 also includes a front side and a back side corresponding to the front side. Generally, the anode is disposed on the front side of the diode chip 13, and the cathode is disposed on the back side of the diode chip 13.

[0054] In Embodiment 1, the power chip 12 is an IGBT chip. The back of the IGBT chip is soldered to the electrical connection area 11, so that the collector of the IGBT chip is electrically connected to the electrical connection area 11. The back of the diode chip 13 is soldered to the electrical connection area 11, so that the cathode of the diode chip 13 is electrically connected to the electrical connection area 11, thereby electrically connecting to the collector of the IGBT chip. The collector of the IGBT chip is electrically connected to the anode of the diode chip 13 through bonding wires, and the capacitor integration area 21 is electrically connected to the anode of the diode chip 13 through bonding wires, so that one end of the protection capacitor is electrically connected to the emitter of the IGBT chip.

[0055] In Embodiment 1, the first DBC substrate 10 further includes an electrode lead-out area 14, which is electrically connected to the first electrode of the power chip 12. The electrode lead-out area 14 and the electrical connection area 11 are both conductive areas formed by patterning the top copper layer of the first DBC substrate 10. The electrode lead-out area 14 is electrically connected to the anode of the diode chip 13 through a bonding wire, thereby being electrically connected to the first electrode of the power chip 12.

[0056] Furthermore, the second DBC substrate 20 also includes a grounding area 24, which is electrically connected to the capacitor integration area 21;

[0057] The grounding area 24 is provided with a grounding through hole 26, which penetrates the second DBC substrate 20 and the supporting substrate 1. The grounding through hole 26 is filled with a grounding post 25, and the grounding area 24 is grounded through the grounding post 25.

[0058] Specifically, the grounding area 24 and the capacitor integration area 21 are both conductive areas formed by patterning the top copper layer of the second DBC substrate 20. The grounding area 24 is electrically connected to the capacitor integration area 21 through bonding wires. Figure 3 As shown, the grounding through hole 26 penetrates the second DBC substrate 20 and the support substrate 1. The grounding through hole 26 is filled with a grounding post 25. The grounding post 25 provides a grounding path for the power module. The grounding post 25 contacts the grounding area 24 so that the grounding area 24 is grounded through the grounding post 25. The specific form of the grounding post 25 can be consistent with the prior art.

[0059] To facilitate the electrode lead-out of the power module, the power module also includes a first electrode terminal 2, a second electrode terminal 3, and a ground terminal 4. In Embodiment 1, the first electrode terminal 2 is welded to the electrode lead-out area 14, the second electrode terminal 3 is welded to the electrical connection area 11, and the ground terminal 4 is welded to the grounding area 24.

[0060] In Embodiment 1, the back side of the power chip 12 is soldered to the electrical connection layer 11 of the first DBC substrate 10. The first electrode on the front side of the power chip 12 is connected to the anode of the diode chip 13 via a bonding wire, and is also electrically connected to the electrode lead-out area 14 via a bonding wire. However, the bonding wire is prone to breakage, reducing the stability of the electrode lead-out. To improve the stability of the electrode lead-out and enhance the reliability of the power module, Embodiment 2 of the present invention provides another electrode lead-out method for the power chip 12.

[0061] The difference between Embodiment 2 and Embodiment 1 is that the first DBC substrate 10 includes a plurality of first electrode leads 15 and a plurality of third electrode leads 16; the first electrode leads 15 are electrically connected to the first electrode of the power chip 12, and the third electrode leads 16 are electrically connected to the third electrode of the power chip 12.

[0062] A second insulating dielectric layer 17 is also disposed above the first DBC substrate 10, and a conductive layer group is disposed on the second insulating dielectric layer 17; the second insulating dielectric layer 17 is disposed above the first electrode lead 15 and the third electrode lead 16, and the power chip 12 is disposed above the conductive layer group, the conductive layer group including the second conductive layer 201 and the third conductive layer 202.

[0063] The second insulating dielectric layer 17 contains a plurality of first conductive pillars 18 and a plurality of second conductive pillars 19, which penetrate the second insulating dielectric layer 17. One end of the first conductive pillar 18 contacts the first electrode lead 15, and the other end of the first conductive pillar 18 contacts one side of the second conductive layer 201, which in turn contacts the first electrode of the power chip 12. One end of the second conductive pillar 19 contacts the third electrode lead 16, and the other end of the second conductive pillar 19 contacts one side of the third conductive layer 202, which in turn contacts the third electrode of the power chip 12. The third electrode of the power chip 12 represents the gate of an IGBT chip or a SiC MOSFET chip.

[0064] Figure 4 and Figure 5 The diagram shows a schematic of the first DBC substrate 10 in Embodiment 2 of the present invention. The first electrode lead 15 and the third electrode lead 16 are conductive patterns formed after the top copper layer of the first DBC substrate 10 is patterned. In Embodiment 2, two first electrode leads 15 and one third electrode lead 16 are arranged in parallel on the ceramic layer of the first DBC substrate 10. The third electrode lead 16 is disposed between the two first electrode leads 15.

[0065] The second insulating dielectric layer 17 is disposed above the first electrode lead 15 and the third electrode lead 16, and the first electrode lead 15 and the third electrode lead 16 extend from below the second insulating dielectric layer 17 along the ceramic layer of the first DBC substrate 10 to the outside of the second insulating dielectric layer 17 to facilitate the lead-out of the electrodes.

[0066] The first conductive post 18 and the second conductive post 19 are perpendicular to the surface of the second insulating dielectric layer 17 and penetrate the second insulating dielectric layer 17. The first conductive post 18 and the second conductive post 19 can be obtained by forming through holes in the second insulating dielectric layer 17 and filling them with conductive dielectric. In this embodiment, a total of two rows of first conductive posts 18 and one second conductive post 19 are provided, with the second conductive post 19 located between the two rows of first conductive posts 18. Each row of first conductive posts 18 corresponds to a first electrode lead 15, and any row of first conductive posts 18 is provided with three first conductive posts 18 spaced apart along the length direction of the first electrode lead 15. One end of the first conductive post 18 is welded to the corresponding first electrode lead 15, and one end of the second conductive post 19 is welded to the third electrode lead 16.

[0067] The power chip 12 is disposed on the conductive layer group and faces the conductive layer group. The second conductive layer 201 and the third conductive layer 202 have the same thickness and are mutually insulated. The other end of the first conductive post 18 is soldered to one side of the second conductive layer 201. The first electrode disposed on the front side of the power chip 12 is soldered to the other side of the second conductive layer 201 so that the first electrode of the power chip 12 is led out through the second conductive layer 201, the first conductive post 18 and the first electrode lead-out line 15.

[0068] The other end of the second conductive post 19 is soldered to one side of the third conductive layer 202, and the third electrode disposed on the front side of the power chip 12 is soldered to the other side of the third conductive layer 202, so that the third electrode of the power chip 12 is led out through the third conductive layer 202, the second conductive post 19, and the third electrode lead-out line 16. The second electrode disposed on the power chip 12 can be led out through a copper frame in the prior art. In the second embodiment, the power chip 12 is a SiC MOSFET chip, in which case the diode chip 13 is not required.

[0069] Leading out the electrodes of the power chip 12 in the manner described in Embodiment 2 not only reduces the number of bonding wires used and lowers the risk of failure due to bonding wire breakage, but also expands the heat dissipation path of the power chip 12 through the conductive layer group, increasing the heat dissipation area and further improving the reliability of the power module. In Embodiment 2, one end of the protection resistor 32 can be directly electrically connected to the third electrode of the power chip 12 through a bonding wire, and the capacitor integration area 21 can be electrically connected to the first electrode lead 15 through a bonding wire, so that the protection circuit is set between the first electrode and the second electrode of the power chip 12. In Embodiment 2, the first electrode terminal 2 can be soldered to the first electrode lead 15, the second electrode terminal 3 can be soldered to the second electrode on the back of the power chip 12, and the ground terminal 4 is soldered to the grounding area 24. The material of the second insulating dielectric layer 17 can be the same as the material of the ceramic layer of the DBC substrate, and the materials of the second conductive layer 201 and the third conductive layer 202 can be copper.

[0070] It should be noted that the terms "front," "rear," "left," "right," "up," and "down" used in the above description refer to the directions in the accompanying drawings of this application, and the terms "front" and "back," "inner" and "outer" refer to facing or away from a specific component, respectively. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated.

[0071] The above descriptions are merely preferred embodiments of the present invention, and the present invention is not limited to the above embodiments. It is understood that other improvements and variations that can be directly derived or conceived by those skilled in the art without departing from the spirit and concept of the present invention should be considered to be included within the protection scope of the present invention.

Claims

1. A power module packaging structure with integrated protection circuitry, characterized in that, It includes a support substrate and a first DBC substrate and a second DBC substrate disposed on the support substrate; At least one power chip is disposed on the first DBC substrate; The second DBC substrate includes a capacitor integration area, in which at least one capacitor module is disposed; The capacitor module includes a first insulating dielectric layer fabricated on the capacitor integration region, and a first conductive layer fabricated on the first insulating dielectric layer. A protective capacitor is formed based on the capacitor integration area, the first insulating dielectric layer and the first conductive layer, and the protective capacitor is electrically connected between the first electrode and the second electrode of the power chip. The first DBC substrate includes a plurality of first electrode leads and a plurality of third electrode leads; The first electrode lead is electrically connected to the first electrode of the power chip, and the third electrode lead is electrically connected to the third electrode of the power chip. A second insulating dielectric layer is disposed above the first DBC substrate, and a conductive layer group is disposed on the second insulating dielectric layer; The second insulating dielectric layer is disposed above the first electrode lead and the third electrode lead, and the power chip is disposed above the conductive layer group, which includes a second conductive layer and a third conductive layer. The second insulating dielectric layer is provided with a plurality of first conductive pillars and a plurality of second conductive pillars, the first conductive pillars and the second conductive pillars penetrating the second insulating dielectric layer; One end of the first conductive post is in contact with the first electrode lead, and the other end of the first conductive post is in contact with one side of the second conductive layer. The other side of the second conductive layer is in contact with the first electrode of the power chip. One end of the second conductive post is in contact with the third electrode lead, and the other end of the second conductive post is in contact with one side of the third conductive layer. The other side of the third conductive layer is in contact with the third electrode of the power chip.

2. The power module packaging structure of the integrated protection circuit according to claim 1, characterized in that, A third DBC substrate is also provided on the support substrate, and the third DBC substrate includes a resistor integration area. The first DBC substrate includes an electrical connection area, the power chip is disposed in the electrical connection area, and at least one protective resistor is disposed in the resistor integration area; The second electrode of the power chip is electrically connected to the electrical connection area, the electrical connection area is electrically connected to one end of the protection resistor, the other end of the protection resistor is electrically connected to the first conductive layer, and the capacitor integration area is electrically connected to the first electrode of the power chip.

3. The power module packaging structure of the integrated protection circuit according to claim 1, characterized in that, The second DBC substrate also includes a grounding area, which is electrically connected to the capacitor integration area; The grounding area is provided with a grounding through hole, which penetrates the second DBC substrate and the supporting substrate. The grounding through hole is filled with a grounding post, and the grounding area is grounded through the grounding post.

4. The power module packaging structure of the integrated protection circuit according to claim 3, characterized in that, The first DBC substrate further includes an electrode lead-out area, which is electrically connected to the first electrode of the power chip.

5. The power module packaging structure of the integrated protection circuit according to claim 4, characterized in that, It also includes a first electrode terminal, a second electrode terminal, and a grounding terminal. The first electrode terminal is electrically connected to the electrode lead-out area, the second electrode terminal is electrically connected to the electrical connection area, and the grounding terminal is electrically connected to the grounding area.

6. The power module packaging structure of the integrated protection circuit according to claim 1, characterized in that, The power chip is an IGBT chip or a SiC MOSFET chip.

7. The power module packaging structure of the integrated protection circuit according to claim 6, characterized in that, When the power chip is an IGBT chip, at least one diode chip is also disposed on the first DBC substrate. The anode of the diode chip is electrically connected to the first electrode of the power chip, and the cathode of the diode chip is electrically connected to the second electrode of the power chip.

8. The power module packaging structure of the integrated protection circuit according to claim 1, characterized in that, The materials of the first conductive layer, the second conductive layer, and the third conductive layer include copper.

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