Encapsulation Substrate and Its Manufacturing Method

Abstract

The present invention provides an encapsulation substrate and a manufacturing method thereof. The encapsulation substrate includes forming a circuit structure on a core layer having a plurality of conductive posts, and forming a support structure in the core layer and in the circuit structure and disposed corresponding to the peripheral region of the core layer, so that the support structure can effectively inhibit delamination of the circuit structure.

Description

Technical Field

[0001] The present invention relates to a semiconductor packaging technology, and particularly to a packaging substrate capable of improving reliability and a manufacturing method thereof. Background Art

[0002] With the evolution of semiconductor packaging technology, different packaging forms have been developed for semiconductor devices. The semiconductor device mainly disposes a semiconductor chip on a packaging substrate, electrically connects the semiconductor chip to the packaging substrate, and then coats the semiconductor chip with a packaging colloid.

[0003] Figures 1A to 1C It is a schematic cross-sectional view of the manufacturing method of the existing packaging substrate 1.

[0004] As Figure 1A shown, a plurality of through holes 100 are formed in a core layer 10.

[0005] As Figure 1B shown, a wiring layer 12 is respectively formed on the upper and lower sides of the core layer 10 by a patterning process, and a plurality of conductive posts 11 electrically connecting the wiring layer 12 are formed in each of the through holes 100.

[0006] As Figure 1C shown, a circuit structure 14 is respectively formed on the upper and lower sides of the core layer 10, and a metal sheet 15 is formed at the edge of the circuit structure 14. The circuit structure 14 includes at least one dielectric layer 140, a circuit layer 141 formed on the dielectric layer 140, and a plurality of conductive blind holes 142 formed in the dielectric layer 140 and electrically connecting the circuit layer 141 and the wiring layer 12.

[0007] In subsequent processes, a solder mask such as green paint can be formed on the circuit structure 14 (figure omitted).

[0008] However, in the manufacturing method of the existing packaging substrate 1, the metal sheet 15 is too thin. In the process of the entire layout specification, due to excessive stress between the dielectric layers 140, it is difficult to suppress delamination between the dielectric layers 140, resulting in moisture infiltration and damage to the electrical function or poor reliability.

[0009] On the other hand, the bonding force between the dielectric layer 140 and the core layer 10 is also poor, and delamination problems are likely to occur at high temperatures during the process. Moreover, the metal sheet 15 is too thin to effectively suppress the occurrence of delamination, as Figure 1C-1 shown at the edge C, resulting in moisture infiltration and damage to the electrical function or poor reliability.

[0010] Therefore, how to avoid various defects of the prior art has actually become an urgent issue to be solved at present. Summary of the Invention

[0011] In view of the above-mentioned various defects of the prior art, the present invention provides a packaging substrate, including: a core layer, defining a wiring area and a peripheral area surrounding the wiring area; a plurality of conductive posts, formed in the wiring area of the core layer and connecting opposite sides of the core layer; a wiring layer, formed on opposite sides of the core layer and electrically connecting the plurality of conductive posts; a circuit structure, formed on at least one side of the wiring area and the peripheral area of the core layer and electrically connecting the wiring layer; and a support structure, formed in the core layer and the circuit structure and disposed corresponding to the peripheral area.

[0012] The present invention also provides a method for manufacturing a packaging substrate, including: providing a core layer defining a wiring area and a peripheral area surrounding the wiring area; forming a plurality of conductive posts in the wiring area of the core layer and connecting opposite sides of the core layer, and forming a wiring layer on opposite sides of the core layer and electrically connecting the plurality of conductive posts; forming a circuit structure on at least one side of the wiring area and the peripheral area of the core layer, and electrically connecting the circuit structure to the wiring layer; and forming a support structure in the core layer and the circuit structure and disposing the support structure corresponding to the peripheral area.

[0013] In a specific embodiment of the foregoing packaging substrate and its manufacturing method, the circuit structure is formed on opposite sides of the core layer, making the packaging substrate symmetric.

[0014] In a specific embodiment of the foregoing packaging substrate and its manufacturing method, the circuit structure is only formed on one side of the core layer, making the packaging substrate asymmetric.

[0015] In a specific embodiment of the foregoing packaging substrate and its manufacturing method, the support structure is not electrically connected to the circuit structure.

[0016] In a specific embodiment of the foregoing packaging substrate and its manufacturing method, the support structure includes at least one support post formed in the core layer and at least one support block formed in the circuit structure. For example, the support block is connected to the support post, making the support structure stacked. Or, the support block is not connected to the support post, making the support structure in a stepped form. Further, the support block can be in the shape of a rivet, a grid, or a frame.

[0017] In a specific embodiment of the foregoing packaging substrate and its manufacturing method, the support structure can include a plurality of support blocks, and the support structure further includes connection pads for overlapping adjacent upper and lower support blocks.

[0018] In a specific embodiment of the foregoing packaging substrate and its manufacturing method, when the support structure is in a stacked form, a connection pad may be formed between the support block and the support column to connect the support block and the support column.

[0019] In a specific embodiment of the foregoing packaging substrate and its manufacturing method, the material of the core layer is an organic material, glass, ceramic, silicon carbide (SiC), AlO 2 or a composite material with a modulus of 50 to 100 GPa.

[0020] As can be seen from the above, in the packaging substrate and its manufacturing method of the present invention, mainly through the design that the support structure is formed in the core layer and the circuit structure and corresponds to the peripheral area, the adhesion between the dielectric layers and between the dielectric layer and the core layer is enhanced. Therefore, compared with the prior art, when delamination occurs between the dielectric layers (or between the dielectric layer and the core layer) at high temperature during the process, the support structure (especially the support block) can effectively inhibit the occurrence of delamination to avoid problems such as moisture infiltration damaging the electrical function or poor reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figures 1A to 1C It is a schematic cross-sectional view of the manufacturing method of the existing packaging substrate.

[0022] Figure 1C-1 is Figure 1C a partial enlarged schematic cross-sectional view of.

[0023] Figures 2A to 2C It is a schematic cross-sectional view of the manufacturing method of the packaging substrate of the present invention.

[0024] Figure 3A and Figure 3B It is a schematic top view of different specifications of the packaging substrate of the present invention.

[0025] Figures 4A to 4C is Figure 2C a schematic cross-sectional view of other different embodiments of.

[0026] Figure 5A and Figure 5B is Figure 3A and Figure 3B a schematic top view of other different embodiments of.

[0027] Figure 6A and Figure 6B is Figure 5A and Figure 5B a schematic top view of other different embodiments of.

[0028] The reference numerals are as follows:

[0029] 1, 2~6 Packaging substrate

[0030] 10, 20 Core Layer

[0031] 100, 200 Perforation

[0032] 11, 21 Conductive Posts

[0033] 12, 22 Wiring Layers

[0034] 14, 24 Circuit Structures

[0035] 140, 240 Dielectric Layers

[0036] 141, 241 Circuit Layers

[0037] 142, 242 Conductive Blind Holes

[0038] 15 Metal Sheets

[0039] 2a, 4a, 4b, 4c, 5a, 5b, 6a, 6b Support Structures

[0040] 201 Grooves

[0041] 23 Support Posts

[0042] 25, 45, 55, 65 Support Blocks

[0043] 250, 450 Connection Pads

[0044] 3a Strips

[0045] A Wiring Area

[0046] B Peripheral Area

[0047] C Edge

[0048] D1, D2, R Diameter Detailed Implementation Manner

[0049] The following illustrates the implementation manners of the present invention through specific embodiments. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification.

[0050] It should be noted that the structures, ratios, sizes, etc. shown in the attached drawings of this specification are only used to cooperate with the content disclosed in the specification for the understanding and reading of those skilled in the art, and are not used to limit the limiting conditions under which the present invention can be implemented. Therefore, they do not have technical substantial significance. Any modification of the structure, change of the proportional relationship, or adjustment of the size, without affecting the effects that the present invention can produce and the purposes that can be achieved, should still fall within the scope that can be covered by the technical content disclosed in the present invention. At the same time, the terms such as "upper", "first", "second", "one", etc. cited in this specification are only for the convenience of clear narration and are not used to limit the scope under which the present invention can be implemented. The change or adjustment of their relative relationships, without substantial change in the technical content, should also be regarded as the scope under which the present invention can be implemented.

[0051] Figures 2A to 2C It is a schematic cross-sectional view of the manufacturing method of the encapsulation substrate 2 of the present invention.

[0052] As Figure 2A shown, a core layer 20 is provided, which defines a wiring area A and a peripheral area B surrounding the wiring area A, and at least one through hole 200 is formed on the wiring area A of the core layer 20 and at least one through groove 201 is formed on the peripheral area B of the core layer 20 by means of laser, drilling or other methods.

[0053] In this embodiment, the material of the core layer 20 can be an organic material, glass, ceramic, silicon carbide (SiC), AlO 2 or a high-rigidity composite material with a modulus of 50 to 100 Gpa.

[0054] As Figure 2B shown, a wiring layer 22 is formed on the opposite sides of the core layer 20 by means of electroplating and patterning processes respectively, and a conductive column 21 electrically connecting the wiring layer 22 is formed in each through hole 200, and a support column 23 not electrically connecting the wiring layer 22 is formed in each through groove 201.

[0055] In this embodiment, the wiring layer 22, the conductive column 21 and the support column 23 can be formed by electroplated metal (such as copper) or other methods.

[0056] Furthermore, the plurality of conductive columns 21 are solid metal column bodies, such as copper columns. Or, in other embodiments, the plurality of conductive columns 21 can also be hollow copper columns, and the hollow parts can be filled with plugging materials such as insulating materials or conductive materials (not shown in the figure), and there is no special limitation.

[0057] As Figure 2CAs shown, a circuit structure 24 electrically connected to the wiring layer 22 and a support block 25 stacked and connected to the support pillar 23 are respectively formed on opposite sides of the core layer 20 to form a symmetric package substrate 2, and a support structure 2a is formed in the peripheral area B of the package substrate 2. In subsequent processes, a solder mask such as green paint can be formed on the circuit structure 24 (figure omitted).

[0058] The circuit structure 24 described above includes at least one dielectric layer 240, a circuit layer 241 formed on the dielectric layer 240, and a plurality of conductive blind vias 242 formed in the dielectric layer 240 and electrically connecting the circuit layer 241 and the wiring layer 22. At the same time, when forming the circuit layer 241, connection pads 250 connecting the upper and lower adjacent support blocks 25 can be correspondingly formed, and connection pads 250 connecting the support pillar 23 and the support block 25 can also be formed.

[0059] In this embodiment, the dielectric layer 240 can include bismaleimide triazine (BT for short), prepreg (PP for short), ABF film, polybenzoxazole (PBO for short), polyimide (PI for short), or other dielectric materials.

[0060] The support block 25 is combined with the dielectric layer 240 and is not electrically connected to the circuit layer 241 and the wiring layer 22.

[0061] In this embodiment, the manufacturing of the support block 25 is the same as that of the circuit layer 241 and the conductive blind via 242. For example, the support block 25 is in the shape of a rivet, and the diameter D1 of the connection pad 250 serving as the cap part is larger than the diameter D2 of the support block 25 serving as the nail part and the diameter R of the support pillar 23. It should be understood that the support structure 2a uses any material suitable for bonding the core layer 20 and the dielectric layer 240.

[0062] Furthermore, the end face of the support structure 2a (or the outer end of the support block 25) is in the shape of a circular pad, as Figure 3A or Figure 3B shown, and a plurality of support structures 2a are arranged in a surrounding manner in the peripheral area B of the package substrate 2. For example, the package substrate 2 has a full-panel specification including a plurality of strips, as Figure 3A shown, so that the plurality of support structures 2a surround the wiring area A of each strip 3a. Or, as Figure 3B shown, the package substrate 3 has a single-substrate specification, as Figure 3B shown, so that the plurality of support structures 2a surround the wiring area A of the package substrate 3.

[0063] In addition, there are numerous embodiments of the support structure 2a, which can be designed according to requirements. For example, in the symmetric packaging substrate 4 shown in Figure 4A , the support block 45 is not connected to the support column 23, causing the support structure 4a to form a fault type. However, connection pads 450 can be formed at the ends of the support column 23 and the support block 45 as needed to strengthen the interlayer adhesion. Alternatively, the support structures 4b and 4c change according to the shapes of the packaging substrates 5 and 6, as shown in Figure 4B or Figure 4C . Circuit structures 24 and support blocks 25 and 45 are formed only on one side of the core layer 20 to form asymmetric packaging substrates 5 and 6, so that the support structure 4b is in an asymmetric stacked type or the support structure 4c is in an asymmetric fault type.

[0064] In addition, the occupied area of the support structure 2a can also be designed according to requirements. For example, in the full-page size specification shown in Figure 5A or in the single-substrate size specification shown in Figure 5B , the support block 55 can be in a hedge shape, and its end face (or the outer end of the support block 55) is rectangular. Alternatively, in the full-page size specification shown in Figure 6A or in the single-substrate size specification shown in Figure 6B , the support block 65 forms a frame, and its end face (or the outer end of the support block 65) is annular.

[0065] It should be understood that Figure 5A and Figure 5B and Figure 6A and Figure 6B , connection pads (not shown in the figure) can also be formed between the upper and lower adjacent support blocks 55 and 65. Connection pads (not shown in the figure) can also be formed between the support blocks 55 and 65 and the support column 23. In addition, regardless of the full-page size specification or the single-substrate size specification, the packaging substrates 2 to 6 can be divided into 12 embodiments according to the support structures 2a, 4a, 4b, 4c, 5a, 5b, 6a, and 6b, as shown in Table 1:

[0066] Table 1: 12 Embodiments of the Support Structures 2a, 4a, 4b, 4c, 5a, 5b, 6a, and 6b

[0067]

[0068] Therefore, the packaging substrates 2-6 of the present invention mainly form support blocks 25, 45, 55, 65 in the shape of rivets, grids or frames in the peripheral area B through the support structures 2a, 4a, 4b, 4c, 5a, 5b, 6a, 6b, which can enhance the adhesion between the dielectric layer 240 and the core layer 20, and can also enhance the adhesion between the dielectric layers 240. Therefore, compared with the prior art, when delamination occurs between the dielectric layers 240 (or between the dielectric layer 240 and the core layer 20) at high temperatures during the process, the support structures 2a, 4a, 4b, 4c, 5a, 5b, 6a, 6b (especially the support blocks 25, 45, 55, 65) can effectively inhibit the occurrence of delamination, especially at the edges of the packaging substrates 2-6, to avoid moisture infiltration and damage to electrical functions or poor reliability and other problems.

[0069] Furthermore, the stacked support structures 2a, 4b can simultaneously inhibit delamination between the dielectric layer 240 and the core layer 20 and between the dielectric layers 240, while the stepped support structures 4a, 4c are used to inhibit delamination between the dielectric layers 240.

[0070] Moreover, regardless of whether the packaging substrates 2-6 are of full-panel specifications (strip 3a specifications) or single-substrate specifications, the support structures 2a, 4a, 4b, 4c, 5a, 5b, 6a, 6b can be easily configured on the peripheral area B for easy layout, so that the packaging substrates 2-6 can effectively reduce the occurrence of delamination problems according to the distribution area (or quantity) of the support structures 2a, 4a, 4b, 4c, 5a, 5b, 6a, 6b during both the production and reliability testing stages. Therefore, the packaging substrates 2-6 can configure the support structures 2a, 4a, 4b, 4c, 5a, 5b, 6a, 6b in areas with high delamination risks according to requirements to avoid delamination problems.

[0071] The present invention also provides a packaging substrate 2-6, comprising: a core layer 20, a plurality of conductive posts 21, a wiring layer 22, a circuit structure 24, and support structures 2a, 4a, 4b, 4c, 5a, 5b, 6a, 6b.

[0072] The core layer 20 defines a wiring area A and a peripheral area B surrounding the wiring area A.

[0073] The plurality of conductive posts 21 are formed in the wiring area A of the core layer 20 and connect the opposite sides of the core layer 20.

[0074] The wiring layer 22 is formed on the opposite side of the core layer 20 and is electrically connected to the plurality of conductive posts 21.

[0075] The described circuit structure 24 is formed on the wiring area A and the peripheral area B on at least one side of the core layer 20 and is electrically connected to the wiring layer 22.

[0076] The described support structures 2a, 4a, 4b, 4c, 5a, 5b, 6a, 6b are formed in the core layer 20 and in the circuit structure 24 and are provided corresponding to the peripheral area B.

[0077] In a specific embodiment, the circuit structure 24 is formed on opposite sides of the core layer 20, making the packaging substrate 2 symmetric.

[0078] In a specific embodiment, the circuit structure 24 is only formed on one side of the core layer 20, making the packaging substrates 4, 6 asymmetric.

[0079] In a specific embodiment, the support structures 2a, 4a, 4b, 4c, 5a, 5b, 6a, 6b are not electrically connected to the circuit structure 24.

[0080] In a specific embodiment, the support structures 2a, 4a, 4b, 4c, 5a, 5b, 6a, 6b include at least one support column 23 formed in the core layer 20 and at least one support block 25, 45, 55, 65 formed in the circuit structure 24. For example, the support block 25 is connected to the support column 23, making the support structures 2a, 4b stacked. Or, the support block 45 is not connected to the support column 23, making the support structures 4a, 4c in a stepped form.

[0081] In a specific embodiment, the support structures 2a, 4a, 4b, 4c, 5a, 5b, 6a, 6b may include multiple support blocks 25, 45, 55, 65, and the support structures 2a, 4a, 4b, 4c, 5a, 5b, 6a, 6b further include connection pads 250, 450 for overlapping adjacent upper and lower support blocks 25, 45, 55, 65.

[0082] In a specific embodiment, connection pads 250, 450 may also be formed between the support blocks 25, 45, 55, 65 and the support column 23 to connect the support blocks 25, 45, 55, 65 and the support column 23.

[0083] In an embodiment, the support blocks 25, 45 are in the shape of rivets. Or, the support block 55 is in the shape of a grid. Even more, the support block 65 is in the shape of a frame.

[0084] In summary, for the packaging substrate and its manufacturing method of the present invention, through the design that the support structure is formed in the core layer and the circuit structure and corresponds to the peripheral area, the adhesion between the dielectric layers and between the dielectric layer and the core layer is enhanced. Therefore, compared with the prior art, when delamination occurs between the dielectric layers (or between the dielectric layer and the core layer) at high temperatures during the process, the support structure (especially the support block) can effectively inhibit the occurrence of delamination to avoid problems such as moisture infiltration damaging the electrical function or poor reliability.

[0085] The above embodiments are used to illustratively explain the principles and effects of the present invention, rather than to limit the present invention. Those skilled in the art can modify the above embodiments without departing from the spirit and scope of the present invention. Therefore, the scope of the rights protection of the present invention should be as listed in the claims.

Claims

1. A packaging substrate, characterized in that: include: A core layer, which is defined with a wiring area and a peripheral area surrounding the wiring area; A plurality of conductive pillars are formed in a wiring region of the core layer and connect two opposite sides of the core layer; a wiring layer formed on opposite sides of the core layer and electrically connected to the plurality of conductive pillars; A circuit structure formed on the wiring area and the peripheral area of ​​at least one side of the core layer and electrically connected to the wiring layer; as well as A support structure is formed in the core layer and the circuit structure and is arranged corresponding to the peripheral area, and includes at least one support column formed in the core layer and at least one support block formed in the circuit structure, the support column is not electrically connected to the wiring layer and the support block is not electrically connected to the circuit structure and the wiring layer.

2. The packaging substrate according to claim 1, wherein: The support block is connected to the support column so that the support structure is stacked, or the support block is not connected to the support column.

3. The packaging substrate according to claim 1, wherein: The support structure includes a plurality of support blocks, and the support structure also includes a connection pad, and the connection pad is used to overlap the upper and lower adjacent support blocks, and when the support structure is in a stacked type, the connection pad connects the support block and the support column.

4. The packaging substrate according to claim 1, wherein: The support block is in the shape of a rivet, a grid or a frame.

5. The packaging substrate according to claim 1, wherein: The core layer is made of organic material, glass, ceramic, silicon carbide, AlO2 or a composite material with a modulus of 50 to 100 GPa.

6. A method for manufacturing a packaging substrate, characterized in that: include: Providing a core layer defining a wiring area and a peripheral area surrounding the wiring area; Forming a plurality of conductive pillars in the wiring region of the core layer and connecting two opposite sides of the core layer, and forming a wiring layer on two opposite sides of the core layer and electrically connecting the plurality of conductive pillars; Forming a circuit structure on the wiring area and the peripheral area of ​​at least one side of the core layer, and electrically connecting the circuit structure to the wiring layer; as well as A support structure is formed in the core layer and the circuit structure, and the support structure is arranged corresponding to the peripheral area. The support structure includes at least one support column formed in the core layer and at least one support block formed in the circuit structure. The support column is not electrically connected to the wiring layer, and the support block is not electrically connected to the circuit structure and the wiring layer.

7. The method for manufacturing a packaging substrate according to claim 6, wherein: The support block is connected to the support column so that the support structure is stacked, or the support block is not connected to the support column.

8. The method for manufacturing a packaging substrate according to claim 6, wherein: The support structure includes a plurality of support blocks, and the support structure also includes a connection pad, and the connection pad is used to overlap the upper and lower adjacent support blocks, and when the support structure is in a stacked type, the connection pad connects the support block and the support column.

9. The method for manufacturing a packaging substrate according to claim 6, wherein: The support block is in the shape of a rivet, a grid or a frame.

10. The method for manufacturing a packaging substrate according to claim 6, wherein: The core layer is made of organic material, glass, ceramic, silicon carbide, AlO2 or a composite material with a modulus of 50 to 100 GPa.

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