A dual-mode switched buck converter

Abstract

The application is suitable for the technical field of switching power supply, and provides a Buck converter with double-mode switching. The application realizes system protection function and low-power mode by adding a HVT (High Voltage Threshold) module to control the conduction and turn-off of the power tube in a loop. The HVT module compares the output feedback voltage VFB with the reference voltage Vref, can quickly turn off the upper and lower power tubes in the soft start stage, effectively avoids the chip from burning due to the transient overvoltage of the system, turns off the power tube to reduce the conduction loss and start the low-power mode in the PFM mode, and can turn off the upper power tube and turn on the lower power tube to release the excess current in the loop and prevent the backflow phenomenon when triggering the current limiting ILIM mechanism. The application realizes the double-mode switching control strategy of the Buck converter in the heavy load PWM and the light load PFM, improves the overall working efficiency, effectively improves the stability of the converter, increases the ECO (energy saving) mode, and reduces the system power consumption.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of power electronic converters, and particularly relates to a Buck converter with dual-mode switching. BACKGROUND

[0002] In recent years, various portable electronic products are constantly updated, and consumer electronic products such as mobile phones and wearable devices are constantly integrated into people's lives. The power management chip is the heart of the electronic product, mainly responsible for stably providing the voltage required by the system to ensure the normal operation of the system. As the cornerstone of future social and technological development, its core position is unshakable.

[0003] With the increasing demand for low power consumption, in order to ensure high efficiency while prolonging battery life, Buck type converters stand out and become the main force in the power consumption market. At present, some Buck converters use a single control strategy, such as pure PWM mode or pure PFM mode. The PWM mode control loop is simple, the output ripple is small, the frequency response is good, the linearity is high, and it has quite excellent efficiency performance under heavy load conditions, but the efficiency is poor under light load conditions. This control mode will cause the power tube to bear a large voltage and current stress. In contrast, the PFM mode has high efficiency under light load, but the ripple is large, and the ripple spectrum is dispersed and irregular, which leads to complex filter circuit design. This control mode cannot be applied to low-noise scenarios.

[0004] Therefore, in view of the shortcomings of single control mode, a new logic circuit is designed to combine the two modes, complement each other, optimize the existing topology, and design a more perfect Buck converter system architecture, thereby reducing overall power consumption, enhancing system stability and conversion efficiency. SUMMARY

[0005] To solve the above problems, the present application provides a Buck converter with dual-mode switching, which realizes adaptive switching of the converter working mode with the load by setting the HVT module and changing the trigger mechanism of ZCD, improves the overall efficiency, enhances the stability, and reduces the system power consumption.

[0006] The technical scheme of the present application is:

[0007] A dual-mode switching Buck converter, comprising a logic drive circuit, a gate drive unit, a power tube, an input / output circuit, further comprising a HVT (High Voltage Threshold) module, a ZCD (zero-crossing detection) circuit, an RS flip-flop, a PWM comparator, an error amplifier, an inductor current detection circuit, a slope compensation circuit, an oscillator, a current limiting module, a D flip-flop, an inverter, an AND gate, an NOR gate, and a NOT gate; wherein the positive input terminal of the error amplifier is connected to an internal reference voltage, the negative input terminal is connected to a feedback voltage, and the output terminal is connected to the negative input terminal of the PWM comparator; the source terminal of the upper power tube is connected to an input voltage, the source terminal of the lower power tube is connected to the ground, and the drain terminals of the upper and lower power tubes are connected; the inductor current detection circuit samples the current flowing through the power tube and outputs to the slope compensation circuit; one output terminal of the oscillator is connected to one input terminal of the AND gate, and the other output terminal is connected to the slope compensation circuit; the output terminal of the slope compensation circuit is connected to the PWM comparator, and the output terminal of the PWM comparator is connected to the R input terminal of the RS flip-flop; the positive input terminal of the ZCD is connected to the drain terminal of the power tube, the negative input terminal is connected to the ground, one output terminal is connected to the D input terminal of the D flip-flop, and the other output terminal is connected to the input terminal of the NOT gate; one input terminal of the HVT module is connected to the internal reference voltage, the other input terminal is connected to the feedback voltage, and the output terminal is connected to the input terminal of the NOR gate; the output terminal of the NOT gate is connected to the other input terminal of the NOR gate; the output terminal of the NOR gate is connected to the other input terminal of the AND gate; the output terminal of the AND gate is connected to the S input terminal of the RS flip-flop; the gate terminal of the upper power tube is connected to the input terminal of the inverter, and the output terminal of the inverter is connected to the CLK terminal of the D flip-flop; the input terminal of the current limiting module is connected to the drain terminal of the power tube; the Q output terminal of the RS flip-flop, the Q output terminal of the D flip-flop, and the output terminal of the current limiting module are all connected to the input terminal of the logic drive circuit, and under the cooperative action of the three, the output pulse signal is output to the gate drive unit; the gate drive unit is connected to the gate terminals of the upper and lower power tubes respectively, and the drain terminals of the power tubes are connected to the output circuit.

[0008] Further, the current limiting module ILIM works in PFM mode, and when the inductor current value is higher than the set threshold current, the system is regulated by opening the lower power tube and closing the upper power tube.

[0009] Further, the slope compensation circuit intervenes when the system starts to reduce the frequency and the oscillator outputs the normal working frequency.

[0010] Further, the clock of the D flip-flop is obtained by collecting the inverse voltage of the upper power tube switching signal, and the output signal of the ZCD is input to the D terminal.

[0011] Further, the output of the PWM comparator is a first-level RESET signal, the current limiting module ILIM outputs a second-level RESET signal in the case of overcurrent, and the first-level RESET signal and the second-level RESET signal are used to adapt the system to different working modes by closing the power tube.

[0012] Further, the ZCD (zero-crossing detection) circuit and the D flip-flop jointly constitute a control circuit for switching between PWM mode and PFM mode, and the system determines to enter a light load state and enter a PFM working mode by setting a reasonable number of times.

[0013] Further, the HVT module includes ten PMOS tubes, fifteen NMOS tubes and three resistors, wherein: the source of the first PMOS tube MP1, the source of the second PMOS tube MP2, the source of the fifth PMOS tube MP5, the source of the sixth PMOS tube MP6, the source of the seventh NMOS tube MN7, the source of the eighth NMOS tube MP8, the source of the ninth PMOS tube MP9 and the source of the tenth PMOS tube are connected with the power supply VCC; the source of the third NMOS tube MN3, the source of the second NMOS tube MN2, the source of the fifth NMOS tube MN5, the source of the eighth NMOS tube MN8, the source of the eleventh NMOS tube MN11, the source of the fourteenth NMOS tube MN14 and the source of the fifteenth NMOS tube MN15 are connected with the ground; the gate of the third NMOS tube MN3, the gate of the fifth NMOS tube MN5 and the gate of the eighth NMOS tube MN8 are connected with the gate of the eleventh NMOS tube.

[0014] The first PMOS transistor MP1 has its gate connected to the gate of the second PMOS transistor MP2 and its source connected to the bias voltage IBIAS. The second PMOS transistor MP2 has its drain connected to the source of the third PMOS transistor MP3. The third PMOS transistor MP3 has its gate connected to the gate of the second PMOS transistor MP2 and its drain connected to the drain of the first NMOS transistor MN1. The first NMOS transistor MN1 has its gate connected to its drain and its source connected to the drain of the third NMOS transistor MN3. The gate of the third NMOS transistor MN3 is connected to its drain. The fourth PMOS transistor MP4 has its gate connected to the output VOUT, its source connected to the drain of the sixth PMOS transistor MP6, and its drain connected to the drain of the second NMOS transistor MN2. The second NMOS transistor MN2 has its gate connected to the gate of the first NMOS transistor MN1. The fourth NMOS transistor MN4 has its drain connected to the drain of the sixth PMOS transistor MP6, and its gate connected to the gate of the first NMOS transistor MN1. The fifth NMOS transistor MN5 has its drain connected to the drain of the sixth PMOS transistor MP6. The first resistor R1 is connected between the source of the fourth PMOS transistor MP4, the drain of the fourth NMOS transistor MN4, the drain of the fifth NMOS transistor MN5, and the drain of the sixth PMOS transistor MP6. The fifth PMOS transistor MP5 has its gate connected to its drain and its drain connected to the drain of the sixth NMOS transistor MN6. The second resistor R2 is connected between the drain of the fifth PMOS transistor MP5 and the drain of the sixth NMOS transistor MN6. The sixth PMOS transistor MP6 has its gate connected to its drain and its drain connected to the drain of the seventh NMOS transistor MN7. The third resistor R3 is connected between the drain of the sixth PMOS transistor MP6 and the drain of the seventh NMOS transistor MN7. The sixth NMOS transistor MN6 has its gate connected to the input signal VIP and its source connected to the source of the seventh NMOS transistor MN7. The seventh NMOS transistor MN7 has its gate connected to the input signal VIN. The eighth NMOS transistor MN8 has its drain connected to the source of the sixth NMOS transistor MN6 and the source of the seventh NMOS transistor MN7. The seventh PMOS transistor MP7 has its gate connected to the gate of the tenth PMOS transistor MP10 and its drain connected to the drain of the ninth NMOS transistor MN9. The eighth PMOS transistor MP8 has its gate connected to its drain and its drain connected to the drain of the tenth NMOS transistor MN10. The ninth NMOS transistor MN9 has its gate connected to the drain of the seventh NMOS transistor and its source connected to the source of the tenth NMOS transistor MN10. The tenth NMOS transistor MN10 has its gate connected to the drain of the sixth NMOS transistor MN6. The eleventh NMOS transistor MN11 has its source connected to the source of the ninth NMOS transistor MN9 and the source of the tenth NMOS transistor. The ninth PMOS transistor MP9 has its gate connected to the gate of the eighth PMOS transistor MP8 and its drain connected to the drain of the twelfth NMOS transistor MN12. The tenth PMOS transistor MP10 has its drain connected to the drain of the thirteenth NMOS transistor MN13.Twelfth NMOS MN12, the grid is connected with the drain, the source is connected with the drain of fourteenth NMOS MN14;Thirteenth NMOS MN13, the grid is connected with the grid of twelfth NMOS MN12, the source is connected with the drain of fifteenth NMOS MN15;Fourteenth NMOS MN14, the drain is connected with the grid;Fifteenth NMOS MN15, the grid is connected with the grid of fourteenth NMOS MN14;Output terminal VOUT is drawn between the drain of tenth PMOS MP10 and the drain of thirteenth NMOS MN13.

[0015] Further, the HVT module compares the feedback voltage VFB and the reference voltage Vref, and outputs threshold switching in the reference voltage ±102.3%, when the voltage is higher than the upper threshold voltage in the PFM working mode, HVT=1, the chip is closed, and enters the ECO (energy saving) mode;When the voltage is lower than the lower threshold voltage, HVT=0, the system works normally.

[0016] Further, the RS trigger S end normally accesses the voltage signal of the oscillator output, when the system appears transient overvoltage, VFB is higher than the voltage threshold of HVT module, HVT=1, the power tube is closed, and the chip is prevented from being burned out due to overvoltage.

[0017] The application has the following beneficial effects:

[0018] After the circuit is used, the system can adaptively switch work to realize heavy load PWM mode and light load PFM mode, greatly improve the overall working efficiency, and reduce the output ripple;By changing the zero-crossing detection circuit (ZCD) output signal zero-crossing times, the system determination accuracy can be improved, and the PFM mode can be accurately entered;By increasing the HVT module, the chip can be effectively prevented from being burned out due to transient overvoltage;The system can enter the ECO (energy saving) mode in the PFM mode, and the overall power consumption is reduced;At the same time, when the current limiting ILIM mechanism is triggered, the upper power tube is closed and the lower power tube is opened, the excess current in the loop is released to prevent backflow phenomenon. BRIEF DESCRIPTION OF DRAWINGS

[0019] Figure 1 The circuit schematic diagram of the application is shown.

[0020] Figure 2 The key waveform diagram of PWM mode entering PFM mode is shown.

[0021] Figure 3 The circuit schematic diagram of the HVT module of the application is shown.

[0022] Figure 4 The inductance current key waveform in the PFM mode is shown. DETAILED DESCRIPTION

[0023] In the following description, for purposes of explanation and not limitation, specific details are set forth such as particular architectures, techniques, etc. in order to provide a thorough understanding of the embodiments of the present application. However, it will be apparent to those skilled in the art that the present application can be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known methods, devices, circuits, and

[0024] The present application is described in detail below with reference to the attached drawing figures.

[0025] The dual-mode switching Buck converter control architecture of the present application realizes system protection function and low-power mode by adding a HVT (High Voltage Threshold) module in the loop to control the turn-on and turn-off of the power tube. The HVT module compares the output feedback voltage VFB with the reference voltage Vref, and can quickly turn off the upper and lower power tubes in the soft start stage, effectively avoiding chip burnout caused by transient overvoltage in the system; in the PFM mode, the power tube is turned off to reduce the conduction loss and turn on the low-power mode; at the same time, when the current limiting ILIM mechanism is triggered, the upper power tube is turned off and the lower power tube is turned on to release the excess current in the loop and prevent backflow. The present application realizes the dual-mode switching control strategy of Buck converter overload PWM and light load PFM, improves the overall work efficiency, effectively improves the stability of the converter, increases the ECO (energy saving) mode, and reduces the system power consumption.

[0026] Reference is made to Figure 1 When the system is normally powered on, the upper power tube is turned on and the lower power tube is turned off, and the converter works in the charging stage (on duty), and the voltage is output from the power tube drain through the inductor 117, the capacitor C OUT stores energy, and the output voltage V OUT gradually rises, and at this time the output voltage is divided by R1 and R2 to output the system feedback voltage VFB. The OSC oscillator 105 of the system mainly outputs three waveforms, first, in the soft start stage, a low-frequency signal is output, which aims to avoid the phenomenon of inductor surge current caused by the insufficient discharge capacity of the lower power tube when the output V OUT has not been formally established; when V OUTThe gradually rising, feedback voltage VFB reaches 200mV, OSC switch to normal working frequency output; while providing a triangular wave to the slope compensation circuit 104. Error amplifier (EA) 101 by comparing the reference voltage Vref and feedback voltage VFB, the comparison results sent to the PWM comparator 116 of the inverting input (-), error amplifier in soft start stage also played a clamping effect, to prevent the system working in the ring state. Inductor current detection circuit 106 will be converted into a voltage signal sent to the slope compensation circuit 104, the signal through the slope compensation sent to the positive input (+) of the PWM comparator 116, two signals through the PWM comparator 116 comparison, reset signal RESET1 is generated. RS flip-flop 103 S end in normal mode receives the working frequency pulse signal, Q output logic pulse signal sent to the Logic Drive drive logic unit, close the upper power tube, open the lower power tube, the converter works in the discharge phase (off duty). RS flip-flop S input end waiting for VSET signal, enter the next cycle. In the whole system soft start stage, forced control system works in PWM mode, until the system soft start module output SSDN (Soft Start Done) signal, after which the system will be adapted to switch mode according to the load current change work.

[0027] UGB_SNS is the gate voltage of the upper power tube, the signal is sent to the CLK end of the D flip-flop 109, the voltage at the switch SW is sent to the positive input (+) of the ZCD (zero-crossing detection circuit) 110, the negative input is grounded, the ZCD determines the zero-crossing times of the inductor current, and the output signal is sent to the D input port of the D flip-flop 109. Referring to Figure 2 When the system completes the formal start, the load at the output end changes, and the output current drops to below 100mA, the system detects ZCD through the Buck high-side power tube opening. RB is the internal counter signal of the D flip-flop 109, when ZCD is continuously triggered 27 times, the Q end of the D flip-flop 109 outputs high level; if a ZCD signal is lost, the counter will be reset. The Q output end of the D flip-flop 109 sends the PFM signal to the Logic Drive drive logic unit, and the whole system switches to PFM working mode. Before the ILIM mechanism is triggered, the system will close the power tube at the same time, enter the ECO (energy saving) mode, which greatly reduces the conduction loss of the power tube.

[0028] Referring to Figure 3, including constant bias current IBIAS, ten PMOS tubes, fifteen NMOS tubes, three resistors. Its circuit mainly consists of three parts, the first PMOS tube MP1, the second PMOS tube MP2, the third PMOS tube MP3, the first NMOS tube MN1 and the third NMOS tube MN3 jointly constitute the bias circuit 301, the source of the first PMOS tube MP1 is connected with the bias current IBIAS, the gate thereof is connected with the gate of the second PMOS tube MP2 and the third PMOS tube MP3, forming a current mirror structure to copy the IBIAS current. The gate and the drain of the first NMOS tube MN1 are connected, providing bias voltage for the second NMOS tube MN2 and the fourth NMOS tube MN4. The gate and the drain of the third NMOS tube are connected, providing bias voltage for the fifth NMOS tube MN5, the eighth NMOS tube MN8 and the eleventh NMOS tube MN11, etc. The fourth PMOS tube MP4, the second NMOS tube MP2, the fourth NMOS tube MN4 and the fifth NMOS tube MN5 constitute the HVT auxiliary functional circuit 302. The source of the fourth PMOS tube MP4 is connected with one end of the first resistor R1, the other end of the first resistor R1 is connected with the source of the fifth PMOS tube, a current path is led out from the comparison circuit 303 module, the gate thereof is directly connected with the output end VOUT of the HVT module, the hysteresis time of the output end VOUT is controlled by changing the width-length ratio of the fourth PMOS tube MP4. The second NMOS tube MN2, the fourth NMOS tube MN4 and the fifth NMOS tube jointly act, the PVT performance of the circuit is optimized by reasonably setting the width-length ratio; the part 303 is a two-stage comparator circuit, wherein the gate of the sixth NMOS tube MN6 is a positive phase input port, the reference voltage Vref is externally connected, the gate of the seventh NMOS tube MN7 is a negative phase input port, the feedback voltage VFB is externally connected. The gate and the drain of the fifth PMOS tube MP5 and the sixth PMOS tube MP6 are connected, being a diode load. The gate of the ninth NMOS tube MN9 and the gate of the tenth NMOS tube are the input ends of the second stage comparator, being connected with the drain of the seventh NMOS tube MN7 and the sixth NMOS tube MN6 respectively. The two-stage comparator can amplify the signal step by step, optimize the processing mode of the signal, has a faster response speed; the way of step gain can greatly improve the input sensitivity of the comparator; at the same time, the common mode rejection ratio (CMRR) and the noise rejection ratio can be improved, the reliability of the system in the complex electromagnetic environment can be improved; and the power consumption can be dynamically optimized in different working states, prolonging the working time of the system. Therefore, the structure of the two-stage comparator is very suitable for the application scene of the Buck system and the battery power supply in the application. The input end VIP of the HVT module is connected with the Vref voltage, the input end VIN is connected with the feedback voltage VFB, the two voltages are compared, the output is switched at the threshold value of the reference voltage ±102.3%, when the voltage is higher than the upper threshold value, HVT=1, the chip is closed; when the voltage is lower than the lower threshold value, HVT=0, the system works normally.

[0029] HVT module plays two main functions in the system, protection and energy saving. Firstly, when the Buck converter starts, the system appears transient over-voltage phenomenon, at this time the output voltage is much higher than the rated output voltage, if the converter continues to work, it will cause power tube over-current and over-voltage, resulting in being burned, the feedback voltage VFB is sent to the negative input terminal of HVT module, because VFB is greater than 102.3% of the reference voltage, HVT = 1, the chip is closed until the VFB voltage drops to the normal voltage range, HVT = 0, the system continues to work; in the normal working stage of the converter, the internal power is sufficient, it is detected that the VFB voltage is greater than the set threshold voltage, HVT = 1, the power tube is closed, and the ECO (energy saving) mode is entered, which can effectively reduce the system power consumption; when the system works in PFM mode, ILIM is the main control logic, which controls the conduction and turn-off of the upper and lower power tubes, Figure 4 is the inductor current key waveform in PFM mode, before the third peak of inductor current comes, HVT signal detects that the feedback voltage is too high, HVT = 1, intervenes in advance, closes the upper power tube and opens the lower power tube, releases the excess current in the loop to prevent backflow phenomenon.

[0030] Although the embodiments of the present application have been shown and described, it is to be understood that various changes, modifications, substitutions and alterations can be made to the embodiments without departing from the principles and spirit of the present application, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A dual-mode switching Buck converter, comprising a logic drive circuit, a gate drive unit, a power tube, and an input / output circuit, characterized in that: The positive input of the error amplifier is connected to the internal reference voltage, the negative input is connected to the feedback voltage, and the output of the error amplifier is connected to the negative input of the PWM comparator; the source of the upper power tube is connected to the input voltage, the source of the lower power tube is grounded, and the drains of the upper and lower power tubes are connected; the inductor current detection circuit samples the current flowing through the power tube, and the output is connected to the slope compensation circuit; one output of the oscillator is connected to one input of the AND gate, and the other output is connected to the slope compensation circuit; the output of the slope compensation circuit is connected to the PWM comparator, and the output of the PWM comparator is connected to the R input of the RS trigger; the positive input of the ZCD is connected to the drain of the power tube, the negative input is grounded, one output is connected to the D input of the D trigger, and the other output is connected to the input of the NOT gate; HVT module One input terminal is connected to the internal reference voltage, the other input terminal is connected to the feedback voltage, and the output terminal is connected to the input terminal of the NOR gate; the output terminal of the NOR gate is connected to the other input terminal of the NOR gate; the output terminal of the NOR gate is connected to the other input terminal of the AND gate; the output terminal of the AND gate is connected to the S input terminal of the RS trigger; the gate of the upper power tube is connected to the input terminal of the inverter, and the output terminal of the inverter is connected to the CLK terminal of the D trigger; the input terminal of the current limiting module is connected to the drain terminal of the power tube; the Q output terminal of the RS trigger, the Q output terminal of the D trigger and the output terminal of the current limiting module are all connected to the input terminal of the logic drive circuit. Under the coordinated action of the three, a pulse signal is output to the gate drive unit; the gate drive unit is connected to the gate terminals of the upper and lower power tubes respectively, and the drain terminal of the power tube is connected to the output circuit; The clock of the D flip-flop is obtained by collecting the inverted voltage of the upper power tube switch signal, and the output signal of the ZCD is used as the D terminal input; The output of the PWM comparator is a primary RESET signal, and the current limiting module is a secondary RESET signal in the case of output overcurrent. The primary RESET signal and the secondary RESET signal are used to adapt to different working modes of the system by turning off the power tube; The ZCD circuit and the D flip-flop together form a control circuit for switching from PWM mode to PFM mode. By setting a reasonable number of times, the system determines that it has entered a light load state and enters the PFM working mode; The HVT module includes ten PMOS transistors, fifteen NMOS transistors, and three resistors, wherein: the source of the first PMOS transistor MP1, the source of the second PMOS transistor MP2, the source of the fifth PMOS transistor MP5, the source of the sixth PMOS transistor MP6, the source of the seventh NMOS transistor MN7, the source of the eighth MOS transistor MP8, the source of the ninth PMOS transistor MP9, and the source of the tenth PMOS transistor are connected to the power supply VCC; the source of the third NMOS transistor MN3, the source of the second NMOS transistor MN2, the source of the fifth NMOS transistor MN5, the source of the eighth NMOS transistor MN8, the source of the eleventh NMOS transistor MN11, the source of the fourteenth NMOS transistor MN14, and the source of the fifteenth NMOS transistor MN15 are connected to the ground; the gate of the third NMOS transistor MN3, the gate of the fifth NMOS transistor MN5, and the gate of the eighth NMOS transistor MN8 are connected to the gate of the eleventh NMOS transistor; The first PMOS transistor MP1 has a gate connected to the gate of the second PMOS transistor MP2, and a source connected to the bias voltage IBIAS; the second PMOS transistor MP2 has a drain connected to the source of the third PMOS transistor MP3; the third PMOS transistor MP3 has a gate connected to the gate of the second PMOS transistor MP2, and a drain connected to the drain of the first NMOS transistor MN1; the first NMOS transistor MN1 has a gate and a drain connected, and a source connected to the drain of the third NMOS transistor MN3; the gate and the drain of the third NMOS transistor MN3 are connected; the fourth PMOS transistor MP4 has a gate connected to the output terminal VOUT, a source connected to the drain of the sixth PMOS transistor MP6, and a drain connected to the drain of the second NMOS transistor MN2; the second The gate of the NMOS transistor MN2 is connected to the gate of the first NMOS transistor MN1; the drain of the fourth NMOS transistor MN4 is connected to the drain of the sixth PMOS transistor MP6, and the gate is connected to the gate of the first NMOS transistor MN1; the drain of the fifth NMOS transistor MN5 is connected to the drain of the sixth PMOS transistor MP6; the first resistor R1 is connected across the source of the fourth PMOS transistor MP4, the drain of the fourth NMOS transistor MN4, the drain of the fifth NMOS transistor MN5, and the drain of the sixth PMOS transistor MP6; the gate and drain of the fifth PMOS transistor MP5 are connected, and the drain is connected to the drain of the sixth NMOS transistor MN6; the second resistor R2 is connected across the drain of the fifth PMOS transistor MP5 and the drain of the sixth NMOS transistor MN6. 6; the sixth PMOS transistor MP6 has its gate and drain connected, and its drain is connected to the drain of the seventh NMOS transistor MN7; the third resistor R3 is connected across the drain of the sixth PMOS transistor MP6 and the drain of the seventh NMOS transistor MN7; the sixth NMOS transistor MN6 has its gate connected to the input signal VIP, and its source connected to the source of the seventh NMOS transistor MN7; the seventh NMOS transistor MN7 has its gate connected to the input signal VIN; the eighth NMOS transistor MN8 has its drain connected to the source of the sixth NMOS transistor MN6 and the source of the seventh NMOS transistor MN7; the seventh PMOS transistor MP7 has its gate connected to the gate of the tenth PMOS transistor MP10, and its drain connected to the drain of the ninth NMOS transistor MN9 The eighth PMOS transistor MP8 has a gate connected to its drain, and its drain is connected to the drain of the tenth NMOS transistor MN10. The ninth NMOS transistor MN9 has a gate connected to the drain of the seventh NMOS transistor, and its source is connected to the source of the tenth NMOS transistor MN10. The tenth NMOS transistor MN10 has a gate connected to the drain of the sixth NMOS transistor MN6. The eleventh NMOS transistor MN11 has a source connected to the source of the ninth NMOS transistor MN9 and the source of the tenth NMOS transistor. The ninth PMOS transistor MP9 has a gate connected to the gate of the eighth PMOS transistor MP8, and its drain is connected to the drain of the twelfth NMOS transistor MN12. The tenth PMOS transistor MP10 has a drain connected to the drain of the thirteenth NMOS transistor MN13.The gate and drain of the twelfth NMOS transistor MN12 are connected, and the source is connected to the drain of the fourteenth NMOS transistor MN14. The gate of the thirteenth NMOS transistor MN13 is connected to the gate of the twelfth NMOS transistor MN12, and the source is connected to the drain of the fifteenth NMOS transistor MN15. The drain and gate of the fourteenth NMOS transistor MN14 are connected. The gate of the fifteenth NMOS transistor MN15 is connected to the gate of the fourteenth NMOS transistor MN14. The output terminal VOUT is connected between the drain of the tenth PMOS transistor MP10 and the drain of the thirteenth NMOS transistor MN13.

2. A dual-mode switching Buck converter according to claim 1, characterized in that: The current limiting module operates in the PFM mode. When the inductor current value is higher than the set threshold current, the system is regulated by turning on the lower power tube and turning off the upper power tube.

3. The dual-mode switching Buck converter according to claim 1, characterized in that: The slope compensation circuit intervenes when the system frequency reduction startup is completed and the oscillator outputs a normal operating frequency.

4. The dual-mode switching Buck converter according to claim 1, characterized in that: The HVT module compares the feedback voltage VFB with the reference voltage Vref, and outputs a threshold switch at ±102.3% of the reference voltage. In the PFM working mode, when the voltage is higher than the upper threshold, HVT=1, the chip is turned off and enters the ECO (energy saving) mode; when the voltage is lower than the lower threshold, HVT=0, and the system operates normally.

5. The dual-mode switching Buck converter according to claim 1, characterized in that: The RS trigger S terminal is normally connected to the voltage signal output by the oscillator. When a transient overvoltage occurs in the system, VFB is higher than the voltage threshold of the HVT module, HVT=1, and the power tube is turned off to prevent the chip from burning due to overvoltage.

Images