Low-noise power supply chip for optical module

Abstract

The invention provides a low-noise power supply chip for an optical module in the technical field of optical modules. Comprising a logic controller U1, an overvoltage protection chip U2, a current-limiting protection chip U3, a logic gate control chip U4, a logic gate control chip U5, a power management chip U6, a discharge chip U7, an operational amplifier OP1, an operational amplifier OP2, an inductor L1, an MOS tube Q1, an MOS tube Q2, an MOS tube Q3, an MOS tube Q4, an MOS tube Q5, an MOS tube Q6, a capacitor C1, a capacitor C2, a resistor R1, a resistor R2, a power input terminal J1 and a working mode selection terminal J2. The circuit comprises a power supply output terminal J1, a chip enabling terminal J2, a chip enabling terminal J3, a voltage ready terminal J4, a grounding terminal J5, a voltage debugging terminal J6, a power supply output terminal J7, a switch terminal J8 and a switch terminal J9. The low-noise power supply circuit has the advantages that the power consumption and the cost of the low-noise power supply circuit are greatly reduced, the chip integration level is improved, the use of chips is reduced, and the PCB layout space of a product is effectively saved.

Description

Technical Field

[0001] The present invention relates to the technical field of optical modules, and in particular to a low-noise power supply chip for an optical module. Background Art

[0002] The optical module is an optoelectronic device that performs photoelectric conversion and electro-optical conversion. According to the protocol and specifications of the optical module, the total power input of the optical module is generally 3.3V, and the 3.3V voltage needs to be converted into multiple power supply voltages of different levels inside the optical module to power different subsystems inside the optical module, such as 0.65V, 0.94V, 1.2V, 1.8V, 2.5V, 3.3V, 4V, 5V and other voltages.

[0003] In order to achieve voltage conversion of different levels, a variety of different power conversion chips are used inside the optical module, and some of the subsystems have high requirements for voltage stability and power noise (power ripple), such as DSP power supply circuit, clock source, reference level loop, etc. Especially as the optical module rate increases to 400G&800G&1.6T, the requirements for power noise are more stringent. Multiple subsystems require the power ripple to be controlled below 1mV, and conventional boost (BOOST) power chips or buck (DC-DC) power chips cannot meet the power ripple requirements. Therefore, it is necessary to use a low-noise power chip such as a primary LDO after the power conversion chip for voltage adjustment and ripple control to ensure that the power ripple meets the design requirements.

[0004] Traditionally, low-noise power supply circuits used in optical modules generally have two power supply voltage levels: Loop 1 is a power supply circuit with low noise requirements and greater than 3.3V, and Loop 2 is a power supply circuit with low noise requirements and less than 3.3V. Loop 1 consists of the first boost module (refer to Figure 2 ) and the first step-down module (refer to Figure 3 );Circuit 2 consists of the second step-down module (refer to Figure 4 ) and the third step-down module (refer to Figure 5 )composition.

[0005] The working principle of loop 1 from 3.3V to 4V is as follows: by adjusting the resistance values ​​of resistors R12 and R13, combined with power chip U11 (BOOST chip), the 3.3V power supply is boosted to 5V; by adjusting the resistance values ​​of resistors R15 and R16, combined with power chip U12 (LDO chip), the 5V power supply is reduced to 4V. VCC5V_EN and VCC4V_EN are used as host computer control signals to control the power chip U11 and the power chip U12 to enable work.

[0006] The working principle of loop 2 from 3.3V to 1.2V is as follows: by adjusting the resistance of resistors R18 and R19, combined with power chip U21 (DC-DC chip), the 3.3V power supply is reduced to 1.8V; by adjusting the resistance of resistors R21 and R2, combined with power chip U22 (LDO chip), the 1.8V power supply is reduced to 1.2V. VCC1V8_EN and VCC1V2_EN are used as host computer control signals to control the power chip U21 and the power chip U22 to enable work.

[0007] The traditional low-noise power supply circuit has the following disadvantages: 1. For the needs of boosting and bucking, different power supply chips need to be used for boosting or bucking first. The boosting and bucking circuits are not compatible, which increases the types of chip materials and thus increases the circuit cost; 2. The power supply chips of the primary power supply (first boost module, second buck module) and the secondary power supply (first buck module, third buck module) need to be controlled separately. In order to keep the circuit working stably, the output voltage of the first power supply will be kept with sufficient margin, which will cause the voltage difference of the LDO chip of the secondary power supply to increase; Since the working principle of the LDO chip is to keep the input and output currents the same, the goal of stable voltage drop and low noise is achieved by controlling the internal MOS tube to work, the energy loss caused by the voltage difference between the output and input ends of the LDO chip in the loop will all be used as the thermal power consumption of the LDO chip, resulting in greater heating of the LDO chip; 3. The power supply chips of the primary power supply and the secondary power supply need to be controlled independently, and the host computer IO output EN signal is required to control the power supply chip to enable the work, that is, a large amount of IO resources are occupied, which increases the circuit cost.

[0008] Therefore, how to provide a low-noise power chip for an optical module to reduce the power consumption and cost of the low-noise power circuit has become a technical problem that needs to be solved urgently. Summary of the invention

[0009] The technical problem to be solved by the present invention is to provide a low-noise power chip for an optical module, so as to reduce the power consumption and cost of the low-noise power circuit.

[0010] The present invention is implemented as follows: a low-noise power chip for an optical module, comprising a logic controller U1, an overvoltage protection chip U2, a current limiting protection chip U3, a logic gate control chip U4, a logic gate control chip U5, a power management chip U6, a discharge chip U7, an operational amplifier OP1, an operational amplifier OP2, an inductor L1, a MOS tube Q1, a MOS tube Q2, a MOS tube Q3, a MOS tube Q4, a MOS tube Q5, a MOS tube Q6, a capacitor C1, a capacitor C2, a resistor R1, a resistor R2, a power input terminal J1, a working mode selection terminal J2, a chip enable terminal J3, a voltage ready terminal J4, a ground terminal J5, a voltage debugging terminal J6, a power output terminal J7, a switch terminal J8 and a switch terminal J9;

[0011] The power input terminal J1, the working mode selection terminal J2, the chip enable terminal J3, the voltage ready terminal J4, the ground terminal J5, the voltage debugging terminal J6, the power output terminal J7, the switch terminal J8, the switch terminal J9 and the power input terminal J1 are connected in sequence;

[0012] One end of the inductor L1 is connected to the switch terminal J8, and the other end is connected to the switch terminal J9; one end of the overvoltage protection chip U2 is connected to the logic controller U1, and the other end is connected to the power input terminal J1 and the S pole of the MOS tube Q1; one end of the logic gate control chip U4 is connected to the logic controller U1, and the other end is connected to the G pole of the MOS tube Q1; the G pole of the MOS tube Q2 is connected to the logic gate control chip U4, the S pole is connected to the D pole of the MOS tube Q1 and the switch terminal J9, and the D pole is connected to the ground terminal J5; the G pole of the MOS tube Q3 is connected to the logic gate control chip U5, the S pole is connected to the D pole of the MOS tube Q4 and the switch terminal J8, and the D pole is connected to the ground terminal J5; one end of the logic gate control chip U5 is connected to the logic controller U1, and the other end is connected to the G pole of the MOS tube Q4; one end of the capacitor C1 is connected to the S pole of the MOS tube Q4 and the current limiting protection chip U3, and the other end is connected to the ground terminal J5;

[0013] Pin 1 of the operational amplifier OP2 is connected to the G pole of the MOS tube Q5, pin 2 is connected to pin 2 of the operational amplifier OP1, one end of the capacitor C2, one end of the resistor R1, one end of the resistor R2 and the voltage debugging terminal J6, pin 4 is connected to the current limiting protection chip U3, and pin 5 is connected to the logic controller U1 and the discharge chip U7; the D pole of the MOS tube Q5 is connected to the current limiting protection chip U3, and the S pole is connected to the discharge chip U7, the other end of the capacitor C2, the other end of the resistor R1 and the power output terminal J7; the other end of the resistor R2 is connected to the ground terminal J5; pin 1 of the operational amplifier OP1 is connected to the logic controller U1; one end of the power management chip U6 is connected to the logic controller U1, and the other end is connected to the G pole of the MOS tube Q6; the S pole of the MOS tube Q6 is connected to the ground terminal J5, and the D pole is connected to the voltage ready terminal J4; the working mode selection terminal J2 and the chip enable terminal J3 are both connected to the logic controller U1.

[0014] Furthermore, the MOS transistor Q1 and the MOS transistor Q4 are both PMOS transistors.

[0015] Furthermore, the MOS transistor Q2 , the MOS transistor Q3 , the MOS transistor Q5 , and the MOS transistor Q6 are all NMOS transistors.

[0016] Furthermore, pin 1 of the operational amplifier OP1 is an output pin, pin 2 is a negative input pin, and pin 3 is a positive input pin.

[0017] Furthermore, pin 1 of the operational amplifier OP2 is an output pin, pin 2 is a negative input pin, pin 3 is a positive input pin, pin 4 is a positive power pin, and pin 5 is a negative power pin.

[0018] The advantages of the present invention are:

[0019] By setting a low-noise power supply chip including a logic controller U1, an overvoltage protection chip U2, a current limiting protection chip U3, a logic gate control chip U4, a logic gate control chip U5, a power management chip U6, a discharge chip U7, two operational amplifiers, an inductor L1, six MOS tubes, two capacitors, two resistors, and nine terminals, the logic controller U1 can control the on and off of MOS tubes Q1, MOS tube Q2, MOS tube Q3, and MOS tube Q4 through the logic gate control chip U4 and the logic gate control chip U5 to switch between the boost mode and the buck mode, so that the low-noise power supply chip can be compatible with the boost and buck modes. The need for voltage reduction does not require the use of different power chips for processing, which reduces the types of chip materials, reduces the number of IO resources occupied by the host computer, and reduces the PCB layout area; through the feedback loop (op amp OP2, resistor R1, resistor R2, capacitor C2), the current and voltage level of the MOS tube Q5 are adjusted in real time, and there is no need to maintain a sufficient margin for the first-level output voltage as traditionally, which effectively reduces the voltage difference of the MOS tube Q5 to reduce thermal power consumption, and ultimately greatly reduces the power consumption and cost of the low-noise power supply circuit. At the same time, reducing the use of chips can greatly save the layout space of the product PCB. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The present invention will be further described below in conjunction with embodiments with reference to the accompanying drawings.

[0021] Figure 1 The present invention is a circuit diagram of a low-noise power chip for an optical module.

[0022] Figure 2 It is a circuit diagram of the first boost module of the conventional circuit 1.

[0023] Figure 3 This is a circuit diagram of the first step-down module of the conventional circuit 1.

[0024] Figure 4 This is the circuit diagram of the second step-down module of traditional circuit two.

[0025] Figure 5 This is the circuit diagram of the third step-down module of the traditional circuit 2. DETAILED DESCRIPTION

[0026] The technical solution in the embodiment of the present application has the following general idea: the on and off of MOS tubes Q1, Q2, Q3 and Q4 are controlled by logic gate control chip U4 and logic gate control chip U5 to switch between boost mode and buck mode, so that the low-noise power supply chip can be compatible with the requirements of boost and buck, without the need to use different power supply chips for processing, thereby reducing the types of chip materials, the number of upper computer IO resources occupied, and the PCB layout area; the current size and voltage level of MOS tube Q5 are adjusted in real time through the feedback loop, without the need to maintain a sufficient margin for the first-level output voltage as traditionally, and the voltage difference of MOS tube Q5 is effectively reduced to reduce thermal power consumption, thereby reducing the power consumption and cost of the low-noise power supply circuit.

[0027] Please refer to Figures 1 to 5 As shown, a preferred embodiment of a low-noise power chip for an optical module of the present invention includes a logic controller U1, an overvoltage protection chip U2, a current limiting protection chip U3, a logic gate control chip U4, a logic gate control chip U5, a power management chip U6, a discharge chip U7, an operational amplifier OP1, an operational amplifier OP2, an inductor L1, a MOS tube Q1, a MOS tube Q2, a MOS tube Q3, a MOS tube Q4, a MOS tube Q5, a MOS tube Q6, a capacitor C1, a capacitor C2, a resistor R1, a resistor R2, a power input terminal J1, a working mode selection terminal J2, a chip enable terminal J3, a voltage ready terminal J4, a ground terminal J5, a voltage debugging terminal J6, a power output terminal J7, a switch terminal J8 and a switch terminal J9;

[0028] The logic controller U1 is used to connect the external interface (J2, J3) and logic control, that is, to collect and process the external interface and internal function control signals, and output the corresponding logic control level, so that the low-noise power supply chip can finally output the target required output voltage. It collects the signals of each sub-circuit through the IO port, processes the internal signal logic, and then outputs different levels through the IO port connected to the sub-circuit to control the operation of the corresponding chip and sub-circuit. In specific implementation, a chip that can realize this function can be selected, and it is not limited to any model. For example, a logic controller of model SN74LS00D is selected, and the control program is well known to those skilled in the art, which can be obtained by those skilled in the art without creative labor.

[0029] The overvoltage protection chip U2 and the current limiting protection chip U3 are used for self-protection of the low-noise power chip to prevent the low-noise power chip from being abnormally damaged during use. In specific implementation, a chip that can achieve this function can be selected without being limited to any model. For example, an overvoltage protection chip of model WS3202E61-6 / TR and a current limiting protection chip of model ME6231 C36N4CG are selected. The control program is well known to those skilled in the art, and can be obtained by those skilled in the art without creative labor.

[0030] The logic gate control chip U4 and the logic gate control chip U5 are used to control the working modes (PWM / PFM) of the MOS tubes Q1, Q2, Q3 and Q4. The logic gate control chip U4 controls the on and off of the MOS tubes Q1 and Q2, and the logic gate control chip U5 controls the on and off of the MOS tubes Q3 and Q4. In specific implementation, a chip that can realize this function can be selected, and is not limited to any model. For example, a logic gate control chip of model SN74LS00D is selected, and the control program is well known to those skilled in the art, and can be obtained by those skilled in the art without creative labor.

[0031] The power management chip U6 is used to output a chip ready signal when the low-noise power chip normally outputs the target voltage according to the set requirements. In specific implementation, an operational amplifier that can achieve this function can be selected, and is not limited to any model. For example, a power management chip of model BQ25790 is selected;

[0032] The discharge chip U7 is used to discharge after the low-noise power chip is turned off to protect the safety of the low-noise power chip and the external circuit; in specific implementation, a chip that can achieve this function can be selected, and is not limited to any model, for example, a discharge chip of model UN3E6-230M is selected;

[0033] The operational amplifier OP1 and the operational amplifier OP2 are used to perform logic operations on the level input by the voltage debugging terminal J6 and the reference voltage, and output the level signal to the logic controller U1 and the MOS tube Q5 to control the output voltage of the low-noise power chip; in specific implementation, an operational amplifier that can realize this function can be selected, and is not limited to any model, for example, an operational amplifier of model LM324 is selected;

[0034] The power input terminal J1 is used for chip power input; the working mode selection terminal J2 is used to switch the working mode of the chip including PWM (pulse width modulation) and PFM (pulse frequency modulation); the chip enable terminal J3 is used to control the chip to be turned on and off through high and low levels; the voltage ready terminal J4 is used to output the working state of the chip, that is, after the chip normally outputs the target voltage, the ready signal is output through the voltage ready terminal J4; the voltage debugging terminal J6 is used to adjust the output voltage; the power output terminal J7 is used for chip power output; the switch terminal J8 and the switch terminal J9 are SW pins;

[0035] The power input terminal J1, the working mode selection terminal J2, the chip enable terminal J3, the voltage ready terminal J4, the ground terminal J5, the voltage debugging terminal J6, the power output terminal J7, the switch terminal J8, the switch terminal J9 and the power input terminal J1 are connected in sequence;

[0036] One end of the inductor L1 is connected to the switch terminal J8, and the other end is connected to the switch terminal J9; one end of the overvoltage protection chip U2 is connected to the logic controller U1, and the other end is connected to the power input terminal J1 and the S pole of the MOS tube Q1; one end of the logic gate control chip U4 is connected to the logic controller U1, and the other end is connected to the G pole of the MOS tube Q1; the G pole of the MOS tube Q2 is connected to the logic gate control chip U4, the S pole is connected to the D pole of the MOS tube Q1 and the switch terminal J9, and the D pole is connected to the ground terminal J5; the G pole of the MOS tube Q3 is connected to the logic gate control chip U5, the S pole is connected to the D pole of the MOS tube Q4 and the switch terminal J8, and the D pole is connected to the ground terminal J5; one end of the logic gate control chip U5 is connected to the logic controller U1, and the other end is connected to the G pole of the MOS tube Q4; one end of the capacitor C1 is connected to the S pole of the MOS tube Q4 and the current limiting protection chip U3, and the other end is connected to the ground terminal J5;

[0037] Pin 1 of the operational amplifier OP2 is connected to the G pole of the MOS tube Q5, pin 2 is connected to pin 2 of the operational amplifier OP1, one end of the capacitor C2, one end of the resistor R1, one end of the resistor R2 and the voltage debugging terminal J6, pin 4 is connected to the current limiting protection chip U3, and pin 5 is connected to the logic controller U1 and the discharge chip U7; the D pole of the MOS tube Q5 is connected to the current limiting protection chip U3, and the S pole is connected to the discharge chip U7, the other end of the capacitor C2, the other end of the resistor R1 and the power output terminal J7; the other end of the resistor R2 is connected to the ground terminal J5; pin 1 of the operational amplifier OP1 is connected to the logic controller U1; one end of the power management chip U6 is connected to the logic controller U1, and the other end is connected to the G pole of the MOS tube Q6; the S pole of the MOS tube Q6 is connected to the ground terminal J5, and the D pole is connected to the voltage ready terminal J4; the working mode selection terminal J2 and the chip enable terminal J3 are both connected to the logic controller U1.

[0038] The MOS transistor Q1 and the MOS transistor Q4 are both PMOS transistors.

[0039] The MOS transistor Q2 , the MOS transistor Q3 , the MOS transistor Q5 and the MOS transistor Q6 are all NMOS transistors.

[0040] Pin 1 of the operational amplifier OP1 is an output pin, pin 2 is a negative input pin, and pin 3 is a positive input pin.

[0041] Pin 1 of the operational amplifier OP2 is an output pin, pin 2 is a negative input pin, pin 3 is a positive input pin, pin 4 is a positive power pin, and pin 5 is a negative power pin.

[0042] Working principle of the present invention:

[0043] Boost mode:

[0044] 1. The power input terminal J1 is connected to the power supply, the logic controller U1 is started through the chip enable terminal J3, the input signal of the working mode selection terminal J2 is modulated to the PWM working mode, and the PWM waveform with the target duty cycle D is output to control the logic gate control chip U4 and the logic gate control chip U5;

[0045] 2. The logic gate control chip U4 controls the MOS tube Q1 to remain on and controls the MOS tube Q2 to remain off according to the PWM waveform;

[0046] 3. The logic gate control chip U5 controls the on and off of the MOS tubes Q3 and Q4 according to the PWM waveform; according to the voltage volt-second balance law V1=Vi n / (1-D) of the inductor L1, the voltage V1 output by the MOS tube Q4 can be obtained;

[0047] 4. Since the voltage V1 has a large ripple, it is filtered through capacitor C1;

[0048] 5. In order to further obtain an output voltage Vout with lower noise, the MOS tube Q5 and the operational amplifier OP2 form a feedback loop (operational amplifier OP2, resistor R1, resistor R2, capacitor C2) in real time according to the difference between the reference voltage and the target voltage debugging level, and adjust the current size and voltage level of the MOS tube Q5 in real time, so as to obtain a low-noise stable output voltage Vout;

[0049] Wherein Vout=V1=Vi n / (1-D), where Vout is the output voltage, Vin is the input voltage, and D is the duty cycle of the PWM mode waveform.

[0050] Buck Mode:

[0051] 1. The power input terminal J1 is connected to the power supply, the logic controller U1 is started through the chip enable terminal J3, the input signal of the working mode selection terminal J2 is modulated to the PWM working mode, and the PWM waveform with the target duty cycle D is output to control the logic gate control chip U4 and the logic gate control chip U5;

[0052] 2. The logic gate control chip U4 controls the on and off of the MOS tubes Q1 and Q2 according to the PWM waveform; according to the voltage volt-second balance law Vout=Vi n*D of the inductor L1, the voltage V1 output by the MOS tube Q4 can be obtained;

[0053] 3. The logic gate control chip U5 controls the MOS tube Q3 to remain disconnected and controls the MOS tube Q4 to remain turned on according to the PWM waveform;

[0054] 4. Since the voltage V1 has a large ripple, it is filtered through capacitor C1;

[0055] 5. In order to further obtain an output voltage Vout with lower noise, the MOS tube Q5 and the operational amplifier OP2 form a feedback loop (operational amplifier OP2, resistor R1, resistor R2, capacitor C2) in real time according to the difference between the reference voltage and the target voltage debugging level, and adjust the current size and voltage level of the MOS tube Q5 in real time, so as to obtain a low-noise stable output voltage Vout;

[0056] Wherein Vout=V1=Vi n*D, wherein Vout is the output voltage, Vin is the input voltage, and D is the duty cycle of the PWM mode waveform.

[0057] In summary, the advantages of the present invention are:

[0058] By setting a low-noise power supply chip including a logic controller U1, an overvoltage protection chip U2, a current limiting protection chip U3, a logic gate control chip U4, a logic gate control chip U5, a power management chip U6, a discharge chip U7, two operational amplifiers, an inductor L1, six MOS tubes, two capacitors, two resistors, and nine terminals, the logic controller U1 can control the on and off of MOS tubes Q1, MOS tube Q2, MOS tube Q3, and MOS tube Q4 through the logic gate control chip U4 and the logic gate control chip U5 to switch between the boost mode and the buck mode, so that the low-noise power supply chip can be compatible with the boost and buck modes. The need for voltage reduction does not require the use of different power chips for processing, which reduces the types of chip materials, reduces the number of IO resources occupied by the host computer, and reduces the PCB layout area; through the feedback loop (op amp OP2, resistor R1, resistor R2, capacitor C2), the current and voltage level of the MOS tube Q5 are adjusted in real time, and there is no need to maintain a sufficient margin for the first-level output voltage as traditionally, which effectively reduces the voltage difference of the MOS tube Q5 to reduce thermal power consumption, and ultimately greatly reduces the power consumption and cost of the low-noise power supply circuit. At the same time, reducing the use of chips can greatly save the layout space of the product PCB.

[0059] Although the specific implementation modes of the present invention are described above, those skilled in the art should understand that the specific implementation modes described are only illustrative and are not intended to limit the scope of the present invention. Equivalent modifications and changes made by those skilled in the art in accordance with the spirit of the present invention should be included in the scope of protection of the claims of the present invention.

Claims

1. A low-noise power chip for an optical module, characterized in that: It includes a logic controller U1, an overvoltage protection chip U2, a current limiting protection chip U3, a logic gate control chip U4, a logic gate control chip U5, a power management chip U6, a discharge chip U7, an operational amplifier OP1, an operational amplifier OP2, an inductor L1, a MOS tube Q1, a MOS tube Q2, a MOS tube Q3, a MOS tube Q4, a MOS tube Q5, a MOS tube Q6, a capacitor C1, a capacitor C2, a resistor R1, a resistor R2, a power input terminal J1, a working mode selection terminal J2, a chip enable terminal J3, a voltage ready terminal J4, a ground terminal J5, a voltage debugging terminal J6, a power output terminal J7, a switch terminal J8 and a switch terminal J9; The power input terminal J1, the working mode selection terminal J2, the chip enable terminal J3, the voltage ready terminal J4, the ground terminal J5, the voltage debugging terminal J6, the power output terminal J7, the switch terminal J8, the switch terminal J9 and the power input terminal J1 are connected in sequence; One end of the inductor L1 is connected to the switch terminal J8, and the other end is connected to the switch terminal J9; one end of the overvoltage protection chip U2 is connected to the logic controller U1, and the other end is connected to the power input terminal J1 and the S pole of the MOS tube Q1; one end of the logic gate control chip U4 is connected to the logic controller U1, and the other end is connected to the G pole of the MOS tube Q1; the G pole of the MOS tube Q2 is connected to the logic gate control chip U4, the S pole is connected to the D pole of the MOS tube Q1 and the switch terminal J9, and the D pole is connected to the ground terminal J5; the G pole of the MOS tube Q3 is connected to the logic gate control chip U5, the S pole is connected to the D pole of the MOS tube Q4 and the switch terminal J8, and the D pole is connected to the ground terminal J5; one end of the logic gate control chip U5 is connected to the logic controller U1, and the other end is connected to the G pole of the MOS tube Q4; one end of the capacitor C1 is connected to the S pole of the MOS tube Q4 and the current limiting protection chip U3, and the other end is connected to the ground terminal J5; Pin 1 of the operational amplifier OP2 is connected to the G pole of the MOS tube Q5, pin 2 is connected to pin 2 of the operational amplifier OP1, one end of the capacitor C2, one end of the resistor R1, one end of the resistor R2 and the voltage debugging terminal J6, pin 4 is connected to the current limiting protection chip U3, and pin 5 is connected to the logic controller U1 and the discharge chip U7; the D pole of the MOS tube Q5 is connected to the current limiting protection chip U3, and the S pole is connected to the discharge chip U7, the other end of the capacitor C2, the other end of the resistor R1 and the power output terminal J7; the other end of the resistor R2 is connected to the ground terminal J5; pin 1 of the operational amplifier OP1 is connected to the logic controller U1; one end of the power management chip U6 is connected to the logic controller U1, and the other end is connected to the G pole of the MOS tube Q6; the S pole of the MOS tube Q6 is connected to the ground terminal J5, and the D pole is connected to the voltage ready terminal J4; the working mode selection terminal J2 and the chip enable terminal J3 are both connected to the logic controller U1.

2. A low-noise power chip for an optical module as claimed in claim 1, characterized in that: The MOS transistor Q1 and the MOS transistor Q4 are both PMOS transistors.

3. A low-noise power chip for an optical module as claimed in claim 1, characterized in that: The MOS transistor Q2 , the MOS transistor Q3 , the MOS transistor Q5 and the MOS transistor Q6 are all NMOS transistors.

4. A low-noise power chip for an optical module as claimed in claim 1, characterized in that: Pin 1 of the operational amplifier OP1 is an output pin, pin 2 is a negative input pin, and pin 3 is a positive input pin.

5. A low-noise power chip for an optical module as claimed in claim 1, characterized in that: Pin 1 of the operational amplifier OP2 is an output pin, pin 2 is a negative input pin, pin 3 is a positive input pin, pin 4 is a positive power pin, and pin 5 is a negative power pin.

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