A Low-Noise Amplifier Based on Inverter and Its Multi-Objective Optimization Method

Abstract

This invention discloses a low-noise amplifier based on an inverter and its multi-objective optimization method, including an inverter and an input capacitor C. I Feedback capacitor C F And a single-stage operational amplifier. An inverter consists of a PMOS transistor and an NMOS transistor connected in series, with an input capacitor C. I and feedback capacitor C F All amplifiers use a split capacitor structure. The positive input of the single-stage operational amplifier is connected to the output of the inverter, the negative input is connected to the reference voltage, and the output is connected to the gate of the NMOS transistor through resistor R2. At the same time, the gate of the PMOS transistor is connected to resistor R1, and the resistance values ​​of R1 and R2 are equal. This improves the stability and noise performance of the amplifier circuit. A multi-objective optimization design method is used to optimize the design parameters of the low-noise amplifier to meet the amplification requirements of ultrasonic pulse echo signals of different frequencies, thereby improving design efficiency.

Description

Technical Field

[0001] This invention belongs to the field of ultrasonic imaging simulation technology, and relates to a low-noise amplifier based on an inverter and its multi-objective optimization method. Background Technology

[0002] In recent years, with the continuous advancement of medical technology, ultrasound imaging has become an indispensable tool in modern medical diagnosis. Especially in the field of intracardiac echocardiography, its application has greatly improved the accuracy and efficiency of diagnosing heart diseases. To achieve more refined imaging results, the design of ultrasound probes has continuously evolved towards miniaturization and integration, and has now been successfully reduced to the millimeter level. This technological breakthrough not only provides doctors with a more convenient operating experience but also places higher demands on the overall performance of ultrasound imaging systems.

[0003] In the analog front-end of an ultrasound imaging system, the low-noise amplifier (LNA) plays a crucial role. Its main function is to amplify the weak echo signals received by the ultrasound probe, ensuring that these signals can be effectively processed by subsequent circuitry. Since the signals that need to be detected in ultrasound imaging are usually very weak, the LNA must have extremely low input equivalent noise to avoid introducing excessive noise interference during signal amplification.

[0004] Traditional ultrasonic analog front-end LNA designs often use a transimpedance amplifier composed of a common-source amplifier and a source follower, applied to piezoelectric ultrasonic transducers made of PZT material, which has low efficiency. Capacitor feedback amplifiers based on inverter structures amplify signals by inducing voltage and are also convenient for impedance matching. However, inverter-structured LNAs also have some significant drawbacks, such as high noise, limited operating bandwidth, and insufficient gain stability. In addition, when multiple performance indicators need to be met, the trade-off process of traditional circuit design methods is very time-consuming and inefficient. Summary of the Invention

[0005] The purpose of this invention is to solve the technical problems of traditional low-noise amplifiers in the prior art, such as high noise, limited operating bandwidth, and insufficient gain stability. At the same time, when multiple performance indicators need to be met, the traditional circuit design method is very time-consuming and inefficient in terms of trade-offs. The invention provides a low-noise amplifier based on an inverter and its multi-objective optimization method.

[0006] To achieve the above objectives, the present invention employs the following technical solution:

[0007] The first aspect of this invention provides a low-noise amplifier based on an inverter, comprising an inverter and an input capacitor C. I Feedback capacitor C F and single-stage operational amplifiers;

[0008] The inverter is composed of a PMOS transistor M P1 and NMOS transistor M N1 The PMOS and NMOS transistors are connected in series, with their gates serving as input terminals and their drains as output terminals. The source of the PMOS transistor is connected to the power supply V. DD The source of the NMOS transistor is connected to ground;

[0009] The input capacitor C I and feedback capacitor C F Parallel connection; the input capacitor C I For capacitor C I1 and capacitor C I2 A series-connected split capacitor structure; capacitor C is connected at the signal input terminal. I1 and capacitor C I2 Between; the input capacitor C I The two ends are respectively connected to PMOS transistors M P1 The gate and NMOS transistor M N1 The gate; the feedback capacitor C F For capacitor C F1 and capacitor C F2 A series-connected split capacitor structure, with capacitor C connected to the output of the inverter. F1 and capacitor C F2 between;

[0010] The positive input terminal of the single-stage operational amplifier is connected to the output terminal of the inverter, and the negative input terminal is connected to the reference voltage V. REF The output terminal is connected to resistor R2 and then to NMOS transistor M. N1 The gate of the PMOS transistor M P1 The gate is connected to a resistor R1, and the resistance values ​​of resistor R1 and resistor R2 are equal.

[0011] Furthermore, the resistor R1 is connected to a PMOS transistor M. P2 , with PMOS transistor M P2 The gate of the PMOS transistor M is connected to the gate of the PMOS transistor M. P2 The source terminal is connected to the power supply V. DD The PMOS transistor M P2 The drain of the PMOS transistor M P2 The gate is connected.

[0012] Furthermore, the PMOS transistor M P2 The drain connection has a bias current.

[0013] A second aspect of the present invention provides a multi-objective optimization method for a low-noise amplifier, comprising the following steps:

[0014] S1. Based on the circuit structure of the low-noise amplifier and the target performance indicators to be optimized, determine the design parameters, fitness function, and circuit constraints.

[0015] S2, Based on the determined design parameters, the circuit structure of the low-noise amplifier is simulated and analyzed to obtain the design parameters and corresponding target performance indexes of the circuit structure.

[0016] S3, Based on the design parameters and corresponding target performance index dataset under this circuit structure, train the neural network model to obtain the trained neural network model;

[0017] S4. Based on the trained neural network model, fitness function, and circuit constraints, the PSO-LDIW algorithm is used to find the optimal design parameters for the circuit structure.

[0018] Furthermore, the design parameters include the magnitude of the bias current, the magnitude of the input capacitance, the gate width of the NMOS transistor in the inverter, the gate width of the PMOS transistor in the inverter, and the gate length of the inverter.

[0019] Furthermore, the target performance metrics include open-loop voltage gain, bandwidth, total power consumption, noise, and center frequency.

[0020] Furthermore, the fitness function is described as follows:

[0021] min f(x)=α(A V -A V,TAR ) 2 +β(BW-BW TAR ) 2 +γ(P t -P t,TAR ) 2 +κ(Noise-Noise TAR ) 2 +η(C F -C F,TAR ) 2

[0022] Among them, A V Here, BW is the open-loop voltage gain, and P is the bandwidth. t C represents total power consumption, and Noise represents noise. F Indicates the center frequency, A V,TAR BW represents the target value of the open-loop voltage gain. TAR Indicates the target bandwidth value; P t,TAR Indicates the target value for total power consumption; Noise TAR Indicates the target value of the noise; C F,TAR The target value of the center frequency is represented; α, β, γ, η and κ are all weighting coefficients.

[0023] Furthermore, the constraints on the circuit are the basic performance requirements for the operation of the low-noise amplifier circuit.

[0024] Furthermore, the neural network model is an NN model.

[0025] Furthermore, based on the trained neural network model, fitness function, and circuit constraints, the PSO-LDIW algorithm is used to find the optimal design parameters for this circuit structure, specifically as follows:

[0026] Several particles are randomly generated; each particle represents a set of design parameters.

[0027] Each particle is input into a trained neural network model to obtain the corresponding target performance index.

[0028] Particles are screened based on circuit constraints.

[0029] For qualified particles, their fitness is evaluated using a fitness function, and the position and velocity of the particles are updated until the particle with the best fitness is found; thus, the optimal design parameters are obtained; the fitness function is obtained based on the target performance index.

[0030] Compared with the prior art, the present invention has the following beneficial effects:

[0031] This invention discloses a low-noise amplifier based on an inverter, which, through a designed inverter structure, uses a PMOS transistor M P1 and NMOS transistor M N1 The series connection effectively balances the current and reduces noise generation. This structure helps provide low-noise performance at the input, thereby improving the overall noise figure of the amplifier; input capacitor C I Employing a split capacitor structure (capacitor C) I1 and capacitor C I2 (Series connection), this design can further reduce noise interference at the input while maintaining signal integrity, thereby further improving the noise performance of the LNA; feedback capacitor C F It also adopts a split capacitor structure (capacitor C) F1 and capacitor C F2 (Series connection) This design not only helps stabilize the amplifier's output but also provides the required gain within a specific frequency range, enabling the LNA to maintain good performance over a wide bandwidth. The introduction of a single-stage operational amplifier enhances the circuit's gain capability, while a reasonable negative feedback design ensures the amplifier's stability and avoids unstable phenomena such as self-oscillation. By properly configuring symmetrical resistors R1 and R2, the amplifier's frequency response characteristics can be adjusted, allowing the LNA to have a flat gain curve and low phase distortion within the required frequency band.

[0032] This invention discloses a multi-objective optimization method for low-noise amplifiers. By determining design parameters, fitness functions, and circuit constraints, it enables efficient multi-objective optimization of inverter-based low-noise amplifiers. Utilizing detailed datasets obtained from simulation analysis, combined with a trained neural network model, it can rapidly predict target performance indicators under different design parameters, thereby significantly shortening the design cycle and improving design accuracy. The introduced PSO-LDIW (Particle Swarm Optimization-Linear Decreasing Inertia Weight) algorithm, based on the trained neural network model, maintains global search capabilities while employing a local density optimization strategy to more accurately locate the optimal combination of design parameters that satisfies all constraints. This not only improves optimization efficiency but also ensures the practicality and reliability of the optimization results. Through the implementation of multi-objective optimization, this method can effectively balance various key performance indicators of low-noise amplifiers, such as gain, noise figure, linearity, and power consumption, achieving overall performance optimization. Attached Figure Description

[0033] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0034] Figure 1 This is a schematic diagram of a low-noise amplifier circuit based on an inverter, according to an embodiment of the present invention.

[0035] Figure 2 This is a flowchart of the low-noise amplifier optimization method according to an embodiment of the present invention;

[0036] Figure 3 This is the result of multiple runs of the low-noise amplifier optimization method in this embodiment of the invention;

[0037] Figure 4 This refers to the voltage gain of the low-noise amplifier when the loop is closed in an embodiment of the present invention for amplifying signals of various frequencies.

[0038] Figure 5 This is a diagram illustrating the effect of a low-noise amplifier amplifying pulse echo signals of different frequencies in an embodiment of the present invention. Detailed Implementation

[0039] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and marked in the accompanying drawings can generally be arranged and designed in various different configurations.

[0040] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0041] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0042] In the description of the embodiments of the present invention, it should be noted that if terms such as "upper," "lower," "horizontal," or "inner" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship commonly used when the product of the invention is in use, they are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the present invention. Furthermore, terms such as "first" and "second" are only used to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0043] Furthermore, the use of the term "horizontal" does not imply that the component must be absolutely horizontal, but rather that it can be slightly tilted. For example, "horizontal" simply means that its direction is more horizontal than "vertical," and does not mean that the structure must be completely horizontal, but can be slightly tilted.

[0044] In the description of the embodiments of the present invention, it should also be noted that, unless otherwise explicitly specified and limited, the terms "set," "install," "connect," and "link" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in the present invention according to the specific circumstances.

[0045] The present invention will now be described in further detail with reference to the accompanying drawings:

[0046] See Figure 1 This invention discloses a low-noise amplifier based on an inverter, comprising an inverter and an input capacitor C. I Feedback capacitor C F and DC control loop;

[0047] The inverter consists of a PMOS transistor M P1 and NMOS transistor M N1 The PMOS and NMOS transistors are connected in series, with their gates serving as input terminals and their drains as output terminals. The source of the PMOS transistor is connected to the power supply V. DD The source of the NMOS transistor is connected to ground;

[0048] The input capacitor C I and feedback capacitor C F Parallel connection; the input capacitor C I For capacitor C I1 and capacitor C I2 A series-connected split capacitor structure; capacitor C is connected at the signal input terminal. I1 and capacitor C I2 Between; the input capacitor C I The two ends are respectively connected to PMOS transistors M P1 The gate and NMOS transistor M N1 The gate; the feedback capacitor C F For capacitor C F1 and capacitor C F2 A series-connected split capacitor structure, with capacitor C connected to the output of the inverter. F1 and capacitor C F2 between;

[0049] The DC control loop includes a single-stage operational amplifier. The positive input of the single-stage operational amplifier is connected to the output of the inverter, and the negative input is connected to the reference voltage V. REF The output terminal is connected to resistor R2 and then to NMOS transistor M. N1 The gate of the PMOS transistor M P1 The gate connection resistor R1, and the resistor R2 has the same resistance value as resistor R1; for a device-matched CMOS inverter structure, the highest gain point is V. DD At position / 2, the DC control loop is used to control the inverter output at V. DD / 2, thus achieving the highest gain. The DC control loop consists of a single-stage operational amplifier, with its positive input connected to the output of an inverter and its negative input connected to the reference voltage V. REF This makes the output voltage V OUT =V REF V REF =V DD / 2; Resistor R1 is connected to PMOS transistor M P2 , with PMOS transistor MP2 The gate of the PMOS transistor M is connected to the gate of the PMOS transistor M. P2 The source terminal is connected to the power supply V. DD The PMOS transistor M P2 The drain of the PMOS transistor M P2 The gate of the PMOS transistor is connected to the gate. P2 The drain is connected to a bias current. The bias current I B This stabilizes the DC operating point of the low-noise amplifier. Small signal V IN When it arrives, the bias current I B Through C I Coupled to the gate of the inverter, the output voltage V OUT For V IN Amplified voltage and reference voltage V REF The superposition of.

[0050] This invention effectively optimizes the amplifier's frequency response through a split capacitor design, resulting in a flatter gain within a specific frequency range, reduced noise interference, improved signal-to-noise ratio, and bandpass amplification, further filtering low- and high-frequency noise. The DC control loop controls the inverter's output at half the power supply voltage VDD (VDD / 2), ensuring the amplifier operates at its optimal operating point, thus achieving the highest gain and lowest noise figure. The single-stage operational amplifier in the DC control loop effectively stabilizes the amplifier's output voltage through a negative feedback mechanism, maintaining stability even with input signal fluctuations or changes in the external environment, enhancing the amplifier's robustness. The introduction of resistors R1 and R2, and the symmetrical resistor R1 at the PMOS transistor M... P1 The connection of the gate further improves the symmetry and stability of the circuit, which helps to reduce distortion and improve linearity.

[0051] See Figure 2 This invention discloses a multi-objective optimization method for low-noise amplifiers, comprising the following steps:

[0052] S1. Based on the circuit structure of the low-noise amplifier and the target performance indicators to be optimized, determine the design parameters, fitness function, and circuit constraints. The circuit constraints are the basic performance requirements for circuit operation, including requirements for device size and amplifier performance. The target performance indicators are the circuit performance corresponding to each design parameter, which are obtained based on the actual needs of the ultrasonic system. Based on the target performance indicators to be optimized, construct a fitness function for the performance requirements to be achieved.

[0053] The design parameters for the low-noise amplifier in this embodiment are:

[0054] x = [I B C I,L,W n W p (1)

[0055] Among them, I B For bias current, C I Where is the input capacitor, L is the gate length of the inverter, and W is the input capacitance. n W is the gate width of the NMOS transistor in the inverter. p This represents the gate width of the PMOS transistor in the inverter.

[0056] Fitness function:

[0057]

[0058] Constraints:

[0059]

[0060] Among them, A V Here, BW is the open-loop voltage gain, and P is the bandwidth. t C represents total power consumption, and Noise represents noise. F Indicates the center frequency, A V,TAR BW represents the target value of the open-loop voltage gain. TAR Indicates the target bandwidth value; P t,TAR Indicates the target value for total power consumption; Noise TAR Indicates the target value of the noise; C F,TAR The target value of the center frequency is represented; α, β, γ, η, and κ are all weighting coefficients, summing to 1. In the constraints, PM is the phase margin, SR is the slew rate, and V... gs,N1 For M N1 The gate-source voltage, V th,N1 For M N1 Threshold voltage, V ds,N1 For M N1 The drain-source voltage, V gs,P1 For M P1 The gate-source voltage, V th,P1 For M P1 Threshold voltage, V ds,P1 For M P1 The drain-source voltage.

[0061] S2, Based on the determined design parameters, the circuit structure of the low-noise amplifier is simulated and analyzed to obtain the design parameters and corresponding target performance indexes of the circuit structure.

[0062] Based on the various design parameters under this circuit structure, the circuit of the low-noise amplifier is simulated. The dataset of design parameters and corresponding target performance indicators under this circuit structure is used to generate training data. The training data is then used to train the neural network model to obtain the trained neural network model.

[0063] The low-noise amplifier circuit is simulated using Cadence to generate training data. The simulation training data is then used to train the NN model. The trained NN model can effectively describe the relationship between design variables and target performance indicators. The structure of the NN model is: input layer - hidden layer - output layer. This invention establishes an NN model for each performance indicator, such as voltage gain and bandwidth, thereby enabling the prediction of multiple performance indicators.

[0064] By inputting the various design parameters into a pre-trained neural network model, the corresponding objective function is obtained.

[0065] S3, based on the trained neural network model, fitness function, and circuit constraints, uses the PSO-LDIW (Particle Swarm Optimization-Linear Decreasing Inertia Weight) algorithm to find the optimal design parameters for the circuit structure. The PSO-LDIW algorithm adds inertia weight to the PSO algorithm, and enhances the search capability and expands the search space by linearly decreasing the inertia weight, thus finding the global optimum.

[0066] In the particle swarm initialization phase, particles are randomly generated, each representing a set of design parameters. Each particle is input into a pre-trained neural network (NN) model, which obtains the target performance metrics and simultaneously filters whether the particles satisfy the constraints. The fit of particles that satisfy the constraints is evaluated, and the particle positions and velocities are updated until the particle with the best fit is found, i.e., the optimal design parameters are found.

[0067] This invention defines the design parameters, fitness function, and circuit constraints, providing a clear direction and criteria for the optimization of low-noise amplifiers. The construction of the fitness function fully considers the actual needs of the ultrasonic system, ensuring the practicality and relevance of the optimization objective. Accurate simulation analysis of the circuit structure is performed using simulation tools such as Cadence, generating a large dataset of reliable design parameters and target performance indicators, providing a foundation for training the neural network model. A neural network model (NN model) is used to model the relationship between the design parameters and target performance indicators, enabling rapid prediction of multiple performance indicators. This model structure (input layer—hidden layer—output layer) is not only simple and efficient, but also has high prediction accuracy. By establishing an independent NN model for each performance index, the accuracy and flexibility of prediction are further improved. The PSO-LDIW algorithm, based on the Particle Swarm Optimization (PSO) algorithm, significantly enhances search capability and expands the search space by introducing inertia weights and linearly reducing them, making it easier to find the global optimum. During optimization, the algorithm efficiently selects particles that meet the constraints and evaluates them based on the fitness function. By continuously updating the position and velocity of the particles, the optimal design parameters are finally found. Using the optimization method of this invention, the low-noise amplifier achieves significant improvements in multiple performance indicators such as voltage gain, bandwidth, power consumption, noise, and center frequency, meeting the high-performance requirements of applications such as ultrasonic systems. Simultaneously, the use of efficient simulation analysis and optimization algorithms greatly shortens the design cycle.

[0068] One embodiment of the present invention provides a low-noise amplifier, wherein the parameters of which include, but are not limited to, PMOS transistor M P1 Size, NMOS transistor M N1 Size, input capacitance C I The size of the amplifier and the magnitude of the bias current are both designed using the aforementioned low-noise amplifier optimization method.

[0069] To demonstrate the superiority of this invention, this embodiment evaluates the performance of the low-noise amplifier multi-objective optimization method and the inverter-based low-noise amplifier of this invention, and the results are as follows:

[0070] See Figure 3 The results of running the low-noise amplifier multi-objective optimization method of this invention 20 times are shown. It can be seen that the fluctuations of the optimized indicators are very small, indicating that this invention can stably find the optimal solution. Due to the small fluctuations, it can be considered that the multi-objective optimization method of this invention can maintain consistent optimization results in multiple runs, thus verifying its stability and reliability.

[0071] See Figure 4This paper demonstrates the closed-loop gain of the inverter-based low-noise amplifier of this invention at different frequencies. It shows that the closed-loop gain of the inverter-based low-noise amplifier is stable at around 20dB, indicating that it maintains a stable gain output at different frequencies. Stable gain output is crucial for signal amplification, especially in applications requiring precise amplification, such as the amplification of ultrasonic pulse echo signals.

[0072] See Figure 5 The diagram illustrates the time-domain and frequency-domain amplification effects of the inverter-based low-noise amplifier of this invention at different frequencies. It is evident that the time-domain signal is significantly amplified, demonstrating that the amplifier of this invention can effectively enhance weak signals. IN (Input voltage) and V OUT The normalized dB values ​​of the output voltage all coincide above -6dB, indicating that the amplifier has very low distortion and can maintain the original characteristics of the signal. Low distortion is one of the important indicators of amplifier performance, especially in applications requiring high-fidelity amplification. Figure 5 The results show that the amplifier can maintain the original waveform and characteristics of the signal well while amplifying it.

[0073] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A low-noise amplifier based on an inverter, characterized in that, Including inverter, input capacitor C I Feedback capacitor C F and single-stage operational amplifiers; The inverter is composed of a PMOS transistor M P1 and NMOS transistor M N1 The PMOS and NMOS transistors are connected in series, with their gates serving as input terminals and their drains as output terminals. The source of the PMOS transistor is connected to the power supply V. DD The source of the NMOS transistor is connected to ground; The input capacitor C I and feedback capacitor C F Parallel connection; the input capacitor C I For capacitor C I1 and capacitor C I2 A series-connected split capacitor structure; capacitor C is connected at the signal input terminal. I1 and capacitor C I2 Between; the input capacitor C I The two ends are respectively connected to PMOS transistors M P1 The gate and NMOS transistor M N1 The gate; the feedback capacitor C F For capacitor C F1 and capacitor C F2 A series-connected split capacitor structure, with capacitor C connected to the output of the inverter. F1 and capacitor C F2 between; The positive input terminal of the single-stage operational amplifier is connected to the output terminal of the inverter, and the negative input terminal is connected to the reference voltage V. REF The output terminal is connected to resistor R2 and then to NMOS transistor M. N1 The gate of the PMOS transistor M P1 The gate of the transistor is connected to a resistor R1, and the resistances of resistors R1 and R2 are equal; resistor R1 is connected to a PMOS transistor M. P2 , with PMOS transistor M P2 The gate of the PMOS transistor M is connected to the gate of the PMOS transistor M. P2 The source terminal is connected to the power supply V. DD The PMOS transistor M P2 The drain of the PMOS transistor M P2 The gate is connected.

2. The low-noise amplifier based on an inverter according to claim 1, characterized in that, The PMOS transistor M P2 The drain connection has a bias current.

3. A multi-objective optimization method for a low-noise amplifier, based on the inverter-based low-noise amplifier according to any one of claims 1-2, characterized in that, Includes the following steps: S1. Based on the circuit structure of the low-noise amplifier and the target performance indicators to be optimized, determine the design parameters, fitness function, and circuit constraints. S2, Based on the determined design parameters, the circuit structure of the low-noise amplifier is simulated and analyzed to obtain the design parameters and corresponding target performance indexes of the circuit structure. S3, Based on the design parameters and corresponding target performance index dataset under this circuit structure, train the neural network model to obtain the trained neural network model; S4. Based on the trained neural network model, fitness function, and circuit constraints, the PSO-LDIW algorithm is used to find the optimal design parameters for the circuit structure.

4. The low-noise amplifier multi-objective optimization method according to claim 3, characterized in that, The design parameters include the magnitude of the bias current, the magnitude of the input capacitance, the gate width of the NMOS transistor in the inverter, the gate width of the PMOS transistor in the inverter, and the gate length of the inverter.

5. The low-noise amplifier multi-objective optimization method according to claim 3, characterized in that, The target performance metrics include open-loop voltage gain, bandwidth, total power consumption, noise, and center frequency.

6. The low-noise amplifier multi-objective optimization method according to claim 3, characterized in that, The fitness function is described as follows: in, For open-loop voltage gain, For bandwidth, Total power consumption For noise, Indicates the center frequency. This represents the target value of the open-loop voltage gain. Indicates the target bandwidth value; This represents the target value for total power consumption; Indicates the target value of the noise; This represents the target value of the center frequency; 、 、 、 and All are weighting coefficients.

7. The low-noise amplifier multi-objective optimization method according to claim 3, characterized in that, The constraints of the circuit are: in, PM For phase margin, SR The slew rate, For M N1 Gate-source voltage, For M N1 Threshold voltage, For M N1 The drain-source voltage, For M P1 Gate-source voltage, For M P1 Threshold voltage, For M P1 The drain-source voltage, This refers to the gate width of the NMOS transistor in the inverter. This represents the gate width of the PMOS transistor in the inverter. The grid length of the inverter is 1. This is the bias current.

8. The low-noise amplifier multi-objective optimization method according to claim 3, characterized in that, Based on the trained neural network model, fitness function, and circuit constraints, the PSO-LDIW algorithm is used to find the optimal design parameters for this circuit structure, specifically: Several particles are randomly generated; each particle represents a set of design parameters. Each particle is input into a trained neural network model to obtain the corresponding target performance index. Particles are screened based on circuit constraints. For qualified particles, their fitness is evaluated using a fitness function, and the position and velocity of the particles are updated until the particle with the best fitness is found; thus, the optimal design parameters are obtained; the fitness function is obtained based on the target performance index.

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