High-opening output circuit and operation method thereof

Abstract

The invention discloses a high-open output circuit and an operation method thereof, and relates to the technical field of aviation power distribution. The method comprises the following steps: when a control signal is effective, an input signal forms a loop, so that a voltage difference is generated between a source electrode and a grid electrode of a PMOS (P-channel Metal Oxide Semiconductor), the PMOS is switched on, and a high state is output. And when the control signal is invalid, the PMOS outputs an on state. Besides the control output function, the circuit also has the functions of current-limiting output, alarm and output prompt. The circuit is high in reliability and good in portability, and has typical popularization value.

Description

Technical Field

[0001] The invention belongs to the technical field of aviation power distribution system, and in particular relates to a high-open output circuit and an operation method thereof. Background Art

[0002] With the continuous development of airborne products, the application scenarios of high / open output circuits are increasing, and products also put forward more requirements for high / open output circuits, such as current limiting output, alarm, output prompt and other functions. The present invention aims at various requirements of high / open circuits and forms a high / open output circuit and operation method with current limiting output, alarm, and output prompt functions. Summary of the invention

[0003] The technical problem to be solved by the present invention is to provide an airborne product high / open output circuit and an operating method with current limiting output, alarm, and output prompt functions in view of the limitations of traditional airborne product high / open output circuits.

[0004] In view of this, according to one aspect of an embodiment of the present invention, a high-open output circuit is provided, including a MOS tube driving circuit, a MOS tube peripheral circuit, a current limiting output circuit, an alarm circuit, and an output prompt circuit, wherein the circuit includes resistors R30, R99, R96, R104, R98, R105, R103, R100, R3, R14, R94, RA1, R101, R110, RA2, capacitors C32, C9, CA1, transistors Q5, Q10, Q4, Q6, a first end of R96 is connected to a first end of R99, and a first end of R96 is connected to the alarm circuit. The output signal AA5 is connected, the second end of R96 is connected in parallel with the second end of C32 and connected to GND, the second end of R99 is connected to the second end of R99 and the first end of R104, and the second end of R99 is connected to the first end of C32, the second end of R104 is connected to the collector of Q5, the emitter of Q5 is connected to the high open circuit input signal, the base of Q5 is connected to the first end of R98, the second end of R98 is connected to the first end of R105, and the second end of R98 is connected to the first end of R103, the second end of R105 is connected to the base of Q10, the second end of R103 is connected to the second end of R30, and the second end of R103 is connected to The source of Q6 is connected, the emitter of Q10 is connected to the high open circuit input signal, and the emitter of Q10 is connected to the first end of R30, and the emitter of Q10 is connected to the emitter of Q5, the collector of Q10 is connected to the second end of R100, and the collector of Q10 is connected to the gate of Q6, and the collector of Q10 is connected to the first end of C9, and the collector of Q10 is connected to the first end of R3, and the first end of R30 is connected to the high open circuit input signal, the drain of Q6 is connected to the second end of RA1, the drain of Q6 is connected to the first end of R101, and the drain of Q6 is connected to the output signal of the high open circuit, C9 The second end is connected to the first end of RA1, the second end of R3 is connected to the collector of Q4, the emitter of Q4 is connected to the second end of R94 and connected to GND, the base of Q4 is connected to the first end of R94, the first end of R14 is connected to the high open circuit control signal, the first end of R101 is connected to the second end of RA1, the second end of R101 is connected to the second end of R101 and the first end of R110, and the second end of R101 is connected to the first end of CA1, the second end of R110 is connected to the first end of RA2, and the second end of R110 is connected to the output prompt signal AA6, and the second end of CA1 is connected to the second end of RA2 and connected to GND.

[0005] Optionally, a diode D61 is added to protect the control signal output circuit, the base of Q4 is connected to the cathode of D61, the anode of D61 is connected to the second end of R14, and the reverse withstand voltage value of D61 is +75V.

[0006] Optionally, a diode D60 is added to provide clamping protection for the circuit receiving the AA5 signal, the second end of R99 is connected to the anode of D60, and the cathode of D60 is connected to the +5V power supply.

[0007] Optionally, a diode D7 is added to provide clamping protection for the circuit receiving the AA6 signal, the second end of R101 is connected to the anode of D7, and the cathode of D7 is connected to the +5V power supply.

[0008] Optionally, a voltage regulator diode D11 is configured to protect the gate-source of the MOS tube, the collector of Q10 is connected to the anode of D11, the cathode of D11 is connected to the second end of R30, the cathode of D11 is connected to the second end of R103, the cathode of D11 is connected to the first end of R100, and the cathode of D11 is connected to the source of Q6.

[0009] Optionally, the input signal voltage is +28V.

[0010] According to another aspect of an embodiment of the present invention, a method for operating a high-open output circuit is also provided. Based on any of the above circuits, RA1 is configured between the gate and drain of the MOS tube peripheral circuit and the Q6 peripheral circuit, and C9 forms an RC circuit for adjusting the resistance and capacitance values ​​to configure the MOS tube to be turned on and off, and R100 is configured to discharge the charge at the source and gate of Q6;

[0011] In the MOS tube driving circuit, when the control signal is valid, the base of Q4 receives a high-level signal, the base-emitter PN junction of Q4 is forward biased, the collector and emitter of Q4 are turned on, and Q4 works in the saturation region. At this time, the input signal is output to the ground through resistors R30, R100, R3, and Q4, forming a current path. At this time, there is a voltage difference between the source and gate of Q6, which meets the Q6 turn-on condition, Q6 is turned on, and the input signal passes through resistor R30, and Q6 outputs a "high" state;

[0012] When the control signal is invalid, the Q4 base-emitter PN junction is not biased, and Q4 works in the cut-off region. At this time, the input signal cannot form a current path through R30, R100, R3, and Q4. There is no voltage difference across R100, and there is no voltage difference between the source and gate of Q6, so it will not be turned on. At this time, the input signal cannot be output, and the circuit is in the "open" state;

[0013] The current limiting output circuit has a sampling resistor R30 in the output loop. When the line current reaches the limit value, the sampling resistor voltage drop biases the emitter-base PN junction of the transistor Q10, and the source-gate voltage difference of the MOS tube Q6 is equal to the emitter-collector voltage of Q10. The emitter-collector voltage of Q10 begins to decrease, and the source-gate voltage of Q6 also decreases. According to the output characteristics of the MOS tube, Q6 enters the constant current region, the source-drain voltage difference remains unchanged, and the current passing through Q6 decreases as the source-gate voltage decreases. When the current decreases below the threshold value, Q10 tends to the cut-off region, the emitter-collector voltage of Q10 increases, and the source-gate voltage of Q6 also increases;

[0014] The alarm circuit has a sampling resistor R30 in the output loop. When the line current causes the sampling resistor to drop and bias the emitter-base PN junction of the transistor Q5, the voltage of the emitter-collector of Q5 begins to drop. The input signal is grounded through Q5, R104, R99, and R96 to form a loop, and the AA5 signal changes from a low level to a high level, indicating an alarm.

[0015] In the output prompt circuit, when the input signal is output through the Q6 MOS tube, the AA6 signal changes from a low level to a high level after being divided by the R101, R110, and RA2 resistors, indicating that the input signal has been output.

[0016] Optionally, when the line current reaches a limit, the voltage drop of R30 is used to forward bias the emitter-base PN junctions of Q5 and Q10.

[0017] Aiming at the problem that the high / open output circuit of traditional airborne products is incomplete in function, a high / open output circuit applied to airborne products is provided. The present invention comprises: a MOS tube driving circuit, a MOS tube peripheral circuit, a current limiting output circuit, an alarm circuit, and an output prompt circuit. The circuit features that the high / open signal output can be controlled and the line current can be monitored to achieve current limiting output. At the same time, the current limit value can be flexibly set, and the circuit scale is small. The present invention has high reliability, good circuit portability, and typical promotion value. The entire circuit design, calculation process, and control logic method of the present invention meet the forward design requirements of aviation airborne products. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 FIG. 4 is a schematic diagram of a high / open output circuit according to the present invention. DETAILED DESCRIPTION

[0019] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0020] According to one aspect of an embodiment of the present invention, a high-open output circuit is provided, including a MOS tube driving circuit, a MOS tube peripheral circuit, a current limiting output circuit, an alarm circuit, and an output prompt circuit, wherein the circuit includes resistors R30, R99, R96, R104, R98, R105, R103, R100, R3, R14, R94, RA1, R101, R110, RA2, capacitors C32, C9, CA1, transistors Q5, Q10, Q4, Q6, a first end of R96 is connected to a first end of R99, and a first end of R96 is connected to an alarm circuit output signal. AA5 is connected, the second end of R96 is connected in parallel with the second end of C32 and connected to GND, the second end of R99 is connected to the second end of R99 and the first end of R104, and the second end of R99 is connected to the first end of C32, the second end of R104 is connected to the collector of Q5, the emitter of Q5 is connected to the high open circuit input signal, the base of Q5 is connected to the first end of R98, the second end of R98 is connected to the first end of R105, and the second end of R98 is connected to the first end of R103, the second end of R105 is connected to the base of Q10, the second end of R103 is connected to the second end of R30, and the second end of R103 is connected to Q6 The source is connected, the emitter of Q10 is connected to the high open circuit input signal, and the emitter of Q10 is connected to the first end of R30, and the emitter of Q10 is connected to the emitter of Q5, the collector of Q10 is connected to the second end of R100, and the collector of Q10 is connected to the gate of Q6, and the collector of Q10 is connected to the first end of C9, and the collector of Q10 is connected to the first end of R3, the first end of R30 is connected to the high open circuit input signal, the drain of Q6 is connected to the second end of RA1, the drain of Q6 is connected to the first end of R101, and the drain of Q6 is connected to the high open circuit output signal, and the first end of C9 is connected to the gate of Q6. The two ends are connected to the first end of RA1, the second end of R3 is connected to the collector of Q4, the emitter of Q4 is connected to the second end of R94 and connected to GND, the base of Q4 is connected to the first end of R94, the first end of R14 is connected to the high open circuit control signal, the first end of R101 is connected to the second end of RA1, the second end of R101 is connected to the second end of R101 and the first end of R110, and the second end of R101 is connected to the first end of CA1, the second end of R110 is connected to the first end of RA2, and the second end of R110 is connected to the output prompt signal AA6, and the second end of CA1 is connected to the second end of RA2 and connected to GND.

[0021] Furthermore, a diode D61 is added to protect the control signal output circuit. The base of Q4 is connected to the cathode of D61, and the anode of D61 is connected to the second end of R14. The reverse withstand voltage of D61 is +75V. Under the working temperature of +25℃, the high open input signal is prevented from affecting the control signal output circuit.

[0022] Furthermore, a diode D60 is added to provide clamping protection for the AA5 signal receiving circuit. The second end of R99 is connected to the anode of D60, and the cathode of D60 is connected to the +5V power supply. The maximum forward voltage drop of D60 (operating temperature +25°C) is +1.25V. According to theoretical analysis, when voltage clamping occurs (operating temperature +25°C), the maximum voltage at the second end of R99 is +6.25V, which can protect the AA5 signal receiving circuit.

[0023] Furthermore, a diode D7 is added to provide clamping protection for the AA6 signal receiving circuit. The second end of R101 is connected to the anode of D7, and the cathode of D7 is connected to the +5V power supply. The maximum forward voltage drop of D7 (operating temperature +25°C) is +1.25V. According to theoretical analysis, when voltage clamping occurs (operating temperature +25°C), the maximum voltage of the first end of R110 is +6.25V, which can protect the AA6 signal receiving circuit.

[0024] Furthermore, a voltage stabilizing diode D11 is configured to protect the gate-source of the MOS tube, the collector of Q10 is connected to the anode of D11, the cathode of D11 is connected to the second end of R30, the cathode of D11 is connected to the second end of R103, the cathode of D11 is connected to the first end of R100, and the cathode of D11 is connected to the source of Q6. This prevents overvoltage breakdown at both the gate and source levels. The gate-source voltage limit parameter of the Q6 MOS tube is ±15V, so when selecting the D11 voltage stabilizing tube, the stable voltage value of D11 shall not exceed +15V.

[0025] Furthermore, the input signal voltage is +28V.

[0026] According to another aspect of an embodiment of the present invention, a method for operating a high-open output circuit is also provided, based on any circuit, a MOS tube peripheral circuit, and a Q6 peripheral circuit. RA1 is configured between the gate and drain of the Q6 peripheral circuit, and C9 forms an RC circuit for adjusting the resistance and capacitance values ​​to configure the MOS tube to be turned on and off. R100 is configured to discharge the charges at the source and gate of Q6 to prevent Q6 from malfunctioning.

[0027] MOS tube driving circuit, when the control signal is valid, the base of Q4 receives a high-level signal, the base-emitter PN junction of Q4 is forward biased, the collector and emitter of Q4 are turned on, and Q4 works in the saturation region. At this time, the input signal is output to the ground through resistors R30, R100, R3, and Q4, forming a current path. At this time, there is a voltage difference between the source and gate of Q6, which meets the Q6 turn-on condition, Q6 is turned on, the input signal passes through resistor R30, and Q6 outputs a "high" state;

[0028] When the control signal is invalid, the Q4 base-emitter PN junction is not biased, and Q4 works in the cut-off region. At this time, the input signal cannot form a current path through R30, R100, R3, and Q4. There is no voltage difference across R100, and there is no voltage difference between the source and gate of Q6, so it will not be turned on. At this time, the input signal cannot be output, and the circuit is in the "open" state;

[0029] The current limiting output circuit has a sampling resistor R30 set in the output loop. When the line current reaches the limit, the sampling resistor voltage drop biases the emitter-base PN junction of the transistor Q10, and the voltage difference between the source-gate of the MOS tube Q6 and the emitter-collector of Q10 is equal. The emitter-collector voltage of Q10 begins to decrease, and the source-gate voltage of Q6 also decreases. According to the output characteristics of the MOS tube, Q6 enters the constant current region, the source-drain voltage difference remains unchanged, and the current through Q6 decreases as the source-gate voltage decreases. When the current decreases below the threshold value, Q10 tends to the cut-off region, the emitter-collector voltage of Q10 increases, and the source-gate voltage of Q6 also increases; finally, a dynamic balance is formed, and Q6 is in a constant current state and is not affected by the output load.

[0030] Alarm circuit, the output loop is set with sampling resistor R30. When the line current causes the sampling resistor voltage drop to bias the emitter-base PN junction of transistor Q5, the voltage of Q5 emitter-collector begins to drop. The input signal is grounded through Q5, R104, R99, and R96 to form a loop. The AA5 signal changes from low level to high level, indicating an alarm.

[0031] Output prompt circuit, when the input signal is output through the Q6 MOS tube, after being divided by R101, R110, and RA2 resistors, the AA6 signal changes from a low level to a high level, indicating that the input signal has been output.

[0032] Furthermore, when the line current reaches the limit, the voltage drop of R30 is required to make the emitter-base PN junction of Q5 and Q10 forward biased. Therefore, the resistance value of R30 can be flexibly configured according to the required current limit to adjust the current limit point.

[0033] Example 1

[0034] The circuit of the present invention includes a MOS tube driving circuit, a MOS tube peripheral circuit, a current limiting output circuit, an alarm circuit, and an output prompt circuit. The circuit includes resistors R30, R99, R96, R104, R98, R105, R103, R100, R3, R14, R94, RA1, R101, R110, RA2, capacitors C32, C9, CA1, transistors Q5, Q10, Q4, Q6, a voltage stabilizing diode D11, and diodes D61, D7, and D60. The first end of R96 is connected to the first end of R99, and the first end of R96 is connected to the alarm circuit output signal AA5, and the second end of R96 is connected to the second end of C32 to GND. The second end of R99 is connected to the anode of D60, and the second end of R99 is connected to the first end of R104, and the second end of R99 is connected to the first end of C32. The cathode of D60 is connected to a +5V power supply. The second end of R104 is connected to the collector of Q5, the emitter of Q5 is connected to the high open circuit input signal, and the base of Q5 is connected to the first end of R98. The second end of R98 is connected to the first end of R105, and the second end of R98 is connected to the first end of R103, the second end of R105 is connected to the base of Q10, the second end of R103 is connected to the second end of R30, and the second end of R103 is connected to the source of Q6, the emitter of Q10 is connected to the high open circuit input signal, and the emitter of Q10 is connected to the first end of R30, and the emitter of Q10 is connected to the emitter of Q5. The collector of Q10 is connected to the anode of D11, and the collector of Q10 is connected to the second end of R100, and the collector of Q10 is connected to the gate of Q6, and the collector of Q10 is connected to the first end of C9, and the collector of Q10 is connected to the first end of R3, and the first end of R30 is connected to the high open circuit input signal. The cathode of D11 is connected to the second end of R30, and the cathode of D11 is connected to the second end of R103, and the cathode of D11 is connected to the first end of R100, and the cathode of D11 is connected to the source of Q6, the drain of Q6 is connected to the second end of RA1, the drain of Q6 is connected to the first end of R101, and the drain of Q6 is connected to the high open circuit output signal. The second end of C9 is connected to the first end of RA1. The second end of R3 is connected to the collector of Q4, the emitter of Q4 is connected to the second end of R94 connected to GND, the base of Q4 is connected to the first end of R94, and the base of Q4 is connected to the cathode of D61. The anode of D61 is connected to the second end of R14, and the first end of R14 is connected to the high open circuit control signal. The first end of R101 is connected to the second end of RA1, the second end of R101 is connected to the anode of D7, and the second end of R101 is connected to the first end of R110, and the second end of R101 is connected to the first end of CA1. The cathode of D7 is connected to the +5V power supply, the second end of R110 is connected to the first end of RA2, and the second end of R110 is connected to the output prompt signal AA6. The second end of CA1 is connected to the second end of RA2 and connected to GND.

[0035] MOS tube peripheral circuit, Q6 peripheral circuit gate-drain is configured with RA1 and C9 to form an RC circuit, which is used to adjust the resistance and capacitance values ​​to configure the MOS tube on and off time. R100 is configured to discharge the charge of Q6 source and gate to prevent Q6 from malfunctioning.

[0036] MOS tube drive circuit, when the control signal is valid, Q4 base receives a high-level signal, Q4 base-emitter PN junction is forward biased, Q4 collector and emitter are turned on, and Q4 works in the saturation region. At this time, the input signal is output to the ground through resistors R30, R100, R3, and Q4, forming a current path. At this time, there is a voltage difference between the source and gate of Q6, which meets the Q6 turn-on condition, Q6 is turned on, and the input signal is output through resistor R30 and Q6.

[0037] When the control signal is invalid, the Q4 base-emitter PN junction is not biased, and Q4 works in the cut-off region. At this time, the input signal cannot form a current path through R30, R100, R3, and Q4. There is no voltage difference across R100, and there is no voltage difference between the source and gate of Q6, so it will not be turned on. At this time, the input signal cannot be output.

[0038] That is, when the control signal is valid, the circuit outputs the "high" state. When the control signal is invalid, the circuit outputs the "on" state.

[0039] The current limiting output circuit has a sampling resistor R30 set in the output loop. When the line current reaches the limit, the sampling resistor voltage drop biases the emitter-base PN junction of the transistor Q10. The voltage difference between the source-gate of the MOS tube Q6 and the emitter-collector of Q10 is equal, the emitter-collector voltage of Q10 begins to decrease, and the source-gate voltage of Q6 also decreases. According to the output characteristics of the MOS tube, Q6 enters the constant current region, the source-drain voltage difference remains unchanged, and the current through Q6 decreases as the source-gate voltage decreases. When the current decreases below the threshold value, Q10 tends to the cut-off region, the emitter-collector voltage of Q10 increases, and the source-gate voltage of Q6 also increases, eventually forming a dynamic balance, and Q6 is in a constant current state, which is not affected by the output load.

[0040] The alarm circuit has a sampling resistor R30 set in the output loop. When the line current causes the sampling resistor voltage drop to bias the transistor Q5 emitter-base PN junction, the Q5 emitter-collector voltage begins to drop. The input signal is grounded through Q5, R104, R99, and R96 to form a loop, and the AA5 signal changes from a low level to a high level, indicating an alarm.

[0041] Output prompt circuit, when the input signal is output through the Q6 MOS tube, after being divided by R101, R110, and RA2 resistors, the AA6 signal changes from a low level to a high level, indicating that the input signal has been output.

[0042] The high-open output circuit is characterized in that the high-open input signal voltage is +28V.

[0043] The high-open output circuit is characterized in that when the line current reaches the limit, the voltage drop of R30 makes the emitter-base PN junction of Q5 and Q10 forward biased. Therefore, the resistance value of R30 can be flexibly configured according to the required current limit to adjust the current limit point.

[0044] The high-open output circuit is characterized in that a diode D61 is added to protect the control signal output circuit, and the reverse withstand voltage value of D61 is +75V (under the working temperature of +25°C) to prevent the high-open input signal from affecting the control signal output circuit.

[0045] The high-open output circuit is characterized in that a diode D60 is added to provide clamping protection for the circuit receiving the AA5 signal. The maximum forward voltage drop of D60 (operating temperature +25°C) is +1.25V. According to theoretical analysis, when voltage clamping occurs (operating temperature +25°C), the maximum voltage at the second end of R99 is +6.25V, which can protect the circuit receiving the AA5 signal.

[0046] The high-open output circuit is characterized in that a diode D7 is added to provide clamping protection for the circuit receiving the AA6 signal. The maximum forward voltage drop of D7 (operating temperature +25°C) is +1.25V. According to theoretical analysis, when voltage clamping occurs (operating temperature +25°C), the maximum voltage at the first terminal of R110 is +6.25V, which can protect the circuit receiving the AA6 signal.

[0047] The high-open output circuit is characterized in that a voltage regulator diode D11 is configured to protect the gate-source of the MOS tube to prevent overvoltage breakdown at both the gate and source levels. The gate-source voltage limit parameter of the Q6 MOS tube is ±15V, so when selecting the D11 voltage regulator tube, the stable voltage value of D11 shall not exceed +15V.

[0048] Example 2

[0049] like Figure 1As shown, the high / open output circuit of the present invention includes a MOS tube driving circuit, a MOS tube peripheral circuit, a current limiting output circuit, an alarm circuit, and an output prompt circuit. The circuit includes resistors R30, R99, R96, R104, R98, R105, R103, R100, R3, R14, R94, RA1, R101, R110, RA2, capacitors C32, C9, CA1, transistors Q5, Q10, Q4, Q6, a voltage regulator diode D11, and diodes D61, D7, and D60. The first end of R96 is connected to the first end of R99, and the first end of R96 is connected to the alarm circuit output signal AA5, and the second end of R96 is connected to the second end of C32 to GND. The second end of R99 is connected to the anode of D60, and the second end of R99 is connected to the first end of R104, and the second end of R99 is connected to the first end of C32. The cathode of D60 is connected to the +5V power supply. The second end of R104 is connected to the collector of Q5, the emitter of Q5 is connected to the high open circuit input signal, and the base of Q5 is connected to the first end of R98. The second end of R98 is connected to the first end of R105, and the second end of R98 is connected to the first end of R103, the second end of R105 is connected to the base of Q10, the second end of R103 is connected to the second end of R30, and the second end of R103 is connected to the source of Q6, the emitter of Q10 is connected to the high open circuit input signal, and the emitter of Q10 is connected to the first end of R30, and the emitter of Q10 is connected to the emitter of Q5. The collector of Q10 is connected to the anode of D11, and the collector of Q10 is connected to the second end of R100, and the collector of Q10 is connected to the gate of Q6, and the collector of Q10 is connected to the first end of C9, and the collector of Q10 is connected to the first end of R3, and the first end of R30 is connected to the high open circuit input signal. The cathode of D11 is connected to the second end of R30, and the cathode of D11 is connected to the second end of R103, and the cathode of D11 is connected to the first end of R100, and the cathode of D11 is connected to the source of Q6, the drain of Q6 is connected to the second end of RA1, the drain of Q6 is connected to the first end of R101, and the drain of Q6 is connected to the high open circuit output signal. The second end of C9 is connected to the first end of RA1. The second end of R3 is connected to the collector of Q4, the emitter of Q4 is connected to the second end of R94 connected to GND, the base of Q4 is connected to the first end of R94, and the base of Q4 is connected to the cathode of D61. The anode of D61 is connected to the second end of R14, and the first end of R14 is connected to the high open circuit control signal. The first end of R101 is connected to the second end of RA1, the second end of R101 is connected to the anode of D7, and the second end of R101 is connected to the first end of R110, and the second end of R101 is connected to the first end of CA1. The cathode of D7 is connected to the +5V power supply, the second end of R110 is connected to the first end of RA2, and the second end of R110 is connected to the output prompt signal AA6. The second end of CA1 is connected to the second end of RA2 and connected to GND.

[0050] MOS tube peripheral circuit, Q6 peripheral circuit gate-drain is configured with RA1 and C9 to form an RC circuit, which is used to adjust the resistance and capacitance values ​​to configure the MOS tube on and off time. R100 is configured to discharge the charge of Q6 source and gate to prevent Q6 from malfunctioning.

[0051] Circuit operation method: MOS tube drive circuit, when the control signal is valid, Q4 base receives a high-level signal, Q4 base-emitter PN junction is forward biased, Q4 collector and emitter are turned on, and Q4 works in the saturation region. At this time, the input signal is output to the ground through resistors R30, R100, R3, and Q4, forming a current path. At this time, there is a voltage difference between the source and gate of Q6, which meets the Q6 turn-on condition, Q6 is turned on, and the input signal is output through resistor R30 and Q6.

[0052] When the control signal is invalid, the Q4 base-emitter PN junction is not biased, and Q4 works in the cut-off region. At this time, the input signal cannot form a current path through R30, R100, R3, and Q4. There is no voltage difference across R100, and there is no voltage difference between the source and gate of Q6, so it will not be turned on. At this time, the input signal cannot be output.

[0053] That is, when the control signal is valid, the circuit outputs the "high" state. When the control signal is invalid, the circuit outputs the "on" state.

[0054] The current limiting output circuit has a sampling resistor R30 set in the output loop. When the line current reaches the limit, the sampling resistor voltage drop biases the emitter-base PN junction of the transistor Q10. The voltage difference between the source-gate of the MOS tube Q6 and the emitter-collector of Q10 is equal, the emitter-collector voltage of Q10 begins to decrease, and the source-gate voltage of Q6 also decreases. According to the output characteristics of the MOS tube, Q6 enters the constant current region, the source-drain voltage difference remains unchanged, and the current through Q6 decreases as the source-gate voltage decreases. When the current decreases below the threshold value, Q10 tends to the cut-off region, the emitter-collector voltage of Q10 increases, and the source-gate voltage of Q6 also increases, eventually forming a dynamic balance, and Q6 is in a constant current state, which is not affected by the output load.

[0055] The alarm circuit has a sampling resistor R30 set in the output loop. When the line current causes the sampling resistor voltage drop to bias the transistor Q5 emitter-base PN junction, the Q5 emitter-collector voltage begins to drop. The input signal is grounded through Q5, R104, R99, and R96 to form a loop, and the AA5 signal changes from a low level to a high level, indicating an alarm.

[0056] Output prompt circuit, when the input signal is output through the Q6 MOS tube, after being divided by R101, R110, and RA2 resistors, the AA6 signal changes from a low level to a high level, indicating that the input signal has been output.

[0057] The high-open input signal voltage is +28V. When the line current reaches the limit, the voltage drop of R30 makes the emitter-base PN junction of Q5 and Q10 forward biased. Therefore, the resistance value of R30 can be flexibly configured according to the required current limit to adjust the current limit point.

[0058] Diode D61 is added to protect the control signal output circuit. The reverse withstand voltage of D61 is +75V (under the working temperature of +25℃) to prevent the high open input signal from affecting the control signal output circuit.

[0059] Diode D60 is added to provide clamping protection for the circuit receiving AA5 signal. The maximum forward voltage drop of D60 (operating temperature +25℃) is +1.25V. Theoretical analysis shows that when voltage clamping occurs (operating temperature +25℃), the maximum voltage at the second end of R99 is +6.25V, which can protect the circuit receiving AA5 signal.

[0060] Add diode D7 to clamp the circuit receiving AA6 signal. The maximum forward voltage drop of D7 (operating temperature +25℃) is +1.25V. Theoretical analysis shows that when voltage clamping occurs (operating temperature +25℃), the maximum voltage at the first end of R110 is +6.25V, which can protect the circuit receiving AA6 signal.

[0061] The voltage stabilizing diode D11 is configured to protect the gate-source of the MOS tube to prevent overvoltage breakdown at both the gate and source. The gate-source voltage limit parameter of the Q6 MOS tube is ±15V, so when selecting the D11 voltage stabilizing diode, the D11 stable voltage value must not exceed +15V.

[0062] The above is only a specific embodiment of the present invention, and the present invention is described in detail. The unexplained part is a conventional technology. However, the protection scope of the present invention is not limited to this. Any changes or substitutions that can be easily thought of by any technician familiar with the technical field within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. The protection scope of the present invention shall be based on the protection scope of the claims.

Claims

1. A high-open output circuit, characterized in that: It includes a MOS tube driving circuit, a MOS tube peripheral circuit, a current limiting output circuit, an alarm circuit, and an output prompt circuit, including resistors R30, R99, R96, R104, R98, R105, R103, R100, R3, R14, R94, RA1, R101, R110, RA2, capacitors C32, C9, CA1, transistors Q5, Q10, Q4, Q6, the first end of R96 is connected to the first end of R99, and the first end of R96 is connected to the alarm circuit output signal AA5, and the second end of R96 is connected to the second end of C32 Connect in parallel to GND, the second end of R99 is connected to the second end of R99 and the first end of R104, and the second end of R99 is connected to the first end of C32, the second end of R104 is connected to the collector of Q5, the emitter of Q5 is connected to the high open circuit input signal, the base of Q5 is connected to the first end of R98, the second end of R98 is connected to the first end of R105, and the second end of R98 is connected to the first end of R103, the second end of R105 is connected to the base of Q10, the second end of R103 is connected to the second end of R30, and the second end of R103 is connected to the source of Q6, and the emitter of Q10 is connected to the high The open circuit input signal is connected, and the emitter of Q10 is connected to the first end of R30, and the emitter of Q10 is connected to the emitter of Q5, and the collector of Q10 is connected to the second end of R100, and the collector of Q10 is connected to the gate of Q6, and the collector of Q10 is connected to the first end of C9, and the collector of Q10 is connected to the first end of R3, and the first end of R30 is connected to the high open circuit input signal, the drain of Q6 is connected to the second end of RA1, and the drain of Q6 is connected to the first end of R101, and the drain of Q6 is connected to the high open circuit output signal, and the second end of C9 is connected to RA1 The first end is connected, the second end of R3 is connected to the collector of Q4, the emitter of Q4 is connected to the second end of R94 and connected to GND, the base of Q4 is connected to the first end of R94, the first end of R14 is connected to the high open circuit control signal, the first end of R101 is connected to the second end of RA1, the second end of R101 is connected to the second end of R101 and the first end of R110, and the second end of R101 is connected to the first end of CA1, the second end of R110 is connected to the first end of RA2, and the second end of R110 is connected to the output prompt signal AA6, and the second end of CA1 and the second end of RA2 are connected to GND.

2. The circuit according to claim 1, characterized in that Add diode D61 to protect the control signal output circuit, Q4 base is connected to D61 cathode, D61 anode is connected to the second end of R14, and D61 reverse withstand voltage value is +75V.

3. The circuit according to claim 1, characterized in that: Diode D60 is added to provide clamping protection for the circuit receiving AA5 signal. The second end of R99 is connected to the anode of D60, and the cathode of D60 is connected to the +5V power supply.

4. The circuit according to claim 1, characterized in that Add diode D7 to clamp the circuit receiving AA6 signal, connect the second end of R101 to the anode of D7, and connect the cathode of D7 to the +5V power supply.

5. The circuit according to claim 1, characterized in that: A voltage zener diode D11 is configured to protect the gate-source of the MOS tube, the collector of Q10 is connected to the anode of D11, the cathode of D11 is connected to the second end of R30, the cathode of D11 is connected to the second end of R103, the cathode of D11 is connected to the first end of R100, and the cathode of D11 is connected to the source of Q6.

6. The circuit according to claim 1, characterized in that The input signal voltage is +28V.

7. A method for operating a high-open output circuit, based on any circuit as claimed in claim 1-6, characterized in that: The MOS tube peripheral circuit, Q6 peripheral circuit, is configured with RA1 between the gate and drain, C9 forms an RC circuit, which is used to adjust the resistance and capacitance values ​​to configure the MOS tube to be turned on and off, and R100 is configured to discharge the charge at the source and gate of Q6; In the MOS tube driving circuit, when the control signal is valid, the base of Q4 receives a high-level signal, the base-emitter PN junction of Q4 is forward biased, the collector and emitter of Q4 are connected, and Q4 works in the saturation region. At this time, the input signal is output to the ground through resistors R30, R100, R3, and Q4, forming a current path. At this time, there is a voltage difference between the source and gate of Q6, which meets the Q6 on condition. Q6 is turned on, and the input signal passes through the resistor R30, and Q6 outputs the "high" state; When the control signal is invalid, the Q4 base-emitter PN junction is not biased, and Q4 works in the cut-off region. At this time, the input signal cannot form a current path through R30, R100, R3, and Q4. There is no voltage difference across R100, and there is no voltage difference between the source and gate of Q6, so it will not be turned on. At this time, the input signal cannot be output, and the circuit is in the "open" state; The current limiting output circuit has a sampling resistor R30 in the output loop. When the line current reaches the limit value, the sampling resistor voltage drop biases the emitter-base PN junction of the transistor Q10, and the source-gate voltage difference of the MOS tube Q6 is equal to the emitter-collector voltage of Q10. The emitter-collector voltage of Q10 begins to decrease, and the source-gate voltage of Q6 also decreases. According to the output characteristics of the MOS tube, Q6 enters the constant current region, the source-drain voltage difference remains unchanged, and the current passing through Q6 decreases as the source-gate voltage decreases. When the current decreases below the threshold value, Q10 tends to the cut-off region, the emitter-collector voltage of Q10 increases, and the source-gate voltage of Q6 also increases; The alarm circuit has a sampling resistor R30 in the output loop. When the line current causes the sampling resistor to drop and bias the emitter-base PN junction of the transistor Q5, the voltage of the emitter-collector of Q5 begins to drop. The input signal is grounded through Q5, R104, R99, and R96 to form a loop, and the AA5 signal changes from a low level to a high level, indicating an alarm. In the output prompt circuit, when the input signal is output through the Q6 MOS tube, the AA6 signal changes from a low level to a high level after being divided by the R101, R110, and RA2 resistors, indicating that the input signal has been output.

8. The method according to claim 1, characterized in that: When the line current reaches the limit, the voltage drop of R30 makes the emitter-base PN junction of Q5 and Q10 forward biased.

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