A digital-to-analog conversion circuit, a digital-to-analog converter, and an electronic device

Abstract

The application provides a digital-to-analog conversion circuit, a digital-to-analog converter and an electronic device, and relates to the technical field of integrated circuits.The application comprises at least one conversion unit and a plurality of buffer units; the at least one conversion unit is connected with the plurality of buffer units; the at least one conversion unit is configured to receive a digital signal, determine a target buffer unit to be gated according to the digital signal, and convert the digital signal into a corresponding analog signal; and the plurality of buffer units are configured to transmit the analog signal to a subsequent circuit. The digital-to-analog conversion circuit of the application adopts a resistance string multiplexing mode, the key nodes between the resistance strings are connected with each other to ensure that the analog output quantities of the resistance strings are basically consistent, the nonlinearity of the circuit is reduced, and high conversion precision is achieved. The resistance string multiplexing can also effectively reduce the number of resistance strings, reduce the area cost, reduce the complexity of the layout structure, and meet the digital-to-analog conversion precision requirement.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and more particularly to a digital-to-analog conversion circuit, a digital-to-analog converter, and an electronic device. Background Technology

[0002] Digital signals are typically single-channel, and the range of the output analog signal is insufficient to meet the requirements of subsequent circuits, making it difficult to drive the load of those circuits. The most common structure of traditional digital-to-analog converters (DACs) is multi-channel, requiring multiple DAC circuits composed of multiple resistor strings and multiple clocks. The digital logic and clock settings of these circuits are complex.

[0003] Currently, most traditional digital-to-analog converter (DAC) architectures use a single resistor string as a single DAC circuit, driving a buffer, with each channel operating independently. The buffer uses negative feedback, following the analog output of the DAC. However, the large number of resistor strings not only results in a complex layout and significant area overhead, but also leads to unequal voltages between the nodes, causing inconsistent analog outputs from the DAC, sometimes with significant differences. This results in lower DAC accuracy and fails to adequately meet the requirements of digital-to-analog conversion. Summary of the Invention

[0004] In view of the above problems, the present invention is proposed to provide a digital-to-analog conversion circuit, a digital-to-analog converter, and an electronic device that solves or partially solves the above problems.

[0005] A first aspect of the present invention provides a digital-to-analog converter circuit, the digital-to-analog converter circuit comprising: at least one conversion unit and a plurality of buffer units;

[0006] At least one of the conversion units is connected to a plurality of the buffer units;

[0007] At least one of the conversion units is configured to receive a digital signal, determine a selected target buffer unit based on the digital signal, convert the digital signal into a corresponding analog signal, and transmit the analog signal to the target buffer unit.

[0008] Multiple buffer units are configured to transmit the analog signal to subsequent circuitry;

[0009] One of the conversion units is connected to at least two of the buffer units;

[0010] The number of input registers connected to a conversion unit is equal to the number of cache units connected to it.

[0011] Optionally, the conversion unit includes: multiple sets of gating switches and multiple unit resistors, wherein each set of gating switches includes: row switches and column switches;

[0012] The number of groups of gating switches is the same as the number of buffer units, and one group of gating switches is connected to one buffer unit; multiple unit resistors are connected in series in a serpentine manner between the reference voltage terminal and the low potential terminal to form a resistor string, with the first row being the row connected to the reference voltage terminal and the last row being the row connected to the low potential terminal.

[0013] Each row of the resistor string is provided with multiple row switches, and the number of row switches in each row is the same as the number of connected buffer units.

[0014] Each of the multiple unit resistors has its two ends connected to multiple column switches. The number of column switches connected to each end of the unit resistor is the same as the number of row switches in its row. Among the multiple column switches, one end of the first column switch is connected to the unit resistor, and the other end is connected to one end of the first row switch in the row where the unit resistor is located. The other end of the first row switch is connected to a buffer unit. One end of the second column switch is connected to the unit resistor, and the other end is connected to one end of the second row switch in the row where the unit resistor is located. The other end of the second row switch is connected to another buffer unit.

[0015] Optionally, the row switch is controlled by a row selection signal; the column switch is controlled by a column selection signal.

[0016] The row selection signal and the column selection signal are determined by the number of bits in the digital signal;

[0017] When the number of bits of the digital signal is N=M+L, the row selection signal is the high M bits of the number of bits N, and the column selection signal is the low L bits of the number of bits N.

[0018] Optionally, in a resistor string structure formed by connecting multiple unit resistors in a serpentine manner, the number of unit resistors is determined by the number of bits N, and the number of rows in the resistor string structure is determined by M in the number of bits N;

[0019] The total number of unit resistors is 2. N The number of rows is 2 M .

[0020] Optionally, when there are two or more conversion units, each conversion unit has a key node in each row of the resistor string structure. The key node is the end of the last unit resistor in each row of series-connected unit resistors, and the end of the last unit resistor is connected to the beginning of the first unit resistor in the next row.

[0021] Optionally, when M=6, the number of rows is 64, then two or more conversion units are connected through 64 key nodes, and key nodes corresponding to the same number of rows are connected, while key nodes corresponding to different numbers of rows are not connected.

[0022] Optionally, the digital-to-analog converter circuit further includes: a plurality of selection switches and a plurality of the input register units;

[0023] One of the selection switches is connected to one of the input register units;

[0024] The plurality of input register units are connected to at least one of the conversion units;

[0025] Multiple selection switches are configured to be turned on or off according to a selection signal, and when turned on, transmit the digital signal to the corresponding connected input register unit;

[0026] Multiple input register units are configured to send the digital signal to the corresponding target conversion unit;

[0027] The number of the plurality of input register units is equal to the number of the plurality of buffer units, and the number of input register units connected to one conversion unit is equal to the number of buffer units connected to it;

[0028] When one of the conversion units is connected to the first input register unit and the second input register unit, the conversion unit receives a first digital signal from the first input register unit or a second digital signal from the second input register unit, wherein the first input register unit and the second input register unit decide whether to send a digital signal to the conversion unit according to the selection signal;

[0029] When the conversion unit receives the first digital signal, it transmits an analog signal corresponding to the first digital signal to the first buffer unit connected to it through a set of selection switches;

[0030] When the conversion unit receives the second digital signal, it transmits an analog signal corresponding to the second digital signal to the second buffer unit connected to it through another set of selection switches.

[0031] Optionally, when the number of bits N is 12 bits, the high M bits are 6 bits, the low L bits are 6 bits, then the row selection signal is 6 bits, and the column selection signal is 6 bits.

[0032] A second aspect of the present invention provides a digital-to-analog converter, the digital-to-analog converter comprising: a digital-to-analog conversion circuit as described in any of the first aspects.

[0033] A third aspect of the present invention provides an electronic device, the electronic device including a digital-to-analog converter as described in the second aspect.

[0034] The digital-to-analog converter circuit provided by this invention includes: at least one conversion unit and multiple buffer units; the at least one conversion unit is connected to the multiple buffer units; the at least one conversion unit is configured to receive a digital signal, determine a target buffer unit based on the digital signal, convert the digital signal into a corresponding analog signal, and transmit the analog signal to the target buffer unit; the multiple buffer units are configured to transmit analog signals to subsequent circuits. Here, one conversion unit is connected to at least two buffer units; the number of input register units connected to one conversion unit is equal to the number of buffer units connected to it.

[0035] The digital-to-analog converter circuit proposed in this invention creatively proposes a multiplexed structure for the conversion unit. Instead of using a single conversion unit for each path, multiple paths share a single conversion unit, and each conversion unit is connected to at least two or more buffers. The buffers are selected for conduction via a digital signal. The conversion unit structure uses resistor strings to connect the buffers, which have strong load driving capabilities. Key nodes in the resistor strings are interconnected, ensuring that the analog output (i.e., analog voltage value) of the resistor strings is essentially consistent. This not only reduces the nonlinearity of the circuit to a certain extent but also achieves a digital-to-analog converter unit with good accuracy. Furthermore, it reduces the number of resistor strings, decreases area overhead, and lowers the complexity of the layout structure, effectively meeting the requirements of digital-to-analog conversion and possessing high practical value. Attached Figure Description

[0036] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0037] Figure 1 This is a schematic diagram of a traditional 8-channel digital-to-analog converter circuit.

[0038] Figure 2 This is an exemplary structural diagram of a preferred multi-channel digital-to-analog converter circuit in an embodiment of the present invention; it is also an exemplary modular schematic diagram of a digital-to-analog converter circuit.

[0039] Figure 3 This is a schematic diagram of a preferred embodiment of the present invention, showing one conversion unit, two sets of selection switches, and two buffer units. Detailed Implementation

[0040] To make the above-mentioned objects, features, and advantages of the present invention more apparent and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present invention, and are only some, not all, embodiments of the present invention, and are not intended to limit the present invention.

[0041] The inventors discovered that most traditional digital-to-analog converter (DAC) circuit architectures currently use one DAC unit to drive one buffer, with each channel operating independently. (See reference...) Figure 1 The diagram shows a traditional 8-channel digital-to-analog converter unit. Input shift register and control logic ( Figure 1 The input signal is simultaneously fed into 8 channels via the input switch register and control logic. Each of the 8 channels utilizes its own input register. Figure 1 The INPUT REGISTER1~INPUT REGISTER8 units store and forward digital quantities and control logic to their respective digital-to-analog conversion units (DACs). Figure 1 (DAC1~DAC8) Each digital-to-analog converter (DAC1~DAC8) performs digital-to-analog conversion and outputs its own analog output (generally the voltage value corresponding to the digital value) to its corresponding buffer. Figure 1 (Middle BUFFER1~BUFFER8).

[0042] The reason for using a buffer is that it employs negative feedback, allowing it to follow the analog output of the digital-to-analog converter (DAC) and providing good drive capability through unity negative feedback. However, further research by the inventors revealed that this architecture involves a large number of resistor strings, with each path requiring a separate string. This not only results in a complex layout (referring to the integrated circuit layout) and significant area overhead, but also necessitates multiple clocks for synchronization of the timing logic. Furthermore, because each DAC receives its own digital signal, the analog outputs of the various DACs are not entirely consistent due to their individual characteristics, sometimes differing considerably, thus failing to adequately meet the requirements of digital-to-analog conversion.

[0043] Based on the above problems, the inventors have creatively proposed a digital-to-analog conversion circuit, a digital-to-analog converter, and an electronic device according to the present invention. The technical solution proposed in this invention will be explained and described in detail below.

[0044] The digital-to-analog converter circuit of this invention includes at least one conversion unit and multiple buffer units. The at least one conversion unit is connected to the multiple buffer units.

[0045] At least one conversion unit is configured to receive a digital signal, determine the target buffer unit to be selected based on the digital signal, convert the digital signal into a corresponding analog signal, and transmit the analog signal to the target buffer unit; multiple buffer units are configured to transmit analog signals to subsequent circuits. In this configuration, one conversion unit is connected to at least two buffer units; the number of input register units connected to a conversion unit is equal to the number of buffer units it is connected to.

[0046] The conversion unit includes multiple sets of gating switches and multiple unit resistors. Each set of gating switches includes a row switch and a column switch. The number of gating switch sets is the same as the number of buffer units, and each set of gating switches is connected to one buffer unit. That is, multiple sets of gating switches share a single resistor string.

[0047] Multiple unit resistors are connected in series in a serpentine pattern between the reference voltage terminal and the low potential terminal to form a resistor string. The first row is defined as the row connected to the reference voltage terminal, and the last row as the row connected to the low potential terminal. In this serpentine resistor string, the number of row switches in each row is the same as the number of connected buffer units. That is, when one resistor string is connected to two sets of selector switches and two buffer units, assuming there are 64 rows in the resistor string, each of the 64 rows has two row switches. For example, one resistor string connects two sets of selector switches and two buffer units, and two resistor strings connect a total of four sets of selector switches and four buffer units. Theoretically, one resistor string can be connected to three or more buffer units (and similarly, three or more sets of selector switches). However, due to limitations in the manufacturing process of physical integrated circuits, such as layout structure, connecting one resistor string to a larger number of buffer units, such as four or more, can lead to a complex layout and a larger footprint. After repeated testing and verification by the inventors, the structure of connecting one resistor string with two buffer units is the optimal choice in terms of layout. In the foreseeable future, when integrated circuit manufacturing processes break through existing technologies and disrupt current layout design methods, the optimal choice may surpass this current optimal structure of connecting one resistor string with two buffer units, and physically achieve a structure with one resistor string connected with four or more buffer units and a simple layout.

[0048] Each conversion unit has the same structure, with one preferred structure including multiple sets of gating switches and multiple unit resistors. Each set of gating switches includes row switches and column switches. For example, if one conversion unit is connected to two buffer units, then there are two sets of gating switches.

[0049] Each of the multiple unit resistors has its two ends connected to multiple column switches. The number of column switches connected to each end of the unit resistor is the same as the number of row switches in its row. Among the multiple column switches, one end of the first column switch is connected to the unit resistor, and the other end is connected to one end of the first row switch in the row where the unit resistor is located. The other end of the first row switch is connected to a buffer unit. One end of the second column switch is connected to the unit resistor, and the other end is connected to one end of the second row switch in the row where the unit resistor is located. The other end of the second row switch is connected to another buffer unit. For example, when one conversion unit is connected to two buffer units (defined as buffer units #1 and #2), assuming the resistor string has 64 rows and each row has two row switches (defined as row switches #1 and #2), then each unit resistor is connected to two column switches at both ends. One end of each of these two column switches is connected to the unit resistor, and the other end of one of the column switches is connected to one end of row switch #1 of the two row switches in the row containing the unit resistor. The other end of row switch #1 is connected to buffer unit #1 of the two buffer units. The other end of the other column switch is connected to one end of row switch #2 of the two row switches in the row containing the unit resistor. The other end of row switch #2 is connected to buffer unit #2 of the two buffer units.

[0050] For cases with two or more conversion units, each conversion unit has a key node in each row of its resistor string structure. This key node is the end of the last unit resistor in each row, and this end is connected to the beginning of the first unit resistor in the next row. For example, with four conversion units, each with a 64-row resistor string structure, there are 64 key nodes. The first key node is located at the end of the last unit resistor in the first row, and this end is connected to the beginning of the first unit resistor in the second row. The second key node is located at the end of the last unit resistor in the second row, and this end is connected to the beginning of the first unit resistor in the third row, and so on. Thus, the first key node of each of the four conversion units is connected, and their second key nodes are also connected. The first key node cannot be connected to any other key node in any of the other conversion units. This ensures that the value of the analog signal output by any conversion unit based on the digital signal is equal to the value of the analog signal output by any other conversion unit.

[0051] To better understand the structure of the above conversion unit, refer to... Figure 2 The diagram shows an exemplary structure of a preferred multi-channel digital-to-analog converter circuit, with reference to... Figure 3 The diagram shows an exemplary structure of a preferred conversion unit, two sets of selector switches, and two buffer units. Figure 2 In this context, X represents X channels, corresponding to X input register units ( Figure 3 Chinese and Israeli INPUT REGISTER1, INPUT REGISTER2, INPUT REGISTER3,...INPUT REGISTER X-2 INPUTREGISTER X-1 INPUT REGISTER X (represented), X buffer units ( Figure 2 Chinese BUFFER1, BUFFER2, BUFFER3,...BUFFER X-2 BUFFER X-1 BUFFER X (Representation). Assuming that both INPUT REGISTER1 and INPUT REGISTER2 are connected to an N-bit resistor string 1, then BUFFER1 receives the analog signal corresponding to the digital signal of INPUT REGISTER1, and BUFFER2 receives the analog signal corresponding to the digital signal of INPUT REGISTER2.

[0052] Each input register is connected to a selection switch. Figure 3 In the table, SELECT[1], SELECT[2], SELECT[3], ..., SELECT[X-2], SELECT[X-1], SELECT[X] represent selection switches, selection signals, and N-bit digital signals ( Figure 3 The function `S ELECT[X] + INPUT(N)` determines which selector switch is turned on based on the selection signal. Once the selector switch is turned on, the N-bit digital signal is transmitted to its corresponding input register. For example, after the first selector switch is turned on, the N-bit digital signal is transmitted to the first input register `INPUT REGISTER1`. Generally, the input N-bit digital signal is a serial signal, which becomes a parallel signal `D1[N:1]` after passing through `INPUT REGISTER1`. This parallel signal `D1[N:1]` serves as the control signal for the selector switch, controlling the corresponding selector switch. Figure 2 In this circuit, MUX represents a gating switch. The corresponding gating switch controls an N-bit resistor string of 1 to convert the N-bit digital signal output from INPUT REGISTER1 into a corresponding analog signal and transmit it to BUFFER1. The output of BUFFER1 serves as the output V of a conversion unit. DAC1 It is transmitted to the subsequent circuit.

[0053] Figure 3 The example in the text uses the resistor string of conversion unit 1 (i.e., the corresponding...) Figure 2Taking an N-bit resistor string structure as an example, and combining its row and column switches, the connection relationship between it and two sets of selectors and two buffer units BUFFER1 and BUFFER2 is shown. In the resistor string structure formed by multiple unit resistors connected in a serpentine manner, the number of unit resistors is determined by the number of bits N, and the number of rows in the resistor string structure is determined by M in the number of bits N; the total number of unit resistors is 2. N The number of rows is 2 M That is, N = M + L, where the row selection signal is the high M bits of N, and the column selection signal is the low L bits of N. N The unit resistances are evenly distributed across 2 M Line up.

[0054] The resistors are connected in a serpentine pattern between the reference voltage terminal VREF and the low potential terminal. Figure 3 (The grounding symbol is used to represent the area between them). Figure 3 For the sake of simplicity, the illustration shows an example of 4 rows, each with 2 row switches. Figure 3 The example in the text identifies two row switches X1<2 corresponding to the row. M >、X2<2 M >、X1<2 M -1>、X2<2 M -1>, X1<2>, X2<2>, X1<1>, X2<1>).

[0055] Similarly, an example of four columns of resistors is shown, taking the first unit resistor R1 as an example: each end of the unit resistor R1 is connected to two column switches, for a total of four column switches: 1#, 2#, 3#, and 4#. One end of each column switch is connected to one end of the unit resistor R1, and the other ends of column switches 1# and 2# are connected to the row switch X1<2 of the row containing the unit resistor R1. M Connect one end of the > switch, and the row switch X1 < 2 M The second end of the > is connected to the buffer unit BUFFER1. The other ends of column switches 3# and 4# are both connected to the row switch X2<2 in the row where unit resistor R1 is located. M Connect one end of the > switch, and the row switch X2<2 M The second terminal of the > is connected to the buffer unit BUFFER2. For any row j, the voltage VR < 2. j >、First row voltage VR<2 M +1>, tail voltage VR<1> has:

[0056]

[0057] Figure 2 Except for the first row voltage VR < 2 M Except for +1> and the tail voltage VR<1>, all other voltages VR<2 M >, VR<2M -1>、……VR<3>、VR<2>、etc. all represent the voltage of critical nodes.

[0058] Taking a 12-bit digital signal as an example, the row selection signal and column selection signal are determined by the 12-bit digital signal. The row selection signal is 6 bits, and the column selection signal is 6 bits. The row switch is controlled by the row selection signal; the column switch is controlled by the column selection signal.

[0059] Figure 3 High-bit decoders 1 and 2 represent the decoding of the high M bits of the corresponding two input registers, while low-bit decoders 1 and 2 represent the decoding of the low L bits of the corresponding two input registers. When the number of bits N = 12 bits, the row selection signal is 6 bits and the column selection signal is 6 bits. Assuming that channel 1 is currently selected, the high M bits of the N-bit digital signal output by INPUT REGISTER1 control the row selection switch through high-bit decoder 1, and the low L bits control the column selection switch through low-bit decoder 1, causing the corresponding row and column switches to close, and the resistor string outputs the corresponding voltage value to BUFFER1. Similarly, if channel 2 is selected, the high M bits of the N-bit digital signal output by INPUT REGISTER2 control the row selection switch through high-bit decoder 2, and the low L bits control the column selection switch through low-bit decoder 2, causing the corresponding row and column switches to close, and the resistor string outputs the corresponding voltage value to BUFFER2. This design, along with the design of key nodes in the resistor strings, is intended to reduce the mismatch of resistor strings in multiple conversion units and ensure that all key nodes selected in each resistor string receive relatively equal voltages, thereby ensuring that the analog output (i.e., the analog voltage value) is basically consistent.

[0060] Since a conversion unit is connected to multiple buffer units, the connection method of the input registers that provide digital signals to the conversion unit differs from the traditional structure for the entire digital-to-analog converter circuit. Preferably, the digital-to-analog converter circuit further includes: multiple selection switches and multiple input registers; one selection switch is connected to one input register; multiple input registers are connected to at least one conversion unit; the multiple selection switches are configured to be turned on or off according to a selection signal, and when on, transmit digital signals to the corresponding connected input registers; the multiple input registers are configured to send digital signals to the corresponding target conversion unit.

[0061] In this system, the number of input registers is equal to the number of buffer units, and the number of input registers connected to a conversion unit is equal to the number of buffer units connected to it. That is, when there are 8 buffer units, there are 8 input registers. If one resistor string connects 2 sets of select switches and 2 buffer units, then one resistor string is connected to 2 input registers.

[0062] When a conversion unit is connected to a first input register unit and a second input register unit, the conversion unit receives a first digital signal from the first input register unit or a second digital signal from the second input register unit. The first and second input register units determine whether to send a digital signal to the conversion unit based on a selection signal. That is, assuming one conversion unit is connected to two input register units, the specific input register unit the conversion unit receives from is determined by the selection signal. Therefore, when the conversion unit receives the first digital signal, it transmits an analog signal corresponding to the first digital signal to the first buffer unit connected to it through a set of selection switches; when the conversion unit receives the second digital signal, it transmits an analog signal corresponding to the second digital signal to the second buffer unit connected to it through another set of selection switches.

[0063] By using a buffer connected to the output of the conversion unit, the conversion unit as a whole gains stronger driving force, and the circuit with the buffer exhibits optimized power consumption and delay. The buffer's input range is full swing, ensuring a wide range of input signals, and the monotonicity of the resistor strings in the conversion unit structure guarantees good linearity. Using resistor string multiplexing (each resistor string is multiplexed by two buffer units) to drive multiple loads, with key nodes interconnected between resistor strings, ensures that the voltage across the resistor strings is essentially consistent, resulting in good accuracy for each conversion unit.

[0064] Based on the above-described digital-to-analog conversion circuit, this embodiment of the invention also provides a digital-to-analog converter, which includes: the digital-to-analog conversion circuit as described above.

[0065] Based on the above-described digital-to-analog converter, this invention also provides an electronic device, which includes the digital-to-analog converter described above.

[0066] In summary, the digital-to-analog converter circuit provided by this invention includes: at least one conversion unit and multiple buffer units; at least one conversion unit is connected to multiple buffer units; at least one conversion unit is configured to receive a digital signal, determine a target buffer unit based on the digital signal, convert the digital signal into a corresponding analog signal, and transmit the analog signal to the target buffer unit; multiple buffer units are configured to transmit analog signals to subsequent circuits. Here, one conversion unit is connected to at least two buffer units; the number of input registers connected to one conversion unit is equal to the number of buffer units it is connected to.

[0067] The digital-to-analog converter circuit proposed in this invention creatively proposes a multiplexed structure for the conversion unit. Instead of using a single resistor string for each path, multiple paths share a single conversion unit, and each conversion unit is connected to at least two or more buffers. The selected buffer is activated by an input control signal. The conversion unit structure uses resistor string multiplexing to connect the buffers, which have strong load driving capabilities. Key nodes in the resistor strings are interconnected, ensuring that the analog output (i.e., analog voltage value) of the resistor strings is basically consistent. This not only reduces the nonlinearity of the circuit to a certain extent but also achieves a digital-to-analog converter unit with good accuracy. Furthermore, it reduces the number of resistor strings, decreases area overhead, and lowers the complexity of the layout structure, effectively meeting the requirements of digital-to-analog conversion and possessing high practical value.

[0068] Although preferred embodiments of the present invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of the embodiments of the present invention.

[0069] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or terminal device that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or terminal device. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or terminal device that includes said element.

[0070] The embodiments of the present invention have been described above with reference to the accompanying drawings. However, the present invention is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of the present invention without departing from the spirit and scope of the claims. All of these forms are within the protection scope of the present invention.

Claims

1. A digital-to-analog converter circuit, characterized in that, The digital-to-analog conversion circuit includes: at least one conversion unit and multiple buffer units; At least one of the conversion units is connected to a plurality of the buffer units; At least one of the conversion units is configured to receive a digital signal, determine a selected target buffer unit based on the digital signal, convert the digital signal into a corresponding analog signal, and transmit the analog signal to the target buffer unit. Multiple buffer units are configured to transmit the analog signal to subsequent circuitry; One of the conversion units is connected to at least two of the buffer units; The number of input registers connected to one of the conversion units is equal to the number of cache units connected to it; The conversion unit includes multiple sets of gating switches and multiple unit resistors, wherein each set of gating switches includes a row switch and a column switch. The number of groups of gating switches is the same as the number of buffer units, and one group of gating switches is connected to one buffer unit; multiple unit resistors are connected in series in a serpentine manner between the reference voltage terminal and the low potential terminal to form a resistor string, with the first row being the row connected to the reference voltage terminal and the last row being the row connected to the low potential terminal. Each row of the resistor string is provided with multiple row switches, and the number of row switches in each row is the same as the number of connected buffer units. Each of the multiple unit resistors is connected to multiple column switches at both ends. The number of column switches connected to each end of the unit resistor is the same as the number of row switches in the row it is in. Among the multiple column switches, one end of the first column switch is connected to the unit resistor, and the other end is connected to one end of the first row switch in the row where the unit resistor is located. The other end of the first row switch is connected to a buffer unit. One end of the second column switch is connected to the unit resistor, and the other end is connected to one end of the second row switch in the row where the unit resistor is located. The other end of the second row switch is connected to another buffer unit. The digital-to-analog converter circuit further includes: multiple selection switches and multiple input register units; One of the selection switches is connected to one of the input register units; The plurality of input register units are connected to at least one of the conversion units; Multiple selection switches are configured to be turned on or off according to a selection signal, and when turned on, transmit the digital signal to the corresponding connected input register unit; Multiple input register units are configured to send the digital signal to the corresponding target conversion unit; The number of the plurality of input register units is equal to the number of the plurality of buffer units, and the number of input register units connected to one conversion unit is equal to the number of buffer units connected to it; When one of the conversion units is connected to the first input register unit and the second input register unit, the conversion unit receives a first digital signal from the first input register unit or a second digital signal from the second input register unit, wherein the first input register unit and the second input register unit decide whether to send a digital signal to the conversion unit according to the selection signal; When the conversion unit receives the first digital signal, it transmits an analog signal corresponding to the first digital signal to the first buffer unit connected to it through a set of selection switches; When the conversion unit receives the second digital signal, it transmits an analog signal corresponding to the second digital signal to the second buffer unit connected to it through another set of selection switches.

2. The digital-to-analog converter circuit according to claim 1, characterized in that, The row switch is controlled by a row selection signal; the column switch is controlled by a column selection signal. The row selection signal and the column selection signal are determined by the number of bits in the digital signal; When the number of bits of the digital signal is N=M+L, the row selection signal is the high M bits of the number of bits N, and the column selection signal is the low L bits of the number of bits N.

3. The digital-to-analog converter circuit according to claim 1, characterized in that, In a resistor string structure formed by multiple unit resistors connected in a serpentine manner, the number of unit resistors is determined by the number of bits N, and the number of rows in the resistor string structure is determined by M in the number of bits N. The total number of unit resistors is 2. N The number of rows is 2 M .

4. The digital-to-analog converter circuit according to claim 3, characterized in that, When there are two or more conversion units, each conversion unit has a key node in each row of the resistor string structure. The key node is the end of the last unit resistor in each row of series-connected unit resistors, and this end is connected to the beginning of the first unit resistor in the next row.

5. The digital-to-analog converter circuit according to claim 4, characterized in that, When M=6, the number of rows is 64. Then, two or more conversion units are connected through 64 key nodes, and key nodes corresponding to the same number of rows are connected, while key nodes corresponding to different numbers of rows are not connected.

6. The digital-to-analog converter circuit according to claim 2, characterized in that, When the number of bits N is 12 bits, the high M bits are 6 bits, the low L bits are 6 bits, the row selection signal is 6 bits, and the column selection signal is 6 bits.

7. A digital-to-analog converter, characterized in that, The digital-to-analog converter includes: a digital-to-analog conversion circuit as described in any one of claims 1-6.

8. An electronic device, characterized in that, The electronic device includes the digital-to-analog converter as described in claim 7.

Images