A current steering DAC architecture

Abstract

The application discloses a current steering DAC architecture, and relates to microelectronic circuit technology, comprising a differential pair decoding module, a multiplexer network, a switch driving circuit array and a current source array; the differential pair decoding module comprises two decoding units with consistent structures, which are decoding unit one and decoding unit two; the decoding unit one is provided with an input signal input end, the decoding unit two is provided with an inverted input signal input end, the decoding unit is provided with a low bit decoding signal output end, a second decoding signal output end and a third decoding signal output end, the low bit decoding signal output end is connected with the input end of the switch driving circuit array, the second decoding signal output end and the third decoding signal output end are respectively connected with the input end of the switch driving circuit array through the multiplexer network, and the multiplexer network is further provided with a shift control signal input end. The application reduces transmission delay and high voltage transmission loss under high frequency, and improves conversion rate.

Description

Technical Field

[0001] This invention relates to microelectronic circuit technology, and more specifically, to a current-steering DAC architecture. Background Technology

[0002] With the widespread application of TFT products in wearable flexible electronic devices, electronic skin, and the detection of bioelectric medical signals, TFT DAC circuits are needed in flexible sensing systems to convert digital signals to analog signals. To achieve high conversion rates and high precision, current-controlled TFT DACs have been extensively researched.

[0003] Figure 1 The current-steering TFT DAC architecture in this paper is a commonly used current-steering TFT DAC architecture. Figure 2 The structure of the D latch, Figure 3 It is a structure of a switch drive circuit array. Figure 4 With a unit current source structure, when the electrical signal output by the thermometer decoder reaches its rising edge, the D latch outputs the non-inverting input signal Q and the inverting input signal QN to drive the switch drive circuit array. At this time, because the output of QN is delayed by the delay of one inverter I2 of Q, as shown... Figure 5 As shown, this will cause the windows of the non-inverting output signal Vp and the inverting output signal Vn of the switch driver circuit array to be asymmetrical, and may even cause Vp and Vn to be high or low at the same time, increasing the output current glitches and deteriorating SFDR. At the same time, when Vp and Vn are both low, the common gate transistor Mcs and the current source transistor Mcm of the unit current source enter the cutoff region. When the unit current source is turned on again, it needs to charge the relevant node capacitors of the common gate transistor Mcs and the current source transistor Mcm, which leads to a decrease in conversion rate. At the same time, since the switch driver circuit array is driven by inverters I1 and I2 when the clock signal is at a level, it is equivalent to one inverter needing to drive another inverter and one input port of the switch driver circuit array. If the size of inverters I1 and I2 is increased at this time, although the driving capability of the D latch can be enhanced, when the rising edge of the clock arrives, the thermometer decoding output signal needs to break the stronger gain loop of inverters I1 and I2, resulting in an increase in delay, which in turn leads to a decrease in conversion rate.

[0004] Figure 6 The capacitor bootstrap inverter is the most commonly used logic gate in circuits built with all NMOS TFTs. However, if the capacitor bootstrap inverter does not flip for a long time, the capacitor C will leak charge, causing a decrease in the logic level swing VOUT. Figure 7As shown. In the TFT DAC digital circuit, when the capacitor in the bootstrap logic gate experiences charge leakage, the reduced logic level is insufficient to maintain the normal operation of the switch drive circuit array in the analog circuit, resulting in an error in the output current of the current-controlled TFT DAC.

[0005] Classical DEM (Dynamic Error Matching Error) techniques include random sequence generation circuits and multiplexer networks, such as... Figure 8 As shown, a traditional multiplexer network consists of a 2-to-1 selector. A 2-to-1 selector comprises two TFT NMOS transmission gates and an inverter, as shown below. Figure 9 As shown. However, a 2-to-1 selector built entirely with TFT NMOS does not contain PMOS, as shown... Figure 10 As shown, when transmitting a high level, a threshold voltage Vth is lost, and the conducting NMOS is in the saturation region, resulting in a large resistance. This leads to a significant voltage drop and delay when high-frequency signals pass through. The series connection of multiple 2-to-1 selectors increases the delay and causes a substantial loss of high-frequency voltage levels. Summary of the Invention

[0006] The technical problem to be solved by the present invention is to provide a current-driven DAC architecture that addresses the shortcomings of the prior art, thereby reducing transmission delay and voltage loss in high-frequency and high-voltage transmission.

[0007] The present invention discloses a current-steering DAC architecture, comprising a differential dual decoding module, a multiplexer network, a switch driver circuit array, and a current source array. The differential dual decoding module includes two decoding units with identical structures, namely decoding unit one and decoding unit two. Decoding unit one has an input signal input terminal, and decoding unit two has an inverting input signal input terminal. Each decoding unit has a low-order decoded signal output terminal, a second decoded signal output terminal, and a third decoded signal output terminal. The low-order decoded signal output terminal is connected to the input terminal of the switch driver circuit array. The second and third decoded signal output terminals are respectively connected to the input terminal of the switch driver circuit array through the multiplexer network. The multiplexer network also has a shift control signal input terminal. The output terminal of the switch driver circuit array is connected to the input terminal of the current source array.

[0008] Preferably, the input terminal of the decoding unit receives an N-bit input signal. The decoding unit includes an M-bit thermometer decoder and two (NM) / 2-bit thermometer decoders. The m-bit thermometer decoder is provided with a low-bit decoding signal output terminal, and the two (NM) / 2-bit thermometer decoders are respectively provided with a second decoding signal output terminal and a third decoding signal output terminal.

[0009] Preferably, the decoding signal output terminal of the (NM) / 2-bit thermometer decoder outputs a K-bit decoded output signal, the shift control signal input terminal inputs K as a shift control signal, the multiplexer network consists of K rows and K columns of NMOS TFTs, the gate of each row of the NMOS TFTs inputs the shift control signal, the drains of each column of the NMOS TFTs are connected together, the drains of the K columns of the NMOS TFTs are respectively input with one bit of the K-bit decoded output signal, and the source of each column of the NMOS TFTs serves as a K-bit network signal output terminal.

[0010] Preferably, the NMOS TFTs in the first column are arranged in the order of 1 to K. The NMOS TFTs after the first column take the last NMOS TFT in the previous column as the first NMOS TFT in the current column, and the remaining NMOS TFTs in the previous column are all shifted down one position to form the arrangement of the NMOS TFTs in the current column.

[0011] Preferably, the current-steering DAC architecture further includes a random sequence generator, which takes a clock signal CLK as input and outputs a K-bit shift control signal.

[0012] Preferably, the input terminals of both decoding units are connected to D flip-flops.

[0013] Preferably, one of the D flip-flops receives an input signal, and the input of the other D flip-flop is connected to an inverter, the input of which receives an input signal.

[0014] Preferably, the current-driven DAC architecture further includes a timing refresh module, the output of which is connected to two D flip-flops simultaneously.

[0015] Preferably, the timed refresh module includes multiple 2-to-1 selectors, the input of each 2-to-1 selector is connected to the output of a D flip-flop, and the control terminal of each 2-to-1 selector receives a timed refresh signal.

[0016] Beneficial effects

[0017] The advantages of this invention are:

[0018] 1. To address the charge leakage problem in the capacitor bootstrap logic gate built with all NMOS TFTs, a timed refresh module was designed to replenish the charge leaked by the capacitors in the capacitor bootstrap logic gate, thereby preventing the attenuation of the output swing of the capacitor bootstrap logic gate and maintaining the correct output current of the current-controlled TFT DAC.

[0019] 2. A differential dual thermometer decoding structure is adopted to ensure that the signals at the non-inverting and inverting inputs of the switch drive circuit arrive after experiencing the same logic gate link delay, thereby ensuring the symmetry of the rising and falling windows, reducing current output glitches, and thus improving SFDR.

[0020] 3. The differential dual thermometer decoding structure allows the in-phase decoding circuit to drive the in-phase input of the switch driving circuit, and the inverting input to drive the inverting input of the switch driving circuit, thereby improving the driving capability of the switch driving circuit and increasing the conversion rate of the current-controlled TFT DAC.

[0021] 4. To address the issues of increased transmission delay and excessive power loss during high-frequency, high-voltage transmission caused by multiple 2-to-1 selectors connected in series in a multiplexer network, this invention employs a 1-to-7 selector to form a DEM-structured multiplexer network, thereby reducing transmission delay and voltage loss during high-frequency, high-voltage transmission. Attached Figure Description

[0022] Figure 1 This is a schematic diagram of a traditional current-controlled TFT DAC structure;

[0023] Figure 2 This is a schematic diagram of the D latch structure;

[0024] Figure 3 This is a schematic diagram of the switch drive circuit structure;

[0025] Figure 4 This is a schematic diagram of a unit current source structure;

[0026] Figure 5 This is a schematic diagram of the curves showing the large current spikes caused by the asymmetry of the rising and falling windows in the existing switch drive circuit.

[0027] Figure 6 This is a schematic diagram of a capacitor bootstrap logic gate structure.

[0028] Figure 7 This is a schematic diagram illustrating how capacitor charge leakage leads to a decrease in the output swing of the output logic gate in related technologies.

[0029] Figure 8 This is a schematic diagram of a conventional 3-bit shifted multiplexer network structure according to the present invention.

[0030] Figure 9 This is a schematic diagram of the result of a 2-to-1 selector;

[0031] Figure 10 A schematic diagram of the threshold loss caused by the NMOS transmission gate;

[0032] Figure 11 This is a schematic diagram of the current-steering DAC architecture of the present invention;

[0033] Figure 12 This is a schematic diagram of the current spike reduction curve of the switch drive circuit of the present invention, which is symmetrical in the rising and falling windows.

[0034] Figure 13 This is a schematic diagram of the frame of the 3-bit thermometer decoder 1 of the present invention;

[0035] Figure 14 This is a schematic diagram of the frame of the 3-bit thermometer decoder 2 of the present invention;

[0036] Figure 15 This is a schematic diagram of the frame of the 3-bit thermometer decoder of the present invention;

[0037] Figure 16 This is a schematic diagram of the frame of the 3-bit thermometer decoder 4 of the present invention;

[0038] Figure 17 This is a schematic diagram of the frame of the 2-bit thermometer decoder 1 of the present invention;

[0039] Figure 18 This is a schematic diagram of the frame of the 2-bit thermometer decoder 2 of the present invention;

[0040] Figure 19 This is a schematic diagram showing the improvement curves of conversion rate and SFDR of the present invention;

[0041] Figure 20 This is a schematic diagram of the connection structure of the timed refresh module of the present invention;

[0042] Figure 21 This is a schematic diagram of the logic gate levels of the timed refresh module of the present invention;

[0043] Figure 22 A curve comparing the output current of a traditional current-controlled TFT DAC and the output current of a current-controlled TFT DAC with an added timer refresh module;

[0044] Figure 23 This is a schematic diagram of the multiplexer network structure of the present invention;

[0045] Figure 24 Comparison diagrams of square wave signals transmitted in a multiplexer network. Detailed Implementation

[0046] The present invention will be further described below with reference to embodiments, but this does not constitute any limitation on the present invention. Any limited modifications made by any person within the scope of the claims of the present invention are still within the scope of the claims of the present invention.

[0047] like Figure 11As shown, a current-driven DAC architecture of the present invention comprises a timing refresh module, a random sequence generator, a multiplexer network, a D flip-flop, a differential dual decoding module, a switch driver circuit array, and a current source array. The differential dual decoding module includes two identical decoding units, namely decoding unit one and decoding unit two. Decoding unit one has an input signal input terminal, and decoding unit two has an inverting input signal input terminal. Each decoding unit has a low-order decoded signal output terminal, a second decoded signal output terminal, and a third decoded signal output terminal. The low-order decoded signal output terminal is connected to the input terminal of the switch driver circuit array. The second and third decoded signal output terminals are respectively connected to the input terminal of the switch driver circuit array through the multiplexer network, and the multiplexer network also has a shift control signal input terminal. The output terminal of the switch driver circuit array is connected to the input terminal of the current source array.

[0048] exist Figure 11 In this context, CLK is the clock signal, refresh is the timer refresh signal, and B0 to B7 are 8-bit input signals, where B0 is the least significant bit and B7 is the most significant bit. These are the inverted signals B0 through B7. When the rising edge of the clock arrives, B0 through B7 and... Simultaneously, the data is transmitted to the differential dual decoding module for decoding. This embodiment employs a 2+3+3 segmented thermometer decoding mode, meaning the lower two bits of B0 and B1 are decoded using thermometer decoding, the middle three bits of B2–B4 are decoded using thermometer decoding, and the higher three bits of B5–B7 are decoded using thermometer decoding. The inverting input… The lower two bits use dual thermometer decoding. The middle 3 bits use dual thermometer decoding. The high 3 bits employ dual thermometer decoding. The decoded thermometer signals La0-La2 and Lb0-Lb2 are inverted, as are signals Ua0-Ua6 and Ub0-Ub6, and signals Ma0-Ma6 and Mb0-Mb6. Among these signals, La0-La2 and Lb0-Lb2 are input to the non-inverting and inverting inputs of their respective switch driver circuits. Signals Ua0-Ua6 and Ub0-Ub6 are connected to a multiplexing network, which then outputs two sets of inverted signals, Dua0-Dua6 and Dub0-Dub6. These signals are then input to the non-inverting and inverting inputs of their respective switch driver circuits. Signals Ma0-Ma6 and Mb0-Mb6 are input into the multiplexing network, and then output two sets of mutually inverted signals Dma0-Dma6 and Dmb0-Dmb6 respectively. Signals Dma0-Dma6 and Dmb0-Dmb6 are input to the non-inverting and inverting input terminals of their corresponding switch driver circuits, respectively. Q1-Q7 are the shift control signals of the multiplexer network, controlling the shift operation of the input signals of the multiplexer network. The outputs of the switch driver circuit array, Vpl0-Vpl2 and Vnl0-Vnl2, control the non-inverting and inverting switches of the lower 3 current source array, respectively; Vpu0-Vpu6 and Vnu0-Vnu2 control the non-inverting and inverting switches of the middle 7 current source array, respectively; and Vpm0-Vpm6 and Vnm0-Vnm6 control the non-inverting and inverting switches of the higher 7 current sources, respectively. Finally, the output current Ip at the non-inverting terminal and the output current In at the inverting terminal are obtained.

[0049] This invention proposes obtaining the inverted signals of input signals B0 to B7 by passing them through an inverter at the input terminal. When the rising edge of the clock arrives, both input signals will be decoded simultaneously, experiencing the same logic gate link delay. After decoding, the signals are synchronously input to the switch driver circuit, thus making the windows of the non-inverting output signal Vp and the inverting output signal Vn of the switch driver circuit symmetrical, reducing current glitches and improving SFDR. Figure 12 As shown. Simultaneously, the non-inverting and inverting inputs of the switch drive circuit are driven by the non-inverting and inverting thermometer decoder circuits, respectively, enhancing the driving capability of the switch drive circuit and thus improving the conversion rate of the current-controlled TFT DAC. For example... Figure 11 The inputs of 3-bit thermometer decoder 1 and 3-bit thermometer decoder 2 are inverted, and the decoding results are inverted. They are in a dual relationship. 3-bit thermometer decoder 3 and 3-bit thermometer decoder 4 are also in a dual relationship. 2-bit thermometer decoder 1 and 2-bit thermometer decoder 2 are also in a dual relationship.

[0050] In this embodiment, the block diagrams of 3-bit thermometer decoder 1 and 3-bit thermometer decoder 2 are as follows: Figure 13 , Figure 14 As shown, the truth tables for both are shown in Table 1 and Table 2.

[0051] Table 1 Truth Table of 3-bit Thermometer Decoder 1

[0052] B7 B6 B5 Ma1 Ma2 Ma3 Ma4 Ma5 Ma6 Ma7 0 0 0 O 0 0 O 0 0 0 0 0 1 1 0 O 0 0 0 0 0 1 0 1 1 0 O 0 0 O 0 1 1 1 1 1 0 0 0 0 1 0 0 1 1 1 1 O 0 0 1 0 1 1 1 1 1 1 0 0 1 1 0 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1

[0053] Table 2 Truth Table of 3-bit Thermometer Decoder 2

[0054]

[0055] The block diagrams of 3-bit thermometer decoder 3 and 3-bit thermometer decoder 4 are as follows: Figure 15 , Figure 16 As shown, the truth tables for both are shown in Table 3 and Table 4.

[0056] Table 3 Truth Table of 3-bit Thermometer Decoder 3

[0057] B4 B3 B2 Ua1 Ua2 Ua3 Ua4 Ua5 Ua6 Ua7 O 0 0 O 0 0 O 0 O 0 0 0 1 1 0 0 0 O 0 0 0 1 0 1 1 0 O O 0 0 0 1 1 1 1 1 0 O 0 0 1 0 0 1 1 1 1 O 0 0 1 0 1 1 1 1 1 1 0 0 1 1 0 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1

[0058] Table 4 Truth Table of 3-bit Thermometer Decoder 4

[0059]

[0060] The block diagrams of 2-bit thermometer decoder 1 and 2-bit thermometer decoder 2 are as follows: Figure 17 , Figure 18 As shown, the truth tables for both are shown in Table 5 and Table 6.

[0061] Table 5 Truth Table of 2-bit Thermometer Decoder 1

[0062] B1 B0 La1 La2 La3 0 0 0 0 0 0 1 1 0 0 1 0 1 1 0 1 1 1 1 1

[0063] Table 6 Truth Table of 2-bit Thermometer Decoder 2

[0064]

[0065] like Figure 19 As shown, taking an 8-bit current-steering TFT DAC as an example, when this architecture is adopted, the maximum slew rate of the current-steering TFT DAC is 32KS / s, while the maximum slew rate of the traditional current-steering TFT DAC is 4KS / s. At the same time, SFDR is also improved compared with the traditional current-steering TFT DAC at the same input signal frequency.

[0066] To address the capacitor charge leakage problem under low-frequency signals in logic gates built with all NMOS TFTs, this invention incorporates a timed refresh circuit module, such as... Figure 20As shown, this module is a 2-to-1 selector. That is, a 2-to-1 selector is added after the D flip-flop, causing all input signals to flip once within a certain period. This replenishes the charge of the capacitor in the bootstrap inverter, keeping the logic gate level swing VOUT constant. Figure 21 As shown.

[0067] Figure 22 This demonstrates the output current of a traditional current-controlled TFT DAC and the output current of a current-controlled TFT DAC with an added timed refresh module. The traditional TFT current-controlled DAC output current can experience a prolonged period of erroneous current output due to charge leakage from the capacitor bootstrap logic gate. The TFT current-controlled DAC with timed refresh avoids this error caused by capacitor leakage from the capacitor bootstrap logic gate by refreshing the output current at regular intervals.

[0068] To address the issues of significantly increased delay and substantial signal loss in high-frequency signals caused by cascading multiplexer switches, such as... Figure 23 As shown, a 1-to-7 selector network is constructed using a single-stage 1-to-7 selector, avoiding a significant increase in delay and substantial loss during high-frequency high-level signal transmission. Specifically, the multiplexer network consists of 7 rows and 7 columns of NMOS TFTs. The gate of each row of NMOS TFTs receives a shift control signal, and the drains of each column of NMOS TFTs are connected together. The drains of the 7 columns of NMOS TFTs are sequentially input with one bit of the 7-bit decoded output signal, and the source of each column of NMOS TFTs serves as a 7-bit network signal output terminal. The specific layout is as follows: the NMOS TFTs in the first column are arranged in order from 1 to 7; the NMOS TFTs after the first column take the last NMOS TFT in the previous column as the first NMOS TFT in the current column, and the remaining NMOS TFTs in the previous column are shifted down one bit to form the arrangement of the NMOS TFTs in the current column. See [reference needed] for details. Figure 23 The layout.

[0069] exist Figure 23In this circuit, the signals Ma0 to Ma6, decoded from the high 3-bit thermometer, are used as inputs, and Dmma0 to Dma6 are the output signals. Q1 to Q7 are shift control signals generated by a random sequence generator. The working principle is as follows: When Q1 is high and Q2 to Q7 are low, all transistors connected to Q1 are turned on, and the remaining transistors are turned off. At this time, Ma0 is transferred to Dma0, Ma1 is transferred to Dma1, Ma2 is transferred to Dmma2, Ma3 is transferred to Dmma3, Ma4 is transferred to Dmma4, Ma5 is transferred to Dma5, and Ma6 is transferred to Dmma6. There is no shift operation. When Q2 is high and Q3-Q7 and Q1 are low, all transistors connected to Q2 are turned on, and the remaining transistors are turned off. At this time, Ma0 is transferred to Dma1, Ma1 to Dma2, Ma2 to Dma3, Ma3 to Dma4, Ma4 to Dma5, Ma5 to Dma6, and Ma6 to Dma1, completing the right shift operation by 1 bit. This process continues until the shift operation is complete, and the final shift is shown in Table 7.

[0070] Table 7. Multiplexer Network Shift Status

[0071] Q1 Q2 Q3 Q4 Q5 Q6 Q7 Number of bits to shift to the right 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 1 0 0 0 0 2 O O 0 1 0 0 0 3 0 0 0 0 1 0 0 4 0 0 0 0 0 1 0 5 0 0 0 0 0 0 1 6

[0072] Of the Q1 to Q7 signals generated by the random sequence generator that matches the multiplexer network proposed in this invention, only one signal outputs a high level, while the rest output a low level. Q1 to Q7 are refreshed once every time the rising edge of the clock arrives. Figure 24 The paper compares the transmission of square wave signals using a conventional multiplexer network with that of the present invention. Relatively speaking, the multiplexer network of the present invention has better speed and voltage loss when transmitting square wave signals than the conventional multiplexer network.

[0073] The above description is only a preferred embodiment of the present invention. It should be noted that those skilled in the art can make several modifications and improvements without departing from the structure of the present invention, and these will not affect the effectiveness of the implementation of the present invention or the practicality of the patent.

Claims

1. A current-driven DAC architecture, characterized in that, The system includes a differential dual decoding module, a multiplexer network, a switch driver circuit array, and a current source array. The differential dual decoding module comprises two identical decoding units, namely decoding unit one and decoding unit two. Decoding unit one has an input signal input terminal, and decoding unit two has an inverting input signal input terminal. Each decoding unit has a low-order decoded signal output terminal, a second decoded signal output terminal, and a third decoded signal output terminal. The low-order decoded signal output terminal is connected to the input terminal of the switch driver circuit array. The second and third decoded signal output terminals are respectively connected to the input terminal of the switch driver circuit array through the multiplexer network. The multiplexer network also has a shift control signal input terminal. The output terminal of the switch driver circuit array is connected to the input terminal of the current source array. The decoding unit receives an N-bit input signal at its input terminal. The decoding unit includes an M-bit thermometer decoder and two (NM) / 2-bit thermometer decoders. The M-bit thermometer decoder has a low-order decoding signal output terminal, and the two (NM) / 2-bit thermometer decoders each have a second decoding signal output terminal and a third decoding signal output terminal. The decoding signal output terminal of the (NM) / 2-bit thermometer decoder outputs a K-bit decoding output signal. The multiplexer network consists of 7 rows and 7 columns of NMOS TFTs. The gate of each row of NMOS TFTs is input with a shift control signal, and the drains of each column of NMOS TFTs are connected together. The drains of the 7 columns of NMOS TFTs are sequentially input with one bit of a 7-bit decoded output signal. The source of each column of NMOS TFTs serves as a 7-bit network signal output terminal. The NMOS TFTs in the first column are arranged in the order of 1 to 7. The NMOS TFTs after the first column take the last NMOS TFT in the previous column as the first NMOS TFT in the current column, and the remaining NMOS TFTs in the previous column are shifted down one bit to form the arrangement of the NMOS TFTs in the current column.

2. The current-steering DAC architecture according to claim 1, characterized in that, The current-steering DAC architecture also includes a random sequence generator, which takes a clock signal CLK as input and outputs a K-bit shift control signal.

3. The current-steering DAC architecture according to claim 1, characterized in that, Both of the decoding units have D flip-flops connected to their inputs.

4. The current-steering DAC architecture according to claim 3, characterized in that, One of the D flip-flops receives an input signal, and the input of the other D flip-flop is connected to an inverter, the input of which receives an input signal.

5. A current-steering DAC architecture according to claim 3, characterized in that, The current-controlled DAC architecture also includes a timing refresh module, the output of which is connected to two D flip-flops.

6. A current-steering DAC architecture according to claim 5, characterized in that, The timed refresh module includes multiple 2-to-1 selectors. The input of each 2-to-1 selector is connected to the output of a D flip-flop. The control terminal of each 2-to-1 selector receives a timed refresh signal (refresh).

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