Control method, device, system and equipment of Ethernet physical layer transceiver PHY

Abstract

The invention provides a control method, device, system and equipment of an Ethernet physical layer transceiver PHY, and the control method of the Ethernet physical layer transceiver PHY comprises the steps that a control chip receives a clock signal line MDC signal and a data signal line MDIO signal of the control equipment, the MDIO signal comprises an instruction value, and the MDC signal has the currently accumulated number of falling edges; determining whether the falling edge of the MDIO signal is detected currently to obtain a first determination result, determining whether the current falling edge of the MDC signal is valid to obtain a second determination result, and determining whether the current rising edge of the MDC signal is valid to obtain a third determination result; analyzing at least one of the instruction value, the number of the falling edges, the first determination result, the second determination result and the third determination result to determine a target working state required by the control chip; and controlling the control chip to switch to the target working state so as to control the PHY in the target working state. According to the PHY control method and device, the PHY can be controlled based on the signal provided by the control device under the condition that the external control device serves as the master control, and therefore the requirement of the control device for PHY control is effectively met.

Description

Technical Field

[0001] The present disclosure relates to the technical field of electronic equipment, and in particular to a control method, device, system and equipment for an Ethernet physical layer transceiver PHY. Background Art

[0002] In the related art, a control chip refers to a chip used to implement some control logic. The control chip can be, for example, a Field Programmable Gate Array (FPGA). Based on the internal MicroBlaze embedded soft core of the FPGA (MicroBlaze embedded soft core is a processor soft core that can be embedded in the FPGA) and the Ethernet physical layer transceiver PHY (Physical) are directly connected through the Management Data Input Output (MDIO) interface. Based on this interface connection scheme, it can support FPGA to configure PHY through the MDIO interface.

[0003] In this way, when an external control device (such as a central processing unit (CPU) or a microcontroller unit (MCU)) is used as the main control, since the interface of the control device does not match the interface of the PHY, and the control chip in the related art does not support the control of the PHY based on the signal provided by the control device, it cannot effectively support the control device's demand for PHY control. Summary of the invention

[0004] The present disclosure aims to solve one of the technical problems in the related art at least to some extent.

[0005] To this end, the purpose of the present disclosure is to propose a control method, device, system, electronic device, non-transitory computer-readable storage medium storing computer instructions, and computer program product for an Ethernet physical layer transceiver PHY, which can support the control of PHY based on the signal provided by the control device when an external control device acts as the main control, thereby effectively supporting the control device's demand for PHY control.

[0006] A control method for an Ethernet physical layer transceiver PHY proposed in an embodiment of the first aspect of the present disclosure includes: receiving a clock signal line MDC signal and a data signal line MDIO signal of a control device, wherein the MDIO signal includes an instruction value and the MDC signal has a currently accumulated number of falling edges; determining whether a falling edge of the MDIO signal is currently detected to obtain a first determination result, determining whether the current falling edge of the MDC signal is valid to obtain a second determination result, and determining whether the current rising edge of the MDC signal is valid to obtain a third determination result; analyzing at least one of the instruction value, the number of falling edges, the first determination result, the second determination result, and the third determination result to determine a target working state that a control chip needs to be in; and controlling the control chip to switch to the target working state to control the PHY in the target working state.

[0007] The control method of the Ethernet physical layer transceiver PHY proposed in the second aspect embodiment of the present disclosure includes: providing a clock signal line MDC signal and a data signal line MDIO signal to a control chip, wherein the MDIO signal includes an instruction value, the MDC signal has a currently accumulated number of falling edges, and the MDIO signal, the instruction value and the number of falling edges are used to determine the target working state that the control chip needs to be in.

[0008] A control device for an Ethernet physical layer transceiver PHY proposed in an embodiment of the third aspect of the present disclosure includes: a receiving module, used to receive a clock signal line MDC signal and a data signal line MDIO signal of a control device, wherein the MDIO signal includes an instruction value and the MDC signal has a currently accumulated number of falling edges; a determination module, used to determine whether a falling edge of the MDIO signal is currently detected to obtain a first determination result, and to determine whether the current falling edge of the MDC signal is valid to obtain a second determination result, and to determine whether the current rising edge of the MDC signal is valid to obtain a third determination result; and a control module, used to analyze at least one of the instruction value, the number of falling edges, the first determination result, the second determination result and the third determination result to determine the target working state that the control chip needs to be in, and control the control chip to switch to the target working state to control the PHY in the target working state.

[0009] The control device of the Ethernet physical layer transceiver PHY proposed in the fourth aspect embodiment of the present disclosure includes: a sending module, which is used to provide a clock signal line MDC signal and a data signal line MDIO signal to a control chip, wherein the MDIO signal includes an instruction value, the MDC signal has a current accumulated number of falling edges, and the MDIO signal, the instruction value and the number of falling edges are used to determine the target working state that the control chip needs to be in.

[0010] A control system for an Ethernet physical layer transceiver PHY proposed in an embodiment of a fifth aspect of the present disclosure includes: a control device, a control chip connected to the control device, and a PHY connected to the control chip; wherein the control device is used to provide a clock signal line MDC signal and a data signal line MDIO signal to the control chip, wherein the MDIO signal includes an instruction value, and the MDC signal has a currently accumulated number of falling edges; the control chip is used to receive the clock signal line MDC signal and the data signal line MDIO signal of the control device, wherein the MDIO signal includes an instruction value, and the MDC signal has a currently accumulated number of falling edges, and determine whether a falling edge of the MDIO signal is currently detected to obtain a first determination result, and determine whether the current falling edge of the MDC signal is valid to obtain a second determination result, and determine whether the current rising edge of the MDC signal is valid to obtain a third determination result, analyze at least one of the instruction value, the number of falling edges, the first determination result, the second determination result, and the third determination result to determine the target working state that the control chip needs to be in, and control the control chip to switch to the target working state to control the PHY in the target working state.

[0011] The electronic device proposed in the sixth aspect embodiment of the present disclosure includes: a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the program, the control method of the Ethernet physical layer transceiver PHY proposed in the first or second aspect embodiment of the present disclosure is implemented.

[0012] The seventh aspect embodiment of the present disclosure proposes a non-temporary computer-readable storage medium, on which a computer program is stored. When the program is executed by a processor, it implements the control method of the Ethernet physical layer transceiver PHY proposed in the first or second aspect embodiment of the present disclosure.

[0013] An eighth aspect embodiment of the present disclosure proposes a computer program product. When the instructions in the computer program product are executed by a processor, the control method of the Ethernet physical layer transceiver PHY proposed in the first or second aspect embodiment of the present disclosure is executed.

[0014] The control method, device, system, electronic device, non-transitory computer-readable storage medium storing computer instructions and computer program product of the Ethernet physical layer transceiver PHY provided by the present disclosure receive the clock signal line MDC signal and the data signal line MDIO signal of the control device, wherein the MDIO signal contains the instruction value, the MDC signal has the current accumulated number of falling edges, and determines whether the falling edge of the MDIO signal is currently detected to obtain a first determination result, and determines whether the current falling edge of the MDC signal is valid to obtain a second determination result, and determines whether the current rising edge of the MDC signal is valid to obtain a third determination result, and analyzes at least one of the instruction value, the number of falling edges, the first determination result, the second determination result and the third determination result to determine the target working state that the control chip needs to be in, and controls the control chip to switch to the target working state to control the PHY in the target working state. Thus, when the external control device is used as the master control, it can support the control of the PHY based on the signal provided by the control device, thereby effectively supporting the control device's demand for PHY control.

[0015] Additional aspects and advantages of the present disclosure will be given in part in the following description and in part will be obvious from the following description or learned through practice of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The above and / or additional aspects and advantages of the present disclosure will become apparent and easily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:

[0017] Figure 1 It is a flowchart of a control method of an Ethernet physical layer transceiver PHY proposed in an embodiment of the present disclosure;

[0018] Figure 2 is a flow chart of a control method of an Ethernet physical layer transceiver PHY proposed in another embodiment of the present disclosure;

[0019] Figure 3 is a flow chart of a control method of an Ethernet physical layer transceiver PHY proposed in another embodiment of the present disclosure;

[0020] Figure 4 is a flow chart of a control method of an Ethernet physical layer transceiver PHY proposed in another embodiment of the present disclosure;

[0021] Figure 5 is a flow chart of a control method of an Ethernet physical layer transceiver PHY proposed in another embodiment of the present disclosure;

[0022] Figure 6 is a schematic diagram of FPGA state switching in an embodiment of the present disclosure;

[0023] Figure 7 It is a structural schematic diagram of a control device for an Ethernet physical layer transceiver PHY proposed in an embodiment of the present disclosure;

[0024] Figure 8 is a structural schematic diagram of a control device for an Ethernet physical layer transceiver PHY proposed in another embodiment of the present disclosure;

[0025] Fig. 9 is a structural schematic diagram of a control system of an Ethernet physical layer transceiver PHY proposed in another embodiment of the present disclosure;

[0026] Fig.10 is a structural schematic diagram of a control system of an Ethernet physical layer transceiver PHY proposed in another embodiment of the present disclosure;

[0027] Fig.11 A block diagram of an exemplary electronic device suitable for implementing embodiments of the present disclosure is shown. DETAILED DESCRIPTION

[0028] Embodiments of the present disclosure are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present disclosure, and are not to be construed as limitations of the present disclosure. On the contrary, the embodiments of the present disclosure include all changes, modifications, and equivalents that fall within the spirit and connotation of the appended claims.

[0029] Figure 1 FIG. 1 is a flow chart of a control method of an Ethernet physical layer transceiver PHY proposed in an embodiment of the present disclosure. Figure 1 As shown, the control method of the Ethernet physical layer transceiver PHY can be executed by a control chip. For example, the control chip can be, for example, an FPGA. The method includes:

[0030] S101: receiving a clock signal line (Management Data Clock, MDC) signal and a data signal line MDIO signal of a control device, wherein the MDIO signal includes an instruction value, and the MDC signal has a currently accumulated number of falling edges.

[0031] The control device may be, for example, a central processing unit (CPU) or a microcontroller unit (MCU), and there is no limitation to this.

[0032] In the embodiments of the present disclosure, the control chip may be FPGA for example, but of course, the control chip may also be any other possible form of chip, which is not limited thereto.

[0033] In some embodiments, the control device may provide the FPGA with an MDC signal and an MDIO signal, which are serial interface buses managed between the Media Access Control (MAC) layer and the PHY, wherein the MDC signal is a bus clock signal and the MDIO signal is a data line signal. This interface is mainly used for the MAC controller to read and set the status of the PHY, obtain the link status, control the physical layer negotiation, and other operations, and there is no restriction on this.

[0034] In some embodiments, the MDIO signal may include an instruction value, which is used to control the PHY, and there is no restriction on this. The instruction value may refer to the assignment of an instruction bit, and the instruction bit refers to a value containing some control semantics. It should be noted that the signal includes an instruction bit assignment with some values ​​having control semantics, which is a common control processing method in the related art and will not be repeated here. The instruction bit in the MDIO signal in the embodiment of the present disclosure may be, for example, stcode (stcode is an existing instruction bit in the related art. In the embodiment of the present disclosure, the value of the instruction bit stcode, the falling edge of the MDIO signal, etc. are referenced to determine the target working state that the control chip needs to be in), stcode is used to be related to the specific mode in which the control chip is located, and stcode can take the value of 2'b00 or 2'b00, and different values ​​are related to the specific mode in which the control chip is located.

[0035] In some embodiments, the MDC signal may be a continuous signal, and the MDC signal includes several falling edges of the clock, without limitation. In the disclosed embodiment, the falling edge of the clock is used to trigger the target working state that the control chip needs to be in. The number of falling edges of the clock is, for example, 1, 2, 3, 4, and the like. In the disclosed embodiment, the number of falling edges of the clock is, for example, 1, 3, 8, 13, 15, 31, and the like, without limitation. The number of different falling edges of the clock may not correspond to a specific indication of meaning separately, and the number of different falling edges of the clock is a combination of the instruction value contained in the MDIO signal to determine the target working state that the control chip currently needs to be in. For details, please refer to the following embodiments.

[0036] In the embodiment of the present disclosure, the FPGA can be determined to be in a specified state by referring to the instruction value contained in the MDIO signal and the number of currently accumulated falling edges of the MDC signal, and the FPGA can control the PHY accordingly based on the specified state, without limitation. The specified state can be referred to as the target working state.

[0037] In some embodiments, the target working state that the FPGA needs to be in can be determined by referring to the instruction value included in the MDIO signal and the current accumulated number of falling edges of the MDC signal, as well as the control rules, without limitation.

[0038] S102: Determine whether the falling edge of the MDIO signal is currently detected to obtain a first determination result, determine whether the current falling edge of the MDC signal is valid to obtain a second determination result, and determine whether the current rising edge of the MDC signal is valid to obtain a third determination result.

[0039] In some embodiments, the MDIO signal may be subjected to a falling edge detection to determine whether the falling edge of the MDIO signal is currently detected, and obtain a first determination result. That is, the first determination result may indicate whether the falling edge of the MDIO signal is currently detected, and this is not limited.

[0040] In some other embodiments, it is also possible to determine whether the current falling edge of the MDC signal is valid, for example, whether the value corresponding to the current falling edge is 0. If the value is 0, it indicates that the current falling edge of the MDC signal is valid. If it is not 0, it may indicate that the current falling edge of the MDC signal is invalid, and a second determination result is obtained, that is, the second determination result is used to indicate whether the current falling edge of the MDC signal is valid, and there is no restriction on this.

[0041] In some other embodiments, it is also possible to determine whether the current rising edge of the MDC signal is valid, for example, whether the value corresponding to the current rising edge is 1. If the value is 1, it indicates that the current rising edge of the MDC signal is valid. If it is not 1, it indicates that the current rising edge of the MDC signal is invalid, and a third determination result is obtained, that is, the third determination result is used to indicate whether the current rising edge of the MDC signal is valid, and there is no restriction on this.

[0042] S103: Analyze at least one of the command value, the number of falling edges, the first determination result, the second determination result, and the third determination result to determine the target working state that the control chip needs to be in.

[0043] In the embodiment of the present disclosure, at least one of the instruction value, the number of falling edges, the first determination result, the second determination result and the third determination result can be analyzed to determine the target working state that the FPGA needs to be in. When the FPGA is in the target working state, the PHY can be controlled accordingly, and there is no restriction on this.

[0044] In some embodiments, the target working state that the FPGA needs to be in can be determined by referring to the instruction value included in the MDIO signal, the number of currently accumulated falling edges of the MDC signal, at least one of the first determination result, the second determination result, and the third determination result, and the control rule, without limitation. In other embodiments, any other possible method can be combined to determine that the FPGA is in the target working state according to at least one of the instruction value, the number of falling edges, the first determination result, the second determination result, and the third determination result, without limitation.

[0045] In some embodiments, the target working state can be any one of an idle state, an MDIO read / write mode detection state, an MDIO current read / write detection state, a PHY address resolution state, a device register state, an MDIO read / write conversion state, a clause45 mode, a clause22 mode, a register address write state, a PHY register write data state, a PHY register read data state, and a continuous register read data state, thereby effectively improving the control flexibility of the Ethernet physical layer transceiver PHY and effectively meeting personalized control application requirements.

[0046] In some embodiments, the idle state indicates a non-working state. When the FPGA is in the idle state, it indicates that the FPGA is not working, such as sleeping or shutting down. In some embodiments, the MDIO read-write mode detection state refers to whether the detection is based on the MDIO read-write mode of the caluse22 mode or the MDIO read-write mode of the clause45 mode. The MDIO read-write mode indicates the state of determining whether it needs to be in read mode or write mode. The read mode indicates the state of reading data (reading data from the PHY), and the write mode indicates the state of writing data (writing data to the PHY). In some embodiments, the current read-write detection state of the MDIO indicates the state of determining whether it is currently in read mode or write mode. The read mode indicates the state of reading data (reading data from the PHY), and the write mode indicates the state of writing data (writing data to the PHY). In some embodiments, the PHY address resolution state indicates the state of parsing and analyzing the PHY address.

[0047] In some embodiments, the device register state refers to the current value or configuration of registers in the FPGA. Registers are component parts used to store and manipulate data, and can be used to store various information, such as control signals, status bits, counters, etc. The device register state can be used to represent various properties, states, or configuration options of the FPGA. For example, for an FPGA, the device register state can be used to represent information such as instruction execution status, memory address, etc.

[0048] In some embodiments, the MDIO read-write conversion state indicates that the FPGA is converted from a read mode to a write mode, or indicates that the FPGA is converted from a write mode to a read mode.

[0049] In some embodiments, Clause45 refers to a mode in the Ethernet physical layer specification, also known as the Extended Sublayer in the IEEE802.3ae standard. This standard is used to describe the fiber optic transmission system used in high-speed Ethernet connections. In Clause45 mode, the fiber optic network device is configured and managed by accessing the MDIO interface of the physical layer device (the physical layer device can be, for example, PHY). The MDIO interface is a dedicated interface for accessing the physical layer device, which can read and write registers to modify the configuration of the physical layer device and obtain status information. Specifically, Clause45 provides a higher-level interface for accessing the extended registers of the physical layer device.

[0050] In some embodiments, Clause22 refers to a mode in the Ethernet physical layer specification, also known as the Basic Sublayer in the IEEE802.3 standard. This standard is used to describe the electrical transmission system used in lower-speed Ethernet connections. In Clause22 mode, Ethernet devices are configured and managed by accessing the media-independent interface of the physical layer device. The media-independent interface is a common physical layer interface that is used to transmit data and control signals, allowing the host to communicate with the physical layer device. In Clause22 mode, the registers of the physical layer device can be read and written. The registers contain various parameters and status information, such as speed, flow control, automatic negotiation, etc. In high-speed Ethernet connections, such as Gigabit Ethernet or higher-speed connections, the Clause45 mode can usually be used to provide higher-level interfaces and functions. The Clause22 mode is mainly used for lower-speed Ethernet connections.

[0051] In some embodiments, the register address write state refers to the state in the process of sending the register address to the device and performing a write operation when accessing the device (e.g., PHY) register. In this process, steps such as sending the register address to be written to the device, waiting for the response of the device, and confirming whether the write operation is successful are generally included. In some embodiments, the state of writing data to the PHY register refers to the state of writing data in the register of the PHY. For example, if the FPGA is in the state of writing data to the PHY register, the FPGA can currently write the data to be written into the register of the PHY. In some embodiments, the state of reading PHY register data refers to the state of reading data from the register of the PHY. For example, if the FPGA is in the state of reading PHY register data, the FPGA can currently read the data to be read from the register of the PHY. In some embodiments, the state of continuously reading register data refers to the state of continuously reading data from the register of the PHY. For example, if the FPGA is in the state of continuously reading register data, it means that the FPGA continuously reads data from the register of the PHY.

[0052] S104: Control the control chip to switch to a target working state, so as to control the PHY in the target working state.

[0053] After analyzing at least one of the instruction value, the number of falling edges, the first determination result, the second determination result and the third determination result to determine the target working state that the control chip needs to be in, the control chip can be switched to the target working state to control the PHY in the target working state.

[0054] In this embodiment, by receiving the clock signal line MDC signal and the data signal line MDIO signal of the control device, wherein the MDIO signal includes an instruction value, the MDC signal has the current accumulated number of falling edges, and determining whether the falling edge of the MDIO signal is currently detected, a first determination result is obtained, and determining whether the current falling edge of the MDC signal is valid, a second determination result is obtained, and determining whether the current rising edge of the MDC signal is valid, a third determination result is obtained, and at least one of the instruction value, the number of falling edges, the first determination result, the second determination result, and the third determination result is analyzed to determine the target working state that the control chip needs to be in, and control the control chip to switch to the target working state, so as to control the PHY in the target working state. Therefore, when the external control device is used as the master control, it can support the control of the PHY based on the signal provided by the control device, thereby effectively supporting the control device's demand for PHY control.

[0055] Figure 2 It is a flowchart of a control method of an Ethernet physical layer transceiver PHY proposed in another embodiment of the present disclosure.

[0056] like Figure 2 As shown, the control method of the Ethernet physical layer transceiver PHY can be executed by a control chip. For example, the control chip can be, for example, an FPGA. The method includes:

[0057] S201: Receive a data signal line MDIO signal of a control device, wherein the MDIO signal includes an instruction value.

[0058] S202: Determine whether a falling edge of the MDIO signal is currently detected to obtain a first determination result.

[0059] S203: If the first determination result indicates that a falling edge of the MDIO signal is currently detected, and the instruction value is used to set the shift register to the first value, it is determined that the control chip needs to be in the MDIO read / write mode detection state.

[0060] In some embodiments, in the power-on reset or user reset state, the PHY register is read and written once to complete the process, and the IDLE state is entered (the IDLE state is an optional example of an idle state), and there is no limitation on this.

[0061] In the embodiment of the present disclosure, if a neg_mcu_mdio falling edge is detected and an mcu_mdio shift register value of 32'hffff_ffff is detected, ST is entered, wherein the neg_mcu_mdio falling edge may be an optional example of a falling edge of an MDIO signal, the mcu_mdio shift register may be an optional example of a shift register, the first value may be, for example, 32'hffff_ffff, and ST may be used to indicate the MDIO read / write mode detection status, without limitation.

[0062] In some embodiments, if the instruction value also includes stcode, the MDIO read / write mode based on caluse22 or based on caluse45 can be determined according to the value of stcode, and there is no limitation on this.

[0063] In some embodiments, if stcode=2'b00, it is determined to be an MDIO read / write mode based on clause45, and if stcode=2'b01, it is determined to be an MDIO read / write mode based on clause22, and there is no limitation on this.

[0064] In this embodiment, a first determination result is obtained by receiving an MDIO signal from a data signal line of a control device, wherein the MDIO signal includes an instruction value, and determining whether a falling edge of the MDIO signal is currently detected. If the first determination result indicates that a falling edge of the MDIO signal is currently detected, and the instruction value is used to set the shift register to a first value, it is determined that the control chip needs to be in an MDIO read-write mode detection state, thereby effectively switching to the MDIO read-write mode detection state according to the MDIO signal provided by the control device.

[0065] Figure 3 It is a flowchart of a control method of an Ethernet physical layer transceiver PHY proposed in another embodiment of the present disclosure.

[0066] like Figure 3 As shown, the control method of the Ethernet physical layer transceiver PHY can be executed by a control chip. For example, the control chip can be, for example, an FPGA. The method includes:

[0067] S301: Receive a clock signal line MDC signal and a data signal line MDIO signal of a control device, wherein the MDC signal has a currently accumulated number of falling edges.

[0068] S302: Determine whether the current falling edge of the MDC signal is valid, and obtain a second determination result.

[0069] S303: If the number of falling edges is 1, and the second determination result indicates that the current falling edge of the MDC signal is valid, it is determined that the control chip needs to be in the MDIO current read / write state.

[0070] In some embodiments, when mdc_cnt == 1 and neg_mcu_mdc is valid, it is possible to jump to the OP state, where mdc_cnt represents the current accumulated number of falling edges of the MDC signal, neg_mcu_mdc may be an optional example of the current falling edge of the MDC signal, and the OP state may be an optional example of determining the current read and write state of the MDIO, and there is no limitation on this.

[0071] In some embodiments, if it is determined that the control chip needs to be in the current read / write state of the MDIO, it may be further determined whether the current MDIO signal is in the read state or the write state, and no limitation is imposed on this.

[0072] In this embodiment, by receiving the clock signal line MDC signal and the data signal line MDIO signal of the control device, wherein the MDC signal has the current accumulated number of falling edges, and determining whether the current falling edge of the MDC signal is valid, a second determination result is obtained. If the number of falling edges is 1, and the second determination result indicates that the current falling edge of the MDC signal is valid, it is determined that the control chip needs to be in the MDIO current read / write state, so as to effectively switch to the MDIO current read / write state according to the clock signal line MDC signal provided by the control device.

[0073] In some embodiments of the present disclosure, if the number of falling edges is 3, and the second determination result indicates that the current falling edge of the MDC signal is valid, it is determined that the control chip needs to be in the PHY address resolution state, so as to effectively switch to the PHY address resolution state according to the clock signal line MDC signal provided by the control device.

[0074] In some embodiments, when mdc_cnt == 3&&neg_mcu_mdc is valid, the PHYAD state is entered, and the PHYAD state is an optional example of the PHY address resolution state. When in the PHYAD (PHY Address) state, it indicates the resolution of the PHY address (in Ethernet communication, each PHY has a unique PHY address, called PHYAD. This address is used to distinguish different PHYs so that the system can correctly access and control each PHY). mdc_cnt indicates the current accumulated number of falling edges of the MDC signal, neg_mcu_mdc can be an optional example of the current falling edge of the MDC signal, and "&&" indicates AND logic, which is not limited.

[0075] In some embodiments of the present disclosure, if the number of falling edges is 8, and the second determination result indicates that the current falling edge of the MDC signal is valid, it is determined that the control chip needs to be in the device register state, so as to effectively switch to the device register state according to the clock signal line MDC signal provided by the control device.

[0076] In some embodiments, when mdc_cnt == 8&&neg_mcu_mdc is valid, the DEVAD state is entered (DEVAD (Device Address) state generally refers to the address state of the device in Ethernet or other network protocols. It represents the unique identifier or address of each device in the network. In network communication, each device needs to have a unique address so that other devices can correctly identify and locate the device. This address can be a hardware address, a logical address, or another type of identifier. In the embodiment of the present disclosure, the DEVAD state is an optional example of a device register state, that is, in the embodiment of the present disclosure, the DEVAD state can specifically refer to a device register state), mdc_cnt represents the current accumulated number of falling edges of the MDC signal, neg_mcu_mdc can be an optional example of the current falling edge of the MDC signal, and "&&" represents AND logic, which is not limited.

[0077] Figure 4 It is a flowchart of a control method of an Ethernet physical layer transceiver PHY proposed in another embodiment of the present disclosure.

[0078] like Figure 4 As shown, the control method of the Ethernet physical layer transceiver PHY can be executed by a control chip. For example, the control chip can be, for example, an FPGA. The method includes:

[0079] S401: Receive a clock signal line MDC signal and a data signal line MDIO signal of a control device, wherein the MDIO signal includes an instruction value, and the MDC signal has a currently accumulated number of falling edges.

[0080] S402: Determine whether the current falling edge of the MDC signal is valid, and obtain a second determination result.

[0081] S403: If the number of falling edges is 13, and the second determination result indicates that the current falling edge of the MDC signal is valid, it is determined that the control chip needs to be in the MDIO read-write conversion state.

[0082] In some embodiments, when mdc_cnt == 13&&neg_mcu_mdc is valid, the TA state is entered. The TA state is an optional example of the MDIO read-write conversion state. mdc_cnt represents the current accumulated number of falling edges of the MDC signal. neg_mcu_mdc can be an optional example of the current falling edge of the MDC signal. "&&" represents AND logic, which is not limited.

[0083] S404: If the number of falling edges is 13, and the second determination result indicates that the current falling edge of the MDC signal is valid, and the instruction value is the first value, it is determined that the control chip needs to be in clause 45 mode.

[0084] In some embodiments, the MDIO signal may include an instruction value. If it is confirmed that the second determination result indicates that the current falling edge of the MDC signal is valid, and the instruction value is the first value, which may be, for example, stcode==2'b00, then it is determined that the control chip needs to be in clause45 mode. For example, when it is determined that the number of falling edges is 13, and the second determination result indicates that the current falling edge of the MDC signal is valid, and stcode==2'b00, it is determined that the control chip needs to be in clause45 mode, and there is no limitation on this.

[0085] S405: If the number of falling edges is 13, and the second determination result indicates that the current falling edge of the MDC signal is valid, and the instruction value is the second value, it is determined that the control chip needs to be in clause 22 mode.

[0086] In some other embodiments, the MDIO signal may include an instruction value. If the number of falling edges is 13, and the second determination result indicates that the current falling edge of the MDC signal is valid, and the instruction value is confirmed to be the second value, then it is determined that the control chip needs to be in clause22 mode. The instruction value may be, for example, the value of the instruction bit stcode. The instruction value is the second value, which may be, for example, stcode==2'b01. Then, when it is determined that the number of falling edges is 13, and the second determination result indicates that the current falling edge of the MDC signal is valid, and stcode==2'b01, it is determined that the control chip needs to be in clause22 mode. There is no limitation on this.

[0087] In this embodiment, by receiving the clock signal line MDC signal and the data signal line MDIO signal of the control device, wherein the MDIO signal includes an instruction value, and the MDC signal has the current accumulated number of falling edges, it is determined whether the current falling edge of the MDC signal is valid, and a second determination result is obtained. If the number of falling edges is 13, and the second determination result indicates that the current falling edge of the MDC signal is valid, it is determined that the control chip needs to be in the MDIO read-write conversion state. It is achieved that the clock signal line MDC signal provided by the control device is effectively switched to the MDIO read-write conversion state. If the number of falling edges is 13, and the second determination result indicates that the current falling edge of the MDC signal is valid, and the instruction value is the first value, it is determined that the control chip needs to be in the clause45 mode; if the number of falling edges is 13, and the second determination result indicates that the current falling edge of the MDC signal is valid, and the instruction value is the second value, it is determined that the control chip needs to be in the clause22 mode. It is also possible to effectively switch to the clause45 mode or the clause22 mode according to the clock signal line MDC signal and the MDIO signal provided by the control device.

[0088] In some embodiments of the present disclosure, if the number of falling edges is 15, the instruction value indicates that the type of operation to be performed is the first type, and the second determination result indicates that the current falling edge of the MDC signal is valid, then it is determined that the control chip needs to be in a state of writing data to the PHY register, so as to effectively switch to the state of writing data to the PHY register according to the clock signal line MDC signal and MDIO signal provided by the control device.

[0089] For example, in clause45 mode, when mdc_cnt==15&&opcode==2'b01&&neg_mcu_mdc is valid, it jumps to REGWR (REGWR indicates the status of writing data to the PHY register). In clause45 mode, it indicates that the control chip is in clause45 mode, mdc_cnt indicates the current accumulated number of falling edges of the MDC signal, neg_mcu_mdc can be an optional example of the current falling edge of the MDC signal, "&&" indicates AND logic, the instruction value can be, for example, the value of the instruction bit opcode, the instruction value indicates that the type of operation to be performed is the first type, which can be, for example, based on setting opcode==2'b01, and there is no restriction on this.

[0090] For example, in clause22 mode, when mdc_cnt==15&&opcode==2'b01&&neg_mcu_mdc is valid, it jumps to REGWR. In clause22 mode, it indicates that the control chip is in clause22 mode, mdc_cnt indicates the current accumulated number of falling edges of the MDC signal, neg_mcu_mdc can be an optional example of the current falling edge of the MDC signal, "&&" indicates AND logic, the instruction value can be, for example, the value of the instruction bit opcode, the instruction value indicates that the type of operation to be performed is the first type, which can be, for example, based on setting opcode==2'b01, REGWR is an optional example of writing data status to the PHY register, and there is no restriction on this.

[0091] In some embodiments of the present disclosure, if the number of falling edges is 15, the instruction value indicates that the type of operation to be performed is the second type, and the second determination result indicates that the current falling edge of the MDC signal is valid, then it is determined that the control chip needs to be in the register address write state, wherein the control chip is already in clause45 mode, and the MDC signal and MDIO signal of the clock signal line provided by the control device are effectively switched to the register address write state.

[0092] For example, when mdc_cnt==15&&opcode==2'b00&&neg_mcu_mdc is valid, jump to REGAD (REGAD is an optional example of the register address write state. That is, REGAD can be used to represent the register address write state). In clause45 mode, it indicates that the control chip is in clause45 mode, mdc_cnt indicates the current accumulated number of falling edges of the MDC signal, neg_mcu_mdc can be an optional example of the current falling edge of the MDC signal, "&&" represents AND logic, the instruction value can be, for example, the value of the instruction bit opcode, the instruction value indicates that the type of operation to be performed is the second type, which can be, for example, based on setting opcode==2'b00, and there is no restriction on this.

[0093] In other embodiments of the present disclosure, if the control chip is already in clause22 mode and the number of falling edges is 15, the instruction value indicates that the type of operation to be performed is the second type, and the second determination result indicates that the current falling edge of the MDC signal is valid, it can be directly determined that it is in an idle state.

[0094] In some embodiments of the present disclosure, if the number of falling edges is 15, the instruction value indicates that the type of operation to be performed is the third type, and the third determination result indicates that the current rising edge of the MDC signal is valid, then it is determined that the control chip needs to be in the read PHY register data state, wherein the control chip is already in clause45 mode, and the MDC signal and MDIO signal of the clock signal line provided by the control device are effectively switched to the read PHY register data state.

[0095] For example, when mdc_cnt==15&&opcode==2'b11&&pos_mcu_mdc is valid, it jumps to REGRD (REGRD is an optional example of reading the data status of the PHY register). In clause45 mode, it indicates that the control chip is in clause45 mode, mdc_cnt indicates the current accumulated number of falling edges of the MDC signal, pos_mcu_mdc can be an optional example of the current rising edge of the MDC signal, "&&" indicates AND logic, the instruction value can be, for example, the value of the instruction bit opcode, the instruction value indicates that the type of operation to be performed is the third type, which can be, for example, based on setting opcode==2'b11, and there is no restriction on this.

[0096] In other embodiments of the present disclosure, if the control chip is already in clause22 mode and the number of falling edges is 15, the instruction value indicates that the type of operation to be performed is the third type, and the third determination result indicates that the current rising edge of the MDC signal is valid, then it is determined to be in an idle state.

[0097] In some embodiments of the present disclosure, if the number of falling edges is 15, the instruction value indicates that the type of operation to be performed is the fourth type, and the third determination result indicates that the current rising edge of the MDC signal is valid, then it is determined that the control chip needs to be in a continuous read register data state, wherein the control chip is already in clause45 mode, and when the control chip is already in clause45 mode, it is implemented to effectively switch to the continuous read register data state according to the clock signal line MDC signal and MDIO signal provided by the control device.

[0098] In some embodiments, when mdc_cnt==15&&opcode==2'b10&&pos_mcu_mdc is valid, jump to REGRD_INC. In clause45 mode, it indicates that the control chip is in clause45 mode. mdc_cnt indicates the current accumulated number of falling edges of the MDC signal. pos_mcu_mdc can be an optional example of the current rising edge of the MDC signal. "&&" indicates AND logic. The instruction value can be, for example, the value of the instruction bit opcode. The instruction value indicates that the type of operation to be performed is the fourth type, which can be, for example, implemented based on setting opcode==2'b10. REGRD_INC is an optional example of the continuous read register data state, and there is no limitation on this.

[0099] In other embodiments, if the number of falling edges is 15, the instruction value indicates that the type of operation to be performed is the fourth type, and the third determination result indicates that the current rising edge of the MDC signal is valid, then it is determined that the control chip needs to be in the state of reading PHY register data, wherein the control chip is already in clause22 mode, and when the control chip is already in clause22 mode, it is implemented to effectively switch to the state of reading PHY register data according to the clock signal line MDC signal and MDIO signal provided by the control device.

[0100] For example, in clause22 mode, when mdc_cnt==15&&opcode==2'b10&&pos_mcu_mdc is valid, jump to REGRD. In clause22 mode, it indicates that the control chip is in clause22 mode, mdc_cnt indicates the current accumulated number of falling edges of the MDC signal, pos_mcu_mdc can be an optional example of the current rising edge of the MDC signal, "&&" indicates AND logic, the instruction value can be, for example, the value of the instruction bit opcode, the instruction value indicates that the type of operation to be performed is the fourth type, which can be, for example, based on setting opcode==2'b10, REGRD is an optional example of reading the data status of the PHY register, and there is no restriction on this.

[0101] In some embodiments of the present disclosure, an optional example of a register address write state may be REGAD; an optional example of a PHY register write data state may be REGWR; an optional example of a PHY register read data state may be REGRD; an optional example of a continuous register read data state may be REGRD_INC, without limitation.

[0102] In some embodiments of the present disclosure, in order to improve the integrity of PHY state control, if the number of falling edges is 31, and the second determination result indicates that the current falling edge of the MDC signal is valid, it is determined that the control chip needs to be in an idle state, wherein the control chip is already in a state of writing data to a PHY register or a state of writing a register address, or, if the number of falling edges is 31, and the third determination result indicates that the current rising edge of the MDC signal is valid, it is determined that the control chip needs to be in an idle state, wherein the control chip is already in a state of continuously reading register data or a state of reading PHY register data, and there is no restriction on this.

[0103] For example, if the control chip is already in REGAD (an optional example of the register address write state), when mdc_cnt==31&&neg_mcu_mdc is valid, it jumps to IDLE (an optional example of the idle state), or, if the control chip is already in REGWR (an optional example of the state of writing data to the PHY register), when mdc_cnt==31&&neg_mcu_mdc is valid, it jumps to IDLE (an optional example of the idle state), and there is no restriction on this.

[0104] For example, if the control chip is already in REGRD (an optional example of the state of reading PHY register data), when mdc_cnt==31&&pos_mcu_mdc is valid, it jumps to IDLE (an optional example of the idle state); if the control chip is already in REGRD_INC (an optional example of the state of continuously reading register data), when mdc_cnt==31&&pos_mcu_mdc is valid, it jumps to IDLE state (an optional example of the idle state); there is no restriction on this.

[0105] It should be noted that, for the description of the methods that are the same as or corresponding to the above embodiments in the following embodiments, specific reference can be made to the above embodiments, which will not be repeated here.

[0106] Figure 5 It is a flowchart of a control method of an Ethernet physical layer transceiver PHY proposed in another embodiment of the present disclosure.

[0107] like Figure 5 As shown, the control method of the Ethernet physical layer transceiver PHY is executed by a control device, wherein the control device can be, for example, a central processing unit (CPU) or a microcontroller unit (MCU), without limitation. The method includes:

[0108] S501: Provide a clock signal line MDC signal and a data signal line MDIO signal to the control chip, wherein the MDIO signal includes an instruction value, and the MDC signal has the current accumulated number of falling edges. The MDIO signal, the instruction value, and the number of falling edges are used to determine the target working state that the control chip needs to be in.

[0109] In some embodiments, a control device may provide a clock signal line MDC signal and a data signal line MDIO signal to the FPGA to control the PHY based on the MDIO signal, the instruction value contained in the MDIO signal, and the current accumulated number of falling edges of the MDC signal, without limitation.

[0110] In this embodiment, the control device provides the control chip with a clock signal line MDC signal and a data signal line MDIO signal, wherein the MDIO signal includes an instruction value, the MDC signal has the current accumulated number of falling edges, and the MDIO signal, the instruction value, and the number of falling edges are used to determine the target working state that the control chip needs to be in. Therefore, when the external control device is used as the master control, it can support the control of PHY based on the signal provided by the control device, thereby effectively supporting the control device's demand for PHY control.

[0111] The control method of the Ethernet physical layer transceiver PHY provided in the embodiment of the present disclosure can solve the design requirement of an external control device to control PHY by switching the MDIO interface through a control chip. During the debugging process of the control chip, the control chip can also control PHY through internal software. The register transfer level (RTL) design language can be used to complete the control device-control chip-PHY switching solution to control the reading and writing functions of PHY.

[0112] It should be noted that the various target working states of the above-mentioned control chip can be, for example, any one of an idle state, an MDIO read / write mode detection state, a determination of the current MDIO read / write state, a PHY address resolution state, a device register state, an MDIO read / write conversion state, a clause45 mode, a clause22 mode, a register address write state, a PHY register write data state, a PHY register read data state, and a continuous register read data state, such as Figure 6 As shown, an example is given by taking the control chip as FPGA. Figure 6: is a schematic diagram of FPGA state switching in the embodiment of the present disclosure. The FPGA can be controlled to switch between different target working states based on the control device, so that the FPGA can control the PHY in the corresponding target working state. For example, it can switch sequentially between IDLE, ST, OP, PHYAD, DEVAD, and TA. The meanings of IDLE, ST, OP, PHYAD, DEVAD, and TA can be referred to the above embodiments, which will not be repeated here. If it is in TA, it can also be determined according to the instruction value stcode and opcode, the current accumulated number of falling edges of the MDC signal, the current falling edge of the MDC signal, and the current rising edge of the MDC signal to be in any one of REGWR, REGAD, REGRD-INC, and REGRD, and the FPGA can be controlled to switch from any one of REGWR, REGAD, REGRD-INC, and REGRD back to IDLE. The jump control logic between different target working states can be specifically referred to the above embodiments, which will not be repeated here.

[0113] Figure 7 It is a structural diagram of a control device for an Ethernet physical layer transceiver PHY proposed in an embodiment of the present disclosure.

[0114] like Figure 7 As shown, the device 70 includes:

[0115] The receiving module 701 is used to receive the clock signal line MDC signal and the data signal line MDIO signal of the control device, wherein the MDIO signal includes the instruction value and the MDC signal has the current accumulated number of falling edges.

[0116] The determination module 702 is used to determine whether the falling edge of the MDIO signal is currently detected to obtain a first determination result, determine whether the current falling edge of the MDC signal is valid to obtain a second determination result, and determine whether the current rising edge of the MDC signal is valid to obtain a third determination result.

[0117] The control module 703 is used to analyze at least one of the instruction value, the number of falling edges, the first determination result, the second determination result and the third determination result to determine the target working state that the control chip needs to be in, and control the control chip to switch to the target working state to control the PHY in the target working state.

[0118] It should be noted that the aforementioned explanation of the control method of the Ethernet physical layer transceiver PHY is also applicable to the control device of the Ethernet physical layer transceiver PHY of this embodiment, and will not be repeated here.

[0119] In this embodiment, by receiving the clock signal line MDC signal and the data signal line MDIO signal of the control device, wherein the MDIO signal includes an instruction value, the MDC signal has the current accumulated number of falling edges, and determining whether the falling edge of the MDIO signal is currently detected, a first determination result is obtained, and determining whether the current falling edge of the MDC signal is valid, a second determination result is obtained, and determining whether the current rising edge of the MDC signal is valid, a third determination result is obtained, and at least one of the instruction value, the number of falling edges, the first determination result, the second determination result, and the third determination result is analyzed to determine the target working state that the control chip needs to be in, and control the control chip to switch to the target working state, so as to control the PHY in the target working state. Therefore, when the external control device is used as the master control, it can support the control of the PHY based on the signal provided by the control device, thereby effectively supporting the control device's demand for PHY control.

[0120] Figure 8 It is a structural schematic diagram of a control device for an Ethernet physical layer transceiver PHY proposed in another embodiment of the present disclosure.

[0121] like Figure 8 As shown, the device 80 includes:

[0122] The sending module 801 is used to provide the clock signal line MDC signal and the data signal line MDIO signal to the control chip, wherein the MDIO signal includes an instruction value, and the MDC signal has the current accumulated number of falling edges. The MDIO signal, the instruction value and the number of falling edges are used to determine the target working state that the control chip needs to be in.

[0123] It should be noted that the aforementioned explanation of the control method of the Ethernet physical layer transceiver PHY is also applicable to the control device of the Ethernet physical layer transceiver PHY of this embodiment, and will not be repeated here.

[0124] In this embodiment, the control device provides the control chip with a clock signal line MDC signal and a data signal line MDIO signal, wherein the MDIO signal includes an instruction value, the MDC signal has the current accumulated number of falling edges, and the MDIO signal, the instruction value, and the number of falling edges are used to determine the target working state that the control chip needs to be in. Therefore, when the external control device is used as the master control, it can support the control of PHY based on the signal provided by the control device, thereby effectively supporting the control device's demand for PHY control.

[0125] Fig. 9 It is a structural diagram of a control system of an Ethernet physical layer transceiver PHY proposed in another embodiment of the present disclosure.

[0126] like Fig. 9As shown, the control system 90 of the Ethernet physical layer transceiver PHY includes: a control device 901, a control chip 902 connected to the control device 901, and a PHY903 connected to the control chip 902; wherein,

[0127] The control device 901 is used to provide a clock signal line MDC signal and a data signal line MDIO signal to the control chip 902, wherein the MDIO signal includes an instruction value and the MDC signal has a currently accumulated number of falling edges;

[0128] The control chip 902 is used to receive the clock signal line MDC signal and the data signal line MDIO signal of the control device, wherein the MDIO signal includes an instruction value, the MDC signal has the current accumulated number of falling edges, and determines whether the falling edge of the MDIO signal is currently detected to obtain a first determination result, and determines whether the current falling edge of the MDC signal is valid to obtain a second determination result, and determines whether the current rising edge of the MDC signal is valid to obtain a third determination result, and analyzes at least one of the instruction value, the number of falling edges, the first determination result, the second determination result and the third determination result to determine the target working state that the control chip 902 needs to be in, and controls the control chip 902 to switch to the target working state to control the PHY in the target working state.

[0129] In some embodiments of the present disclosure, Fig.10 As shown, Fig.10 This is a structural diagram of a control system of an Ethernet physical layer transceiver PHY proposed in another embodiment of the present disclosure, with the control chip being FPGA as an example. 88Q2122 refers to a PHY model, where the control device 901 and FPGA902 are connected via a first clock signal line MDC and a first data signal line MDIO, and the FPGA902 and PHY903 are connected via a second clock signal line MDC and a second data signal line MDIO; wherein,

[0130] The control device 901 uses the first clock signal line MDC to provide an MDC signal to the FPGA 902;

[0131] The control device 901 uses the first data signal line MDIO to provide an MDIO signal to the FPGA 902;

[0132] FPGA902 analyzes at least one of the instruction value, the number of falling edges, the first determination result, the second determination result and the third determination result to determine the target working state that the control chip needs to be in, and uses at least one of the first determination result, the second determination result and the third determination result to generate a clock control signal, uses the instruction value to generate a data control signal, and uses the second clock signal line MDC to provide a clock control signal to PHY903, and uses the second data signal line MDIO to provide a data control signal to PHY903 to control PHY903.

[0133] It should be noted that the aforementioned explanation of the control method of the Ethernet physical layer transceiver PHY is also applicable to the control system of the Ethernet physical layer transceiver PHY of this embodiment, and will not be repeated here.

[0134] In this embodiment, the control chip can receive the clock signal line MDC signal and the data signal line MDIO signal of the control device, wherein the MDIO signal includes an instruction value, the MDC signal has the current accumulated number of falling edges, and determines whether the falling edge of the MDIO signal is currently detected to obtain a first determination result, and determines whether the current falling edge of the MDC signal is valid to obtain a second determination result, determines whether the current rising edge of the MDC signal is valid to obtain a third determination result, and analyzes at least one of the instruction value, the number of falling edges, the first determination result, the second determination result, and the third determination result to determine the target working state that the control chip needs to be in, and controls the control chip to switch to the target working state to control the PHY in the target working state. Therefore, when the external control device is used as the master control, it can support the control of the PHY based on the signal provided by the control device, thereby effectively supporting the control device's demand for PHY control.

[0135] Fig.11 A block diagram of an exemplary electronic device suitable for implementing embodiments of the present disclosure is shown. Fig.11 The electronic device 12 shown is only an example and should not bring any limitation to the functions and scope of use of the embodiments of the present disclosure.

[0136] like Fig.11 As shown, the electronic device 12 is in the form of a general purpose computing device. The components of the electronic device 12 may include, but are not limited to: one or more processors or processing units 16, a memory 28, and a bus 18 that connects various system components (including the memory 28 and the processing unit 16).

[0137] The bus 18 represents one or more of several types of bus structures, including a memory bus or memory controller, a peripheral bus, a graphics acceleration port, a processor or a local bus using any of a variety of bus structures. For example, these architectures include but are not limited to Industry Standard Architecture (ISA) bus, Micro Channel Architecture (MAC) bus, Enhanced ISA bus, Video Electronics Standards Association (VESA) local bus and Peripheral Component Interconnection (PCI) bus.

[0138] The electronic device 12 typically includes a variety of computer system readable media. These media can be any available media that can be accessed by the electronic device 12, including volatile and non-volatile media, removable and non-removable media.

[0139] The memory 28 may include computer system readable media in the form of volatile memory, such as random access memory (RAM) 30 and / or cache 32. The electronic device 12 may further include other removable / non-removable, volatile / non-volatile computer system storage media. By way of example only, the storage system 34 may be used to read and write non-removable, non-volatile magnetic media ( Fig.11 Not shown, often called a "hard drive").

[0140] although Fig.11 Not shown in the figure, a disk drive for reading and writing a removable non-volatile disk (e.g., a "floppy disk"), and an optical disk drive for reading and writing a removable non-volatile optical disk (e.g., a compact disc read only memory (hereinafter referred to as: CD-ROM), a digital versatile disc read only memory (hereinafter referred to as: DVD-ROM) or other optical media) may be provided. In these cases, each drive may be connected to the bus 18 via one or more data medium interfaces. The memory 28 may include at least one program product having a set (e.g., at least one) of program modules that are configured to perform the functions of the various embodiments of the present disclosure.

[0141] A program / utility 40 having a set (at least one) of program modules 42 may be stored, for example, in the memory 28, such program modules 42 including but not limited to an operating system, one or more application programs, other program modules, and program data, each of which or some combination may include an implementation of a network environment. The program modules 42 generally perform the functions and / or methods of the embodiments described in the present disclosure.

[0142] The electronic device 12 may also communicate with one or more external devices 14 (e.g., keyboard, pointing device, display 24, etc.), may also communicate with one or more devices that enable the human body to interact with the electronic device 12, and / or communicate with any device that enables the electronic device 12 to communicate with one or more other computing devices (e.g., network card, modem, etc.). Such communication may be performed through an input / output (I / O) interface 22. In addition, the electronic device 12 may also communicate with one or more networks (e.g., a local area network (LAN), a wide area network (WAN), and / or a public network, such as the Internet) through a network adapter 20. As shown, the network adapter 20 communicates with other modules of the electronic device 12 through a bus 18. It should be understood that, although not shown in the figure, other hardware and / or software modules may be used in conjunction with the electronic device 12, including but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data backup storage systems.

[0143] The processing unit 16 executes various functional applications and data processing by running the programs stored in the memory 28, such as implementing the control method of the Ethernet physical layer transceiver PHY mentioned in the above embodiment.

[0144] In order to implement the above embodiments, the present disclosure further proposes a non-temporary computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the control method of the Ethernet physical layer transceiver PHY proposed in the above embodiments of the present disclosure.

[0145] In order to implement the above embodiments, the present disclosure further proposes a computer program product. When the instructions in the computer program product are executed by a processor, the control method of the Ethernet physical layer transceiver PHY proposed in the above embodiments of the present disclosure is executed.

[0146] It should be noted that, in the description of the present disclosure, the terms "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance. In addition, in the description of the present disclosure, unless otherwise specified, the meaning of "plurality" is two or more.

[0147] Any process or method description in a flowchart or otherwise described herein may be understood to represent a module, segment or portion of code that includes one or more executable instructions for implementing the steps of a specific logical function or process, and the scope of the preferred embodiments of the present disclosure includes alternative implementations in which functions may not be performed in the order shown or discussed, including performing functions in a substantially simultaneous manner or in the reverse order depending on the functions involved, which should be understood by those skilled in the art to which the embodiments of the present disclosure belong.

[0148] It should be understood that the various parts of the present disclosure can be implemented in hardware, software, firmware or a combination thereof. In the above-mentioned embodiments, multiple steps or methods can be implemented in software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, it can be implemented by any one of the following technologies known in the art or their combination: a discrete logic circuit having a logic gate circuit for implementing a logic function for a data signal, a dedicated integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

[0149] A person skilled in the art may understand that all or part of the steps in the method for implementing the above-mentioned embodiment may be completed by instructing related hardware through a program, and the program may be stored in a computer-readable storage medium, which, when executed, includes one or a combination of the steps of the method embodiment.

[0150] In addition, each functional unit in each embodiment of the present disclosure may be integrated into a processing module, or each unit may exist physically separately, or two or more units may be integrated into one module. The above-mentioned integrated module may be implemented in the form of hardware or in the form of a software functional module. If the integrated module is implemented in the form of a software functional module and sold or used as an independent product, it may also be stored in a computer-readable storage medium.

[0151] The storage medium mentioned above can be a read-only memory, a magnetic disk or an optical disk, etc.

[0152] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present disclosure. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0153] Although the embodiments of the present disclosure have been shown and described above, it is to be understood that the above embodiments are exemplary and are not to be construed as limitations of the present disclosure. A person skilled in the art may change, modify, replace and vary the above embodiments within the scope of the present disclosure.

Claims

1. A control method for an Ethernet physical layer transceiver PHY, characterized in that: The method comprises: Receive a clock signal line MDC signal and a data signal line MDIO signal of a control device, wherein the MDIO signal includes an instruction value, and the MDC signal has a currently accumulated number of falling edges; Determine whether a falling edge of the MDIO signal is currently detected to obtain a first determination result, determine whether a current falling edge of the MDC signal is valid to obtain a second determination result, and determine whether a current rising edge of the MDC signal is valid to obtain a third determination result; Analyze at least one of the command value, the number of falling edges, the first determination result, the second determination result, and the third determination result to determine a target working state that the control chip needs to be in; The control chip is controlled to switch to the target working state, so as to control the PHY in the target working state.

2. The method according to claim 1, characterized in that The analyzing at least one of the command value, the number of falling edges, the first determination result, the second determination result, and the third determination result to determine the target working state that the control chip needs to be in includes: If the first determination result indicates that a falling edge of the MDIO signal is currently detected, and the instruction value is used to set the shift register to a first value, it is determined that the control chip needs to be in an MDIO read / write mode detection state.

3. The method according to claim 1, characterized in that The analyzing at least one of the command value, the number of falling edges, the first determination result, the second determination result, and the third determination result to determine the target working state that the control chip needs to be in includes: If the number of falling edges is 1, and the second determination result indicates that the current falling edge of the MDC signal is valid, it is determined that the control chip needs to be in the MDIO current read and write state.

4. The method according to claim 1, characterized in that The analyzing at least one of the command value, the number of falling edges, the first determination result, the second determination result, and the third determination result to determine the target working state that the control chip needs to be in includes: If the number of falling edges is 3, and the second determination result indicates that the current falling edge of the MDC signal is valid, it is determined that the control chip needs to be in a PHY address resolution state.

5. The method according to claim 1, characterized in that The analyzing at least one of the command value, the number of falling edges, the first determination result, the second determination result, and the third determination result to determine the target working state that the control chip needs to be in includes: If the number of falling edges is 8, and the second determination result indicates that the current falling edge of the MDC signal is valid, it is determined that the control chip needs to be in a device register state.

6. The method according to claim 1, characterized in that The analyzing at least one of the command value, the number of falling edges, the first determination result, the second determination result, and the third determination result to determine the target working state that the control chip needs to be in includes any of the following: If the number of falling edges is 13, and the second determination result indicates that the current falling edge of the MDC signal is valid, it is determined that the control chip needs to be in the MDIO read-write conversion state; If the number of falling edges is 13, and the second determination result indicates that the current falling edge of the MDC signal is valid, and the instruction value is the first value, it is determined that the control chip needs to be in clause 45 mode; If the number of falling edges is 13, and the second determination result indicates that the current falling edge of the MDC signal is valid, and the instruction value is the second value, it is determined that the control chip needs to be in clause 22 mode.

7. The method according to claim 1, characterized in that The analyzing at least one of the command value, the number of falling edges, the first determination result, the second determination result, and the third determination result to determine the target working state that the control chip needs to be in includes: If the number of falling edges is 15, the instruction value indicates that the type of operation to be performed is the first type, and the second determination result indicates that the current falling edge of the MDC signal is valid, it is determined that the control chip needs to be in a state of writing data to the PHY register.

8. The method according to claim 1, characterized in that The analyzing at least one of the command value, the number of falling edges, the first determination result, the second determination result, and the third determination result to determine the target working state that the control chip needs to be in includes: If the number of falling edges is 15, the instruction value indicates that the type of operation to be performed is the second type, and the second determination result indicates that the current falling edge of the MDC signal is valid, then it is determined that the control chip needs to be in the register address write state, wherein the control chip is already in clause45 mode.

9. The method according to claim 1, characterized in that The analyzing at least one of the command value, the number of falling edges, the first determination result, the second determination result, and the third determination result to determine the target working state that the control chip needs to be in includes: If the number of falling edges is 15, the instruction value indicates that the type of operation to be performed is the third type, and the third determination result indicates that the current rising edge of the MDC signal is valid, then it is determined that the control chip needs to be in the state of reading PHY register data, wherein the control chip is already in clause45 mode.

10. The method according to claim 1, characterized in that The analyzing at least one of the command value, the number of falling edges, the first determination result, the second determination result, and the third determination result to determine the target working state that the control chip needs to be in includes: If the number of falling edges is 15, the instruction value indicates that the type of operation to be performed is the fourth type, and the third determination result indicates that the current rising edge of the MDC signal is valid, it is determined that the control chip needs to be in a continuous read register data state, wherein the control chip is already in clause 45 mode; If the number of falling edges is 15, the instruction value indicates that the type of operation to be performed is the fourth type, and the third determination result indicates that the current rising edge of the MDC signal is valid, then it is determined that the control chip needs to be in the state of reading PHY register data, wherein the control chip is already in clause22 mode.

11. The method according to any one of claims 7 to 10, characterized in that: The analyzing at least one of the command value, the number of falling edges, the first determination result, the second determination result, and the third determination result to determine the target working state that the control chip needs to be in includes: If the number of falling edges is 31, and the second determination result indicates that the current falling edge of the MDC signal is valid, it is determined that the control chip needs to be in an idle state, wherein the control chip is already in a state of writing data to a PHY register or a state of writing a register address; If the number of falling edges is 31, and the third determination result indicates that the current rising edge of the MDC signal is valid, it is determined that the control chip needs to be in the idle state, wherein the control chip is already in a continuous read register data state or a read PHY register data state.

12. A control method for an Ethernet physical layer transceiver PHY, characterized in that: The method comprises: A clock signal line MDC signal and a data signal line MDIO signal are provided to the control chip, wherein the MDIO signal includes an instruction value, the MDC signal has a currently accumulated number of falling edges, and the MDIO signal, the instruction value and the number of falling edges are used to determine a target working state that the control chip needs to be in.

13. A control device for an Ethernet physical layer transceiver PHY, characterized in that: The device comprises: A receiving module, used for receiving a clock signal line MDC signal and a data signal line MDIO signal of a control device, wherein the MDIO signal includes an instruction value, and the MDC signal has a currently accumulated number of falling edges; a determination module, configured to determine whether a falling edge of the MDIO signal is currently detected to obtain a first determination result, determine whether a current falling edge of the MDC signal is valid to obtain a second determination result, and determine whether a current rising edge of the MDC signal is valid to obtain a third determination result; and A control module is used to analyze at least one of the instruction value, the number of falling edges, the first determination result, the second determination result and the third determination result to determine the target working state that the control chip needs to be in, and control the control chip to switch to the target working state to control the PHY in the target working state.

14. A control device for an Ethernet physical layer transceiver PHY, characterized in that: The device comprises: A sending module is used to provide a clock signal line MDC signal and a data signal line MDIO signal to the control chip, wherein the MDIO signal includes an instruction value, the MDC signal has a currently accumulated number of falling edges, and the MDIO signal, the instruction value and the number of falling edges are used to determine the target working state that the control chip needs to be in.

15. A control system for an Ethernet physical layer transceiver PHY, characterized in that: include: A control device, a control chip connected to the control device, and the PHY connected to the control chip; wherein, The control device is used to provide a clock signal line MDC signal and a data signal line MDIO signal to the control chip, wherein the MDIO signal includes an instruction value, and the MDC signal has a currently accumulated number of falling edges; The control chip is used to receive a clock signal line MDC signal and a data signal line MDIO signal of a control device, wherein the MDIO signal includes an instruction value, and the MDC signal has a currently accumulated number of falling edges, and determines whether a falling edge of the MDIO signal is currently detected to obtain a first determination result, and determines whether a current falling edge of the MDC signal is valid to obtain a second determination result, and determines whether a current rising edge of the MDC signal is valid to obtain a third determination result, and analyzes at least one of the instruction value, the number of falling edges, the first determination result, the second determination result, and the third determination result to determine a target working state that the control chip needs to be in, and controls the control chip to switch to the target working state to control the PHY in the target working state.

16. The control system according to claim 15, characterized in that: The control device and the control chip are connected via a first clock signal line MDC and a first data signal line MDIO, and the control chip and the PHY are connected via a second clock signal line MDC and a second data signal line MDIO; wherein, The control device uses the first clock signal line MDC to provide the MDC signal to the control chip; The control device uses the first data signal line MDIO to provide the MDIO signal to the control chip; The control chip analyzes the instruction value, the number of falling edges, the first determination result, the second determination result and at least one of the third determination results to determine the target working state that the control chip needs to be in, and uses at least one of the first determination result, the second determination result and the third determination result to generate a clock control signal, uses the instruction value to generate a data control signal, and uses the second clock signal line MDC to provide the clock control signal to the PHY, and uses the second data signal line MDIO to provide the data control signal to the PHY to control the PHY.

17. An electronic device, characterized in that: include: A control system for an Ethernet physical layer transceiver PHY as claimed in any one of claims 15 to 16.

18. A non-transitory computer-readable storage medium storing computer instructions, characterized in that: in, The computer instructions are used to cause the computer to execute the method according to any one of claims 1 to 12.

19. A computer program product, characterized in that The invention comprises a computer program which, when executed by a processor, implements the steps of the method according to any one of claims 1 to 12.

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