Preparation technology of fast recovery diode with high voltage and fast recovery diode

Abstract

The embodiment of the invention provides a preparation process of a high-voltage fast recovery diode and the fast recovery diode, and the process comprises the steps: carrying out the dry etching of a third oxide layer, a fourth oxide layer and a fifth oxide layer until side wall regions are formed on the side walls, close to a third injection region, of a first oxide layer and a second oxide layer; the step of contact hole photoetching in the prior art can be reduced, so that the cost is reduced, and the fast recovery diode with high voltage and fast recovery characteristics is realized.

Description

Technical Field

[0001] The embodiments of the present application belong to the field of semiconductor technology, and more particularly to a preparation process of a high-voltage fast recovery diode and a fast recovery diode. Background Art

[0002] The main performance parameters of fast recovery diodes are high voltage and short reverse recovery time. Currently, in addition to epitaxy, high voltage can also be improved through terminal structure; reverse recovery time is achieved by controlling the minority carrier lifetime and forming recombination centers in the drift region of the device through platinum diffusion, electron irradiation or hydrogen (helium) injection to reduce the minority carrier lifetime.

[0003] The specific process example of the current fast recovery diode device manufacturing process is as follows: N-type substrate preparation → thermal oxide layer growth field oxygen → GR photolithography, corrosion, photoresist removal → GR injection, oxidation diffusion → AA photolithography corrosion, photoresist removal → P well injection, P push → N+ photolithography, corrosion, injection, photoresist removal → dielectric layer deposition (TEOS + silicon nitride + BPSG) → contact hole lithography, wet etching + dry etching, photoresist removal → dielectric layer reflow → platinum source coating → platinum diffusion → aqua regia cleaning → metal deposition → metal lithography, etching, photoresist removal → passivation layer deposition → passivation layer lithography, etching, photoresist removal → back thinning back gold.

[0004] The structure of the fast recovery diode currently using the above manufacturing process is shown below Figure 1 As shown:

[0005] It can be seen from the above process flow and structural schematic diagram that the dielectric layer has three layers, namely the first oxide layer C, the silicon nitride layer B, and the third oxide layer A (doped with phosphorus and boron). When etching the contact holes, the third oxide layer is first wet-etched, and then the silicon nitride and the first oxide layer are dry-etched. The process is long and the cost is relatively high. Summary of the invention

[0006] In order to solve or alleviate the problems in the prior art, an embodiment of the present invention provides a preparation process of a high-voltage fast recovery diode and a fast recovery diode.

[0007] In a first aspect, an embodiment of the present application provides a preparation process of a high voltage fast recovery diode, comprising:

[0008] Growing a first oxide layer on the upper surface of the wafer, and performing photolithography on the first oxide layer to obtain a first opening;

[0009] Performing a first ion implantation on the wafer at a position corresponding to the first opening to form a first implantation region having a first doping type;

[0010] Generating a second oxide layer on the upper surface of the wafer at a position corresponding to the first opening and on the upper surface of the first oxide layer;

[0011] Performing photolithography on the first oxide layer and the second oxide layer on one side of the first injection region to remove the first oxide layer and the second oxide layer on the upper surface of the wafer, and first growing a third oxide layer on the upper surface of the wafer from which the first oxide layer and the second oxide layer are removed;

[0012] Performing a second ion implantation in the area where the third oxide layer is located to form a second implantation area having the first doping type, wherein the second implantation area has an overlapping area with the first implantation area, wherein the wafer has the second doping type;

[0013] Performing photolithography on the first oxide layer and the second oxide layer on a side of the first injection region away from the second injection region to remove the first oxide layer and the second oxide layer on the upper surface of the wafer, and performing a third ion implantation in the region where the first oxide layer and the second oxide layer are removed to form a third injection region having a second doping type;

[0014] Performing a drive-in process on the third implantation region, and forming a fourth oxide layer on the upper surface of the wafer where the third implantation region is located;

[0015] Depositing a fifth oxide layer on the upper surfaces of the second oxide layer, the third oxide layer and the fourth oxide layer;

[0016] Dry-etching the third oxide layer, the fourth oxide layer, and the fifth oxide layer until a sidewall region is formed on the sidewalls of the first oxide layer and the second oxide layer close to the third implantation region;

[0017] After removing the metal layers deposited on the upper surfaces of the third oxide layer, the fourth oxide layer and the fifth oxide layer wafer and the upper surface of the second oxide layer, photolithography is performed on the metal layers corresponding to the areas where the first injection area and the third injection area are located to form a second opening;

[0018] A passivation layer is deposited on the upper surface of the metal layer, and the passivation layer is photoetched to form a third opening in the partial area where the first injection area is located, and an electrode is led out through the third opening.

[0019] As a preferred embodiment of the present application, the first implantation region and the second implantation region are of P-type doping type, and the third implantation region and the wafer are of N-type doping type.

[0020] As a preferred embodiment of the present application, the impurities injected into the first injection region and the second injection region are elemental boron, the energy range of the boron element injected into the first injection region is 100KeV~500KeV, and the injection dose range is 5E12~5E13; the energy range of the boron element injected into the second injection region is 30KeV~120KeV, and the injection dose range is 1E13~1E14.

[0021] As a preferred embodiment of the present application, after forming the first implantation region, the method includes:

[0022] The first injection region is subjected to a driving treatment, the driving temperature is 1100° C. to 1250° C., the driving time is 200 minutes to 480 minutes, and the thickness of the second injection region is 6 to 12 microns.

[0023] As a preferred embodiment of the present application, after forming the second implantation region, the method further includes:

[0024] The second implantation region is subjected to a driving treatment, the driving temperature is 1050° C. to 1200° C., the driving time is 60 minutes to 180 minutes, and the junction depth of the third implantation region is about 4 to 8 microns.

[0025] As a preferred embodiment of the present application, the thickness of the first oxide layer is 6000A~14000A, the thickness of the second oxide layer is 15kA~20kA, the thickness of the fourth oxide layer is 150A~350A, and the thickness of the fifth oxide layer is 1500A~3000A.

[0026] As a preferred embodiment of the present application, after the first oxide layer and the second oxide layer form a sidewall region near the sidewall of the third implantation region, the method includes:

[0027] A metal ion sputtering process is performed to form metal ions in the wafer.

[0028] As a preferred embodiment of the present application, after photolithography is performed on the sixth oxide layer to form a third opening in the partial region where the first implantation region is located, the method includes:

[0029] The back side of the wafer is thinned, and then a second metal layer is disposed on the back side of the wafer.

[0030] Compared with the prior art, the embodiment of the present application reduces the need for contact hole lithography as in the prior art by dry-etching the third oxide layer, the fourth oxide layer and the fifth oxide layer until a sidewall region is formed on the sidewalls of the first oxide layer and the second oxide layer near the third injection region, thereby reducing costs and realizing a fast recovery diode with high voltage and fast recovery characteristics.

[0031] In a second aspect, an embodiment of the present application further provides a high voltage fast recovery diode, which is prepared by the preparation process described in any one of the first aspects.

[0032] Compared with the prior art, the beneficial effects of the high-voltage fast recovery diode in the embodiment of the present application are the same as the beneficial effects of the technical solution provided in the first aspect, which will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. Some specific embodiments of the present application will be described in detail in an illustrative and non-restrictive manner with reference to the drawings. The same reference numerals in the drawings indicate the same or similar components or parts. It should be understood by those skilled in the art that these drawings are not necessarily drawn to scale. In the drawings: Figure 1 It is a structural schematic diagram of a high voltage fast recovery diode provided by the prior art; Figure 2 It is a schematic diagram of a process flow of preparing a high voltage fast recovery diode provided in an embodiment of the present application; Figure 3-Figure 15 It is a structural schematic diagram of each step of a preparation process of a high-voltage fast recovery diode provided in an embodiment of the present application. DETAILED DESCRIPTION

[0037] In order to enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only embodiments of a part of the present application, not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work should fall within the scope of protection of the present application.

[0038] In a first aspect, an embodiment of the present application provides a preparation process of a high voltage fast recovery diode, comprising:

[0039] Step S01, growing a first oxide layer 02 on the upper surface of a wafer 01, and performing photolithography on the first oxide layer 02 to obtain a first opening 03;

[0040] It should be noted that the reference Figure 2 and Figure 3, a first oxide layer 02 with a thickness of 6000A to 14000A is thermally oxidized on the single crystal silicon wafer 01, a photolithography is performed, and then a wet etching is performed to obtain a first opening 03, and finally the photoresist is removed. The first oxide layer 02 mainly plays a role in passivating the surface of the wafer 01, and the first opening 03 is formed by etching mainly for ion implantation in the wafer 01 at the position corresponding to the first opening 03.

[0041] Step S02, performing a first ion implantation on the wafer 01 at a position corresponding to the first opening 03 to form a first implantation region 04 having a first doping type;

[0042] It should be noted that the reference Figure 2 and Figure 4 In the embodiment of the present application, P-type ion implantation is performed in the first implantation region 04, the ion implantation is mainly boron element, the boron element implantation energy range is 100KeV~500KeV, and the implantation dose range is 5E12~5E13.

[0043] After forming the first implantation region 04, the method further includes:

[0044] The first implantation region 04 is subjected to a driving treatment, the driving temperature is 1100° C. to 1250° C., the driving time is 200 minutes to 480 minutes, and the junction depth of the first implantation region 04 is 6 to 12 microns.

[0045] Step S03, reference Figure 2 and Figure 5 , forming a second oxide layer 05 on the upper surface of the wafer 01 and the upper surface of the first oxide layer 02 at the position corresponding to the first opening 03;

[0046] It should be noted that the oxidation temperature of the second oxide layer 05 is 1000° C. to 1100° C., and the thickness is 15 kA to 20 kA. The second oxide layer 05 mainly serves to passivate the upper surface of the wafer 01 where the first implantation region 04 is located.

[0047] Step S04, performing photolithography on the first oxide layer 02 and the second oxide layer 05 on one side of the first injection region 04 to remove the first oxide layer 02 and the second oxide layer 05 on the upper surface of the wafer 01, and first growing a third oxide layer 06 on the upper surface of the wafer 01 from which the first oxide layer 02 and the second oxide layer 05 are removed;

[0048] It should be noted that the reference Figure 2 , Figure 6 and Figure 7In order to inject the second injection area 07, it is necessary to perform photolithography on the first oxide layer 02 and the second oxide layer 05 on one side of the first injection area 04 to remove the first oxide layer 02 and the second oxide layer 05 on the upper surface of the wafer 01. In order to protect the upper surface of the wafer 01, a third oxide layer 06 is pre-grown.

[0049] Step S05, performing a second ion implantation in the area where the third oxide layer 06 is located to form a second implantation area 07 having the first doping type, wherein the second implantation area 07 has an overlapping area with the first implantation area 04, wherein the wafer 01 has the second doping type;

[0050] It should be noted that the reference Figure 2 and Figure 8 , P-type ion implantation is performed to form a second implantation region 07. The ion implantation is mainly of boron element. The energy range of the implanted boron element is 30KeV to 120KeV, and the implantation dose range is 1E13 to 1E14.

[0051] After forming the second implantation region 07, the method further includes:

[0052] The second injection zone 07 is subjected to a driving treatment, the driving temperature is 1050° C. to 1200° C., and the driving time is 60 minutes to 180 minutes.

[0053] In the embodiment of the present application, the first injection region 04 and the second injection region 07 have the same doping type, both of which are P-type, and the first injection region 04 and the second injection region 07 have an overlapping area.

[0054] Step S06, performing photolithography on the first oxide layer 02 and the second oxide layer 05 on the side of the first implantation region 04 away from the second implantation region 07 to remove the first oxide layer 02 and the second oxide layer 05 on the upper surface of the wafer 01, and performing a third ion implantation in the area where the first oxide layer 02 and the second oxide layer 05 are removed to form a third implantation region 08 having a second doping type;

[0055] It should be noted that reference Figure 2 and Fig. 9 In order to form the third injection region 08, it is necessary to perform photolithography on the first oxide layer 02 and the second oxide layer 05 on the side of the first injection region 04 away from the second injection region 07 to remove the first oxide layer 02 and the second oxide layer 05 on the upper surface of the wafer 01. The third injection is N-type, and the third injection region 08 is the cut-off ring of the fast recovery diode.

[0056] Step S07, performing a driving process on the third implantation region 08, and forming a fourth oxide layer 09 on the upper surface of the wafer 01 where the third implantation region 08 is located;

[0057] It should be noted that the reference Figure 2 and Fig.10 , the third injection region 08 also needs to be pushed forward, and the side of the third injection region 08 close to the first injection region 04 extends toward the first injection region 04. Then, oxygen is passed through to form a fourth oxide layer 09 with a thickness of 150A to 350A on the upper surface of the wafer 01. The first oxide layer 02 is mainly used to passivate the upper surface of the wafer 01 where the third injection region 08 is located.

[0058] Step S08, depositing a fifth oxide layer 10 on the second oxide layer 05, the third oxide layer 06 and the fourth oxide layer 09;

[0059] It should be noted that the reference Figure 2 and Fig.11 Then, a fifth oxide layer 10 needs to be deposited on the second oxide layer 05, the third oxide layer 06 and the fourth oxide layer 09. The thickness of the fifth oxide layer 10 is 1500A to 3000A. The fifth oxide layer 10 is deposited by a vapor phase chemical deposition method. The fifth oxide layer 10 is mainly used to prepare for the formation of an oxide layer sidewall 11.

[0060] Step S09, dry-etching the third oxide layer 06, the fourth oxide layer 09 and the fifth oxide layer 10 until a sidewall region 11 is formed on the sidewalls of the first oxide layer 02 and the second oxide layer 05 close to the third implantation region 08;

[0061] It should be noted that the reference Figure 2 and Fig.12 By dry etching an oxide layer with a thickness of 2500 Å to 4000 Å, an oxide layer sidewall 11 is formed on the sidewalls of the first oxide layer 02 and the second oxide layer 05 close to the third implantation region 08 .

[0062] The embodiment of the present application performs dry etching on the third oxide layer, the fourth oxide layer and the fifth oxide layer until a sidewall region is formed on the sidewall of the first oxide layer and the second oxide layer near the third injection region, thereby reducing the need for contact hole lithography as in the prior art, thereby reducing costs and realizing a fast recovery diode with high voltage and fast recovery characteristics.

[0063] As a preferred embodiment of this application, refer to Figure 2 and Fig.13 After the first oxide layer 02 and the second oxide layer 05 form a sidewall region 11 near the sidewall of the third implantation region 08, the method includes:

[0064] A metal ion 14 sputtering process is performed to form metal ions 14 in the wafer 01 .

[0065] In the embodiment of the present application, the metal ion 14 is metal platinum. The metal ion 14 is formed in the wafer 01 by sputtering the metal platinum and then diffusing the metal platinum.

[0066] Step S10, depositing a first metal layer 12 on the upper surface of the wafer 01 and the upper surface of the second oxide layer 05 after removing the third oxide layer 06, the fourth oxide layer 09 and the fifth oxide layer 10, and performing photolithography to form a second opening 13 in the first metal layer 12 corresponding to the first injection area 04 and the third injection area 08;

[0067] It should be noted that the reference Figure 2 , Fig.14 and Fig.15 The second opening 13 is formed through this step, mainly to isolate the circuit inside the wafer 01 so as not to lead out.

[0068] Step S11 , depositing a sixth oxide layer on the upper surface of the metal layer, and photolithography the sixth oxide layer to form a third opening 16 in the partial area where the first injection region 04 is located, and leading out the electrode through the third opening 16 .

[0069] It should be noted that the circuit inside the wafer 01 can be led out through the third opening.

[0070] Step S12 , thinning the back side of the wafer 01 , and then disposing a second metal layer on the back side of the wafer 01 .

[0071] In a second aspect, an embodiment of the present application further provides a high voltage fast recovery diode, which is prepared by the preparation process described in any one of the first aspects.

[0072] Compared with the prior art, the beneficial effects of the high-voltage fast recovery diode in the embodiment of the present application are the same as the beneficial effects of the technical solution provided in the first aspect, which will not be repeated here.

[0073] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit it. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A process for preparing a high voltage fast recovery diode, characterized in that: include: Growing a first oxide layer on the upper surface of the wafer, and performing photolithography on the first oxide layer to obtain a first opening; Performing a first ion implantation on the wafer at a position corresponding to the first opening to form a first implantation region having a first doping type; Generating a second oxide layer on the upper surface of the wafer at a position corresponding to the first opening and on the upper surface of the first oxide layer; Performing photolithography on the first oxide layer and the second oxide layer on one side of the first injection region to remove the first oxide layer and the second oxide layer on the upper surface of the wafer, and first growing a third oxide layer on the upper surface of the wafer from which the first oxide layer and the second oxide layer are removed; Performing a second ion implantation in the area where the third oxide layer is located to form a second implantation area having the first doping type, wherein the second implantation area has an overlapping area with the first implantation area, wherein the wafer has the second doping type; Performing photolithography on the first oxide layer and the second oxide layer on a side of the first injection region away from the second injection region to remove the first oxide layer and the second oxide layer on the upper surface of the wafer, and performing a third ion implantation in the region where the first oxide layer and the second oxide layer are removed to form a third injection region having a second doping type; Performing a drive-in process on the third implantation region, and forming a fourth oxide layer on the upper surface of the wafer where the third implantation region is located; Depositing a fifth oxide layer on the upper surfaces of the second oxide layer, the third oxide layer and the fourth oxide layer; Dry-etching the third oxide layer, the fourth oxide layer, and the fifth oxide layer until a sidewall region is formed on the sidewalls of the first oxide layer and the second oxide layer close to the third implantation region; After removing the first metal layer deposited on the upper surface of the third oxide layer, the fourth oxide layer and the fifth oxide layer wafer and the upper surface of the second oxide layer, photolithography is performed on the first metal layer corresponding to the area where the first injection area and the third injection area are located to form a second opening; A sixth oxide layer is deposited on the upper surface of the first metal layer, and the sixth oxide layer is photoetched to form a third opening in a partial area where the first injection region is located, and an electrode is led out through the third opening.

2. A process for preparing a high voltage fast recovery diode as claimed in claim 1, characterized in that: The first implantation region and the second implantation region are of P-type doping type, and the third implantation region and the wafer are of N-type doping type.

3. A process for preparing a high voltage fast recovery diode as claimed in claim 2, characterized in that: The impurities doped into the first and second injection regions are elemental boron. The boron energy range of the first injection region is 100KeV to 500KeV, and the injection dose range is 5E12 to 5E13. The boron energy range of the second injection region is 30KeV to 120KeV, and the injection dose range is 1E13 to 1E14.

4. A process for preparing a high voltage fast recovery diode as claimed in claim 1, characterized in that: After forming the first implantation region, the method comprises: The first injection region is subjected to a driving treatment, the driving temperature is 1100° C. to 1250° C., the driving time is 200 minutes to 480 minutes, and the thickness of the second injection region is 6 to 12 microns.

5. A process for preparing a high voltage fast recovery diode as claimed in claim 1, characterized in that: After forming the second implantation region, the method further comprises: The second implantation region is subjected to a driving treatment, the driving temperature is 1050° C. to 1200° C., the driving time is 60 minutes to 180 minutes, and the junction depth of the third implantation region is about 4 to 8 microns.

6. A process for preparing a high voltage fast recovery diode as claimed in claim 1, characterized in that: The thickness of the first oxide layer is 6000A-14000A, the thickness of the second oxide layer is 15kA-20kA, the thickness of the fourth oxide layer is 150A-350A, and the thickness of the fifth oxide layer is 1500A-3000A.

7. A process for preparing a high voltage fast recovery diode as claimed in claim 1, characterized in that: After the first oxide layer and the second oxide layer form a sidewall region near the sidewall of the third implantation region, the method comprises: A metal ion sputtering process is performed to form metal ions in the wafer.

8. A process for preparing a high voltage fast recovery diode as claimed in claim 1, characterized in that: After the sixth oxide layer is photoetched to form a third opening in the partial area where the first implantation area is located, the method includes: The back side of the wafer is thinned, and then a second metal layer is disposed on the back side of the wafer.

9. A high voltage fast recovery diode, characterized in that: The method is prepared by the preparation process according to any one of claims 1 to 8.

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