Semiconductor structure and method for forming the same

Abstract

An embodiment of the present invention provides a semiconductor structure and a method for forming the same. The method includes providing a substrate having a plurality of discrete gate oxide layers and gate structures located above the gate oxide layers, with trenches between adjacent gate structures; forming an interlayer dielectric layer on the substrate that covers the gate structures and fills the trenches, the interlayer dielectric layer having a predetermined thickness; wherein the step of forming the interlayer dielectric layer includes: forming a first interlayer dielectric layer on the substrate that covers the gate structures and fills the trenches using an ion deposition process; and forming a second interlayer dielectric layer on the first interlayer dielectric layer, the second interlayer dielectric layer filling the trenches in the first interlayer dielectric layer; wherein, along a normal direction to the substrate surface, the first interlayer dielectric layer has a first predetermined thickness, and the second interlayer dielectric layer has a second predetermined thickness. The above technical solution can improve the performance of the semiconductor structure.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] With the rapid development of computer technology, existing memory devices are difficult to meet the size and power consumption requirements of memories such as static random access memory and dynamic random access memory.

[0003] With the development of semiconductor technology, traditional memory devices are gradually transitioning to non-volatile memory. Among them, flash memory devices (NOR Flash) are a non-volatile random access memory with advantages such as data reading, low latency, and high reliability. They are widely used in various storage devices.

[0004] However, the electrical performance of the semiconductor structures formed so far still needs to be improved. Summary of the Invention

[0005] In view of this, an embodiment of the present invention provides a method for forming a semiconductor structure, which can improve the performance of the semiconductor structure.

[0006] An embodiment of the present invention provides a method for forming a semiconductor structure, comprising:

[0007] Providing a substrate, wherein the substrate has a plurality of discrete gate oxide layers and a gate structure located above the gate oxide layers, and a trench is formed between adjacent gate structures;

[0008] An interlayer dielectric layer is formed on the substrate, covering the gate structure and filling the trench, wherein the interlayer dielectric layer has a set thickness; wherein the step of forming the interlayer dielectric layer comprises: forming a first interlayer dielectric layer on the substrate, covering the gate structure and filling the trench, by an ion deposition process; forming a second interlayer dielectric layer on the first interlayer dielectric layer, wherein the second interlayer dielectric layer fills the trench in the first interlayer dielectric layer;

[0009] Wherein, along the normal direction of the substrate surface, the first interlayer dielectric layer has a first preset thickness, the second interlayer dielectric layer has a second preset thickness, and the sum of the first preset thickness and the second preset thickness is the set thickness.

[0010] Optionally, the ion deposition process includes: a high-density plasma deposition process.

[0011] Optionally, the first preset thickness is 1100 nm to 1500 nm.

[0012] Optionally, the step of forming a second interlayer dielectric layer on the first interlayer dielectric layer to fill the trench in the first interlayer dielectric layer includes:

[0013] forming a first interlayer dielectric material layer on the first interlayer dielectric layer to fill the trench in the first interlayer dielectric layer;

[0014] forming a dielectric layer on the first interlayer dielectric material layer;

[0015] The dielectric layer above the first interlayer dielectric material layer is removed, and the first interlayer dielectric material layer and the remaining portion of the dielectric layer within the first interlayer dielectric material layer are used as the second interlayer dielectric layer.

[0016] Optionally, a high aspect ratio deposition process is used to form the first interlayer dielectric material layer.

[0017] Optionally, the second preset thickness is 1800 nm to 2200 nm.

[0018] Optionally, the aspect ratio of the trenches between adjacent gate structures is between 1.5 and 3.5.

[0019] Optionally, before the step of forming a first interlayer dielectric layer covering the gate structure and filling the trench on the substrate using an ion deposition process, the forming method further includes:

[0020] forming a self-aligned layer on top of the gate structure;

[0021] In the step of forming a first interlayer dielectric layer on the substrate covering the gate structure and filling the trench by using an ion deposition process, the first interlayer dielectric layer also covers the top and sidewalls of the self-aligned layer.

[0022] Optionally, before the step of forming a first interlayer dielectric layer covering the gate structure and filling the trench on the substrate using an ion deposition process, the forming method further includes:

[0023] forming a gate spacer on the sidewall of the gate structure, wherein the gate spacer also covers a portion of the top of the gate oxide layer;

[0024] In the step of forming a first interlayer dielectric layer on the substrate to cover the gate structure and fill the trench by using an ion deposition process, the first interlayer dielectric layer also covers the sidewalls and top of the gate spacer.

[0025] Optionally, in the step of providing the substrate, there are source-drain doped layers in the substrate on both sides of the gate structure, and the gate structure exposes the source-drain doped layers; and an isolation structure is located in the substrate between adjacent gate structures and contacts the ends of the source-drain doped layers.

[0026] Optionally, the material of the first interlayer dielectric layer includes one or more of silicon oxide, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide or silicon oxycarbonitride;

[0027] The material of the second interlayer dielectric layer includes one or more of silicon oxide, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide or silicon oxycarbonitride.

[0028] An embodiment of the present invention further provides a semiconductor structure, comprising:

[0029] substrate;

[0030] a plurality of discrete gate oxide layers located on the substrate;

[0031] A plurality of gate structures are respectively located on corresponding gate oxide layers;

[0032] an interlayer dielectric layer having a set thickness, comprising a first interlayer dielectric layer and a second interlayer dielectric layer, wherein the first interlayer dielectric layer is located on the substrate and covers the top and sidewalls of the gate structure and the sidewalls of the gate oxide layer; the second interlayer dielectric layer is located on the first interlayer dielectric layer and within the first interlayer dielectric layer between adjacent gate structures;

[0033] Wherein, along the normal direction of the substrate surface, the first interlayer dielectric layer has a first preset thickness, the second interlayer dielectric layer has a second preset thickness, and the sum of the first preset thickness and the second preset thickness is the set thickness.

[0034] Optionally, the semiconductor structure further comprises:

[0035] a self-aligned layer located on top of the gate structure;

[0036] The first interlayer dielectric layer also covers the top and sidewalls of the self-alignment layer.

[0037] Optionally, the semiconductor structure further comprises:

[0038] A gate spacer, located on the sidewall of the gate structure and on the top of the gate oxide layer;

[0039] The first interlayer dielectric layer also covers the top and sidewalls of the gate spacer.

[0040] Optionally, the semiconductor structure further comprises:

[0041] Source-drain doped layers are located in the substrate on both sides of the gate structure, and the gate structure exposes the source-drain doped layers;

[0042] The isolation structure is located in the substrate between adjacent gate structures and contacts the sidewalls of the source-drain doped layer.

[0043] Optionally, the first preset thickness is 1100 nm to 1500 nm;

[0044] The second preset thickness is 1800 nm to 2200 nm.

[0045] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0046] In the method for forming a semiconductor structure provided by an embodiment of the present invention, in the step of forming an interlayer dielectric layer covering the gate structure and filling the trench on the substrate, an ion deposition process is adopted so that the first interlayer dielectric layer has a first preset thickness, which can control the process time of the ion deposition process, thereby reducing or avoiding damage to the gate oxide layer caused by ions when performing the ion deposition process, improving the formation quality of the gate oxide layer, and reducing the occurrence of leakage; and by forming a second interlayer dielectric layer with a second preset thickness on the first interlayer dielectric layer, the interlayer dielectric layer can have a set thickness, thereby improving the performance of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] Figures 1 to 5 is a schematic cross-sectional view of a semiconductor structure forming process according to an embodiment of the present invention;

[0048] Figure 6 It is a schematic cross-sectional structural diagram of a semiconductor structure corresponding to an embodiment of the semiconductor structure of the present invention. DETAILED DESCRIPTION

[0049] As described in the background art, the performance of currently formed semiconductor structures needs to be improved.

[0050] Research has found that during the production process of a semiconductor structure (for example, 55nm Nor flash), when performing WAT (wafer acceptance test), it was found that the semiconductor structure had a serious breakdown voltage (BV) power-down phenomenon, which made the electrical performance of the semiconductor structure unable to meet the design requirements.

[0051] Further research revealed that during the semiconductor structure formation process, trenches are formed between adjacent gate structures. These trenches have large aspect ratios and angles. Consequently, the deposition time required to form the interlayer dielectric layer filling these trenches using an ion deposition process is excessively long. Consequently, ions accumulate on the gate oxide layer. When these ions accumulate in large numbers, the energy generated is high, which can directly break down the gate oxide layer, leading to a drop in the breakdown voltage (BV).

[0052] To solve the above technical problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate having a plurality of discrete gate oxide layers, and a gate structure located above the gate oxide layers, with trenches between adjacent gate structures; forming an interlayer dielectric layer on the substrate, the interlayer dielectric layer covering the gate structure and filling the trenches, the interlayer dielectric layer having a set thickness; wherein the step of forming the interlayer dielectric layer comprises: using an ion deposition process to form a first interlayer dielectric layer on the substrate, the interlayer dielectric layer covering the gate structure and filling the trenches; forming a second interlayer dielectric layer on the first interlayer dielectric layer, the interlayer dielectric layer filling the trenches in the first interlayer dielectric layer; wherein, along the normal direction of the surface of the substrate, the first interlayer dielectric layer has a first preset thickness, the second interlayer dielectric layer has a second preset thickness, and the sum of the first preset thickness and the second preset thickness is the set thickness.

[0053] In the step of forming an interlayer dielectric layer covering the gate structure and filling the groove on the substrate, the present invention adopts an ion deposition process so that the first interlayer dielectric layer has a first preset thickness, which can control the process time of the ion deposition process, thereby reducing or avoiding the damage of ions to the gate oxide layer when performing the ion deposition process, improving the formation quality of the gate oxide layer, and reducing the occurrence of leakage; and by forming a second interlayer dielectric layer with a second preset thickness on the first interlayer dielectric layer, the interlayer dielectric layer can have a set thickness, thereby improving the performance of the semiconductor structure.

[0054] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are exemplarily described below with reference to the accompanying drawings.

[0055] Figures 1 to 5 A schematic cross-sectional view of a semiconductor structure formation process according to an embodiment of the present invention.

[0056] refer to Figure 1 A substrate 100 is provided, and the substrate 100 has a plurality of discrete gate oxide layers 102 and a gate structure 104 located above the gate oxide layer 102 , and a trench G is formed between adjacent gate structures 104 .

[0057] The substrate 100 is used to provide a process platform for subsequently forming a semiconductor structure (eg, 55 nm Nor flash).

[0058] In this embodiment, the semiconductor structure is a planar transistor, and the corresponding substrate 100 is a planar substrate. In other embodiments, the semiconductor structure may also be a fin field effect transistor, and the substrate 100 may further include a fin.

[0059] In this embodiment, the substrate 100 is made of silicon. In other embodiments, the substrate may be made of other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide, or indium gallium. The substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate. The substrate material may be suitable for process requirements or easy to integrate.

[0060] The gate oxide layer 102 is used to provide electrical insulation to isolate the gate structure 104 from other structures (eg, source and drain doping layers).

[0061] In this embodiment, the gate oxide layer 102 is formed by chemical vapor deposition.

[0062] In this embodiment, the material of the gate oxide layer 102 includes silicon oxide or silicon oxynitride.

[0063] It should be noted that Figure 1 Only two gate oxide layers 102 are shown. In some other embodiments, the number of gate oxide layers 102 may be more than two. This embodiment does not limit the number of gate oxide layers.

[0064] When the device is operating, the gate structure 104 is used to control the on and off of the conductive channel.

[0065] In this embodiment, the gate structure 104 is a metal gate structure, and the gate structure 104 includes a gate dielectric layer (not shown) and a gate electrode layer (not shown) located on the gate dielectric layer.

[0066] The gate electrode layer is used as an external electrode for electrically connecting the gate structure to an external circuit.

[0067] The material of the gate electrode layer includes one or more of titanium nitride (TiN), tantalum nitride (TaN), tantalum (Ta), titanium (Ti), titanium aluminide (TiAl), tungsten (W), aluminum (Al), titanium silicon nitride (TiSiN) and titanium aluminum carbide (TiAlC).

[0068] In this embodiment, the gate electrode layer includes one or both of a work function layer and an electrode layer.

[0069] In this embodiment, the work function layer is used to adjust the threshold voltage of the transistor. For example, when the semiconductor structure is an NMOS transistor, the work function layer is an N-type work function layer, and the material of the N-type work function layer includes one or more of titanium aluminide and aluminum titanium carbide; when the semiconductor structure is a PMOS transistor, the work function layer is a P-type work function layer, and the material of the P-type work function layer includes one or more of titanium nitride, tantalum nitride, and titanium silicon nitride.

[0070] The electrode layer is used to electrically connect to an external circuit. The material of the electrode layer is a conductive material, including one or more of tungsten and aluminum. In this embodiment, the material of the electrode layer is tungsten.

[0071] The gate dielectric layer is used to achieve electrical isolation between the gate electrode layer and the conductive channel.

[0072] In this embodiment, the material of the gate dielectric layer includes one or more of hafnium oxide (HfO2), zirconium oxide (ZrO2), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), aluminum oxide (Al2O3), silicon oxide (SiO2) and lanthanum oxide (La2O3).

[0073] In this embodiment, the gate dielectric layer includes a high-k gate dielectric layer, and the material of the high-k gate dielectric layer is a high-k dielectric material. The material of the high-k gate dielectric layer can be selected from zirconium oxide (ZrO2), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), or aluminum oxide (Al2O3). In other embodiments, the gate dielectric layer may further include a gate oxide layer and a high-k gate dielectric layer located on the gate oxide layer, or the gate dielectric layer may only include the gate oxide layer.

[0074] In this embodiment, a metal gate structure is used as an example for description. In other embodiments, based on actual process requirements, the gate structure may also be other types of gate structures, such as a polysilicon gate structure or an amorphous silicon gate structure.

[0075] See next Figure 1 In the step of providing the substrate 100 , source-drain doped layers 106 are formed in the substrate on both sides of the gate structure 104 , and the gate structure 104 exposes the source-drain doped layers 106 .

[0076] The source-drain doped layer 106 can be used as a source or a drain of a field effect transistor. When the field effect transistor is working, the source-drain doped layer 106 can be used to provide a carrier source.

[0077] In this embodiment, the source / drain doping layer 106 may include a stress layer doped with ions. The stress layer may be used to provide stress to the channel region, thereby improving carrier mobility.

[0078] Specifically, when the semiconductor structure is an NMOS transistor, the source-drain doping layer 106 may include a stress layer doped with N-type ions, and the material of the stress layer may be Si or SiC; when the semiconductor structure is a PMOS transistor, the source-drain doping layer 106 may include a stress layer doped with P-type ions, and the material of the stress layer may be Si or SiGe.

[0079] In this embodiment, see Figure 1 In the step of providing the substrate 100 , the substrate 100 further includes an isolation structure 108 located within the substrate 100 between adjacent gate structures 104 and in contact with the end portion of the source / drain doped layer 106 .

[0080] The isolation structure 108 is used for electrical insulation in a direction parallel to the surface of the substrate 100 .

[0081] In a specific embodiment, the isolation structure 108 includes a first isolation layer 1081 located within the substrate 100 and a second isolation layer 1082 located within the first isolation layer 1081 .

[0082] In this embodiment, the steps of forming the isolation structure 108 include: forming a groove (not shown) in the substrate 100 between adjacent gate structures 104, wherein the process of forming the annular groove is: forming a mask layer (not shown) on the substrate 100, the mask layer having an opening, the width of the opening corresponding to the width of the groove, and the position of the opening corresponding to the position of the groove; etching the substrate 100 along the opening to form a groove in the substrate 100.

[0083] In some embodiments, dry etching may be used to remove a portion of the substrate 100 to form a groove.

[0084] In this embodiment, the dry etching may include a plasma etching process.

[0085] Next, a deposition process is used to form a first isolation material layer (not shown) on the sidewalls and bottom of the groove and a portion of the surface of the substrate 100; the isolation material layer outside the groove is removed, and the first isolation material layer located on the sidewalls and bottom of the groove is used as the first isolation layer 1081.

[0086] In this embodiment, an atomic layer deposition (ALD) process is used to form the isolation material layer. Through multiple ALD cycles, the thickness uniformity of the obtained first isolation layer 1081 can be improved.

[0087] In this embodiment, the material of the first isolation layer 1081 is the same as that of the gate oxide layer 102 , both being silicon dioxide or silicon oxynitride.

[0088] In a specific embodiment, the material of the first isolation layer 1081 may be silicon dioxide.

[0089] Furthermore, a second isolation material layer (not shown) is formed on the substrate 100, and the second isolation material layer fills the groove in the first isolation layer 1081; the second isolation material layer is flattened until the surface of the substrate 100 is exposed, and a second isolation layer 1082 is formed in the groove formed with the first isolation layer 1081.

[0090] In this embodiment, the second isolation layer 1082 may be formed of an insulating material, for example, one or more of silicon dioxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide, silicon oxycarbonitride, boron nitride, and boron carbonitride.

[0091] In a specific embodiment, the material of the second isolation layer 1082 may be silicon dioxide.

[0092] See next Figure 1 In the step of providing the substrate 100, the substrate 100 further includes a first well region 110 with a first type of doping and a second well region 112 with a second type of doping, and the first well region 110 and the second well region 112 are located on both sides of the isolation structure 108, wherein:

[0093] The top surface of the first well region 110 is flush with the top surface of the substrate 100 . Along a direction parallel to the surface of the substrate 100 , the sidewalls of the first well region 110 are in contact with the sidewalls of the isolation structure 108 . The first well region 110 surrounds the source / drain doped layer 106 .

[0094] The top surface of the second well region 112 is flush with the top surface of the substrate 100 . Along a direction parallel to the surface of the substrate 100 , the sidewalls of the second well region 112 are in contact with the sidewalls of the isolation structure 108 . The second well region 112 surrounds the source / drain doped layer 106 .

[0095] In this embodiment, the first well region 110 is a P-type well region, and the second well region 112 is an N-type well region. In some other embodiments, the first well region 110 is an N-type well region, and the second well region 112 is a P-type well region. The present invention is not limited to this, as long as the first well region and the second well region are of different types.

[0096] In this embodiment, part of the first well region 110 is also located below the gate oxide layer 102 along a direction parallel to the surface of the substrate 100; part of the second well region 112 is also located below the gate oxide layer 102 along a direction parallel to the surface of the substrate 100, thereby improving the control ability of the gate structure 104 over the channel.

[0097] The trench G provides a spatial location for forming a dielectric material for isolating adjacent gate structures 104 .

[0098] In this embodiment, the trench G may refer to a spatial structure enclosed by the sidewalls of the adjacent gate structure 104 , the sidewalls of the gate oxide layer 102 , and the top surface of the substrate 100 .

[0099] See also Figures 2 to 5 , an interlayer dielectric layer 130 is formed on the substrate 100 to cover the gate structure 104 and fill the trench G. The interlayer dielectric layer 130 has a set thickness H.

[0100] The interlayer dielectric layer 130 is used to isolate adjacent gate structures 104. By ensuring that the interlayer dielectric layer 130 has a set thickness, on the one hand, it can ensure that the interlayer dielectric layer 130 can cover the top of the gate structure 104 in subsequent processes, reducing or avoiding damage to the gate structure 104, thereby improving the formation quality of the gate structure 104; on the other hand, it can reduce or avoid damage to the gate oxide layer 102, improve the formation quality of the gate oxide layer 102, and reduce the occurrence of leakage.

[0101] In this embodiment, the aspect ratio of the trench G is relatively large (for example, the aspect ratio of the trench G between adjacent gate structures 104 is between 1.5 and 3.5, and the angle between the sidewall of the trench G and the upper surface of the substrate 100 is greater than 85°), that is, the trench G with a high aspect ratio is provided between adjacent gate structures 104.

[0102] If other deposition processes (for example, high aspect ratio deposition process HARP) are used, there will be no problem of ion breakdown of the gate oxide layer 102. However, other deposition processes have conformal coverage. When the depth-to-width ratio of the trench G is large, the filling material in the trench G will produce holes, which will reduce the performance of the semiconductor structure.

[0103] In this embodiment, the interlayer dielectric layer 130 can be formed in two steps. In the first formation process, an ion deposition process is used to form a first interlayer dielectric layer 120 with a first preset thickness H1; in the second formation process, a deposition process without ions is used to form a second interlayer dielectric layer 126 with a second preset thickness H2. In this way, the interlayer dielectric layer 130 can have a set thickness while reducing or avoiding damage to the gate oxide layer 102.

[0104] In short, different deposition processes are used to form the first interlayer dielectric layer 120 and the second interlayer dielectric layer 126 in stages.

[0105] In a specific embodiment, the steps of forming the interlayer dielectric layer 130 include:

[0106] See also Figure 2 , an ion deposition process is used to form a first interlayer dielectric layer 120 covering the gate structure 104 and filling the trench G on the substrate 100 .

[0107] The first interlayer dielectric layer 120 is used to isolate adjacent gate structures 104 .

[0108] In this embodiment, the ion deposition process includes a high density plasma (HDP) deposition process. The HDP deposition process has good filling capability and can improve the thickness uniformity of the formed first interlayer dielectric layer 120 .

[0109] In this embodiment, when the ion deposition process includes an HDP deposition process, oxygen source gas and silicon source gas are used under the action of plasma to form a first interlayer dielectric layer 120 covering the gate structure 104 and filling the trench G on the substrate 100 .

[0110] In this embodiment, high-density plasma is generated during the process of forming the first interlayer dielectric layer 120 using an ion deposition process. If the deposition time is too long, the high-density plasma will gather together, and when the energy is too large, it will break through the gate oxide layer 102.

[0111] Based on this, in this embodiment, by controlling the deposition time and / or deposition rate of the ion deposition process, the first interlayer dielectric layer 120 can have a first preset thickness H1 along the normal direction of the surface of the substrate 100 .

[0112] In a specific embodiment, the deposition rate of the existing process may be kept unchanged while reducing the deposition time of the existing process, so that the first interlayer dielectric layer 120 has the first predetermined thickness H1.

[0113] In some other embodiments, the deposition rate of the existing process may be increased and the deposition time of the existing process may be reduced so that the first interlayer dielectric layer 120 has the first preset thickness H1 , which is not limited in this embodiment of the present invention.

[0114] In this embodiment, along the normal direction of the surface of the substrate 100 , the first predetermined thickness H1 of the first interlayer dielectric layer 120 may be 1100 nm to 1500 nm, for example, 1100 nm, 1200 nm, 1350 nm, and 1500 nm.

[0115] By making the first preset thickness H1 greater than or equal to 1100nm, the formed first interlayer dielectric layer 120 can further protect the gate structure 104 on the basis of completely covering the top of the gate structure 104. In this way, when executing subsequent processes, the first interlayer dielectric layer 120 can cover the gate structure 104, reduce or avoid damage to the gate structure 104, and improve the formation quality of the gate structure 104; and by making the first preset thickness H1 less than or equal to 1500nm, the formation time of the first interlayer dielectric layer 120 is moderate, and ion aggregation problems will not be caused due to a long formation time, thereby reducing or avoiding the gate oxide layer 102 from being broken down, thereby improving the breakdown voltage of the semiconductor device.

[0116] In this embodiment, the material of the first interlayer dielectric layer 120 is silicon oxide. In some other embodiments, the material of the first interlayer dielectric layer 120 can also be other insulating materials, such as one or more of silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide, or silicon oxycarbonitride.

[0117] In this embodiment, as mentioned above, the aspect ratio and angle of the trenches between adjacent gate structures are too large. Therefore, when the ion deposition process is used, Figure 2 As shown, there are still some trenches G between the first interlayer dielectric layers 120 that are not completely filled.

[0118] In one embodiment, after the first interlayer dielectric layer 120 is formed, the depth D of the trench G in the first interlayer dielectric layer 120 may be 1 / 3 of the first thickness H1 of the first interlayer dielectric layer 120 .

[0119] See also Figures 3 to 5 , a second interlayer dielectric layer 126 is formed on the first interlayer dielectric layer 120 , and the second interlayer dielectric layer 126 completely fills the trench G in the first interlayer dielectric layer 120 .

[0120] That is, the trench G is fully filled by forming the second interlayer dielectric layer 126 .

[0121] In this embodiment, the second interlayer dielectric layer 126 plays a role in thickness compensation. This is because in the step of forming the first interlayer dielectric layer 120 having the first preset thickness H1, in order to reduce or avoid damage to the gate oxide layer 102, the first preset thickness H1 of the first interlayer dielectric layer 120 does not meet the design requirements when the deposition rate remains unchanged and the deposition time is reduced. That is, the thickness of the first interlayer dielectric layer 120 cannot keep the semiconductor structure in a normal working state.

[0122] In this way, by forming a second interlayer dielectric layer 126 having a second preset thickness H2 on the first interlayer dielectric layer 120 (i.e., the sum of the first preset thickness H1 and the second preset thickness H2 is the set thickness H), it is possible to isolate adjacent gate structures 104 and reduce or avoid damage to the gate oxide layer 102 while providing an interlayer dielectric layer 130 on the substrate 100 with a thickness that meets the design requirements.

[0123] In this embodiment, along the normal direction of the surface of the substrate 100 , the second predetermined thickness H2 of the second interlayer dielectric layer 126 may be 1800 nm to 2200 nm, for example, 1800 nm, 1900 nm, 1950 nm, 2100 nm, 2200 nm, etc.

[0124] By making the second preset thickness H2 greater than or equal to 1800nm, the thickness of the formed interlayer dielectric layer 130 can meet the design requirements, so that when executing subsequent processes, the interlayer dielectric layer 130 can still cover the gate structure 104, thereby improving the formation quality of the gate structure 104; and by making the second preset thickness H2 less than or equal to 2200nm, the power consumption of the semiconductor structure can be reduced, and the required formation time can be reduced, thereby improving manufacturing efficiency.

[0125] In this embodiment, the steps of forming the second interlayer dielectric layer 126 on the first interlayer dielectric layer 120 and filling the trench G in the first interlayer dielectric layer 120 with the second interlayer dielectric layer 126 include:

[0126] See also Figure 3 , a first interlayer dielectric material layer 122 is formed on the first interlayer dielectric layer 120 , and the first interlayer dielectric material layer 122 completely fills the trench G in the first interlayer dielectric layer 120 .

[0127] The first interlayer dielectric material layer 122 provides a raw material for forming the second interlayer dielectric layer 126 .

[0128] In this embodiment, a high aspect ratio deposition process is used to form the first interlayer dielectric material layer 122 . The high aspect ratio deposition process has good conformal coverage and can improve the thickness consistency of the first interlayer dielectric material layer 122 .

[0129] In this embodiment, during the process of forming the first interlayer dielectric material layer 122 , holes K will be generated on the top of the first interlayer dielectric material layer 122 . The existence of these holes K will affect the performance of the finally formed semiconductor structure.

[0130] It should be noted that Figure 3 The shape, size and distribution position of the holes K are merely illustrative, and are used to illustrate that the top of the first interlayer dielectric material layer 122 has the holes K.

[0131] Based on this, see Figure 4 , a dielectric layer 124 is formed on the first interlayer dielectric material layer 122 .

[0132] The dielectric layer 124 may serve as a filling layer to make the top of the first interlayer dielectric material layer 122 flush and reserve a certain grinding thickness for a subsequent grinding process.

[0133] In this embodiment, a chemical vapor deposition process is used to form the dielectric layer 124 on the first interlayer dielectric material layer 122 .

[0134] In this embodiment, along the surface of the substrate 100 , the thickness of the dielectric layer 124 should be sufficient to fill the hole K on the top of the first interlayer dielectric material layer 122 .

[0135] In this embodiment, the material of the dielectric layer 124 includes one or more of silicon oxide, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide, or silicon oxycarbonitride.

[0136] In one embodiment, the material of the dielectric layer 124 is silicon oxide.

[0137] See also Figure 5 , the dielectric layer 124 above the first interlayer dielectric material layer 122 is removed, and the first interlayer dielectric material layer 122 and the remaining portion of the dielectric layer 124 located within the first interlayer dielectric material layer 122 are used as the second interlayer dielectric layer 126 .

[0138] In this embodiment, the material of the second interlayer dielectric layer 126 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide, or silicon oxycarbonitride.

[0139] It should be noted that the “second preset thickness H2” in this embodiment refers to a thickness parameter value along the normal direction of the surface of the first interlayer dielectric layer 120 with the first interlayer dielectric layer 120 as the base.

[0140] In this embodiment, see Figure 1 and Figure 2 Before the step of forming a covering gate structure 104 on the substrate 100 and filling the first interlayer dielectric layer 120 in the trench G by using an ion deposition process, the forming method may further include:

[0141] A gate spacer 114 is formed on the sidewall of the gate structure 104 . The gate spacer 114 also covers a portion of the top of the gate oxide layer 102 .

[0142] The gate spacer 114 can be used to protect the gate structure 104 , so that the integrity of the gate structure 104 can be improved during the step of forming the first interlayer dielectric layer 120 using an ion deposition process.

[0143] In this embodiment, the material of the gate spacer 114 may include one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide, silicon oxycarbonitride, boron nitride, or boron carbonitride.

[0144] As an example, the material of the gate spacer 114 is silicon nitride.

[0145] Accordingly, an ion deposition process is used to form a first interlayer dielectric layer 120 covering the gate structure 104 on the substrate 100 and filling the trench G. The first interlayer dielectric layer 120 also covers the sidewalls and top of the gate spacer 114 .

[0146] In this embodiment, see Figure 1 and Figure 2 Before the step of forming a covering gate structure 104 on the substrate 100 and filling the first interlayer dielectric layer 120 in the trench G by using an ion deposition process, the forming method may further include:

[0147] A self-aligned layer 116 is formed on top of the gate structure 104 .

[0148] The self-aligned layer 116 is used to electrically connect subsequent metal wirings to reduce the contact resistance between the metal wirings and the semiconductor structure.

[0149] In this embodiment, the step of forming a self-aligned layer 116 on top of the gate structure 104 includes: forming a self-aligned material layer (not shown) above the substrate 100 that at least covers the top of the gate structure 104, and then performing an annealing treatment to allow the self-aligned material layer to react with the gate structure 104 to form the self-aligned layer 116.

[0150] In this embodiment, the annealing process includes a rapid thermal annealing (RTA) process. The RTA process can heat to a high temperature in a short time (usually between tens of seconds and a few minutes) and then quickly cool down, thereby allowing the self-aligned material layer to fully react with the gate structure 104 while reducing thermal damage to the semiconductor structure.

[0151] In some other embodiments, according to the actual process, other suitable annealing processes may be used for annealing, such as spike annealing process, laser spike annealing process (LSA), etc. The present invention does not limit the annealing process.

[0152] In this embodiment, the material of the self-aligned layer 116 includes metal silicide, such as nickel silicide (NiSi) or cobalt silicide (CoSi).

[0153] Accordingly, an ion deposition process is used to form a first interlayer dielectric layer 120 covering the gate structure 104 on the substrate 100 and filling the trench G. The first interlayer dielectric layer 120 also covers the top and sidewalls of the self-aligned layer 216 .

[0154] In this embodiment, in the step of providing the substrate 100 , the gate structure 104 further has an ONO structure (not shown), wherein the ONO structure includes a first oxide layer, a nitride layer, and a second oxide layer.

[0155] The storage and reading operations of the 55nm Nor flash are facilitated by adding an ONO structure to the gate structure 104. Specifically, the ONO structure can store charges, and the current state of the 55nm Nor flash can be determined by reading the state of the charges in the ONO structure.

[0156] In this embodiment, after forming the second interlayer dielectric layer 126, subsequent steps include a grinding process to remove film layers that are higher than the first interlayer dielectric layer 120. However, considering the cost of forming the second interlayer dielectric layer 126 using a high aspect ratio deposition process in actual production, the thickness of the second interlayer dielectric layer 126 cannot be very thick. Therefore, if the control accuracy during the grinding process is not high enough, it may result in the removal of part of the gate structure 104.

[0157] See also Figure 6 A schematic diagram of a semiconductor structure according to an embodiment of the present invention is shown in FIG. Figure 6 As shown, the semiconductor structure includes: a substrate 200; a plurality of discrete gate oxide layers 202, located on the substrate 200; a plurality of gate structures 204, respectively located on corresponding gate oxide layers 202; an interlayer dielectric layer 230, having a set thickness H, including a first interlayer dielectric layer 220 and a second interlayer dielectric layer 226, wherein the first interlayer dielectric layer 220 is located on the substrate 200 and covers the top and sidewalls of the gate structure 204, as well as the sidewalls of the gate oxide layer 202; the second interlayer dielectric layer 226 is located on the first interlayer dielectric layer 220, and within the first interlayer dielectric layer 220 between adjacent gate structures 104; wherein, along the normal direction of the surface of the substrate 200, the first interlayer dielectric layer 220 has a first preset thickness H1, the second interlayer dielectric layer 226 has a second preset thickness H2, and the sum of the first preset thickness H1 and the second preset thickness H2 is the set thickness H.

[0158] The substrate 200 is used to provide a process platform for a semiconductor structure (eg, 55 nm Nor flash).

[0159] In this embodiment, the semiconductor structure is a planar transistor, and the corresponding substrate 200 is a planar substrate. In other embodiments, the semiconductor structure may also be a fin field effect transistor, and the substrate 200 may further include a fin.

[0160] In this embodiment, the material of substrate 200 is silicon. In other embodiments, the substrate may be made of other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide, or indium gallium. The substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate. The substrate material may be a material suitable for process requirements or easy to integrate.

[0161] The gate oxide layer 202 is used to provide electrical insulation to isolate the gate structure 204 from other structures (eg, source and drain doping layers).

[0162] In this embodiment, the material of the gate oxide layer 202 includes silicon oxide or silicon oxynitride.

[0163] When the device is operating, the gate structure 204 is used to control the opening and closing of the conductive channel.

[0164] In this embodiment, the gate structure 204 is a metal gate structure, and the gate structure 204 includes a gate dielectric layer (not shown) and a gate electrode layer (not shown) located on the gate dielectric layer.

[0165] The gate electrode layer is used as an external electrode for electrically connecting the gate structure to an external circuit.

[0166] The material of the gate electrode layer includes one or more of titanium nitride (TiN), tantalum nitride (TaN), tantalum (Ta), titanium (Ti), titanium aluminide (TiAl), tungsten (W), aluminum (Al), titanium silicon nitride (TiSiN) and titanium aluminum carbide (TiAlC).

[0167] In this embodiment, the gate electrode layer includes one or both of a work function layer and an electrode layer.

[0168] In this embodiment, the work function layer is used to adjust the threshold voltage of the transistor. For example, when the semiconductor structure is an NMOS transistor, the work function layer is an N-type work function layer, and the material of the N-type work function layer includes one or more of titanium aluminide and aluminum titanium carbide; when the semiconductor structure is a PMOS transistor, the work function layer is a P-type work function layer, and the material of the P-type work function layer includes one or more of titanium nitride, tantalum nitride, and titanium silicon nitride.

[0169] The electrode layer is used to electrically connect to an external circuit. The material of the electrode layer is a conductive material, including one or more of tungsten and aluminum. In this embodiment, the material of the electrode layer is tungsten.

[0170] The gate dielectric layer is used to achieve electrical isolation between the gate electrode layer and the conductive channel.

[0171] In this embodiment, the material of the gate dielectric layer includes one or more of hafnium oxide (HfO2), zirconium oxide (ZrO2), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), aluminum oxide (Al2O3), silicon oxide (SiO2) and lanthanum oxide (La2O3).

[0172] In this embodiment, the gate dielectric layer includes a high-k gate dielectric layer, and the material of the high-k gate dielectric layer is a high-k dielectric material. The material of the high-k gate dielectric layer can be selected from zirconium oxide (ZrO2), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), or aluminum oxide (Al2O3). In other embodiments, the gate dielectric layer may further include a gate oxide layer and a high-k gate dielectric layer located on the gate oxide layer, or the gate dielectric layer may only include the gate oxide layer.

[0173] In this embodiment, a metal gate structure is used as an example for description. In other embodiments, based on actual process requirements, the gate structure may also be other types of gate structures, such as a polysilicon gate structure or an amorphous silicon gate structure.

[0174] See next Figure 6 The semiconductor structure further includes: a source-drain doped layer 206 located in the substrate 200 on both sides of the gate structure 204 , and the gate structure 204 exposes the source-drain doped layer 206 .

[0175] The source-drain doped layer 206 can be used as a source or a drain of a field effect transistor. When the field effect transistor is working, the source-drain doped layer 206 can be used to provide a carrier source.

[0176] In this embodiment, the source / drain doping layer 206 may include a stress layer doped with ions. The stress layer may be used to provide stress to the channel region, thereby improving carrier mobility.

[0177] Specifically, when the semiconductor structure is an NMOS transistor, the source-drain doping layer 206 may include a stress layer doped with N-type ions, and the material of the stress layer may be Si or SiC; when the semiconductor structure is a PMOS transistor, the source-drain doping layer 206 may include a stress layer doped with P-type ions, and the material of the stress layer may be Si or SiGe.

[0178] In this embodiment, see Figure 6 The semiconductor structure further includes an isolation structure 208 located in the substrate 200 between adjacent gate structures 204 and in contact with sidewalls of the source / drain doped layer 206 .

[0179] The isolation structure 208 is used for electrical insulation in a direction parallel to the surface of the substrate 200 .

[0180] In a specific embodiment, the isolation structure 208 includes a first isolation layer 2081 located within the substrate 100 and a second isolation layer 2082 located within the first isolation layer 2081 .

[0181] In this embodiment, the material of the first isolation layer 2081 is silicon dioxide or silicon oxynitride.

[0182] In a specific embodiment, the material of the first isolation layer 2081 may be silicon dioxide.

[0183] In this embodiment, the second isolation layer 2082 may be formed of an insulating material, for example, one or more of silicon dioxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide, silicon oxycarbonitride, boron nitride, and boron carbonitride.

[0184] In a specific embodiment, the material of the second isolation layer 2082 may be silicon dioxide.

[0185] See next Figure 6 The semiconductor structure further includes: a first well region 210 with a first type of doping, located in the substrate 200 on one side of the gate structure 204 , in contact with the sidewall of the isolation structure 208 , and surrounding the source-drain doped layer 206 .

[0186] The second well region 212 with the second type doping is located in the substrate 200 on the other side of the gate structure 204 , is in contact with the sidewall of the isolation structure 208 , and surrounds the source / drain doped layer 206 .

[0187] In this embodiment, the top surface of the first well region 210 is flush with the top surface of the substrate 200 , and the top surface of the second well region 212 is flush with the top surface of the substrate 200 .

[0188] In this embodiment, the first well region 210 is a P-type well region, and the second well region 212 is an N-type well region. In some other embodiments, the first well region 210 is an N-type well region, and the second well region 212 is a P-type well region. The present invention is not limited to this, as long as the first well region and the second well region are of different types.

[0189] In this embodiment, part of the first well region 210 is also located below the gate oxide layer 202 along a direction parallel to the surface of the substrate 200; part of the second well region 212 is also located below the gate oxide layer 202 along a direction parallel to the surface of the substrate 200, thereby improving the control ability of the gate structure 204 over the channel.

[0190] The interlayer dielectric layer 230 is used to isolate adjacent gate structures 204, and by making the interlayer dielectric layer 230 have a set thickness H, it can be ensured that the interlayer dielectric layer 230 can cover the top of the gate structure 204 in subsequent processes, reducing or avoiding damage to the gate structure 204, thereby improving the formation quality of the gate structure 204.

[0191] More specifically, the interlayer dielectric layer 230 may include a first interlayer dielectric layer 220 and a second interlayer dielectric layer 226 . Along the normal direction of the surface of the substrate 200 , the first interlayer dielectric layer 220 has a first preset thickness H1 , and the second interlayer dielectric layer 226 has a second preset thickness H2 .

[0192] The first interlayer dielectric layer 220 is used to isolate adjacent gate structures 204 .

[0193] In this embodiment, by ensuring that the first interlayer dielectric layer 220 has a first preset thickness H1 along the normal direction of the surface of the substrate 200, the process duration of the ion deposition process can be controlled, thereby reducing or avoiding damage to the gate oxide layer 202 by ions during the ion deposition process, improving the formation quality of the gate oxide layer 202, and reducing the occurrence of leakage.

[0194] In this embodiment, the first predetermined thickness H1 of the first interlayer dielectric layer 220 may be 1100 nm to 1500 nm, for example, 1100 nm, 1200 nm, 1350 nm, and 1500 nm.

[0195] By making the first preset thickness H1 greater than or equal to 1100nm, the formed first interlayer dielectric layer 220 can further protect the gate structure 204 on the basis of completely covering the top of the gate structure 204. In this way, when executing subsequent processes, the first interlayer dielectric layer 220 can cover the gate structure 204, reduce or avoid damage to the gate structure 204, and improve the formation quality of the gate structure 204; and by making the first preset thickness H1 less than or equal to 1500nm, the formation time of the first interlayer dielectric layer 220 is moderate, and ion aggregation problems will not be caused due to a long formation time, thereby reducing or avoiding the breakdown of the gate oxide layer 202, thereby improving the breakdown voltage of the semiconductor device.

[0196] In this embodiment, the material of the first interlayer dielectric layer 220 is silicon oxide. In some other embodiments, the material of the first interlayer dielectric layer 220 can also be other insulating materials, such as one or more of silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide, or silicon oxycarbonitride.

[0197] The second interlayer dielectric layer 226 is used to compensate for the thickness of the first interlayer dielectric layer 220 , so that an interlayer dielectric layer 230 having a designed thickness H that meets design requirements is formed on the substrate 200 .

[0198] In this embodiment, by making the second interlayer dielectric layer 226 have a second preset thickness H2, the substrate 200 can have an interlayer dielectric layer 230 with a thickness that meets design requirements while isolating adjacent gate structures 204 and reducing or avoiding damage to the gate oxide layer 202.

[0199] In this embodiment, the second predetermined thickness H2 of the second interlayer dielectric layer 226 may be 1800 nm to 2200 nm, for example, 1800 nm, 1900 nm, 1950 nm, 2100 nm, 2200 nm, etc.

[0200] By making the second preset thickness H2 greater than or equal to 1800nm, the thickness of the formed interlayer dielectric layer 230 can meet the design requirements, the interlayer dielectric layer 230 can cover the gate structure 204, and the formation quality of the gate structure 204 is improved; and by making the second preset thickness H2 less than or equal to 2200nm, the power consumption of the semiconductor structure can be reduced, and the required formation time can be reduced, thereby improving manufacturing efficiency.

[0201] In this embodiment, the material of the second interlayer dielectric layer 226 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide, or silicon oxycarbonitride.

[0202] In one embodiment, the material of the second interlayer dielectric layer 226 includes silicon oxide.

[0203] In this embodiment, the semiconductor structure further includes a gate spacer 214 located on the sidewalls of the gate structure 204 and on the top of the gate oxide layer 202 .

[0204] The gate spacer 214 may be used to protect the gate structure 204 to improve the integrity of the gate structure 204 .

[0205] In this embodiment, the material of the gate spacer 214 may include one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide, silicon oxycarbonitride, boron nitride, or boron carbonitride.

[0206] As an example, the material of the gate spacer 214 is silicon nitride.

[0207] Accordingly, the first interlayer dielectric layer 220 also covers the sidewalls and top of the gate spacer 214 .

[0208] In this embodiment, the semiconductor structure further includes a self-aligned layer 216 located on top of the gate structure 204 .

[0209] The self-aligned layer 216 is used to electrically connect metal wirings to reduce the contact resistance between the metal wirings and the semiconductor structure.

[0210] In this embodiment, the material of the self-aligned layer 216 includes metal silicide, such as nickel silicide (NiSi) or cobalt silicide (CoSi).

[0211] Accordingly, the first interlayer dielectric layer 220 also covers the top and sidewalls of the self-alignment layer 216 .

[0212] In this embodiment, the gate structure 204 further includes an ONO structure (not shown), wherein the ONO structure includes a first oxide layer, a nitride layer, and a second oxide layer.

[0213] It should be noted that the semiconductor structure of this embodiment can be formed by the formation method described in the previous embodiment, or by other formation methods. For the specific description of the semiconductor structure of this embodiment, reference can be made to the corresponding description in the previous embodiment, and this embodiment will not be repeated here.

[0214] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, wherein the substrate has a plurality of discrete gate oxide layers and a gate structure located above the gate oxide layers, and a trench is formed between adjacent gate structures; An interlayer dielectric layer is formed on the substrate, covering the gate structure and filling the trench, wherein the interlayer dielectric layer has a set thickness; wherein the step of forming the interlayer dielectric layer comprises: forming a first interlayer dielectric layer on the substrate, covering the gate structure and filling the trench, by an ion deposition process; forming a second interlayer dielectric layer on the first interlayer dielectric layer, wherein the second interlayer dielectric layer fills the trench in the first interlayer dielectric layer; Among them, along the normal direction of the substrate surface, the first interlayer dielectric layer has a first preset thickness, the second interlayer dielectric layer has a second preset thickness, and the sum of the first preset thickness and the second preset thickness is the set thickness, and the first preset thickness is used to control the process time of the ion deposition process.

2. The method for forming a semiconductor structure according to claim 1, wherein: The ion deposition process includes: a high-density plasma deposition process.

3. The method for forming a semiconductor structure according to claim 1, wherein: The first preset thickness is 1100 nm to 1500 nm.

4. The method for forming a semiconductor structure according to claim 1, wherein: The step of forming a second interlayer dielectric layer on the first interlayer dielectric layer, wherein the second interlayer dielectric layer fills the trench in the first interlayer dielectric layer, comprises: forming a first interlayer dielectric material layer on the first interlayer dielectric layer to fill the trench in the first interlayer dielectric layer; forming a dielectric layer on the first interlayer dielectric material layer; The dielectric layer above the first interlayer dielectric material layer is removed, and the first interlayer dielectric material layer and the remaining portion of the dielectric layer within the first interlayer dielectric material layer are used as the second interlayer dielectric layer.

5. The method for forming a semiconductor structure according to claim 4, wherein: The first interlayer dielectric material layer is formed by adopting a high aspect ratio deposition process.

6. The method for forming a semiconductor structure according to any one of claims 1, 4 or 5, wherein: The second preset thickness is 1800 nm to 2200 nm.

7. The method for forming a semiconductor structure according to claim 1, wherein: The aspect ratio of the trenches between adjacent gate structures is between 1.5 and 3.

5.

8. The method for forming a semiconductor structure according to claim 1, wherein: Before the step of forming a first interlayer dielectric layer covering the gate structure and filling the trench on the substrate by an ion deposition process, the forming method further includes: forming a self-aligned layer on top of the gate structure; In the step of forming a first interlayer dielectric layer on the substrate covering the gate structure and filling the trench by using an ion deposition process, the first interlayer dielectric layer also covers the top and sidewalls of the self-aligned layer.

9. The method for forming a semiconductor structure according to claim 1, wherein: Before the step of forming a first interlayer dielectric layer covering the gate structure and filling the trench on the substrate by an ion deposition process, the forming method further includes: forming a gate spacer on the sidewall of the gate structure, wherein the gate spacer also covers a portion of the top of the gate oxide layer; In the step of forming a first interlayer dielectric layer on the substrate to cover the gate structure and fill the trench by using an ion deposition process, the first interlayer dielectric layer also covers the sidewalls and top of the gate spacer.

10. The method for forming a semiconductor structure according to claim 1, wherein: In the step of providing the substrate, the substrate on both sides of the gate structure has source-drain doping layers, and the gate structure exposes the source-drain doping layers; and an isolation structure is located in the substrate between adjacent gate structures and contacts the ends of the source-drain doping layers.

11. The method for forming a semiconductor structure according to claim 1, wherein: The material of the first interlayer dielectric layer includes one or more of silicon oxide, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide or silicon oxycarbonitride; The material of the second interlayer dielectric layer includes one or more of silicon oxide, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide or silicon oxycarbonitride.

12. A semiconductor structure, characterized in that: include: substrate; a plurality of discrete gate oxide layers located on the substrate; A plurality of gate structures are respectively located on corresponding gate oxide layers; an interlayer dielectric layer having a set thickness, comprising a first interlayer dielectric layer and a second interlayer dielectric layer, wherein the first interlayer dielectric layer is located on the substrate and covers the top and sidewalls of the gate structure and the sidewalls of the gate oxide layer; the second interlayer dielectric layer is located on the first interlayer dielectric layer and within the first interlayer dielectric layer between adjacent gate structures; the first interlayer dielectric layer is formed by an ion deposition process; Among them, along the normal direction of the substrate surface, the first interlayer dielectric layer has a first preset thickness, the second interlayer dielectric layer has a second preset thickness, and the sum of the first preset thickness and the second preset thickness is the set thickness; the first preset thickness is used to control the process time of the ion deposition process.

13. The semiconductor structure according to claim 12, wherein: Semiconductor structures also include: a self-aligned layer located on top of the gate structure; The first interlayer dielectric layer also covers the top and sidewalls of the self-alignment layer.

14. The semiconductor structure according to claim 12, wherein: Semiconductor structures also include: A gate spacer, located on the sidewall of the gate structure and on the top of the gate oxide layer; The first interlayer dielectric layer also covers the top and sidewalls of the gate spacer.

15. The semiconductor structure according to claim 12, wherein: Semiconductor structures also include: Source-drain doped layers are located in the substrate on both sides of the gate structure, and the gate structure exposes the source-drain doped layers; The isolation structure is located in the substrate between adjacent gate structures and contacts the sidewalls of the source-drain doped layer.

16. The semiconductor structure according to claim 12, wherein: The first preset thickness is 1100 nm to 1500 nm; The second preset thickness is 1800 nm to 2200 nm.

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