Method for manufacturing transistor, transistor, and semiconductor device
By forming an isolation structure inside the transistor cell, the problem of low space utilization of the transistor cell is solved, and the transistor integration density is improved.
CN119653847BActive Publication Date: 2026-06-02PEKING UNIV
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- PEKING UNIV
- Filing Date
- 2024-11-11
- Publication Date
- 2026-06-02
AI Technical Summary
Technical Problem
The low space utilization rate inside the transistor unit leads to insufficient transistor integration density.
Method used
By forming a stacked structure on a semiconductor substrate, etching to form multiple fin structures, and forming an isolation structure between adjacent fin structures, adjacent transistors are electrically isolated, reducing the spacing between transistors.
Benefits of technology
This increases the integration density of transistors, effectively reduces the space requirements between adjacent transistors, and improves space utilization.
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Smart Images
Figure CN119653847B_ABST
Abstract
The application provides a transistor preparation method, a transistor and a semiconductor device. The preparation method comprises the following steps: forming a stack structure on a semiconductor substrate; etching the stack structure to form a plurality of fin structures, the plurality of fin structures are arranged in sequence along a first direction, and a first groove is formed between any two adjacent fin structures in the plurality of fin structures; forming a first side wall covering the side walls of the plurality of fin structures in the first groove; etching the semiconductor substrate below the first groove to obtain a second groove; depositing dielectric material in the first groove and the second groove to form an isolation structure; removing the first side wall to separate the isolation structure and the plurality of fin structures to obtain a first semiconductor structure; and forming a plurality of first transistors based on the plurality of fin structures in the first semiconductor structure, wherein the isolation structure is used for electrically isolating any two adjacent first transistors in the plurality of first transistors, and the polarities of the any two adjacent first transistors are the same or different.
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