Display panel and display device

Abstract

The invention relates to the technical field of display, and discloses a display panel and a display device. The driving array layer is positioned on one side of the substrate; the first planarization layer is located on the side, away from the substrate, of the driving array layer; the first conductive layer is located on the side, away from the substrate, of the first planarization layer, and the first conductive layer comprises a plurality of electrodes; the second planarization layer is located on the side, away from the substrate, of the first conductive layer, the second planarization layer comprises a plurality of first openings, and the first openings penetrate through the second planarization layer; the first opening exposes at least part of the electrode in the direction perpendicular to the plane where the substrate is located. The display device comprises the display panel. The flatness problem of the substrate can be improved, the reliability of the performance of the substrate is ensured, and the display effect is improved.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] Display devices have a wide range of application scenarios in life, such as mobile phones, tablet computers and other electronic devices. Display panels are an important part of display devices.

[0003] In existing display panels, display substrates generally adopt a multi-metal layer stacked structure, and the top metal layer needs to be patterned to form a conductive structure with different functions; however, due to the requirement of uniformity, the thickness of the top metal layer of the display substrate is difficult to thin, resulting in a graphic and obvious concave-convex structure on the top layer of the display substrate. It is difficult to achieve a high degree of flatness on the surface, which can easily affect the performance of the display substrate and thus affect the display quality.

[0004] Therefore, providing a display panel and a display device that can improve the flatness of a substrate and ensure the display effect is a technical problem that needs to be solved urgently by those skilled in the art. Summary of the invention

[0005] In order to solve the above technical problems, the present disclosure provides a display panel and a display device to solve the problem in the prior art that it is difficult to achieve high flatness on the surface of a display substrate of a display panel, which affects the display effect.

[0006] The present disclosure provides a display panel, comprising: a substrate;

[0007] A driving array layer, located on one side of the substrate;

[0008] A first planarization layer is located on a side of the driving array layer away from the substrate;

[0009] A first conductive layer, located on a side of the first planarization layer away from the substrate, the first conductive layer comprising a plurality of electrodes;

[0010] A second planarization layer is located on a side of the first conductive layer away from the substrate, the second planarization layer comprises a plurality of first openings, and the first openings penetrate the second planarization layer;

[0011] Along a direction perpendicular to a plane where the substrate is located, the first opening exposes at least a portion of the electrode.

[0012] Based on the same inventive concept, the present disclosure also provides a display device, which includes the above-mentioned display panel.

[0013] Compared with the prior art, the technical solution provided by the embodiments of the present disclosure has the following advantages:

[0014] The display panel provided by the present disclosure further sets a second planarization layer on the side of the patterned first conductive layer away from the substrate. The material of the second planarization layer can be the same as that of the first planarization layer, that is, the second planarization layer can be an organic film layer to flatten the surface of the first conductive layer away from the substrate, so that the surface of the patterned first conductive layer can be covered by the second planarization layer of organic material, which plays a role in flattening the surface of the first conductive layer, that is, a large number of concave-convex structures presented by the patterned first conductive layer can be flattened by the second planarization layer, which can improve the flatness problem of the substrate and is conducive to improving the performance of the substrate and the display effect. The second planarization layer of the present disclosure includes a plurality of first openings, the first openings penetrate the second planarization layer, and in the direction perpendicular to the plane where the substrate is located, the first openings expose at least part of the electrode, so as to facilitate the subsequent light-emitting device to be bonded to the electrode in the first opening. The present disclosure sets a second planarization layer on the side of the first conductive layer away from the substrate. Through the high flatness performance of the second planarization layer, the flatness problem of the substrate can be improved, the performance of the substrate is guaranteed, and the display effect is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0016] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0017] Figure 1 is a schematic diagram of a planar structure of a display panel provided by an embodiment of the present invention;

[0018] Figure 2 yes Figure 1 A schematic diagram of a cross-sectional structure along the A-A' direction;

[0019] Figure 3 is a schematic diagram of a partial planar structure of a display panel provided by an embodiment of the present invention;

[0020] Figure 4 yes Figure 3 Schematic diagram of the cross-sectional structure along the B-B' direction;

[0021] Figure 5 yes Figure 1 Another schematic diagram of the cross-sectional structure along the A-A' direction;

[0022] Figure 6 yes Figure 1 Another schematic diagram of the cross-sectional structure along the A-A' direction;

[0023] Figure 7 yes Figure 6 A schematic diagram of a top view structure of a first opening and a second opening and an electrode;

[0024] Figure 8 yes Figure 1 A schematic diagram of a cross-sectional structure along the C-C' direction;

[0025] Fig. 9 yes Figure 8 A schematic diagram of a top view structure of a first opening and a second opening and an electrode;

[0026] Fig.10 yes Figure 1 Another cross-sectional structure schematic diagram in the C-C' direction;

[0027] Fig.11 yes Figure 1 Another schematic diagram of the cross-sectional structure along the A-A' direction;

[0028] Fig.12 yes Figure 1 Another cross-sectional structure schematic diagram in the C-C' direction;

[0029] Fig.13 is another schematic diagram of a planar structure of a display panel provided by an embodiment of the present invention;

[0030] Fig.14 yes Fig.13 A schematic diagram of a local enlarged structure of the J2 region;

[0031] Fig.15 yes Fig.13 Another schematic diagram of the partially enlarged structure of the middle J2 region;

[0032] Fig.16 yes Fig.13 Another schematic diagram of the partially enlarged structure of the middle J2 region;

[0033] Fig.17 yes Figure 1 and Fig.13 A schematic diagram of the local area structure of the first conductive layer;

[0034] Fig.18 yes Figure 1 Another cross-sectional structure schematic diagram in the C-C' direction;

[0035] Fig.19 yes Fig.18 A schematic diagram of a top view structure of a first opening and a second opening and an electrode;

[0036] Fig. 20 yes Fig.13Another schematic diagram of the partially enlarged structure of the middle J2 region;

[0037] Fig.21 yes Fig.13 Another schematic diagram of the partially enlarged structure of the middle J2 region;

[0038] Fig. 22 yes Figure 1 Another schematic diagram of the cross-sectional structure along the A-A' direction;

[0039] Fig.23 yes Figure 1 Another schematic diagram of the cross-sectional structure along the A-A' direction;

[0040] Fig.24 yes Figure 1 Another schematic diagram of the cross-sectional structure along the A-A' direction;

[0041] Fig.25 yes Figure 1 Another schematic diagram of the cross-sectional structure along the A-A' direction;

[0042] Fig.26 is another schematic diagram of a planar structure of a display panel provided by an embodiment of the present invention;

[0043] Fig. 27 yes Fig.26 A schematic diagram of a cross-sectional structure along the D-D' direction;

[0044] Fig.28 yes Fig.26 Another cross-sectional structure schematic diagram along the D-D' direction;

[0045] Fig.29 yes Fig.26 Another cross-sectional structure schematic diagram along the D-D' direction;

[0046] Fig.30 yes Fig.26 A schematic diagram of a cross-sectional structure along the F-F' direction;

[0047] Fig.31 is another schematic diagram of a planar structure of a display panel provided by an embodiment of the present invention;

[0048] Fig.32 yes Fig.31 A schematic diagram of a cross-sectional structure along the E-E' direction;

[0049] Fig.33 yes Fig.26 Another cross-sectional structure schematic diagram along the D-D' direction;

[0050] Fig.34 yes Fig.26 Another cross-sectional structure schematic diagram along the D-D' direction;

[0051] Fig.35 yes Fig.26 Another cross-sectional structure schematic diagram along the D-D' direction;

[0052] Fig.36 yes Fig.26 Schematic diagram of the local planar structure of the middle J3 area;

[0053] Fig.37 yes Fig.26 Another local planar structure diagram of the J3 region;

[0054] Fig.38 yes Fig.26 Another cross-sectional structure schematic diagram along the D-D' direction;

[0055] Fig.39 yes Fig.26 Another cross-sectional structure schematic diagram along the D-D' direction;

[0056] Fig.40 It is a schematic diagram of the planar structure of a display device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0057] In order to more clearly understand the above-mentioned objectives, features and advantages of the present disclosure, the scheme of the present disclosure will be further described below. It should be noted that the embodiments of the present disclosure and the features in the embodiments can be combined with each other without conflict.

[0058] In the following description, many specific details are set forth to facilitate a full understanding of the present disclosure, but the present disclosure may also be implemented in other ways different from those described herein; it is obvious that the embodiments in the specification are only part of the embodiments of the present disclosure, rather than all of the embodiments.

[0059] Please refer to Figure 1 and Figure 2 , Figure 1 is a schematic diagram of a planar structure of a display panel provided by an embodiment of the present invention, Figure 2 yes Figure 1 A schematic cross-sectional structure diagram along the line AA' in FIG. 1 , a display panel 000 provided in this embodiment includes:

[0060] Substrate 10;

[0061] The driving array layer 20 is located on one side of the substrate 10;

[0062] A first planarization layer 30 is located on a side of the driving array layer 20 away from the substrate 10;

[0063] A first conductive layer 40 is located on a side of the first planarization layer 30 away from the substrate 10 , and the first conductive layer 40 includes a plurality of electrodes 401 ;

[0064] A second planarization layer 50 is located on a side of the first conductive layer 40 away from the substrate 10 . The second planarization layer 50 includes a plurality of first openings 50K. The first openings 50K penetrate the second planarization layer 50 .

[0065] Along a direction Z perpendicular to the plane where the substrate 10 is located, the first opening 50K exposes at least a portion of the electrode 401 .

[0066] Specifically, the display panel 000 provided in this embodiment can be a micro light-emitting diode (micro LED) display panel or a sub-millimeter light-emitting diode (mini LED) display panel. The film structure of the display panel 000 includes a substrate 10. The substrate 10 can be used as a carrier substrate of the display panel 000, and is used to make and set the remaining structures of the display panel 000 on the substrate 10. For example, in this embodiment, the substrate 10 is used to make a film structure such as a drive array layer 20, a first planarization layer 30, a first conductive layer 40, and a second planarization layer 50 located on one side of the substrate 10. The first planarization layer 30 is located on the side of the drive array layer 20 away from the substrate 10. The first planarization layer 30 can be an organic film layer. The drive array layer 20 is generally used to set circuits and signal line structures such as thin film transistors 20T that drive the light-emitting device to emit light. Therefore, the surface of the drive array layer 20 away from the substrate 10 can be flattened by the first planarization layer 30. It can be understood that the drive array layer 20 of this embodiment can be a combination of multiple metal conductive layers and multiple inorganic layers, or a combination of multiple metal conductive layers and multiple inorganic layers or organic layers. This embodiment does not limit this. During specific implementation, the film layer of the drive array layer 20 can be set according to the actual design requirements of the panel. Figure 2 As shown, the driving array layer 20 may include a gate metal layer 200-1 where the gate of the thin film transistor 20T is located, a source and drain metal layer 200-2 where the source and drain of the thin film transistor 20T are located, a capacitor metal layer 200-3 where the capacitor plate is located, and a semiconductor layer 200-4 where the active part of the thin film transistor 20T is located. Conductive layers such as the inorganic layer or organic layer between adjacent conductive layers, etc., of this embodiment Figure 2 This is only an example. In specific implementation, the film structure of the driving array layer 20 includes but is not limited to this.

[0067] The first conductive layer 40 of the present invention is located on the side of the first planarization layer 30 away from the substrate 10, and the first conductive layer 40 includes a plurality of electrodes 401. It can be understood that in this embodiment, the plurality of electrodes 401 can be located outside the frame of the display panel 000, for transmitting the driving signal provided by the subsequent bound driving chip or flexible circuit board, or the plurality of electrodes 401 can also be located in the non-frame area of ​​the display panel 000 (which can be understood as the display area or light-emitting area of ​​the display panel 000), that is, the plurality of electrodes 401 can be binding electrodes, which are used to transmit the signal driving the light-emitting device to emit light to the subsequent bound light-emitting device after the light-emitting device is bound and bonded to the electrode 401. This embodiment is schematically explained by taking the electrode 401 as a binding electrode as an example. It can be understood that the drive array layer 20 in this embodiment can include a structure of a plurality of conductive film layers and a plurality of insulating layers, and the drive array layer 20 can be understood as a film layer for making a drive circuit structure for driving the light-emitting device to emit light. The first planarization layer 30 of the present embodiment is located on the side of the first conductive layer 40 facing the substrate 10, so that before the first conductive layer 40 is manufactured, the first planarization layer 30 can flatten the surface of the drive array layer 20 on the side away from the substrate 10, and the surface of the substrate is as flat as possible. The first conductive layer 40 is manufactured on the first planarization layer 30 with high flatness, which can effectively ensure the flatness of the electrode 401, and facilitate improving the bonding stability of the light-emitting device subsequently bonded to the electrode 401.

[0068] Optionally, the first conductive layer 40 in this embodiment may be made of a metal material or a transparent conductive material, which is not limited in this embodiment, and it is only required that the first conductive layer 40 has conductive properties.

[0069] Optional, such as Figure 2 As shown, the drive array layer 20 can be made into a circuit structure such as a thin film transistor 20T that drives the light-emitting device to emit light. The source or drain of the thin film transistor 20T can be electrically connected to the anode pin 601 of the light-emitting device 60 through the electrode 401, and the cathode pin 602 of the light-emitting device 60 can be electrically connected to the cathode signal line (not shown in the figure) in the display panel 000 through the electrode 401. The drive array layer 20 can also include a plurality of conductive signal lines (such as scanning signal lines, data signal lines, power signal lines, etc.) to achieve the transmission of driving signals to each light-emitting device 60 and drive the normal light-emitting display effect of the light-emitting device 60 ( Figure 1Different filling patterns are used to represent light-emitting devices of different colors). The light-emitting device 60 of this embodiment can be a light-emitting device such as a micro LED or a mini LED. In specific implementation, the light-emitting device 60 can be transferred to a substrate on which the film layers such as the drive array layer 20 and the first conductive layer 40 have been manufactured by means of a mass transfer technology, so that the anode pin 601 and the cathode pin 602 of the light-emitting device 60 are respectively electrically connected to the electrode 401 of the first conductive layer 40 on the substrate, thereby realizing the drive circuit structure of the drive array layer 20 to drive the light-emitting device 60 to emit light, thereby realizing the display function.

[0070] Optionally, the packaging form of the light emitting device 60 in the display panel 000 of this embodiment can be a horizontal light emitting chip. In specific implementation, the packaging form of the light emitting device 60 can also be a vertical light emitting chip. This embodiment does not limit this. Figure 2 The light emitting device 60 is merely illustrated by taking the packaging form of a horizontal light emitting chip as an example.

[0071] Optionally, the light emitting device 60 of this embodiment can be electrically bonded by setting a conductive structure such as solder or eutectic layer (not shown in the figure) between the electrode 401 and the anode pin 601 and cathode pin 602 of the light emitting device 60. When the light emitting device 60 is transferred, the cathode pin 602 and the anode pin 601 of the light emitting device 60 can be aligned with the electrode 401 on the display substrate by a micro-stamp, and the conductive structure such as solder or eutectic layer can be pressed by the downward pressing action of the micro-stamp, thereby achieving electrical bonding between the light emitting device 60 and the electrode 401. It can be understood that the eutectic layer can be made of a high melting point eutectic material, such as a eutectic material of solder and silver or gold.

[0072] It is understandable that the first conductive layer 40 of this embodiment may include not only multiple electrodes 401, but also other patterned conductive structures, such as signal traces, a plate structure of a capacitor, etc. Therefore, after the first conductive layer 40 is patterned, its surface away from the substrate 10 has a relatively obvious concave-convex structure.

[0073] In this embodiment, a second planarization layer 50 is further provided on the side of the patterned first conductive layer 40 away from the substrate 10. The material of the second planarization layer 50 can be the same as that of the first planarization layer 30, that is, the second planarization layer 50 can be an organic film layer to flatten the surface of the first conductive layer 40 away from the substrate 10, so that the surface of the patterned first conductive layer 40 can be covered by the second planarization layer 50 of organic material, which plays a role in flattening the surface of the first conductive layer 40, that is, a large number of concave and convex structures presented by the patterned first conductive layer 40 can be flattened by the second planarization layer 50, which can improve the flatness problem of the substrate and is conducive to improving the performance of the substrate and the display effect. The second planarization layer 50 of this embodiment includes a plurality of first openings 50K, and the first openings 50K penetrate the second planarization layer 50. In the direction Z perpendicular to the plane where the substrate 10 is located, the first openings 50K expose at least part of the electrode 401, so as to facilitate the subsequent bonding of the light-emitting device 60 with the electrode 401 in the first openings 50K. In this embodiment, a second planarization layer 50 is disposed on a side of the first conductive layer 40 away from the substrate 10. The high flatness of the second planarization layer 50 can improve the flatness of the substrate, ensure the reliability of the substrate performance, and enhance the display effect.

[0074] Optionally, in order to ensure the planarization effect of the second planarization layer 50, the thickness D2 of the second planarization layer 50 in the direction Z perpendicular to the plane where the substrate 10 is located can be set to a range of 0.5-3.5 um, so as to avoid the second planarization layer 50 being too thin and the flatness performance cannot be guaranteed, and to avoid the second planarization layer 50 being too high due to the thickness of the second planarization layer 50, thereby affecting the subsequent binding and bonding of the light-emitting device and the electrode 401. Therefore, the thickness D2 of the second planarization layer 50 in the direction Z perpendicular to the plane where the substrate 10 is located is set to a range of 0.5-3.5 um, which can ensure the flattening effect of the second planarization layer 50 while ensuring that the setting of the second planarization layer 50 does not affect the subsequent binding and bonding effect of the light-emitting device and the electrode 401.

[0075] It should be noted that the figure of this embodiment only illustrates the structure of the display panel by way of example. In specific implementation, the structure of the display panel includes but is not limited to this, and may also include other structures that can realize the display function. For details, please refer to the structure of the mini LED or micro LED display panel in the related technology for understanding, and this embodiment will not be elaborated here.

[0076] like Figure 3 and Figure 4 As shown, Figure 3 is a schematic diagram of a partial planar structure of a display panel provided by an embodiment of the present invention, Figure 4 yes Figure 3Schematic diagram of the cross-sectional structure along the B-B' direction (in order to clearly illustrate the partial plan view of the display panel, Figure 3 The ink encapsulation layer is not shown in FIG. Figure 4 In the structure of the display panel 000 shown, the electrode 401 structure of the first conductive layer 40 is mainly used to supply power to the cathode pin of the corresponding light-emitting device through the electrode 401 and to supply power to the anode pin of the corresponding light-emitting device through the electrode 401. The first conductive layer 40 generally has a large number of through holes 40K to prevent surface film peeling during the manufacturing process. The presence of the through holes 40K makes the surface of the patterned first conductive layer 40 present more concave-convex structures. Figure 4 In the embodiment, an inorganic dielectric layer 01 such as a PV layer is used on the first conductive layer 40 to protect the patterned first conductive layer 40, and the light emitting device 60 is bonded to the electrode 401 through a giant transfer process, and then ink packaging is performed, that is, the ink packaging layer 02 is located on the side of the inorganic dielectric layer 01 away from the substrate 10. Ink packaging can reduce the reflection of the display panel to the ambient light, play a role in reducing reflection, and also avoid color crosstalk between adjacent light emitting devices. However, the inorganic dielectric layer 01 is generally thin and has limited flattening ability, resulting in the presence of a graphic concave-convex structure on the upper surface of the substrate (such as Figure 4 The dotted circle J1 indicates that it is difficult to achieve high flatness on the upper surface of the substrate. When the substrate is packaged with ink, this concave-convex structure affects the diffusion speed and coverage of the ink during packaging, thereby reducing the packaging reliability.

[0077] therefore Figure 3 and Figure 4 In the provided display panel, the patterned first conductive layer presents a large number of concave-convex structures. Subsequently, the applicant discovered that when the display panel is encapsulated with ink, the large number of concave-convex structures presented by the patterned first conductive layer will affect the diffusion speed and covering ability of the ink during the ink encapsulation, affect the ink encapsulation process on the substrate surface, and further affect the ink encapsulation reliability, which is likely to cause the display effect to be less than expected. Although Figure 4 As shown, an inorganic dielectric layer is used to cover the patterned metal layer on the top of the display substrate. However, the thickness of the inorganic dielectric layer is relatively thin, and its planarization effect is limited.

[0078] Therefore, the second planarization layer 50 provided in this embodiment is located on the side of the patterned first conductive layer 40 away from the substrate 10. The second planarization layer 50 may be an organic film layer to flatten the surface of the first conductive layer 40 away from the substrate 10, so that the surface of the patterned first conductive layer 40 can be covered by the second planarization layer 50 of organic material, which plays a role in flattening the surface of the first conductive layer 40. The high flatness performance of the second planarization layer 50 can improve the flatness problem of the substrate. Since a surface with high flatness is conducive to improving the diffusion speed and covering ability of ink, the provision of the second planarization layer 50 can improve the subsequent ink packaging quality of the substrate away from the substrate 10, ensure the reliability of the subsequent substrate ink packaging, and improve the display effect.

[0079] In some optional embodiments, please continue to refer to Figure 1 and Figure 2 In this embodiment, along the direction Z perpendicular to the plane where the substrate 10 is located, the thickness D2 of the second planarization layer 50 is less than the thickness D1 of the first planarization layer 30, and the thickness D2 of the second planarization layer 50 is greater than the thickness D01 of the first conductive layer 40.

[0080] This embodiment explains that along the direction Z perpendicular to the plane where the substrate 10 is located, the thickness D2 of the second planarization layer 50 is less than the thickness D1 of the first planarization layer 30. Since the first planarization layer 30 is used to flatten the surface of the drive array layer 20 away from the substrate 10, the thickness D1 of the first planarization layer 30 can be set larger to ensure the flatness of the side of the drive array layer 20 away from the substrate 10. The thickness D2 of the second planarization layer 50 is used to flatten the surface of the first conductive layer 40 away from the substrate 10, so that the surface of the patterned first conductive layer 40 can be covered by the second planarization layer 50 of organic material, which plays a role in flattening the surface of the first conductive layer 40. However, the first opening 50K of the second planarization layer 50 exposes at least a portion of the electrode 401. The subsequent light-emitting device 60 is bound and bonded to the electrode 401 in the first opening 50K. In order to avoid the thickness D2 of the second planarization layer 50 affecting the rotation and bonding process of the light-emitting device 60, the thickness D2 of the second planarization layer 50 should not be too thick, that is, the thickness D1 of the second planarization layer 50 is less than the thickness D1 of the first planarization layer 30. The second planarization layer 50 can improve the flatness of the substrate while ensuring the rotation and bonding process when the subsequent light-emitting device 60 is bound.

[0081] Optionally, the thickness of the first planarization layer 30 is D1, the thickness of the second planarization layer 50 is D2, 1 / 2D1<D2<4 / 5D1, and the thickness of the second planarization layer 50 is set between 1 / 2 of the thickness D1 of the first planarization layer 30 and 4 / 5 of the thickness D1 of the first planarization layer 30, so as to avoid the second planarization layer 50 being too thin and the flatness performance not being guaranteed, and also to avoid the second planarization layer 50 being too thick and causing the height of the second planarization layer 50 to be too high, thereby affecting the subsequent binding and bonding of the light-emitting device and the electrode 401. Therefore, while ensuring the flatness effect of the second planarization layer 50, it can also be ensured that the setting of the second planarization layer 50 does not affect the subsequent binding and bonding effect of the light-emitting device and the electrode 401.

[0082] In this embodiment, the thickness D2 of the second planarization layer 50 is set to be greater than the thickness D01 of the first conductive layer 40, so that when the second planarization layer 50 is produced on the side of the first conductive layer 40 away from the substrate 10, the second planarization layer 50 can better cover the patterned first conductive layer 40, thereby ensuring the flattening effect on the first conductive layer 40.

[0083] In some optional embodiments, please continue to refer to Figure 1 and Figure 2 In this embodiment, the display panel 000 further includes a second conductive layer 20A, which may be a conductive layer in the drive array layer 20, and is located on a side of the first planarization layer 30 close to the substrate 10; wherein,

[0084] Along a direction Z perpendicular to the plane where the substrate 10 is located, a thickness D02 of the second conductive layer 20A is smaller than a thickness D01 of the first conductive layer 40 .

[0085] This embodiment explains that the driving array layer 20 may include a patterned second conductive layer 20A, and the second conductive layer 20A may be understood as a conductive layer in the driving array layer 20 that is closest to the first conductive layer 40. The second conductive layer 20A is located on the side of the first planarization layer 30 that is close to the substrate 10. The first planarization layer 30 is used to planarize the patterned first conductive layer 40, and plays a role in planarizing the surface of the driving array layer 20 that is away from the substrate 10. The first conductive layer 40 is manufactured on the first planarization layer 30 with high flatness, which can effectively ensure the flatness of the electrode 401, and is convenient for improving the bonding stability of the light-emitting device subsequently bonded to the electrode 401. Since the thickness D1 of the first planarization layer 30 is greater than the thickness of the second planarization layer 50, and the thickness D02 of the second conductive layer 20A is less than the thickness D01 of the first conductive layer 40, of the first conductive layer 40 and the second conductive layer 20A, the second conductive layer 20A with a smaller thickness can be flattened by the first planarization layer 30 with a larger thickness, and the first conductive layer 40 with a larger thickness needs to be flattened by the second planarization layer 50 with a smaller thickness, so as to ensure that the second planarization layer 50 has a flattening effect while ensuring that the setting of the second planarization layer 50 does not affect the subsequent binding and bonding effect between the light-emitting device and the electrode 401.

[0086] Optional, such as Figure 1 and Figure 5 As shown, Figure 5 yes Figure 1 Another cross-sectional structural schematic diagram along the line A-A', in this embodiment, the display panel 000 may further include a third planarization layer 70, the third planarization layer 70 is located on a side of the first planarization layer 30 close to the substrate 10, and a thickness D3 of the third planarization layer 70 is greater than a thickness D2 of the second planarization layer 50;

[0087] The drive array layer 20 may further include a fourth conductive layer 20B, which is located on the side of the second conductive layer 20A close to the substrate 10. If the second conductive layer 20A is used to make a driving signal line such as a power signal line, the fourth conductive layer 20B may be used to make structures such as the source and drain of the thin film transistor 20T. The second conductive layer 20A may also be used to make structures such as the conductive portion of the drain of the thin film transistor 20T electrically connected to the electrode 401. The third planarization layer 70 is located on the side of the first planarization layer 30 close to the substrate 10. The third planarization layer 70 may be located on the side of the fourth conductive layer 20B away from the substrate 10. The third planarization layer 70 is used to play the role of flattening the patterned fourth conductive layer 20B. The thickness D3 of the third planarization layer 70 in this embodiment may be greater than the thickness D2 of the second planarization layer 50 to ensure the flatness of the film layer by the third planarization layer 70. Further optionally, the thickness D03 of the fourth conductive layer 20B can be smaller than the thickness D01 of the first conductive layer 40. Among the first conductive layer 40 and the fourth conductive layer 20B, the fourth conductive layer 20B with a smaller thickness can be flattened with a third planarization layer 70 with a larger thickness, and the first conductive layer 40 with a larger thickness needs to use a second planarization layer 50 with a smaller thickness to ensure that the second planarization layer 50 has a flattening effect while ensuring that the setting of the second planarization layer 50 does not affect the subsequent binding and bonding effect between the light-emitting device and the electrode 401.

[0088] Optionally, the driving array layer 20 of the display panel 000 in this embodiment may further include a fifth conductive layer 20C, which is located on the side of the semiconductor layer where the active part of the thin film transistor 20T is located facing the substrate 10, and the fifth conductive layer 20C may be used for making the bottom gate of the thin film transistor 20T. If the driving circuit of the display panel 000 (such as a pixel circuit or other display driving circuit) includes a dual-gate transistor, the bottom gate of the thin film transistor 20T may be located in the fifth conductive layer 20C; or the fifth conductive layer 20C where the bottom gate of the thin film transistor 20T is located may also be used for light shielding to shield the active part of the thin film transistor 20T, to prevent the light on one side of the substrate 10 from shining on the active part to generate carriers, and thus affect the off-state current characteristics of the thin film transistor 20T, which is beneficial to ensure the driving effect of the thin film transistor 20T in the driving circuit and to ensure the display quality.

[0089] In some optional embodiments, please refer to Figure 1 , Figure 6 and Figure 7 , Figure 6 yes Figure 1 Another cross-sectional structure schematic diagram along the A-A' direction, Figure 7 yes Figure 6A schematic diagram of a top view of the first opening, the second opening, and the electrode (it can be understood that in order to clearly illustrate the positional relationship between the first opening and the second opening and the electrode in this embodiment, Figure 7 In the present embodiment, the display panel 000 further includes a first passivation layer 80, and the first passivation layer 80 is located on a side of the second planarization layer 50 away from the substrate 10;

[0090] The first passivation layer 80 includes a plurality of second openings 80K, and the orthographic projections of the second openings 80K on the substrate 10 are located within the orthographic projection range of the first openings 50K on the substrate 10;

[0091] Surrounding the first opening 50K, the second planarization layer 50 at least covers a portion of the electrode 401 in a direction perpendicular to the plane where the substrate 10 is located;

[0092] Surrounding the second opening 80K, the first passivation layer 80 covers the second planarization layer 50 in a direction perpendicular to the plane where the substrate 10 is located.

[0093] This embodiment explains that the film structure of the display panel 000 also includes a first passivation layer 80 located on the side of the second planarization layer 50 away from the substrate 10. The first passivation layer 80 can be an inorganic film layer. The first passivation layer 80 is used to protect the film layer of the display panel 000, especially to protect the second planarization layer 50 of the organic material, and has a protective effect of isolating water and oxygen corrosion. In this embodiment, the first passivation layer 80 includes a plurality of second openings 80K, and the orthographic projections of the second openings 80K on the substrate 10 are located within the orthographic projection range of the first openings 50K on the substrate 10, that is, the orthographic projection area of ​​the second openings 80K on the substrate 10 is smaller than the orthographic projection area of ​​the first openings 50K on the substrate 10, so that along the direction surrounding the second openings 80K (if the second openings 80K are square, this direction refers to surrounding the square edge; if the second openings 80K are circular, this direction refers to surrounding the circular edge), the first passivation layer 80 covers the second planarization layer 50 in a direction perpendicular to the plane where the substrate 10 is located, and the second openings 80K are used to expose at least part of the electrode 401, so that the subsequent light-emitting device 60 is bonded to the electrode 401 in the overlapping first openings 50K and second openings 80K; the orthographic projections of the second openings 80K on the substrate 10 are located within the orthographic projection range of the first openings 50K on the substrate 10, so that the first passivation layer 80 can completely cover and protect the second planarization layer 50, thereby improving the effect of isolating the substrate from water and oxygen corrosion.

[0094] Optional, such as Figure 6As shown, in this embodiment, the second opening 80K opened in the first passivation layer 80 and the first opening 50K opened in the second planarization layer 50 may have sloped side walls, which is beneficial for improving the leveling performance of the ink when the ink is subsequently packaged on the side of the first passivation layer 80 away from the substrate 10, thereby ensuring the reliability of the ink packaging.

[0095] The present embodiment further provides a direction around the first opening 50K (if the first opening 50K is square, this direction refers to around the edge of the square; if the first opening 50K is circular, this direction refers to around the edge of the circular; the orthographic projection shapes of the first opening 50K and the second opening 80K on the plane where the substrate 10 is located are consistent), and the second planarization layer 50 at least covers a portion of the electrode 401 in a direction perpendicular to the plane where the substrate 10 is located, that is, although the second planarization layer 50 is provided with the first opening 50K that penetrates the thickness of the second planarization layer 50 to expose a portion of the electrode 401, the second planarization layer 50 at least covers a portion of the electrode 401 in a direction perpendicular to the plane where the substrate 10 is located (such as Figure 6 As shown, at least the edge area around the electrode 401 is covered to provide a covering and protective effect on the edge area of ​​the electrode 401 .

[0096] Optionally, in this embodiment, a first passivation layer 80 is provided on the side of the second planarization layer 50 away from the substrate 10, and a portion of the electrode 401 is exposed by overlapping the orthographic projection of the first opening 50K of the second planarization layer 50 on the substrate 10 and the orthographic projection of the second opening 80K of the first passivation layer 80 on the substrate 10, so as to facilitate the subsequent bonding of the light-emitting device 60 to the electrode 401. The ink encapsulation process can be performed after the light-emitting device 60 is bonded to the electrode 401. In this embodiment, the surface of the first passivation layer 80 away from the substrate 10 needs to be set to be lower than the surface of the light-emitting device 60 away from the substrate 10, that is, after the second planarization layer 50 and the first passivation layer 80 are made on the first conductive layer 40 where the electrode 401 is located, the thickness of the two should not be too large, so as to avoid the surface of the first passivation layer 80 away from the substrate 10 being too high when the light-emitting device 60 is subsequently transferred by the giant transfer process, which affects the giant transfer and bonding process. Optionally, after the light-emitting device 60 is bound to the electrode 401 exposed by the first opening 50K and the second opening 80K, the surface of the light-emitting device 60 away from the substrate 10 needs to be higher than the surface of the first passivation layer 80 away from the substrate 10, so as to avoid the first passivation layer 80 and the second planarization layer 50 after stacking being too high to affect the process yield, which is beneficial to improving the process yield of the entire display panel 000.

[0097] It can be understood that Figure 6 and Figure 7In the figure, the first opening 50K of the second planarization layer 50 corresponding to the two electrodes 401 of a light-emitting device 60 is used as an example for explanation, that is, a first opening 50K exposes the binding position of a light-emitting device 60, and the second opening 80K of the first passivation layer 80 not only needs to expose the electrode 401, but also needs to cover at least the edge area of ​​the two electrodes 401. Therefore, the two electrodes 401 of a light-emitting device 60 need to correspond to the two second openings 80K of the first passivation layer 80 respectively, so that a partial area between the two electrodes 401 of a light-emitting device 60 can be covered and protected by the first passivation layer 80.

[0098] Optional, such as Figure 1-Figure 2 , Figure 5-Figure 6 As shown, in this embodiment, the first planarization layer 30 is located on the side of the driving array layer 20 away from the substrate 10, and the first planarization layer 30 is used to flatten the surface of the driving array layer 20 away from the substrate 10, so that the first conductive layer 40 made on the first planarization layer 30 can ensure high flatness as much as possible. The second planarization layer 50 is located on the side of the first conductive layer 40 away from the substrate 10, and after the second planarization layer 50 covers the electrode 401 of the patterned first conductive layer 40, outside the range of the electrode 401, the second planarization layer 50 and the first planarization layer 30 are in direct contact, that is, there is no other film layer between the second planarization layer 50 and the first planarization layer 30 except the first conductive layer 40, which is conducive to achieving the effect that the concave-convex structure presented by the patterned first conductive layer 40 can be flattened by the second planarization layer 50, and it can also avoid the existence of other film layers between the second planarization layer 50 and the first planarization layer 30 to affect the overall thickness of the display panel 000, which is conducive to achieving a thin design.

[0099] In some optional embodiments, please refer to Figure 1 and Figure 8 , Fig. 9 , Figure 8 yes Figure 1 A schematic diagram of a cross-sectional structure along the C-C' direction, Fig. 9 yes Figure 8 A schematic diagram of a top view of the first opening, the second opening, and the electrode (it can be understood that in order to clearly illustrate the positional relationship between the first opening and the second opening and the electrode in this embodiment, Fig. 9 In the embodiment, in the direction Z perpendicular to the plane where the substrate 10 is located, one first opening 50K corresponds to one electrode 401, and one second opening 80K corresponds to one electrode 401.

[0100] This embodiment explains that in the film structure of the display panel 000, a second planarizing layer 50 is provided on top of the patterned first conductive layer 40 to planarize a large number of concave-convex structures formed after the patterned first conductive layer 40 is formed, and then the second planarizing layer 50 is covered and protected by the first passivation layer 80. The first opening 50K for exposing the electrode 401 provided in the second planarizing layer 50 and the second opening 80K for exposing the electrode 401 provided in the first passivation layer 80 may correspond to the electrode 401 in a one-to-one relationship, specifically, in the direction Z perpendicular to the plane where the substrate 10 is located, one first opening 50K corresponds to one electrode 401, and one second opening 80K corresponds to one electrode 401. For an integrated chip of a light-emitting device 60 with a larger size, due to the larger size, the spacing between the anode pin 601 and the cathode pin 602 of the light-emitting device 60 is larger, so it can be designed in a manner that each binding bonding point, i.e., each electrode 401, corresponds to a first opening 50K, and each binding bonding point, i.e., each electrode 401, corresponds to a second opening 80K. As shown in FIG. Figure 8 and Fig. 9As shown, a first conductive layer 40 is fabricated above the driving array layer 20, and the first conductive layer 40 is patterned according to the positions of the anode pin 601 and the cathode pin 602 of the light-emitting device 60 to be bonded and bonded later, and an electrode 401 is formed at a corresponding position, and then the second planarization layer 50 is covered and flattened, and the second planarization layer 50 is subjected to a hole processing, and a first opening 50K is formed at the position of each electrode 401, so that the first opening 50K exposes the middle area of ​​each electrode 401, and the outer edge area of ​​each electrode 401 is covered and protected by the second planarization layer 50, and a first passivation layer 80 is further disposed on the second planarization layer 50 The second planarization layer 50 is covered and protected, and the first passivation layer 80 is opened to form a second opening 80K at the position of each first opening 50K, so that the first passivation layer 80 can cover the edge of the first opening 50K of the second planarization layer 50 and extend into the first opening 50K to ensure that the surface of the second planarization layer 50 can be completely covered and protected by the first passivation layer 80, and then the corresponding light-emitting device 60 is transferred and bonded on the electrode 401 to realize the electrical connection between the anode pin 601 of the light-emitting device 60 and the electrode 401, and the electrical connection between the cathode pin 602 of the light-emitting device 60 and the electrode 401. In this embodiment, a first opening 50K of the second planarization layer 50 is set to correspond to one electrode 401, so that the area of ​​each first opening 50K for exposing the electrode 401 in the entire second planarization layer 50 can be smaller. A second opening 80K of the first passivation layer 80 is set to correspond to one electrode 401, so that the area of ​​each second opening 80K for exposing the electrode 401 in the entire first passivation layer 80 can be smaller, that is, the area of ​​each recess on the upper surface of the substrate is smaller, which has little impact on the overall flatness of the substrate surface, which is beneficial to improving the leveling of the ink in the subsequent ink packaging process and ensuring the packaging reliability.

[0101] It can be understood that the present embodiments are all illustrated by taking the packaging form of the light-emitting device 60 as a horizontal light-emitting chip as an example. In specific implementation, when the present embodiment is arranged in the direction Z perpendicular to the plane where the substrate 10 is located, a first opening 50K corresponds to an electrode 401, and a second opening 80K corresponds to an electrode 401. The packaging form of the light-emitting device 60 can also be a vertical light-emitting chip, which is not elaborated in this embodiment.

[0102] Optional, such as Figure 8As shown, in this embodiment, the second opening 80K opened in the first passivation layer 80 and the first opening 50K opened in the second planarization layer 50 can have sloped sidewalls, which is beneficial to improve the leveling performance of the ink and ensure the reliability of the ink packaging when the ink is subsequently packaged on the side of the first passivation layer 80 away from the substrate 10. In the two electrodes 401 corresponding to the light-emitting device 60, the inclination angle of the sloped sidewall of the first opening 50K can be consistent along the direction from one electrode 401 to the other electrode 401, such as Figure 8 The acute angles α1, α2, α3 and α4 shown in the figure can be the same, so as to simplify the process and improve the process efficiency. In order to improve the leveling of the ink package, the inclination angle of the sloped side wall of the first opening 50K can be set to be smaller, that is, the slope gradient at the first opening 50K is as gentle as possible, which is beneficial to ensure the leveling of the ink at the first opening 50K during ink packaging and improve the packaging reliability.

[0103] In some optional embodiments, please refer to Figure 1 and Fig.10 , Fig.10 yes Figure 1 Another cross-sectional structural schematic diagram along the C-C' direction, in this embodiment, the display panel 000 also includes a plurality of light-emitting devices 60, taking the packaging form of the light-emitting device 60 as a horizontal light-emitting chip as an example, the light-emitting device 60 is electrically connected to at least two electrodes 401, and the light-emitting device 60 is electrically connected to the drive array layer 20 through the electrode 401; optionally, the anode pin 601 of the light-emitting device 60 is electrically connected to the drain of a thin film transistor 20T of the drive array layer 20 through an electrode 401, and the anode signal power supply line provided by the drive array layer 20 is provided to the anode pin 601 of the light-emitting device 60; the cathode pin 602 of the light-emitting device 60 is electrically connected to the cathode signal power supply line of the drive array layer 20 through another electrode 401, and the cathode signal is provided to the cathode pin 602 of the light-emitting device 60 through the cathode signal power supply line;

[0104] In the two electrodes 401 of a light emitting device 60, the direction from one electrode 401 to the other electrode 401 (eg Fig.10 In the direction G1 shown in FIG. 1 , the first opening 50K includes a first slope 50K1 close to the edge 60L of the light emitting device 60 and a second slope 50K2 away from the edge 60L of the light emitting device 60;

[0105] The angle formed by the first slope 50K1 and the plane where the substrate 10 is located is an acute angle A, and the angle formed by the second slope 50K2 and the plane where the substrate 10 is located is an acute angle B. The acute angle A is smaller than the acute angle B.

[0106] This embodiment explains that the second opening 80K opened in the first passivation layer 80 and the first opening 50K opened in the second planarization layer 50 can have sloped sidewalls, which is beneficial to improve the leveling performance of the ink and ensure the reliability of the ink packaging when the ink is subsequently packaged on the side of the first passivation layer 80 away from the substrate 10. In the two electrodes 401 corresponding to the light-emitting device 60, the inclination angles of the sloped sidewalls of the first opening 50K can be inconsistent along the direction from one electrode 401 to the other electrode 401, such as Fig.10 In the two electrodes 401 of a light emitting device 60 shown in FIG. Fig.10 In the direction G1 indicated in the figure, the first opening 50K includes a first slope 50K1 close to the edge 60L of the light-emitting device 60 and a second slope 50K2 away from the edge 60L of the light-emitting device 60. The acute angle A formed by the first slope 50K1 and the plane where the substrate 10 is located is smaller than the acute angle B formed by the second slope 50K2 and the plane where the substrate 10 is located. That is, in a first opening 50K corresponding to the light-emitting device 60, the first slope 50K1 of the outer first opening 50K is more gentle, and the second slope 50K2 of the inner first opening 50K can be slightly steeper, thereby ensuring that the ink has better leveling properties in the peripheral area of ​​the light-emitting device 60 during subsequent ink packaging, thereby improving the packaging effect.

[0107] Optional, please refer to Figure 1 and Fig.11 , Fig.11 yes Figure 1 Another cross-sectional structure schematic diagram along the A-A' direction in the embodiment, in this embodiment, the first conductive layer 40, the second planarization layer 50 and the first passivation layer 80 are formed above the drive array layer 20, and the electrodes 401, the first opening 50K and the second opening 80K are formed respectively, and the direction from one electrode 401 to another electrode 401 (such as Fig.11 In the direction G1 indicated in the figure, the minimum distance L1 between the edge 60L of the light-emitting device 60 and the second opening 80K needs to be greater than 3um, that is, the first passivation layer 80 opens the second opening 80K, so that after the first passivation layer 80 covers the second planarization layer 50, according to the size of the light-emitting device 60 to be bonded later, the edge of the first passivation layer 80 at the second opening 80K needs to have a certain distance relative to the edge 60L of the light-emitting device 60, thereby avoiding affecting the subsequent rotation and bonding process of the light-emitting device 60, which is beneficial to improving the process yield of rotation and bonding.

[0108] In some optional embodiments, please refer to Figure 1 and Fig.12 , Fig.12 yes Figure 1 Another cross-sectional structure schematic diagram of the C-C' direction (it can be understood that Fig.12 The positional relationship between the first opening and the second opening and the electrode in the top view can be referred to Figure 7 ), in this embodiment, the display panel 000 further includes a plurality of light-emitting devices 60, the light-emitting devices 60 are electrically connected to at least two electrodes 401, and the light-emitting devices 60 are electrically connected to the drive array layer 20 through the electrodes 401; optionally, an anode pin 601 of the light-emitting device 60 is electrically connected to a drain of a thin film transistor 20T of the drive array layer 20 through one electrode 401, and an anode signal power supply line provided by the drive array layer 20 is provided to the anode pin 601 of the light-emitting device 60; a cathode pin 602 of the light-emitting device 60 is electrically connected to a cathode signal power supply line of the drive array layer 20 through another electrode 401, and a cathode signal is provided to the cathode pin 602 of the light-emitting device 60 through the cathode signal power supply line;

[0109] In a direction Z perpendicular to the plane where the substrate 10 is located, one first opening 50K corresponds to two electrodes 401 electrically connected to one light emitting device 60 .

[0110] Optionally, in a direction Z perpendicular to the plane where the substrate 10 is located, one second opening 80K corresponds to one electrode 401;

[0111] Between two electrodes 401 electrically connected to one light emitting device 60 , the first passivation layer 80 covers the first planarization layer 30 and a portion of the electrode 401 .

[0112] This embodiment explains that in the film structure of the display panel 000, a second planarization layer 50 is provided on the patterned first conductive layer 40 to planarize a large number of concave-convex structures formed after the patterned first conductive layer 40 is patterned, and then the second planarization layer 50 is covered and protected by the first passivation layer 80. The first opening 50K for exposing the electrode 401 provided in the second planarization layer 50 may correspond to two electrodes 401 electrically connected to one light emitting device 60, and the second opening 80K for exposing the electrode 401 provided in the first passivation layer 80 may correspond to one electrode 401 one by one, specifically, in the direction Z perpendicular to the plane where the substrate 10 is located, one first opening 50K corresponds to two electrodes 401 electrically connected to one light emitting device 60, and one second opening 80K corresponds to one electrode 401. For an integrated chip of a light emitting device 60 with a smaller size, due to the smaller size, the spacing between the anode pin 601 and the cathode pin 602 of the light emitting device 60 is smaller. Due to the limitation of the process capability, it is no longer possible to set each electrode 401 in a one-to-one correspondence with the first opening 50K. Therefore, each light emitting device 60 may have two electrodes 401 electrically connected to each other corresponding to a first opening 50K, and the first passivation layer 80 may be designed such that each binding bonding point, i.e., each electrode 401, corresponds to a second opening 80K in order to fully cover and protect the second planarization layer 50 and the electrodes 401. Fig.12 and Figure 7As shown, a first conductive layer 40 is fabricated above the driving array layer 20, and the first conductive layer 40 is patterned according to the positions of the anode pin 601 and the cathode pin 602 of the light-emitting device 60 to be subsequently bound and bonded, and electrodes 401 are formed at corresponding positions, one light-emitting device 60 corresponds to two electrodes 401, and then the second planarization layer 50 is used to cover and flatten the second planarization layer 50, and the second planarization layer 50 is subjected to a hole-opening process, and a first opening 50K is formed at the position of the two electrodes 401 corresponding to each light-emitting device 60, so that the first opening 50K at least exposes a part of the two electrodes 401, and the outer edge regions on both sides of the two electrodes 401 are covered and protected by the second planarization layer 50, and a first passivation layer 80 is further disposed on the second planarization layer 50 to cover and protect the second planarization layer 50, and the first passivation layer 80 is subjected to a hole-opening process, and a second opening 80K is formed at the position of each electrode 401, The first passivation layer 80 is enabled to cover the edge of the first opening 50K of the second planarization layer 50 and extend into the first opening 50K, ensuring that the surface of the second planarization layer 50 can be completely covered and protected by the first passivation layer 80, and the two electrodes 401 electrically connected to the same light-emitting device 60 can also be covered by the first passivation layer 80, that is, between the two electrodes 401 electrically connected to the same light-emitting device 60, the first passivation layer 80 covers the first planarization layer 30 and part of the electrode 401, and the first passivation layer 80 plays a role in protecting the edge area of ​​the electrode 401, and can also cover and protect the exposed part of the first planarization layer 30; then, the corresponding light-emitting device 60 is transferred and bonded on the electrode 401 to realize the electrical connection between the anode pin 601 of the light-emitting device 60 and the electrode 401, and the electrical connection between the cathode pin 602 of the light-emitting device 60 and the electrode 401. In this embodiment, a first opening 50K of the second planarization layer 50 is arranged to correspond to the two electrodes 401 electrically connected to the light-emitting device 60. The second planarization layer 50 can play a leveling role to ensure the leveling of the ink during the subsequent ink packaging process, which is beneficial to the packaging reliability and can also simplify the process technology, reduce the process difficulty and improve the process efficiency.

[0113] In some optional embodiments, please refer to Fig.13 and Fig.14 , Fig.13 is another schematic diagram of a planar structure of a display panel provided by an embodiment of the present invention, Fig.14 yes Fig.13 A partial enlarged structural diagram of the J2 region in FIG. 1 (It can be understood that in order to clearly illustrate the structure of this embodiment, Fig.14 Transparency filling is performed), in this embodiment, the electrode 401 includes a first area 401A and a second area 401B;

[0114] The two electrodes 401 electrically connected to a light emitting device 60 are a first electrode 4011 and a second electrode 4012;

[0115] A first opening 50K includes a first sub-opening 50KA and a second sub-opening 50KB. In a direction Z perpendicular to the plane of the substrate 10, the first sub-opening 50KA exposes the first region 401A of the first electrode 4011 and the first region 401A of the second electrode 4012, and the second sub-opening 50KB exposes the second region 401B of the first electrode 4011 and the second region 401B of the second electrode 4012.

[0116] This embodiment explains that in the display panel 000, the electrode 401 used for binding and bonding with the pin of the light-emitting device 60 may include a first area 401A and a second area 401B, wherein the first area 401A of the electrode 401 can be understood as the position where the pin of the light-emitting device 60 is normally bound and bonded to the electrode 401, and the second area 401B can be understood as a preset redundant binding position. When the display panel is manufactured, the light-emitting device 60 such as micro LED or mini LED is generally transferred on the motherboard first, and then the motherboard is cut to form a display panel. After the display panel 000 is cut, a series of processing operations will be performed on the display panel 000. During the cutting and processing process, the light-emitting device 60 that has been transferred on the display panel 000 is very easy to be damaged, which easily reduces the yield of the display panel. Therefore, in this embodiment, the electrode 401 for binding and bonding with the pin of the light-emitting device 60 may include a first area 401A and a second area 401B. When the light-emitting device 60 is transferred, the normal binding and bonding of the pin of the light-emitting device 60 and the electrode 401 is first realized in the first area 401A. When it is found during the test process that the light-emitting device 60 at a certain position emits abnormal light and cannot emit light normally, the original light-emitting device 60 can be replaced through a repair process, and a new light-emitting device 60 or a repaired light-emitting device 60 can be placed in the second area 401B of the electrode 401 where the light-emitting device 60 has not been placed, thereby ensuring the yield of the product.

[0117] In this embodiment, the packaging form of the light-emitting device 60 is a horizontal light-emitting chip as an example, and the two electrodes 401 electrically connected to the light-emitting device 60 are defined as the first electrode 4011 and the second electrode 4012. Then, a first opening 50K opened in the second planarization layer 50 may include a first sub-opening 50KA and a second sub-opening 50KB. In the direction Z perpendicular to the plane where the substrate 10 is located, the first sub-opening 50KA exposes the first area 401A of the first electrode 4011 and the first area 401A of the second electrode 4012, that is, the first sub-opening 50KA of the first opening 50K can expose the two electrodes 401 electrically connected to the light-emitting device 60. The second sub-opening 50KB exposes the second region 401B of the first electrode 4011 and the second region 401B of the second electrode 4012, that is, the second sub-opening 50KB of the first opening 50K can expose the redundant binding position region of the two electrodes 401 electrically connected to a light-emitting device 60, so that the first opening 50K corresponds to a light-emitting device 60, and the first opening 50K can expose both the normal binding position of the two electrodes 401 electrically connected to a light-emitting device 60 and the redundant binding position of the two electrodes 401 electrically connected to a light-emitting device 60, so as to facilitate the normal transfer and repair of the subsequent light-emitting device 60. It can be understood that in order to clearly illustrate Fig.14 The structure in Fig.14 Only one light emitting device 60 is shown.

[0118] Optional, such as Fig.14 As shown, a first opening 50K of the present embodiment includes a first sub-opening 50KA and a second sub-opening 50KB, and the first sub-opening 50KA and the second sub-opening 50KB can be two independent sub-openings, that is, the opening of the second planarization layer 50 corresponding to the redundant binding position of the two electrodes 401 electrically connected to a light-emitting device 60 and the opening of the second planarization layer 50 corresponding to the normal binding position of the two electrodes 401 electrically connected to a light-emitting device 60 are independent of each other. Or as Fig.15 As shown, Fig.15 yes Fig.13 Another partial enlarged structural diagram of the J2 region (it can be understood that in order to clearly illustrate the structure of this embodiment, Fig.15Transparency filling is performed), a first opening 50K of the present embodiment includes a first sub-opening 50KA and a second sub-opening 50KB, and the first sub-opening 50KA and the second sub-opening 50KB can be interconnected, that is, an opening of the second planarization layer 50 corresponding to a redundant binding position of two electrodes 401 electrically connected to a light-emitting device 60 and an opening of the second planarization layer 50 corresponding to a normal binding position of two electrodes 401 electrically connected to a light-emitting device 60 are an integral first opening 50K, which is used to meet the requirement of exposing the two electrodes 401 corresponding to the light-emitting device 60. In specific implementation, the setting can be selected according to actual needs.

[0119] Optional, such as Fig.14 and Fig.15 As shown, in this embodiment, one electrode 401 can correspond to two second openings 80K opened in the first passivation layer 80. Specifically, the first area 401A of the first electrode 4011 can correspond to a second opening 80K, the second area 401B of the first electrode 4011 can correspond to a second opening 80K, the first area 401A of the second electrode 4012 can correspond to a second opening 80K, and the second area 401B of the second electrode 4012 can correspond to a second opening 80K, thereby ensuring the covering and protecting effect of the first passivation layer 80 on the second planarization layer 50, the electrode 401 and the first planarization layer 30.

[0120] Optional, such as Fig.16 As shown, Fig.16 yes Fig.13 Another partial enlarged structural diagram of the J2 region (it can be understood that in order to clearly illustrate the structure of this embodiment, Fig.16 Transparency filling is performed), in this embodiment, the second opening 80K opened in the first passivation layer 80 can still be in the relationship of one second opening 80K corresponding to one electrode 401, that is, the first area 401A and the second area 401B of the electrode 401 jointly correspond to one second opening 80K, thereby ensuring the covering and protecting effect of the first passivation layer 80 on the second planarization layer 50, the electrode 401 and the first planarization layer 30.

[0121] In some optional embodiments, please refer to Figure 1-Figure 2 , Fig.13 and Fig.17 , Fig.17 yes Figure 1 and Fig.13 Schematic diagram of the local area structure of the first conductive layer in the embodiment, in this embodiment, the first conductive layer 40 includes a plurality of through holes 40K, and the orthographic projections of the through holes 40K on the substrate 10 do not overlap with the orthographic projections of the first area 401A of the electrode 401 and the second area 401B of the electrode 401 on the substrate 10.

[0122] This embodiment explains that the first conductive layer 40 may include other patterned conductive structures in addition to a plurality of electrodes 401. The electrode structure of the first conductive layer 40 is mainly used to supply power to the cathode pin of the corresponding light-emitting device through the electrode 401 and to supply power to the anode pin of the corresponding light-emitting device through the electrode 401. The electrodes 401 (i.e., cathode binding electrodes) electrically connected to the cathode pins of different light-emitting devices 60 may be connected to form a whole surface structure (e.g., Fig.17 As shown in FIG. 1 , a large number of through holes 40K may be provided in the first conductive layer 40. Different through holes 40K may have different sizes and shapes. The provision of the through holes 40K may prevent peeling of the surface film layer in the manufacturing process of the first conductive layer 40. In this embodiment, the orthographic projection of the through holes 40K on the substrate 10 does not overlap with the orthographic projection of the first area 401A of the electrode 401 and the second area 401B of the electrode 401 on the substrate 10, which may prevent the light emitting device 60 from being unstable due to the presence of the through holes 40K when being bonded, thereby facilitating the product yield.

[0123] In some optional embodiments, please refer to Figure 1 and Fig.18 , Fig.19 , Fig.18 yes Figure 1 Another cross-sectional structure schematic diagram in the C-C' direction, Fig.19 yes Fig.18 A schematic diagram of a top view of the first opening, the second opening, and the electrode (it can be understood that in order to clearly illustrate the positional relationship between the first opening and the second opening and the electrode in this embodiment, Fig.19 In the embodiment, the display panel 000 further includes a plurality of light-emitting devices 60, the light-emitting devices 60 are electrically connected to at least two electrodes 401, and the light-emitting devices 60 are electrically connected to the drive array layer 20 through the electrodes 401; optionally, an anode pin 601 of the light-emitting device 60 is electrically connected to a drain of a thin film transistor 20T of the drive array layer 20 through an electrode 401, and an anode signal power supply line provided by the drive array layer 20 is used to provide an anode signal to the anode pin 601 of the light-emitting device 60; a cathode pin 602 of the light-emitting device 60 is electrically connected to a cathode signal power supply line of the drive array layer 20 through another electrode 401, and a cathode signal is provided to the cathode pin 602 of the light-emitting device 60 through the cathode signal power supply line;

[0124] In a direction Z perpendicular to the plane where the substrate 10 is located, one first opening 50K corresponds to three adjacent light emitting devices 60 of different colors.

[0125] Optionally, in a direction Z perpendicular to the plane where the substrate 10 is located, one second opening 80K corresponds to one electrode 401;

[0126] Between two electrodes 401 electrically connected to one light emitting device 60 and between two adjacent light emitting devices 60 , the first passivation layer 80 covers the first planarization layer 30 and a portion of the electrode 401 .

[0127] This embodiment explains that in the film structure of the display panel 000, a second planarization layer 50 is provided above the patterned first conductive layer 40 to planarize a large number of concave-convex structures formed after the patterned first conductive layer 40 is patterned, and then the second planarization layer 50 is covered and protected by the first passivation layer 80. The first opening 50K opened in the second planarization layer 50 for exposing the electrode 401 may correspond to six electrodes 401 electrically connected to three adjacent light-emitting devices 60 of different colors, that is, the first opening 50K may correspond to three light-emitting devices 60 of different colors included in a pixel unit, and the second opening 80K opened in the first passivation layer 80 for exposing the electrode 401 may correspond to one-to-one with the electrode 401, specifically, in the direction Z perpendicular to the plane where the substrate 10 is located, one first opening 50K corresponds to six electrodes 401 electrically connected to three adjacent light-emitting devices 60 of different colors, and one second opening 80K corresponds to one electrode 401. For display panels with high pixel density, smaller light-emitting devices are required, and the spacing between adjacent light-emitting devices needs to be minimized. Therefore, for integrated chips with smaller light-emitting devices 60, due to the smaller size, the spacing between the anode pin 601 and the cathode pin 602 of the light-emitting device 60 is smaller, and the spacing between adjacent light-emitting devices also needs to be smaller. Due to the limitation of process capabilities, it is no longer possible to set each electrode 401 in a one-to-one correspondence with the first opening 50K. Therefore, six electrodes 401 electrically connected to three light-emitting devices 60 of different colors in a pixel unit can correspond to one first opening 50K, and the first passivation layer 80 can be designed in such a way that each binding bonding point, that is, each electrode 401, corresponds to a second opening 80K separately in order to fully cover and protect the second planarization layer 50 and the electrode 401. Fig.18 and Fig.19As shown, a first conductive layer 40 is fabricated above the driving array layer 20, and the first conductive layer 40 is patterned according to the positions of the anode pin 601 and the cathode pin 602 of the light-emitting device 60 to be subsequently bound and bonded, and the electrodes 401 are formed at corresponding positions, one light-emitting device 60 corresponds to two electrodes 401, and then the second planarization layer 50 is used to cover and flatten the six electrodes 401 electrically connected to the three light-emitting devices 60 of different colors in a pixel unit. A larger first opening 50K is formed, so that the first opening 50K at least exposes a part of the six electrodes 401, and the outer edge regions on both sides of the two outermost electrodes 401 of the six electrodes 401 are covered and protected by the second planarization layer 50, and a first passivation layer 80 is further arranged on the second planarization layer 50 to cover and protect the second planarization layer 50, and the first passivation layer 80 is processed to open a hole, and a second opening 80K is formed at the position of each electrode 401, so that the first passivation layer 80 is The passivation layer 80 can cover the edge of the first opening 50K of the second planarization layer 50, and extend into the first opening 50K, ensuring that the surface of the second planarization layer 50 can be completely covered and protected by the first passivation layer 80, and the two electrodes 401 electrically connected to the same light-emitting device 60 can also be covered by the first passivation layer 80, that is, between the two electrodes 401 electrically connected to a light-emitting device 60, the first passivation layer 80 covers the first planarization layer 30 and part of the electrode 401, and between two adjacent light-emitting devices 60, the first passivation layer 80 also covers the first planarization layer 30 and part of the electrode 401. The first passivation layer 80 plays a role in protecting the edge area of ​​the electrode 401, and can also cover and protect the exposed part of the first planarization layer 30; then, the corresponding light-emitting device 60 is transferred and bonded on the electrode 401 to realize the electrical connection between the anode pin 601 of the light-emitting device 60 and the electrode 401, and the electrical connection between the cathode pin 602 of the light-emitting device 60 and the electrode 401. In this embodiment, a first opening 50K of the second planarization layer 50 is arranged to correspond to three light-emitting devices 60 of different colors in a pixel unit. The second planarization layer 50 can play a leveling role to ensure the leveling of the ink during the subsequent ink packaging process, which is beneficial to the packaging reliability and can also simplify the process technology, reduce the process difficulty and improve the process efficiency.

[0128] Optional, such as Fig.13 and Fig. 20 , Fig.21 As shown, Fig. 20 yes Fig.13 Another local enlarged structural diagram of the J2 area in the middle, Fig.21 yes Fig.13 Another partial enlarged structural diagram of the J2 region (it can be understood that in order to clearly illustrate the structure of this embodiment, Fig. 20 and Fig.21When the electrode 401 for bonding with the pin of the light-emitting device 60 in the display panel 000 includes a first area 401A and a second area 401B, wherein the first area 401A of the electrode 401 can be understood as the position where the pin of the light-emitting device 60 is normally bonded to the electrode 401, and the second area 401B can be understood as a preset redundant bonding position, a first sub-opening 50KA of a first opening 50K of the second planarization layer 50 can be set to correspond to the first area 401A of the six electrodes 401, and a second sub-opening 50KB of the first opening 50K can correspond to the second area 401B of the six electrodes 401 (such as Fig. 20 Alternatively, a first opening 50K of the second planarization layer 50 may be provided to correspond to the first region 401A and the second region 401B of the six electrodes 401 (as shown in FIG. Fig.21 As shown), to improve process efficiency and reduce process difficulty.

[0129] In some optional embodiments, please refer to Figure 1 and Fig. 22 , Fig. 22 yes Figure 1 Another schematic diagram of a cross-sectional structure along the AA' direction, in this embodiment, the display panel further includes a first passivation layer 80, and the first passivation layer 80 is located between the second planarization layer 50 and the first conductive layer 40;

[0130] The first passivation layer 80 includes a plurality of second openings 80K, and the orthographic projections of the second openings 80K on the substrate 10 partially overlap with the orthographic projections of the electrodes 401 on the substrate 10;

[0131] Around the second opening 80K, the first passivation layer 80 at least covers a portion of the electrode 401 in a direction Z perpendicular to the plane where the substrate 10 is located.

[0132] This embodiment explains that the film layer structure of the display panel 000 also includes a first passivation layer 80. The first passivation layer 80 is arranged on the side of the second planarization layer 50 facing the substrate 10, and the first passivation layer 80 is located between the second planarization layer 50 and the first conductive layer 40. The first passivation layer 80 can be an inorganic film layer. The first passivation layer 80 is used to protect the film layer of the display panel 000, especially to protect the first planarization layer 30 of the organic material, and to play a protective effect of isolating water and oxygen corrosion. In this embodiment, the first passivation layer 80 includes a plurality of second openings 80K, and the orthographic projection of the second openings 80K on the substrate 10 partially overlaps with the orthographic projection of the electrode 401 on the substrate 10; surrounding the second openings 80K (if the second openings 80K are square, this direction refers to surrounding the edges of the square; if the second openings 80K are circular, this direction refers to surrounding the edges of the circular), the first passivation layer 80 covers at least a portion of the electrode 401 in a direction perpendicular to the plane of the substrate 10, and the second openings 80K are used to expose at least a portion of the electrode 401, so as to facilitate the subsequent bonding of the light-emitting device 60 to the electrode 401 in the overlapping second openings 80K. The first passivation layer 80 of this embodiment is made after the first conductive layer 40 and before the second planarization layer 50. After the first conductive layer 40 is patterned, the edge of the electrode 401 and the surface of the first planarization layer 30 exposed by the electrode 401 are covered and protected by the first passivation layer 80 to improve the effect of isolating the substrate from water and oxygen erosion. Then, the second planarization layer 50 is made and a plurality of first openings 50K are formed. At this time, the orthographic projection of the first opening 50K on the substrate 10 overlaps with the orthographic projection of the electrode 401 on the substrate 10 at least partially, so that the first opening 50K can also expose part of the electrode 401. The second planarization layer 50 of this embodiment can cover the edge of the first passivation layer 80 or not. At this time, the edges of the first planarization layer 30 and the electrode 401 can be covered and protected by the first passivation layer 80, and the second planarization layer 50 only needs to play the role of the concave-convex structure of the flat substrate surface.

[0133] It can be understood that in this embodiment, other inorganic layers may be provided on the side of the second planarization layer 50 away from the substrate 10 to protect the second planarization layer 50 from water and oxygen corrosion.

[0134] In some optional embodiments, please refer to Figure 1 and Fig.23 , Fig.23 yes Figure 1 Another schematic cross-sectional structure diagram along the AA' direction, in this embodiment, the display panel 000 further includes a third conductive layer 90, and the third conductive layer 90 includes a plurality of raised portions 901;

[0135] In a direction Z perpendicular to the plane where the substrate 10 is located, the raised portion 901 is in direct contact with the electrode 401, and the orthographic projection of the raised portion 901 on the substrate 10 at least partially overlaps with the orthographic projection of the electrode 401 on the substrate 10;

[0136] The display panel 000 further includes a plurality of light emitting devices 60, and the light emitting devices 60 are electrically connected to the drive array layer 20 through the electrode 401 and the padding portion 901. Optionally, the anode pin 601 of the light emitting device 60 is electrically connected to the drain of a thin film transistor 20T of the drive array layer 20 through one electrode 401 and the padding portion 901 directly in contact with the electrode 401, and the anode signal power supply line provided by the drive array layer 20 is provided to the anode pin 601 of the light emitting device 60; the cathode pin 602 of the light emitting device 60 is electrically connected to the cathode signal power supply line of the drive array layer 20 through another electrode 401 and the padding portion 901 directly in contact with the electrode 401, and the cathode signal is provided to the cathode pin 602 of the light emitting device 60 through the cathode signal power supply line.

[0137] This embodiment explains that a second planarization layer 50 is provided on a side of the patterned first conductive layer 40 away from the substrate 10 to flatten the surface of the first conductive layer 40 away from the substrate 10, so that the surface of the patterned first conductive layer 40 can be covered by the second planarization layer 50 of organic material, and a large number of concave-convex structures presented by the patterned first conductive layer 40 can be flattened by the second planarization layer 50 to improve the flatness problem of the substrate and improve the effect of subsequent ink encapsulation. A third conductive layer 90 can also be added to the film structure of the display panel 000. The third conductive layer 90 is graphically designed to form a plurality of raised portions 901. The raised portions 901 can correspond one to one with the electrodes 401. In the direction Z perpendicular to the plane where the substrate 10 is located, the raised portions 901 are in direct contact with the electrodes 401, and the orthographic projection of the raised portions 901 on the substrate 10 at least partially overlaps with the orthographic projection of the electrodes 401 on the substrate 10. Since the first opening 50K opened in the second planarization layer 50 exposes at least part of the electrode 401 area for subsequent macro rotation and bonding of the light-emitting device 60, the second planarization layer 50 needs to have a certain thickness in order to flatly cover a large number of concave-convex structures presented by the patterned first conductive layer 40. Therefore, after the second planarization layer 50 is set, the step difference between the upper surface of the electrode 401 and the upper surface of the second planarization layer 50 increases, which may affect the macro rotation process of the light-emitting device 60. In this embodiment, the padding portion 901 is superimposed on the electrode 401. By superimposing the thickness of the padding portion 901 on the electrode 401, the problem of the step difference around the light-emitting device 60 caused by the setting of the second planarization layer 50 can be reduced, which is beneficial to the subsequent macro rotation process of the light-emitting device 60.

[0138] It can be understood that this embodiment does not limit the material for making the third conductive layer 90. The third conductive layer 90 can be the same as or different from the material of the first conductive layer 40. The material of the third conductive layer 90 can be a metal material or a transparent conductive material. This embodiment does not limit this.

[0139] Optional, such as Fig.23 As shown, along the direction Z perpendicular to the plane where the substrate 10 is located, the raised portion 901 includes a first surface 901A on the side away from the electrode 401, and the second planarization layer 50 includes a second surface 50A on the side away from the substrate 10. If the second planarization layer 50 also includes a first passivation layer 80 on the side away from the substrate 10, the second surface 50A can be understood as the surface of the first passivation layer 80 on the side away from the substrate 10. The distance D4 between the first surface 901A and the second surface 50A ranges from 0.1 to 2um, which can avoid the raised portion 901 provided with the third conductive layer 90 from having a too large thickness, which affects the thin design after the panel is packaged, and can also avoid the raised portion 901 provided with the third conductive layer 90 from having a too small thickness, which will still result in a too large step difference after being superimposed on the electrode 401, which is not conducive to the subsequent giant rotation process of the light-emitting device 60.

[0140] Optionally, in the present embodiment, the plurality of light-emitting devices 60 may include light-emitting devices of different colors. Due to different processes, the thicknesses of different light-emitting devices 60 may be different, that is, the thicknesses in the direction Z perpendicular to the plane where the substrate 10 is located are different. In order to ensure the flatness of the panel after overall packaging, the thickness of the raised portion 901 corresponding to the thicker light-emitting device 60 in the direction Z perpendicular to the plane where the substrate 10 is located can be set to be thin, and the thickness of the raised portion 901 corresponding to the thinner light-emitting device 60 is thick, thereby balancing the height difference of different light-emitting devices 60 on the substrate 10 after giant turn bonding, and finally making the distance from the surface of the thicker light-emitting device 60 away from the substrate 10 to the substrate 10 as equal as possible to the distance from the surface of the thinner light-emitting device 60 away from the substrate 10 to the substrate 10, which is beneficial to improving the flatness of the subsequent packaging of the panel and reducing the difficulty of packaging.

[0141] Optional, such as Figure 1 and Fig.23 As shown, the third conductive layer 90 is located on the side of the first passivation layer 80 away from the substrate 10; or Figure 1 and Fig.24 As shown, Fig.24 yes Figure 1 Another cross-sectional structural schematic diagram along the AA′ direction, the third conductive layer 90 is located between the first passivation layer 80 and the second planarization layer 50;

[0142] The orthographic projection of the raised portion 901 on the substrate 10 is located within the orthographic projection range of the electrode 401 on the substrate 10 .

[0143] This embodiment explains that the third conductive layer 90 used to raise the thickness of the electrode 401 to reduce the step can be set on the side of the first passivation layer 80 away from the substrate 10, that is, it can be set in the second opening 80K of the first passivation layer 80 after the first passivation layer 80 is made. Alternatively, the third conductive layer 90 used to raise the thickness of the electrode 401 to reduce the step can be set between the first passivation layer 80 and the second planarization layer 50, that is, after the second planarization layer 50 is made, a plurality of first openings 50K can be patterned to form a part of the electrode 401, and then the third conductive layer 90 is set in the first opening 50K, and a plurality of raised portions 901 are formed, and the raised portions 901 are directly in contact with the electrode 401, and then the first passivation layer 80 is set, and the first passivation layer 80 after patterning covers the second planarization layer 50 and the edge area of ​​the raised portion 90, and the first passivation layer 80 of inorganic material can form a water-oxygen isolation effect to improve the substrate reliability.

[0144] Optionally, the third conductive layer 90 may be made of a metal material, and the orthographic projection of the raised portion 901 on the substrate 10 is located within the orthographic projection range of the electrode 401 on the substrate 10, which can prevent the electrode 401 from being over-etched and affecting the conductive performance of the electrode 401. It can be understood that in this embodiment, the shapes of the raised portion 901 and the electrode 401 can be the same, such as the orthographic projection shapes on the substrate 10 can both be long strips, so that the raised portion 901 and the electrode 401 are overlapped one by one. The size relationship between the raised portion 901 and the electrode 401 can be that, in the two electrodes 401 corresponding to the electrical connection of the light-emitting device 60, along the direction from one electrode 401 to the other electrode 401, the width of the raised portion 901 can be less than or equal to the width of the electrode 401, so as to form an effect that the orthographic projection of the raised portion 901 on the substrate 10 is located within the orthographic projection range of the electrode 401 on the substrate 10.

[0145] Optional, such as Figure 1 and Fig.25 As shown, Fig.25 yes Figure 1 Another schematic cross-sectional structure diagram along the AA' direction, in which the third conductive layer 90 in this embodiment is located between the first conductive layer 40 and the second planarization layer 50;

[0146] The orthographic projection of the raised portion 901 on the substrate 10 covers the orthographic projection of the electrode 401 on the substrate 10 .

[0147] This embodiment explains that the third conductive layer 90 used to raise the thickness of the electrode 401 to reduce the step difference can be arranged between the first conductive layer 40 and the second planarization layer 50, that is, after the multiple electrodes 401 of the first conductive layer 40 are manufactured, the third conductive layer 90 can be manufactured, and then patterned to form multiple raised portions 901 directly in contact with the electrode 401, and then the second planarization layer 50 and other structures are manufactured. Optionally, the third conductive layer 90 can be made of metal material, and the orthographic projection of the raised portion 901 on the substrate 10 covers the orthographic projection of the electrode 401 on the substrate 10. Among the two electrodes 401 electrically connected to the light-emitting device 60, the width of the raised portion 901 can be greater than the width of the electrode 401 along the direction from one electrode 401 to the other electrode 401, so as to form an effect that the orthographic projection of the raised portion 901 on the substrate 10 covers the orthographic projection of the electrode 401 on the substrate 10. By directly contacting the raised portion 901 with the electrode 401 and covering the electrode 401, it can be avoided that the electrode 401 is over-etched when the first opening 50K of the second planarization layer 50 is subsequently opened, which is beneficial to ensure the conductive performance of the electrode 401.

[0148] In some optional embodiments, please refer to Fig.26 and Fig. 27 , Fig.26 is another schematic diagram of a planar structure of a display panel provided by an embodiment of the present invention, Fig. 27 yes Fig.26 A schematic diagram of a cross-sectional structure along the D-D' direction in the middle, in this embodiment, the first planarization layer 30 includes a plurality of third openings 30K, and in the direction Z perpendicular to the plane where the substrate 10 is located, the third openings 30K at least partially overlap with the first openings 50K. Optionally, the display panel 000 includes a frame area NA and a non-frame area AA, and the frame area NA is at least partially arranged around the non-frame area AA; the frame area NA can be understood as the edge area of ​​the display panel 000, and the non-frame area AA can be understood as the area at least partially surrounded by the frame area NA, and can also be understood as the light-emitting or display area of ​​the display panel 000;

[0149] Optionally, multiple first openings 50K of the second planarization layer 50 penetrate the thickness of the second planarization layer 50, and among the multiple first openings 50K, a part of the first openings 50K can be located in the border area of ​​the display panel 000. The first planarization layer 30 on the side of the first conductive layer 40 facing the substrate 10 may also include multiple third openings 30K. In the direction Z perpendicular to the plane where the substrate 10 is located, the third openings 30K penetrate the thickness of the first planarization layer 30, and the third openings 30K at least partially overlap with the first openings 50K, that is, in the border area of ​​the display panel 000, the first planarization layer 30 and the second planarization layer 50 both include openings, and the third openings 30K at least partially overlap with the first openings 50K, so that the conductive layer in the border area NA of the display panel 000 can be exposed and used as a binding pad LP and other structures for peripheral signal wiring for transmitting driving signals.

[0150] Optional, such as Fig.26 and Fig.28 As shown, Fig.28 yes Fig.26 Another schematic diagram of the cross-sectional structure along the D-D' direction, when the film layer structure of the display panel 000 also includes a third planarization layer 70 located on the side of the first planarization layer 30 close to the substrate 10, the third planarization layer 70 may also include a plurality of fourth openings 70K, in the direction Z perpendicular to the plane of the substrate 10, the fourth openings 70K penetrate the thickness of the third planarization layer 70, and the fourth openings 70K, the third openings 30K and the first openings 50K at least partially overlap.

[0151] Further optional, such as Fig.26 and Fig.28 As shown, in the border area NA, the first opening 50K exposes the third opening 30K, and the third opening 30K exposes the fourth opening 70K, that is, along the direction of the border area NA pointing to the non-border area AA, the opening width of the first opening 50K is greater than the opening width of the third opening 30K, and the opening width of the third opening 30K is greater than the opening width of the fourth opening 70K. In the border area NA, the third opening 30K of the first planarization layer 30 is retracted compared to the fourth opening 70K of the third planarization layer 70, and the first opening 50K of the second planarization layer 50 is retracted compared to the third opening 30K of the first planarization layer 30, that is, along the direction away from the substrate 10, the openings of different planarization layers in the border area NA gradually retract toward the non-border area AA, which can avoid the peeling problem of the metal conductive layer arranged at the steps of each opening in the border area NA, and can also avoid the peeling problem caused by the mutual adhesion between the planarization layers themselves.

[0152] In some optional embodiments, please refer to Fig.26 and Fig.29 , Fig.29 yes Fig.26 Another schematic diagram of the cross-sectional structure along the D-D' direction, in this embodiment, in the border area NA, the first opening 50K includes a first bevel 50K0, the third opening 30K includes a second bevel 30K0, the first bevel 50K0 and the plane where the substrate 10 is located form a first acute angle β1, the second bevel 30K0 and the plane where the substrate 10 is located form a second acute angle β2, wherein the first acute angle β1 is greater than the second acute angle β2.

[0153] This embodiment explains that the slopes of the first opening 50K of the second planarization layer 50 and the third opening 30K of the first planarization layer 30 in the border area NA may be different, and the first inclined surface 50K0 of the first opening 50K forms a first acute angle β1 with the plane where the substrate 10 is located, which is greater than the second acute angle β2 formed by the second inclined surface 30K0 of the third opening 30K with the plane where the substrate 10 is located, that is, in the border area NA, the inclined surface of the third opening 30K of the first planarization layer 30 is a gentle slope compared with the inclined surface of the first opening 50K of the second planarization layer 50, while the inclined surface of the first opening 50K is a steep slope. The first acute angle β1 formed between the first inclined surface 50K0 of the first opening 50K and the plane where the substrate 10 is located is set to be relatively large, which can improve the ink packaging fluidity at the discontinuity of the second planarization layer 50 in the frame area NA during ink packaging, and there is no other metal conductive layer on the surface of the second planarization layer 50 away from the substrate 10, so there is no need to worry about the problem of metal residual short circuit at the first inclined surface 50K0 of the first opening 50K; and the first acute angle β1 formed between the first inclined surface 50K0 of the first opening 50K and the plane where the substrate 10 is located is set to be relatively large, which can also make the overall coverage area of ​​the second planarization layer 50 in the frame area NA larger and thicker, and can effectively cover the structure of the first conductive layer 40 in the frame area NA. In this embodiment, the second acute angle β2 formed between the second inclined surface 30K0 of the third opening 30K and the plane where the substrate 10 is located is set to be relatively small, that is, the inclined surface of the third opening 30K is a gentle slope, which can reduce the probability of the metal layer (such as the first conductive layer 40) on the surface of the first planarization layer 30 remaining at the third opening 30K, which is conducive to improving the process yield and display quality.

[0154] Optional, such as Fig.29As shown, the angle of the slope of the fourth opening 70K of the third planarization layer 70 in the border area NA can be the same as the angle of the slope of the third opening 30K, that is, the slope of the fourth opening 70K in the border area NA forms an acute angle β0 with the plane where the substrate 10 is located, and the acute angle β0 can be consistent with the second acute angle β2 formed by the second slope 30K0 and the plane where the substrate 10 is located, so that the second slope 30K0 of the third opening 30K and the slope of the fourth opening 70K in the border area NA are a continuous inclined surface, which is convenient for the metal layer (such as the first conductive layer 40) on the surface of the first planarization layer 30 and the metal layer on the surface of the third planarization layer 70 to form a binding pad LP and other structures at the overlapping openings in the border area NA.

[0155] Or, in some other optional embodiments, such as Fig.29 As shown, the acute angle β0 formed by the inclined surface of the fourth opening 70K in the border area NA and the plane where the substrate 10 is located may be inconsistent with the second acute angle β2 formed by the second inclined surface 30K0 and the plane where the substrate 10 is located, and the second acute angle β2 may be slightly larger than the acute angle β0 formed by the inclined surface of the fourth opening 70K in the border area NA and the plane where the substrate 10 is located, that is, the slope of the fourth opening 70K of the third planarization layer 70 in the border area NA may be smoother, so as to further reduce the probability of the metal layer remaining at the fourth opening 70K, thereby better improving the process yield and display quality.

[0156] Optional, such as Fig.26 and Fig.29 As shown, in this embodiment, in the non-frame area AA of the display panel 000, the first opening 50K includes a third inclined surface 50K01, and the third inclined surface 50K01 forms a third acute angle β3 with the plane where the substrate 10 is located, wherein the third acute angle β3 is smaller than the first acute angle β1.

[0157] This embodiment explains that among the multiple first openings 50K opened in the second planarization layer 50 of the display panel 000, the first opening 50K in the border area NA is used to expose structures such as the binding pad LP, and the first opening 50K in the non-border area AA is used to include the electrode 401 to bond the light-emitting device 60 through the electrode 401. The slope of the first opening 50K located in the border area NA may be different from the slope of the first opening 50K in the non-border area AA. Specifically, in the non-border area AA, the first opening 50K includes a third inclined plane 50K01, and the third inclined plane 50K01 forms a third acute angle β3 with the plane where the substrate 10 is located; in the border area NA, the first opening 50K includes a first inclined plane 50K0, and the first inclined plane 50K0 forms a first acute angle β1 with the plane where the substrate 10 is located, and the third acute angle β3 is smaller than the first acute angle β1, that is, the slope of the first opening 50K in the non-border area AA is more gentle, which is beneficial to the leveling of the ink in the non-border area AA during ink packaging, thereby ensuring the packaging effect of the display panel 000 in the non-border area AA and improving the display quality and packaging reliability.

[0158] In some optional embodiments, please refer to Fig.26 and Fig.30 , Fig.30 yes Fig.26 A schematic diagram of a cross-sectional structure along the F-F' direction in the embodiment, in this embodiment, taking a light emitting device 60 electrically connected to two electrodes 401 as an example, in the two electrodes 401 electrically connected to a light emitting device 60, the direction from one electrode 401 to the other electrode 401 (such as Fig.30 In the direction G1 shown in the figure, in the non-frame area AA of the display panel 000, the first opening 50K includes a first slope 50K1 close to the edge 60L of the light-emitting device 60 and a second slope 50K2 away from the edge 60L of the light-emitting device 60; the angle formed by the first slope 50K1 and the plane where the substrate 10 is located is an acute angle A, and the angle formed by the second slope 50K2 and the plane where the substrate 10 is located is an acute angle B;

[0159] In the frame area NA of the display panel 000, the first opening 50K includes a first inclined surface 50K0, the third opening 30K includes a second inclined surface 30K0, the first inclined surface 50K0 forms a first acute angle β1 with the plane where the substrate 10 is located, the second inclined surface 30K0 forms a second acute angle β2 with the plane where the substrate 10 is located, and the inclined surface of the fourth opening 70K in the frame area NA forms an acute angle β0 with the plane where the substrate 10 is located.

[0160] Optionally, the acute angle A and the acute angle B of the non-border area AA may be equal, the first acute angle β1 of the border area NA may be greater than the second acute angle β2, and the second acute angle β2 of the border area NA may be equal to or slightly greater than the acute angle β0 (as described in the above embodiment, the effect will not be repeated here in this embodiment); for the second planarization layer 50, the acute angle A and the acute angle B of the non-border area AA, regardless of whether the angles are the same, may be smaller than the first acute angle β1 of the border area NA, so that the slope of the first opening 50K of the non-border area AA is smoother, which is beneficial to improve the leveling of the ink during packaging and ensure the packaging effect.

[0161] Optionally, the acute angle A and the acute angle B of the non-frame area AA may be unequal, and the acute angle A of the non-frame area AA is smaller than the acute angle B, that is, in a first opening 50K corresponding to the light-emitting device 60, the first slope 50K1 of the outer first opening 50K is more gentle, and the second slope 50K2 of the inner first opening 50K can be slightly steeper, thereby ensuring that the ink has better leveling in the peripheral area of ​​the light-emitting device 60 during subsequent ink packaging, thereby improving the packaging effect. The first acute angle β1 of the frame area NA may be greater than the second acute angle β2, and the second acute angle β2 of the frame area NA may be equal to or slightly greater than the acute angle β0 (as described in the above embodiment, the effect is not repeated in this embodiment). In this embodiment, for the second planarization layer 50, the acute angle A and the acute angle B of the non-frame area AA, regardless of whether the angles are the same, may be smaller than the first acute angle β1 of the frame area NA, so that the slope of the first opening 50K of the non-frame area AA is more gentle, which is conducive to improving the leveling of the ink during packaging and ensuring the packaging effect.

[0162] In some optional embodiments, please refer to Fig.31 and Fig.32 , Fig.31 is another schematic diagram of a planar structure of a display panel provided by an embodiment of the present invention, Fig.32 yes Fig.31 A schematic cross-sectional structure diagram along the E-E' direction, in this embodiment, the display panel 000 includes a frame area NA and a non-frame area AA, and the frame area NA is at least partially arranged around the non-frame area AA; the frame area NA can be understood as an edge area of ​​the display panel 000, and the non-frame area AA can be understood as an area at least partially surrounded by the frame area NA, and can also be understood as a light-emitting or display area of ​​the display panel 000;

[0163] Optionally, the plurality of first openings 50K of the second planarization layer 50 penetrate the thickness of the second planarization layer 50. Among the plurality of first openings 50K, some of the first openings 50K may be located in the frame area of ​​the display panel 000, and some of the first openings 50K may be located in the non-frame area AA. The first openings 50K located in the non-frame area AA may be used to expose the electrode 401 to bind and bond the light-emitting device 60. Other first openings 50K may also be included that directly penetrate the thickness of the second planarization layer 50, which is equivalent to hollowing out the second planarization layer 50 at the position of the first opening 50K for transparent display. For example, in the non-frame area AA of the display panel 000, the non-frame area AA includes the light-transmitting area TAA and the light-emitting area FAA (it can be understood that the embodiment of the present invention is not limited to the non-frame area AA of the display panel 000). Fig.31The arrangement of the light-transmitting area TAA and the light-emitting area FAA is only drawn for example. In specific implementation, the arrangement and number of the two include but are not limited to this. This embodiment is only an example); the display panel 000 includes a plurality of light-emitting devices 60, and the light-emitting devices 60 are located in the light-emitting area FAA. A portion of the first openings 50K of the non-border area AA can be used to expose the electrode 401 to bind and bond the light-emitting device 60, and a portion of the first openings 50K of the non-border area AA are used to hollow out to form light-transmitting area TAA to achieve transparent display.

[0164] The first planarization layer 30 of the display panel 000 on the side of the first conductive layer 40 facing the substrate 10 may also include a plurality of third openings 30K, and the orthographic projection of the third opening 30K located in the non-frame area AA on the substrate 10 is located in the light-transmitting area TAA. The orthographic projection of the third opening 30K on the substrate 10 overlaps with the orthographic projection of the first opening 50K on the substrate 10, or the first opening 50K exposes the third opening 30K, so as to hollow out the first planarization layer 30 to form a light-transmitting area TAA to achieve transparent display.

[0165] It is understandable that when the film structure of the display panel 000 includes other organic layers, the light-transmitting area TAA may be hollowed out to form an opening to ensure the transmittance of the light-transmitting area TAA, thereby achieving a transparent display effect of the display panel 000 .

[0166] It should be noted that this embodiment does not elaborate on the film layer structure of the light-transmitting area TAA of the non-border area AA. In the related art, the area where the first opening 50K is formed in the second planarization layer 50 and the third opening 30K is formed in the first planarization layer 30 of the light-transmitting area TAA of the display panel 000 can be filled with transparent insulating material to ensure the overall flatness of the panel. This embodiment is not elaborated here, and the details can be understood by referring to the film layer structure of the transparent display panel.

[0167] In some optional embodiments, please refer to Fig.26 and Fig.33 , Fig.33 yes Fig.26 Another schematic diagram of the cross-sectional structure along the D-D′ direction, in this embodiment, the second planarization layer 50 includes a first hollow portion 50L in the border area NA, and the first hollow portion 50L makes the border area NA not include the second planarization layer 50.

[0168] This embodiment explains that the second planarization layer 50 may not be provided in the frame area NA of the display panel 000, that is, the second planarization layer 50 includes a first hollow portion 50L in the frame area NA, and the structure of the first hollow portion 50L may be a structure in which the second planarization layer 50 in the frame area NA is hollowed out, and the first hollow portion 50L makes the frame area NA not include the second planarization layer 50. The display panel 000 of this embodiment may be a splicing type display panel. In order to realize the splicing of different display panels 000, and then realize the splicing display of at least two display panels 000, the frame area NA of the display panel 000 needs to be cut and edged. Since the organic film layer will affect the laser transmission of the cutting and edge grinding process, carbonization will cause surrounding pollution. In addition, the organic film layer may also cause the problem of peeling of the organic layer at the edge grinding. Therefore, in this embodiment, the second planarization layer 50 of the border area NA is hollowed out, and the first hollow portion 50L is provided so that the border area NA does not include the second planarization layer 50, thereby preventing the presence of the organic layer in the border area NA from affecting the cutting and edge grinding process of the panel, and ensuring the adhesion of the film layer of the display panel 000 in the border area NA, which is beneficial to improving the splicing effect of the display panel 000 when used for splicing display.

[0169] It can be understood that the first hollow portion 50L of the second planarization layer 50 of the present embodiment can be set at least in the border area NA on one edge of the display panel 000, or in the two border areas NA on the opposite side edges of the display panel 000, or in the four border areas NA around the display panel 000, so as to achieve that when the display panel 000 is used as a sub-board of the splicing panel, the organic film layer material is prevented from affecting the laser transmittance of the cutting and edge grinding process when the sub-board is cut and edge-grinded around, thereby ensuring the process technology.

[0170] Optional, such as Fig.26 and Fig.34 As shown, Fig.34 yes Fig.26 Another schematic diagram of the cross-sectional structure along the D-D' direction, when the display panel 000 in this embodiment includes other organic film layers such as a first planarization layer 30 and a third planarization layer 70, the first planarization layer 30 can be provided with a second hollow portion 30L in the border area NA, and the third planarization layer 70 can be provided with a third hollow portion 70L in the border area NA, and the two organic film layers can be hollowed out in the border area NA to ensure that there is no organic material in the border area NA to affect the laser cutting and edge grinding process.

[0171] In some optional embodiments, please refer to Fig.26 , Fig.35 and Fig.36 , Fig.35 yes Fig.26 Another cross-sectional structure schematic diagram along the D-D' direction, Fig.36 yes Fig.26 Schematic diagram of the local planar structure of the J3 region (it can be understood that in order to clearly illustrate the structure of the display panel, Fig.36 Transparency filling is performed), in this embodiment, the non-frame area AA includes a plurality of light-emitting devices 60, and the light-emitting devices 60 are electrically connected to the driving array layer 20 through the electrode 401;

[0172] The light emitting device 60 includes a first light emitting device 60A. No other light emitting device 60 is included between the first light emitting device 60A and the frame area NA, that is, the first light emitting device 60A is the light emitting device closest to the frame area NA among the multiple light emitting devices 60 included in the non-frame area AA.

[0173] The first opening 50K corresponding to the first light emitting device 60A is communicated with the first hollow portion 50L.

[0174] This embodiment explains that the display panel 000 can be used in a spliced ​​display panel. In order to minimize the border of the display panel at the splicing position or even to achieve a borderless display panel, it is necessary to hollow out the organic medium layer at the edge grinding corresponding to the border area NA around the display panel 000, and then make room for the edge cutting and edge grinding to meet the process requirements. At this time, when the first hollow portion 50L of the border area NA is close to the first light-emitting device 60A in the non-border area AA, if the design space is insufficient, that is, the first light-emitting device 60A is very close to the first hollow portion 50L, the first opening 50K corresponding to the first light-emitting device 60A can be connected to the first hollow portion 50L. In this way, the connection area of ​​the second planarization layer 50 between the first opening 50K and the first hollow portion 50L at the cutting and grinding position is eliminated, which is conducive to using the display panel 000 of this embodiment to achieve a borderless spliced ​​panel design.

[0175] It can be understood that Fig.36 The example in which a first opening 50K in the non-border area AA corresponds to three adjacent light-emitting devices 60 of different colors is used for illustration. The first opening 50K in the non-border area AA may also be arranged in other ways. For details, please refer to the above embodiment, which will not be described in detail in this embodiment.

[0176] Optional, such as Fig.35 As shown, in this embodiment, the binding pad LP of the frame area NA can be formed by a conductive structure provided by multiple metal conductive layers through multiple vias, so as to transmit the driving signal provided by the binding pad LP to the non-frame area AA of the display panel 000 through multiple metal layers at different positions, so as to transmit the driving signal and realize the effect of panel driving display. Fig.35This is only an example to illustrate a setting structure of the binding pad LP. In specific implementation, the setting method of the binding pad LP of the border area NA includes but is not limited to this, and may also include other setting methods, which are not limited in this embodiment.

[0177] Optional, such as Fig.26 and Fig.37 As shown, Fig.37 yes Fig.26 Another partial planar structure schematic diagram of the J3 region (it can be understood that in order to clearly illustrate the structure of the display panel, Fig.37 Transparency filling is performed), in this embodiment, the second planarization layer 50 includes a hollow transition portion 50LK, and the first opening 50K corresponding to the first light-emitting device 60A is connected to the first hollow portion 50L through the hollow transition portion 50LK, and the edge of the positive projection of the hollow transition portion 50L on the substrate 10 is arc-shaped.

[0178] This embodiment explains that the first hollow portion 50L of the frame area NA is located close to the first light-emitting device 60A in the non-frame area AA, and the first opening 50K corresponding to the first light-emitting device 60A is connected to the first hollow portion 50L. In this way, the connection area of ​​the second planarization layer 50 between the first opening 50K and the first hollow portion 50L at the cutting and grinding position is eliminated, which is conducive to realizing a frameless splicing panel design. This embodiment further arranges that the first opening 50K corresponding to the first light-emitting device 60A is connected to the first hollow portion 50L through a hollow transition portion 50LK, and the edge of the positive projection of the hollow transition portion 50L on the substrate 10 is an arc shape or other smooth shape for transition, which is conducive to improving the implementation effect of the subsequent packaging process.

[0179] Optional, such as Fig.26 and Fig.38 As shown, Fig.38 yes Fig.26 Another cross-sectional structural schematic diagram along the D-D' direction, in this embodiment, the display panel 000 also includes an ink encapsulation layer 100, which is located on the side of the first passivation layer 80 away from the substrate 10. The ink encapsulation layer 100 is filled between adjacent light-emitting devices 60, and the light-emitting surface of the light-emitting device 60 needs to be exposed. The ink encapsulation layer 100 can reduce the reflection of the display panel to the ambient light, and play a role in reducing reflection while avoiding color crosstalk between adjacent light-emitting devices 60. The edges of the first hollow portion 50L and the hollow transition portion 50L of the second planarization layer 50 in the frame area NA are set to be smooth at the positive projection of the substrate 10, which can ensure the implementation effect of the subsequent ink encapsulation process technology, and can also ensure that the organic film layer in the frame area NA is hollowed out, so as to be suitable for splicing panels while ensuring the process yield.

[0180] Optional, such as Fig.26 and Fig.39 As shown, Fig.39 yes Fig.26 Another cross-sectional structural diagram along the D-D' direction in the middle, the display panel 000 of this embodiment can be applied to a borderless splicing display device, that is, the border area NA of the display panel 000 can be reduced as much as possible, or even borderless. For example, a wire can be drawn through the side wiring of the border area NA to the backlight side of the display panel 000 (the side of the substrate 10 away from the drive array layer 20), and the binding pad LP on the light-emitting side of the display panel 000 can be drawn through the side wiring to the pad on the backlight side of the display panel 000 ( Fig.39 (not shown in the figure), the driving chip or the flexible circuit board is bound on the backlight side of the display panel 000.

[0181] Specifically, Fig.39 As shown, the binding pad LP can be pulled to the side of the substrate 10 away from the driving array layer 20 through the side routing CL, which is equivalent to setting the binding area of ​​the display panel on the backlight surface of the display panel. In this way, the binding area does not need to occupy the space on the front side of the display panel 000, which is conducive to realizing an extremely narrow frame or a frameless design of the display panel and meeting the splicing requirements of large-size display products.

[0182] Further optionally, the side trace CL of this embodiment is covered with a side trace encapsulation layer CZ, which can be a high-resistance ink, used to protect the side trace CL, prevent the side trace CL from being affected by external moisture, oxygen, etc., and corrosion and other problems, affecting the reliability of signal transmission on the side trace CL. The side trace encapsulation layer CZ can be a black or gray light-shielding material, which can avoid or reduce the problem of light leakage on the side of the display panel 000.

[0183] Optionally, the side wiring encapsulation layer CZ may be filled with a filling encapsulation part TF with high buffering performance, and the filling encapsulation part TF may at least partially cover the side wiring encapsulation layer CZ, which can be understood as further encapsulating the side wiring encapsulation layer CZ with the filling encapsulation part TF, and the double encapsulation of the filling encapsulation part TF and the side wiring encapsulation layer CZ is more conducive to improving the encapsulation reliability of the side edge of the display panel 000. Optionally, the filling encapsulation part TF may also be a material with light absorption effect such as black or gray.

[0184] Optionally, the ink encapsulation layer 100 of the display panel 000 of this embodiment, which is away from the substrate 10, may include a transparent encapsulation layer 1001 and a composite film material 1003 bonded by a glue layer 1002 in sequence. The transparent encapsulation layer 1001 and the glue layer 1002 may also be replaced by a transparent glue layer, which can encapsulate the front side of the light-emitting device 60 to prevent the external moisture and oxygen from affecting the light-emitting device 60. At the same time, the surface of the transparent encapsulation layer 1001 away from the substrate 10 is a flat surface, and the composite film material 1003 can be adhered to the glue layer 1002 as a protective layer. For example, the composite film material 1003 may be a transparent cover plate.

[0185] Optionally, a side black layer CH may be disposed at the outermost portion of the frame area NA of the display panel 000 of this embodiment. The side black layer CH may be made of black material or a material with high light absorption or high grayscale. In this way, the side black layer CH can prevent light from leaking sideways from the display panel. The side black layer CH may also be used as an encapsulation layer to improve the encapsulation reliability of the display panel, and as the first line of defense to prevent moisture and oxygen from entering the side of the display panel. Fig.39 As shown, the side blackening layer CH extends from the side to the frame areas of the front, side and back of the display panel, so as to realize the lateral encapsulation of the display panel and block the lateral light leakage.

[0186] In some alternative embodiments, please refer to Fig.40 , Fig.40 1 is a schematic diagram of the planar structure of a display device provided in an embodiment of the present invention. The display device 111 provided in this embodiment includes the display panel 000 provided in the above embodiment of the present invention. The display device 000 of this embodiment may be a transparent display device, or may be a spliced ​​display device including multiple display panels 000 in the above embodiment, which is not limited in this embodiment. The display device 000 of this embodiment may be a large-sized spliced ​​display device, such as a large-screen display device for public display; or optionally, the spliced ​​display device of this embodiment may be composed of Fig.39 The display device 111 provided by the embodiment of the present invention has the beneficial effects of the display panel 000 provided by the embodiment of the present invention. For details, please refer to the specific description of the display panel 000 in the above embodiments, which will not be repeated in this embodiment.

[0187] It should be noted that, in this article, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0188] The above description is only a specific embodiment of the present disclosure, so that those skilled in the art can understand or implement the present disclosure. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present disclosure. Therefore, the present disclosure will not be limited to the embodiments described herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A display panel, characterized in that: include: substrate; A driving array layer, located on one side of the substrate; A first planarization layer, located on a side of the driving array layer away from the substrate; A first conductive layer, located on a side of the first planarization layer away from the substrate, the first conductive layer comprising a plurality of electrodes; A second planarization layer is located on a side of the first conductive layer away from the substrate, the second planarization layer comprises a plurality of first openings, and the first openings penetrate the second planarization layer; Along a direction perpendicular to a plane where the substrate is located, the first opening exposes at least a portion of the electrode.

2. The display panel according to claim 1, characterized in that: Along a direction perpendicular to the plane where the display panel is located, the thickness of the second planarization layer is less than the thickness of the first planarization layer, and the thickness of the second planarization layer is greater than the thickness of the first conductive layer.

3. The display panel according to claim 2, characterized in that: The thickness of the first planarization layer is D1, the thickness of the second planarization layer is D2, and 1 / 2D1<D2<4 / 5D1.

4. The display panel according to claim 2, characterized in that: include: a second conductive layer, the second conductive layer is located on a side of the first planarization layer close to the substrate; wherein, Along a direction perpendicular to a plane where the display panel is located, a thickness of the second conductive layer is smaller than a thickness of the first conductive layer.

5. The display panel according to claim 1, characterized in that: The display panel further includes a first passivation layer, wherein the first passivation layer is located on a side of the second planarization layer away from the substrate; The first passivation layer comprises a plurality of second openings, wherein the orthographic projections of the second openings on the substrate are located within the orthographic projection range of the first openings on the substrate; The second planarization layer surrounds the first opening and covers at least a portion of the electrode in a direction perpendicular to the plane where the substrate is located; Surrounding the second opening, the first passivation layer covers the second planarization layer in a direction perpendicular to a plane where the substrate is located.

6. The display panel according to claim 5, characterized in that: Outside the electrode range, the second planarization layer is in direct contact with the first planarization layer.

7. The display panel according to claim 5, characterized in that: In a direction perpendicular to the plane where the substrate is located, one first opening corresponds to one electrode, and one second opening corresponds to one electrode.

8. The display panel according to claim 7, characterized in that: The display panel further comprises a plurality of light emitting devices, wherein the light emitting devices are electrically connected to at least two of the electrodes, and the light emitting devices are electrically connected to the driving array layer through the electrodes; Among the two electrodes of one of the light-emitting devices, along the direction from one electrode to the other electrode, the first opening comprises a first slope close to the edge of the light-emitting device and a second slope away from the edge of the light-emitting device; The angle formed by the first slope and the plane where the substrate is located is an acute angle A, and the angle formed by the second slope and the plane where the substrate is located is an acute angle B. The acute angle A is smaller than the acute angle B.

9. The display panel according to claim 5, characterized in that: The display panel further comprises a plurality of light emitting devices, wherein the light emitting devices are electrically connected to at least two of the electrodes, and the light emitting devices are electrically connected to the driving array layer through the electrodes; In a direction perpendicular to the plane where the substrate is located, one of the first openings corresponds to two of the electrodes electrically connected to one of the light-emitting devices.

10. The display panel according to claim 9, characterized in that: In a direction perpendicular to the plane where the substrate is located, one of the second openings corresponds to one of the electrodes; Between two electrodes electrically connected to one of the light emitting devices, the first passivation layer covers the first planarization layer and a portion of the electrode.

11. The display panel according to claim 9, characterized in that: The electrode comprises a first region and a second region; The two electrodes electrically connected to one of the light-emitting devices are a first electrode and a second electrode; One of the first openings includes a first sub-opening and a second sub-opening. In a direction perpendicular to the plane where the substrate is located, the first sub-opening exposes a first region of the first electrode and a first region of the second electrode, and the second sub-opening exposes a second region of the first electrode and a second region of the second electrode.

12. The display panel according to claim 11, characterized in that: The first conductive layer includes a plurality of through holes, and the orthographic projections of the through holes on the substrate do not overlap with the orthographic projections of the first region of the electrode and the second region of the electrode on the substrate.

13. The display panel according to claim 5, characterized in that: The display panel further comprises a plurality of light emitting devices, and the light emitting devices are electrically connected to the driving array layer through the electrodes; In a direction perpendicular to the plane where the substrate is located, one first opening corresponds to three adjacent light-emitting devices of different colors.

14. The display panel according to claim 13, characterized in that: In a direction perpendicular to the plane where the substrate is located, one of the second openings corresponds to one of the electrodes; Between two electrodes electrically connected to one light emitting device and between two adjacent light emitting devices, the first passivation layer covers the first planarization layer and a portion of the electrodes.

15. The display panel according to claim 1, characterized in that: The display panel further includes a first passivation layer, wherein the first passivation layer is located between the second planarization layer and the first conductive layer; The first passivation layer comprises a plurality of second openings, wherein the orthographic projection of the second opening on the substrate partially overlaps with the orthographic projection of the electrode on the substrate; Surrounding the second opening, the first passivation layer at least covers a portion of the electrode in a direction perpendicular to a plane where the substrate is located.

16. The display panel according to claim 5, characterized in that: The display panel further includes a third conductive layer, wherein the third conductive layer includes a plurality of raised portions; In a direction perpendicular to the plane where the substrate is located, the raised portion is in direct contact with the electrode, and an orthographic projection of the raised portion on the substrate at least partially overlaps with an orthographic projection of the electrode on the substrate; The display panel further includes a plurality of light emitting devices, and the light emitting devices are electrically connected to the driving array layer through the electrodes and the raised portions.

17. The display panel according to claim 16, characterized in that: Along a direction perpendicular to the plane where the substrate is located, the raised portion includes a first surface away from the electrode side, the second planarization layer includes a second surface away from the substrate side, and the distance between the first surface and the second surface ranges from 0.1-2um.

18. The display panel according to claim 16, characterized in that: The third conductive layer is located on a side of the first passivation layer away from the substrate; or, the third conductive layer is located between the first passivation layer and the second planarization layer; The orthographic projection of the raised portion on the substrate is located within the orthographic projection range of the electrode on the substrate.

19. The display panel according to claim 16, characterized in that: The third conductive layer is located between the first conductive layer and the second planarization layer; The orthographic projection of the raised portion on the substrate covers the orthographic projection of the electrode on the substrate.

20. The display panel according to claim 1, characterized in that: The first planarization layer includes a plurality of third openings, and in a direction perpendicular to the plane where the substrate is located, the third openings at least partially overlap with the first openings.

21. The display panel according to claim 20, characterized in that: The display panel comprises a frame area and a non-frame area, wherein the frame area is at least partially arranged around the non-frame area; In the border area, the first opening exposes the third opening.

22. The display panel according to claim 21, characterized in that: In the border area, the first opening includes a first inclined surface, and the third opening includes a second inclined surface. The first inclined surface forms a first acute angle with the plane where the substrate is located, and the second inclined surface forms a second acute angle with the plane where the substrate is located, wherein the first acute angle is greater than the second acute angle.

23. The display panel according to claim 22, characterized in that: In the non-frame area, the first opening includes a third inclined surface, and the third inclined surface forms a third acute angle with the plane where the substrate is located, wherein the third acute angle is smaller than the first acute angle.

24. The display panel according to claim 21, characterized in that: In the non-frame area, the display panel includes a plurality of light-emitting devices, and the non-frame area includes a light-transmitting area and a light-emitting area; The light emitting device is located in the light emitting area, and the orthographic projection of the third opening on the substrate is located in the light transmitting area.

25. The display panel according to claim 21, characterized in that: The second planarization layer includes a first hollow portion in the frame area, and the first hollow portion prevents the frame area from including the second planarization layer.

26. The display panel according to claim 25, characterized in that: The non-frame area includes a plurality of light-emitting devices, and the light-emitting devices are electrically connected to the driving array layer through the electrodes; The light emitting device includes a first light emitting device, and no other light emitting device is included between the first light emitting device and the border area; The first opening corresponding to the first light emitting device is communicated with the first hollow portion.

27. The display panel according to claim 26, characterized in that: The second planarization layer includes a hollow transition portion, and the first opening corresponding to the first light-emitting device is connected to the first hollow portion through the hollow transition portion, and the edge of the orthographic projection of the substrate of the hollow transition portion is arc-shaped.

28. A display device, characterized in that: A display panel comprising any one of claims 1-27.

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