Display substrate and display device

Abstract

The embodiment provides a display substrate, which is beneficial to narrow the frame. The display substrate comprises a substrate, a circuit structure layer and a light-emitting structure layer arranged on the substrate in sequence. The display area comprises a first display area and a second display area arranged along a first direction, and the second display area is located between the first display area and a first frame area along the first direction. The circuit structure layer comprises a plurality of pixel circuits located in the first display area, a plurality of multiplexing circuits located in the second display area and a plurality of data lines located in the display area; the plurality of data lines are connected with the plurality of pixel circuits and the plurality of multiplexing circuits. The light-emitting structure layer comprises a plurality of light-emitting elements located in the display area. At least one pixel circuit is connected with at least one light-emitting element, and the orthographic projection of the at least one light-emitting element and the connected pixel circuit on the substrate is arranged in a staggered manner along the first direction; the orthographic projection of the plurality of multiplexing circuits on the substrate at least partially overlaps with the orthographic projection of the plurality of light-emitting elements on the substrate.

Description

Technical Field

[0001] This article relates to, but is not limited to, the field of display technology, and in particular to a display substrate and a display device. Background Technology

[0002] Organic light-emitting diodes (OLEDs) and quantum dot light-emitting diodes (QLEDs) are active light-emitting display devices with advantages such as self-illumination, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, flexibility, and low cost. Summary of the Invention

[0003] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0004] This embodiment provides a display substrate and a display device.

[0005] On one hand, this embodiment provides a display substrate, including: a substrate, a circuit structure layer and a light-emitting structure layer sequentially disposed on the substrate. The substrate includes a display area and a first border area located on at least one side of the display area. The display area includes: a first display area and a second display area disposed along a first direction, the second display area being located between the first display area and the first border area along the first direction. The circuit structure layer includes: a plurality of pixel circuits located in the first display area, a plurality of multiplexed circuits located in the second display area, and a plurality of data lines located in the display area; the plurality of data lines are connected to the plurality of pixel circuits and the plurality of multiplexed circuits. The light-emitting structure layer includes: a plurality of light-emitting elements located in the display area; at least one pixel circuit among the plurality of pixel circuits is connected to at least one light-emitting element among the plurality of light-emitting elements, the at least one light-emitting element and the connected pixel circuit are offset along the first direction in their orthogonal projections on the substrate; the orthogonal projections of the plurality of multiplexed circuits on the substrate at least partially overlap with the orthogonal projections of the plurality of light-emitting elements located in the second display area on the substrate.

[0006] In some exemplary embodiments, at least one of the plurality of light-emitting elements has its orthographic projection on the substrate located on the side of the orthographic projection of the connected pixel circuit on the substrate closer to the first border region.

[0007] In some exemplary embodiments, the light-emitting area of ​​at least one of the plurality of light-emitting elements does not overlap with the orthographic projection of the connected pixel circuit on the substrate.

[0008] In some exemplary embodiments, the plurality of light-emitting elements includes: a plurality of light-emitting element groups arranged in an array along a first direction and a second direction, the second direction intersecting the first direction; at least one of the plurality of light-emitting element groups includes: a first light-emitting element emitting a first color light, a second light-emitting element emitting a second color light, and a third light-emitting element emitting a third color light. Within a single light-emitting element group, the first light-emitting element and the second light-emitting element are aligned along the first direction and located on the same side of the third light-emitting element along the second direction.

[0009] In some exemplary embodiments, the at least one light-emitting element includes: a first electrode, a light-emitting functional layer, and a second electrode arranged sequentially along a direction away from the substrate; the first electrode is connected to a corresponding pixel circuit through a first adapter electrode; the first adapter electrode and the plurality of data lines are in the same layer structure, and the first adapter electrode extends along the first direction.

[0010] In some exemplary embodiments, the circuit structure layer further includes: a plurality of first power lines located in the display area; the plurality of first power lines extend along the first direction and are arranged along the second direction, the second direction intersecting the first direction; the plurality of first power lines are connected to the plurality of pixel circuits, and the plurality of first power lines and the plurality of data lines are in the same layer structure.

[0011] In some exemplary embodiments, the circuit structure layer further includes: a first bezel power line located in the second display area, the first bezel power line being located along the first direction on the side of the plurality of multiplexed circuits close to the plurality of pixel circuits; the first bezel power line extending along the second direction and connected to the plurality of first power lines.

[0012] In some exemplary embodiments, the first frame power line is located on the side of the plurality of first power lines closer to the substrate.

[0013] In some exemplary embodiments, the circuit structure layer further includes: a plurality of first pads located in the second display area, wherein the first pads and the first power line are integrally formed. The at least one light-emitting element includes: a first electrode, a light-emitting functional layer, and a second electrode sequentially disposed along a direction away from the substrate; the orthographic projection of the first electrode of the at least one light-emitting element on the substrate at least partially overlaps with the orthographic projection of the first pad on the substrate.

[0014] In some exemplary embodiments, the at least one light-emitting element includes: a first electrode, a light-emitting functional layer, and a second electrode sequentially disposed along a direction away from the substrate. In the second display area, the first electrode of the at least one light-emitting element overlaps with the orthographic projections of the two first power lines on the substrate, and the orthographic projection of the edge of the first electrode extending along the first direction on the substrate at least partially overlaps with the orthographic projections of the two first power lines on the substrate.

[0015] In some exemplary embodiments, the first border area includes: a first sub-border area extending along a second direction, and a first corner area and a second corner area located at both ends of the first sub-border area along the second direction; the second direction intersects the first direction. The second display area includes: a sub-display area extending along the second direction, and a first corner display area and a second corner display area located on both sides of the sub-display area along the second direction; the first corner display area is connected to the first corner area and the first display area, and the second corner display area is connected to the second corner area and the first display area.

[0016] In some exemplary embodiments, the circuit structure layer further includes: a plurality of first signal lines connected to the plurality of pixel circuits and extending along the second direction, and a plurality of connecting lines connected to the plurality of first signal lines, wherein the orthographic projection of the plurality of multiplexed circuits located in the first corner display area and the second corner display area on the substrate overlaps with the orthographic projection of at least one of the plurality of connecting lines on the substrate.

[0017] In some exemplary embodiments, the circuit structure layer further includes: multiple multiplexed data lines. At least one of the multiple multiplexing circuits includes: nine multiplexing control transistors, the gates of the nine multiplexing control transistors being connected to nine different multiplexing control lines, the first terminals of the nine multiplexing control transistors being connected to the same multiplexed data line, and the second terminals of the nine multiplexing control transistors being connected to different data lines; in the sub-display area, the nine multiplexing control transistors of the at least one multiplexing circuit are arranged sequentially along the second direction.

[0018] In some exemplary embodiments, at least one pixel circuit in the plurality of pixel circuits includes: a driving transistor, a compensation transistor, and a data writing transistor. The gate of the driving transistor is connected to the second terminal of the compensation transistor, the first terminal of the driving transistor is connected to the second terminal of the data writing transistor, and the second terminal of the driving transistor is connected to the first terminal of the compensation transistor. The first terminal of the data writing transistor is connected to a data line, the gate of the data writing transistor is connected to a first scan line, and the gate of the compensation transistor is connected to a second scan line. The transistor type of the compensation transistor is different from the transistor types of the driving transistor and the data writing transistor.

[0019] In some exemplary embodiments, the at least one pixel circuit further includes: a first reset transistor, a second reset transistor, and a third reset transistor. The gate of the first reset transistor is connected to a first reset control line, the first electrode of the first reset transistor is connected to a first initial signal line, and the second electrode of the first reset transistor is connected to the second electrode of the driving transistor. The gate of the second reset transistor is connected to a second reset control line, the first electrode of the second reset transistor is connected to a second initial signal line, and the second electrode of the second reset transistor is connected to a first electrode of the light-emitting element. The gate of the third reset transistor is connected to the second reset control line, the first electrode of the third reset transistor is connected to a third initial signal line, and the second electrode of the third reset transistor is connected to the first electrode of the driving transistor. The first reset control line and the second reset control line are in the same layer, while the first initial signal line, the second initial signal line, and the third initial signal line are located in different conductive layers.

[0020] In some exemplary embodiments, the at least one pixel circuit further includes: a first light-emitting control transistor and a second light-emitting control transistor; the gate of the first light-emitting control transistor and the gate of the second light-emitting control transistor are both connected to a light-emitting control line, the first electrode of the first light-emitting control transistor is connected to a first power supply line, the second electrode of the first light-emitting control transistor is connected to the first electrode of the driving transistor, the first electrode of the second light-emitting control transistor is connected to the second electrode of the driving transistor, and the second electrode of the second light-emitting control transistor is connected to the first electrode of the light-emitting element.

[0021] On the other hand, this embodiment provides a display device including the display substrate as described above.

[0022] Other features and advantages of this application will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the application. Other advantages of this application can be realized and obtained by means of the embodiments described in the description and the accompanying drawings. Attached Figure Description

[0023] The accompanying drawings are used to provide an understanding of the technical solutions of this application and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of this application and do not constitute a limitation on the technical solutions of this application.

[0024] Figure 1 This is a schematic diagram of a display substrate according to at least one embodiment of the present disclosure;

[0025] Figure 2 This is an equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0026] Figure 3 for Figure 2 The provided timing diagram for the pixel circuit;

[0027] Figure 4 An equivalent circuit diagram of a multiplexing circuit according to at least one embodiment of this disclosure;

[0028] Figure 5 for Figure 1 A magnified view of a portion of the central region S1;

[0029] Figure 6 for Figure 1 A magnified view of a portion of the central region S2;

[0030] Figure 7 for Figure 1 A magnified view of a portion of the central region S3;

[0031] Figure 8A for Figure 5 A schematic diagram of the first semiconductor layer in the process;

[0032] Figure 8B for Figure 6 A schematic diagram of the first semiconductor layer in the process;

[0033] Figure 8C for Figure 7 A schematic diagram of the first semiconductor layer in the process;

[0034] Figure 9A for Figure 5 A schematic diagram of the display substrate after the first conductive layer has been formed;

[0035] Figure 9B for Figure 9A A schematic diagram of the first conductive layer in the middle;

[0036] Figure 9C for Figure 6 A schematic diagram of the display substrate after the first conductive layer has been formed;

[0037] Figure 9D for Figure 7 A schematic diagram of the display substrate after the first conductive layer has been formed;

[0038] Figure 10A for Figure 5 A schematic diagram of the display substrate after the second conductive layer has been formed;

[0039] Figure 10B for Figure 10A A schematic diagram of the second conductive layer in the middle;

[0040] Figure 10C for Figure 6 A schematic diagram of the display substrate after the second conductive layer has been formed;

[0041] Figure 10D for Figure 7 A schematic diagram of the display substrate after the second conductive layer has been formed;

[0042] Figure 11A for Figure 5 A schematic diagram of a display substrate in which a second semiconductor layer is formed;

[0043] Figure 11B for Figure 6 A schematic diagram of a display substrate after the second semiconductor layer has been formed;

[0044] Figure 12A for Figure 5 A schematic diagram of the display substrate after the third conductive layer has been formed;

[0045] Figure 12B for Figure 6 A schematic diagram of the display substrate after the third conductive layer has been formed;

[0046] Figure 13A for Figure 5 A schematic diagram of the display substrate after the fifth insulating layer has been formed;

[0047] Figure 13B for Figure 6 A schematic diagram of the display substrate after the fifth insulating layer has been formed;

[0048] Figure 13C for Figure 7 A schematic diagram of the display substrate after the fifth insulating layer has been formed;

[0049] Figure 14A for Figure 5 A schematic diagram of the display substrate after the fourth conductive layer has been formed;

[0050] Figure 14B for Figure 14A A schematic diagram of the fourth conductive layer in the diagram;

[0051] Figure 14C for Figure 6 A schematic diagram of the display substrate after the fourth conductive layer has been formed;

[0052] Figure 14D for Figure 14C A schematic diagram of the fourth conductive layer in the diagram;

[0053] Figure 14E for Figure 7 A schematic diagram of the display substrate after the fourth conductive layer has been formed;

[0054] Figure 15A for Figure 5 A schematic diagram of the display substrate after the formation of the sixth insulating layer;

[0055] Figure 15B for Figure 6 A schematic diagram of the display substrate after the formation of the sixth insulating layer;

[0056] Figure 16A for Figure 5 A schematic diagram of the display substrate after the fifth conductive layer has been formed;

[0057] Figure 16B for Figure 16A A schematic diagram of the fifth conductive layer in the diagram;

[0058] Figure 16C for Figure 6 A schematic diagram of the display substrate after the fifth conductive layer has been formed;

[0059] Figure 16D for Figure 16C A schematic diagram of the fifth conductive layer in the diagram;

[0060] Figure 16E for Figure 7 A schematic diagram of the display substrate after the fifth conductive layer has been formed;

[0061] Figure 17 for Figure 5 A schematic diagram of the display substrate after the seventh insulating layer has been formed;

[0062] Figure 18A for Figure 5 A schematic diagram of the display substrate after the anode layer has been formed;

[0063] Figure 18B for Figure 18A A schematic diagram of the anode layer and the fifth conductive layer in the diagram;

[0064] Figure 18C for Figure 7 A schematic diagram of the display substrate after the anode layer has been formed;

[0065] Figure 19 This is a schematic diagram of a display device according to at least one embodiment of the present disclosure. Detailed Implementation

[0066] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. The implementation can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be transformed into other forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the content described in the following embodiments. Unless otherwise specified, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other.

[0067] In the accompanying drawings, the size of one or more constituent elements, the thickness of layers, or areas are sometimes exaggerated for clarity. Therefore, this disclosure is not necessarily limited to these dimensions, and the shape and size of one or more parts in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate ideal examples, and this disclosure is not limited to the shapes or values ​​shown in the drawings.

[0068] The ordinal numbers such as "first," "second," and "third" used in this specification are used to avoid confusion among the constituent elements, not to limit the quantity. The term "multiple" in this disclosure refers to two or more quantities.

[0069] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the orientation of the constituent elements being described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0070] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or joint; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the meaning of these terms in this disclosure as appropriate. "Joining" can include "electrical connection," which can include situations where constituent elements are connected together by a component having some electrical function. There are no particular limitations on "components having some electrical function," as long as they enable the transmission of electrical signals between the connected constituent elements. Examples of "components having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other multifunctional components.

[0071] In this specification, a transistor is a device that includes at least three terminals: a gate (gate electrode), a drain, and a source. A transistor has a channel region between its drain (drain electrode terminal, drain region, or drain electrode) and its source (source electrode terminal, source region, or source electrode), and current can flow through the drain, the channel region, and the source. In this specification, the channel region refers to the region through which current primarily flows.

[0072] In this specification, the first terminal can be the drain and the second terminal can be the source, or vice versa. Additionally, the gate can also be called the control terminal. In cases where transistors with opposite polarities are used or where the current direction changes during circuit operation, the functions of the "source" and "drain" are sometimes interchanged. Therefore, in this specification, the "source" and "drain" can be interchanged.

[0073] In this specification, "parallel" refers to the state where the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore also includes the state where the angle is greater than or equal to -5° and less than 5°. Similarly, "perpendicular" refers to the state where the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore also includes the state where the angle is greater than or equal to 85° and less than 95°.

[0074] In this specification, circles, ellipses, triangles, rectangles, trapezoids, pentagons, or hexagons are not strictly defined. They can be approximate circles, ellipses, triangles, rectangles, trapezoids, pentagons, or hexagons. Small deformations due to tolerances are possible, such as chamfers, curved edges, and other variations.

[0075] In this specification, "about" and "approximately" mean without strictly defined limits, allowing for errors in the process and measurement. In this disclosure, "same" can include values ​​differing by no more than 10%.

[0076] In this specification, "A extends along direction B" means that A may include a main part and a secondary part connected to the main part. The main part is a line, line segment, or strip-shaped solid. The main part extends along direction B, and the length of the main part extending along direction B is greater than the length of the secondary part extending along other directions. In this specification, "A extends along direction B" refers to "the main part of A extends along direction B".

[0077] The phrase "A and B are of the same layer" in this specification means that A and B are formed simultaneously through the same drafting process. "Same layer" does not always mean that the layer thickness or layer height is the same in the cross-sectional view. "The orthographic projection of A includes the orthographic projection of B" means that the orthographic projection of B falls within the orthographic projection area of ​​A, or the orthographic projection of A covers the orthographic projection of B.

[0078] To better meet people's needs for multiple functions and a better screen experience (such as displays with ultra-high screen-to-body ratios), narrow bezel displays have gradually become the mainstream form of display devices. However, multiplexing circuits are usually located in the bottom bezel area, which increases the size of the bottom bezel and is not conducive to narrow bezel design.

[0079] This embodiment provides a display substrate, including: a substrate, a circuit structure layer and a light-emitting structure layer sequentially disposed on the substrate. The substrate includes a display area and a first border area located on at least one side of the display area. The display area includes: a first display area and a second display area disposed along a first direction, with the second display area located between the first display area and the first border area along the first direction. The circuit structure layer includes: a plurality of pixel circuits located in the first display area, a plurality of multiplexed circuits located in the second display area, and a plurality of data lines located in the display area; the plurality of data lines are connected to the plurality of pixel circuits and the plurality of multiplexed circuits. The light-emitting structure layer includes: a plurality of light-emitting elements located in the display area; at least one pixel circuit among the plurality of pixel circuits is connected to at least one light-emitting element among the plurality of light-emitting elements, and the at least one light-emitting element and the connected pixel circuit are offset along the first direction in their orthogonal projections onto the substrate; the orthogonal projections of the plurality of multiplexed circuits onto the substrate at least partially overlap with the orthogonal projections of the plurality of light-emitting elements located in the second display area onto the substrate.

[0080] The display substrate provided in this embodiment, by staggering the pixel circuit and the light-emitting element along the first direction, allows the multiplexing circuit to be placed below some of the light-emitting elements, thereby reducing the space occupied by the multiplexing circuit in the bezel area and facilitating the narrow bezel design.

[0081] In some exemplary embodiments, the orthographic projection of at least one of the plurality of light-emitting elements onto the substrate may be located on the side of the orthographic projection of the connected pixel circuit onto the substrate closer to the first border region. In some examples, the orthographic projection of the light-emitting area of ​​at least one of the plurality of light-emitting elements onto the substrate may not overlap with the orthographic projection of the connected pixel circuit onto the substrate. In this example, the light-emitting area of ​​the light-emitting element may refer to the overlapping area of ​​the anode of the light-emitting element and the light-emitting functional layer and cathode exposed by the pixel opening of the pixel definition layer. By adjusting the relative position of the light-emitting element and the pixel circuit, this example allows the multiplexing circuit to be positioned below the light-emitting element, thereby facilitating a narrow bezel design.

[0082] In some exemplary embodiments, the first border area may include: a first sub-border area extending along a second direction, and a first corner area and a second corner area located at both ends of the first sub-border area along the second direction; the second direction intersects the first direction. The second display area may include: a sub-display area extending along the second direction, and a first corner display area and a second corner display area located on both sides of the sub-display area along the second direction; the first corner display area is connected to the first corner area and the first display area, and the second corner display area is connected to the second corner area and the first display area.

[0083] In some exemplary embodiments, the circuit structure layer may further include: a plurality of first signal lines connected to a plurality of pixel circuits and extending along a second direction, and a plurality of connecting lines connected to the plurality of first signal lines. The orthographic projection of the plurality of multiplexed circuits located in the first corner display area and the second corner display area onto the substrate overlaps with the orthographic projection of at least one of the plurality of connecting lines onto the substrate. In some examples, the plurality of first signal lines may include a plurality of gate lines (e.g., including a first scan line, a second scan line, an emission control line, a first reset control line, and a second reset control line), a plurality of initial signal lines (e.g., including a first initial signal line, a second initial signal line, and a third initial signal line), and a trace transmitting a first voltage signal along the second direction; the plurality of connecting lines may include: a plurality of first connecting lines connected to the plurality of gate lines, a plurality of second connecting lines connected to the plurality of initial signal lines, and a plurality of third connecting lines connected to the plurality of traces transmitting the first voltage signal along the second direction. This example demonstrates how setting up a multiplexed circuit in the first and second corner display areas and placing one or more connecting lines on the side away from the substrate can help ensure the anode flatness of the light-emitting element.

[0084] The following examples illustrate the solution of this embodiment.

[0085] Figure 1 This is a schematic diagram of a display substrate according to at least one embodiment of the present disclosure. In some examples, such as Figure 1As shown, the display substrate can be a closed polygon including linear edges, such as a rectangle with rounded corners. The display substrate can include a display area AA and a border area BB surrounding the display area AA. The border area BB can include a first border area B1 located on one side of the display area AA along the first direction D1, and other border areas located on the remaining sides of the display area AA. The remaining border areas can include a second border area B2 located on the side of the display area AA away from the first border area B1 along the first direction D1, a third border area B3 located on opposite sides of the display area AA along the second direction D2, and a fourth border area B4. For example, the first border area B1 can be the bottom border area of ​​the display substrate, the second border area B2 can be the top border area of ​​the display substrate, the third border area B3 can be the left border area of ​​the display substrate, and the fourth border area B4 can be the right border area of ​​the display substrate.

[0086] In some examples, such as Figure 1 As shown, the first border area B1 may include: a first sub-border area B10 extending along the second direction D2, and a first corner area B11 and a second corner area B12 located at both ends of the first sub-border area B10 along the second direction D2. The first corner area B11 may be connected to the third border area B3, and the second corner area B12 may be connected to the fourth border area B4. The second border area B2 may include: a second sub-border area B20 extending along the second direction D2, and a third corner area B21 and a fourth corner area B22 located at both ends of the second sub-border area B20 along the second direction D2. The third corner area B21 may be connected to the third border area B3, and the fourth corner area B22 may be connected to the fourth border area B4. The first corner area B11, the second corner area B12, the third corner area B21, and the fourth corner area B22 each correspond to the arcuate edge of the display area AA. The edges of the first corner area B11, the second corner area B12, the third corner area B21, and the fourth corner area B22 on the side away from the display area AA can all be curved edges (e.g., arc edges). The first corner area B11 and the second corner area B12 can be referred to as the lower corner area, and the third corner area B21 and the fourth corner area B22 can be referred to as the upper corner area.

[0087] In some examples, the display area AA may include: a first display area A1 and a second display area A2. The second display area A2 may be located between the first display area A1 and the first border area B1 along a first direction D1. The second display area A2 may include: a sub-display area A21 extending along a second direction D2, and a first corner display area A22a and a second corner display area A22b located on both sides of the sub-display area A21 along the second direction D2. The sub-display area A21 may be located between the first display area A1 and the first sub-border area B10 of the first border area B1. The first corner display area A22a may be located between the first corner area B11 and the sub-display area A21 along the second direction D2, and the second corner display area A22b may be located between the second corner area B12 and the sub-display area A21 along the second direction D2. The first corner display area A22a may be connected to the first corner area B11 and the first display area A1, and the second corner display area A22b may be connected to the second corner area B12 and the first display area A1.

[0088] In some examples, the first display area A1 may include multiple pixel circuits, multiple light-emitting elements, multiple gate lines, and multiple data lines. The second display area A2 may include multiple light-emitting elements and multiple multiplexing circuits. Multiple gate lines may extend along a second direction D2 and be arranged along a first direction D1; multiple data lines may extend along the first direction D1 and be arranged along the second direction D2. Multiple data lines may be connected to multiple pixel circuits and configured to provide data signals to the multiple pixel circuits. Multiple gate lines may be connected to multiple pixel circuits and configured to provide gate control signals to the multiple pixel circuits. For example, the gate control signals may include scan signals, or may include scan signals and light-emitting control signals, or may include scan signals, reset control signals, and light-emitting control signals.

[0089] In some examples, the second direction D2 can be the direction in which the grid lines extend within the display area AA (e.g., the row direction); the first direction D1 can be the direction in which the data lines extend within the display area AA (e.g., the column direction). The first direction D1 and the second direction D2 can intersect each other, for example, they can be perpendicular to each other.

[0090] In some examples, a pixel unit of the display area AA may include three light-emitting elements, which may include a first light-emitting element emitting a first color light (e.g., red light), a second light-emitting element emitting a second color light (e.g., green light), and a third light-emitting element emitting a third color light (e.g., blue light). However, this embodiment is not limited to this. In some examples, a pixel unit may include four light-emitting elements, which may include a first light-emitting element emitting red light, a second light-emitting element emitting green light, a third light-emitting element emitting blue light, and a fourth light-emitting element emitting white light. As another example, a pixel unit may include four light-emitting elements, which may include one first light-emitting element emitting red light, one third light-emitting element emitting blue light, and two second light-emitting elements emitting green light.

[0091] In some examples, the shape of the light-emitting element can be rectangular, rhomboid, pentagonal, or hexagonal. When a pixel unit includes three light-emitting elements, the three light-emitting elements can be arranged horizontally side by side, vertically side by side, or in a triangular arrangement; when a pixel unit includes four light-emitting elements, the four light-emitting elements can be arranged horizontally side by side, vertically side by side, or in a square arrangement. However, this embodiment is not limited in this respect.

[0092] In some examples, the light-emitting element can be any of the following: a light-emitting diode (LED), an organic light-emitting diode (OLED), a quantum dot light-emitting diode (QLED), or a micro-LED (including mini-LED or micro-LED). For example, the light-emitting element can be an OLED, which can emit red, green, blue, or white light under the drive of its corresponding pixel circuit. The color of the light emitted by the light-emitting element can be determined as needed. In some examples, the light-emitting element may include an anode, a cathode, and a light-emitting functional layer located between the anode and cathode. The anode of the light-emitting element can be electrically connected to the corresponding pixel circuit. However, this embodiment is not limited in this respect.

[0093] In some examples, the pixel circuit may include multiple transistors and at least one capacitor. For example, the pixel circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure. In these circuit structures, T refers to a thin-film transistor, C refers to a capacitor, the number before T represents the number of thin-film transistors in the circuit, and the number before C represents the number of capacitors in the circuit. In some examples, the multiple transistors in the pixel circuit may include both P-type and N-type transistors. In other examples, the multiple transistors in the pixel circuit can be either P-type or N-type transistors. Using the same type of transistors in the pixel circuit simplifies the process flow, reduces the processing difficulty of the display substrate, and improves product yield.

[0094] Figure 2 This is an equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure. The pixel circuit of this exemplary embodiment is described using an 8T1C structure as an example. In some examples, such as... Figure 2 As shown, the pixel circuit in this example may include eight transistors (i.e., first transistor T1 to eighth transistor T8) and a storage capacitor Cst. The first transistor T1 is also called the first reset transistor, the second transistor T2 is also called the compensation transistor, the third transistor T3 is also called the driving transistor, the fourth transistor T4 is also called the data writing transistor, the fifth transistor T5 is also called the first light-emitting control transistor, the sixth transistor T6 is also called the second light-emitting control transistor, the seventh transistor T7 is also called the second reset transistor, and the eighth transistor T8 is the third reset transistor. The light-emitting element EL may include a first electrode, a second electrode, and a light-emitting functional layer disposed between the first electrode and the second electrode. The first electrode of the light-emitting element EL can be the anode, and the second electrode of the light-emitting element EL can be the cathode.

[0095] In some examples, the first transistor T1, the third transistor T3 through the eighth transistor T8 can be first-type transistors, such as P-type transistors, and the second transistor T2 can be a second-type transistor, such as an N-type transistor. However, this embodiment is not limited to this. For example, the multiple transistors in the pixel circuit can all be P-type transistors, or they can all be N-type transistors.

[0096] In some examples, the first type of transistor in the pixel circuit (e.g., including the first transistor T1, the third transistor T3 through the eighth transistor T8) can be a low-temperature polycrystalline silicon (LTPS) thin-film transistor, and the second type of transistor in the pixel circuit (e.g., including the second transistor T2) can be an oxide (O) thin-film transistor. The active layer of the LTPS thin-film transistor is made of low-temperature polycrystalline silicon (LTPS), while the active layer of the Oxide thin-film transistor is made of oxide. LTPS thin-film transistors have advantages such as high mobility and fast charging, while Oxide thin-film transistors have advantages such as low leakage current. Integrating LTPS and Oxide thin-film transistors onto a single display substrate to form a low-temperature polycrystalline oxide (LTPS+Oxide) display substrate allows for the utilization of the advantages of both, enabling low-frequency driving, reducing power consumption, and improving display quality.

[0097] In some examples, such as Figure 2 As shown, the pixel circuit can be electrically connected to the first scan line GL1, the second scan line GL2, the data line DL, the first power line VDD, the second power line VSS, the light emission control line EML, the first initial signal line INIT1, the second initial signal line INIT2, the third initial signal line INIT3, the first reset control line RST1, and the second reset control line RST2. The first power line VDD is configured to provide a constant first voltage signal to the pixel circuit, and the second power line VSS is configured to provide a constant second voltage signal to the pixel circuit, wherein the first voltage signal is greater than the second voltage signal. The first scan line GL1 is configured to provide a first scan signal to the pixel circuit. The second scan line GL2 is configured to provide a second scan signal to the pixel circuit. The data line DL is configured to provide a data signal to the pixel circuit. The light emission control line EML is configured to provide a light emission control signal to the pixel circuit. The first reset control line RST1 is configured to provide a first reset control signal to the pixel circuit. The second reset control line RST1 is configured to provide a second reset control signal to the pixel circuit.

[0098] In some examples, such as Figure 2As shown, the gate of the third transistor T3 is electrically connected to the first node N1, the first terminal of the third transistor T3 is electrically connected to the second node N2, and the second terminal of the third transistor T3 is electrically connected to the third node N3. The gate of the fourth transistor T4 is electrically connected to the first scan line GL1, the first terminal of the fourth transistor T4 is electrically connected to the data line DL, and the second terminal of the fourth transistor T4 is electrically connected to the second node N2. The gate of the second transistor T2 is electrically connected to the second scan line GL2, the first terminal of the second transistor T2 is electrically connected to the third node N3, and the second terminal of the second transistor T2 is electrically connected to the first node N1. The gate of the fifth transistor T5 is electrically connected to the light emission control line EML, the first terminal of the fifth transistor T5 is electrically connected to the first power supply line VDD, and the second terminal of the fifth transistor T5 is electrically connected to the second node N2. The gate of the sixth transistor T6 is electrically connected to the light emission control line EML, the first terminal of the sixth transistor T6 is electrically connected to the third node N3, and the second terminal of the sixth transistor T6 is electrically connected to the fourth node N4. The gate of the first transistor T1 is electrically connected to the first reset control line RST1, the first electrode of the first transistor T1 is electrically connected to the first initial signal line INIT1, and the second electrode of the first transistor T1 is electrically connected to the third node N3. The gate of the seventh transistor T7 is electrically connected to the second reset control line RST2, the first electrode of the seventh transistor T7 is electrically connected to the second initial signal line INIT2, and the second electrode of the seventh transistor T7 is electrically connected to the fourth node N4. The gate of the eighth transistor T8 is electrically connected to the second reset control line RST2, the first electrode of the eighth transistor T8 is electrically connected to the third initial signal line INIT3, and the second electrode of the eighth transistor T8 is electrically connected to the second node N2. The first electrode of the storage capacitor Cst is electrically connected to the first node N1, and the second electrode of the storage capacitor Cst is electrically connected to the first power supply line VDD.

[0099] In this example, the first node N1 is the connection point of the storage capacitor Cst, the second transistor T2 and the third transistor T3; the second node N2 is the connection point of the fifth transistor T5, the fourth transistor T4, the eighth transistor T8 and the third transistor T3; the third node N3 is the connection point of the first transistor T1, the third transistor T3, the second transistor T2 and the sixth transistor T6; and the fourth node N4 is the connection point of the sixth transistor T6, the seventh transistor T7 and the light-emitting element EL.

[0100] Figure 3 for Figure 2 The provided timing diagram for the pixel circuit is shown below. Figure 3 right Figure 2 The operation of the pixel circuit shown is explained. The first transistor T1, the third transistor T3 through the eighth transistor T8 in the pixel circuit can be P-type transistors, and the second transistor T2 can be an N-type transistor.

[0101] In some examples, such as Figure 2 and Figure 3 As shown, during a single frame display period, the operation of the pixel circuit can include at least the following stages: first stage P1, second stage P2, third stage P3, and fourth stage P4.

[0102] The first stage, P1, is called the first reset stage. The second reset control signal provided by the second reset control line RST2 is a low-level signal, turning on the seventh transistor T7 and the eighth transistor T8; the second scan signal provided by the second scan line GL2 is a high-level signal, turning on the second transistor T2. The eighth transistor T8 turns on, allowing the third initial signal provided by the third initial signal line INIT3 to be provided to the second node N2. The seventh transistor T7 turns on, allowing the second initial signal provided by the second initial signal line INIT2 to be provided to the fourth node N4, initializing the fourth node N4. The first scan signal provided by the first scan line GL1 is a high-level signal, the first reset control signal provided by the first reset control line RST1 is a high-level signal, and the light emission control signal provided by the light emission control line EML is a high-level signal, turning off the fourth transistor T4, the first transistor T1, the fifth transistor T5, and the sixth transistor T6. During this stage, the light-emitting element EL does not emit light.

[0103] The second stage, P2, is called the second reset stage. The first reset control signal provided by the first reset control line RST1 is a low-level signal, turning on the first transistor T1; the second scan signal provided by the second scan line GL2 is a high-level signal, turning on the second transistor T2. The turning on of the first transistor T1 and the second transistor T2 allows the first initial signal line INIT1 to be provided to the first node N1, initializing N1. The second reset control signal provided by the second reset control line RST2 is a high-level signal, the first scan signal provided by the first scan line GL1 is a high-level signal, and the light emission control signal provided by the light emission control line EML is a high-level signal, causing the seventh transistor T7, the eighth transistor T8, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 to turn off. During this stage, the light-emitting element EL does not emit light.

[0104] The third stage, P3, is called the data writing stage or threshold compensation stage. The first scan signal provided by the first scan line GL1 is a low-level signal, and the fourth transistor T4 is turned on; the second scan signal provided by the second scan line GL2 is a high-level signal, and the second transistor T2 is turned on. During this stage, the first electrode of the storage capacitor Cst is at a low level, and the third transistor T3 is turned on. The turn-on of the second transistor T2, the fourth transistor T4, and the third transistor T3 allows the data voltage Vdata output from the data line DL to be supplied to the first node N1 via the second node N2, the turned-on third transistor T3, the third node N3, and the turned-on second transistor T2. The difference between the data voltage Vdata output from the data line DL and the threshold voltage of the third transistor T3 is charged into the storage capacitor Cst. The voltage at the first electrode of the storage capacitor Cst (i.e., the first node N1) is Vdata - |Vth|, where Vdata is the data voltage output from the data line DL, and Vth is the threshold voltage of the third transistor T3. The first reset control signal provided by the first reset control line RST1 is a high-level signal, the second reset control signal provided by the second reset control line RST2 is a high-level signal, and the light emission control signal provided by the light emission control line EML is a high-level signal, causing the first transistor T1, the seventh transistor T7, the eighth transistor T8, the fifth transistor T5, and the sixth transistor T6 to disconnect.

[0105] In the fourth stage (P4), the light-emitting control signal provided by the light-emitting control line EML can switch from a high-level signal to a low-level signal, turning on the fifth transistor T5 and the sixth transistor T6. The second scan signal provided by the second scan line GL2 is a low-level signal, turning off the second transistor T2. The first scan signal provided by the first scan line GL1, the first reset control signal provided by the first reset control line RST1, and the second reset control signal provided by the second reset control line RST2 are all high-level signals, turning off the fourth transistor T4, the first transistor T1, the seventh transistor T7, and the eighth transistor T8. The first voltage signal output by the first power supply line VDD can provide a driving voltage to the anode of the light-emitting element EL through the turned-on fifth transistor T5, third transistor T3, and sixth transistor T6, driving the light-emitting element EL to emit light.

[0106] During the driving process of the pixel circuit, the driving current flowing through the third transistor T3 is determined by the voltage difference between its gate and first terminal. Since the voltage of the first node N1 is Vdata-|Vth|, the driving current of the third transistor T3 is:

[0107] I = K × (Vgs - Vth) 2 =K×[(Vdd-Vdata+|Vth|)-Vth] 2 =K×[Vdd-Vdata] 2 ;

[0108] Where I is the driving current flowing through the third transistor T3, which is the driving current driving the light-emitting element, K is a constant, Vgs is the voltage difference between the gate and the first electrode of the third transistor T3, Vth is the threshold voltage of the third transistor T3, Vdata is the data voltage output by the data line DL, and Vdd is the voltage of the first voltage signal output by the first power line VDD.

[0109] As can be seen from the above formula, the current flowing through the light-emitting element is independent of the threshold voltage of the third transistor T3. Therefore, the pixel circuit of this embodiment can effectively compensate for the threshold voltage of the third transistor T3. Moreover, the pixel circuit provided in this embodiment can improve display defects caused by low frequencies and enhance the display effect of the light-emitting element.

[0110] Figure 4 This is an equivalent circuit diagram of a multiplexing circuit according to at least one embodiment of the present disclosure. Figure 4 The example shown is a multiplexing circuit 31 with a 1:9 design. In some examples, such as... Figure 4 As shown, a multiplexing circuit 31 can be electrically connected to nine multiplexed control lines (e.g., including first multiplexed control lines ML1 to ninth multiplexed control lines ML9), one multiplexed data line SL, and multiple data lines (e.g., including first data lines DL1 to ninth data lines DL9). The multiplexing circuit 31 may include nine multiplexed control transistors (i.e., first multiplexed control transistor M1 to ninth multiplexed control transistor M9). The gates of the nine multiplexed control transistors can be connected to different multiplexed control lines respectively. Specifically, the gate of the first multiplexed control transistor M1 is connected to the first multiplexed control line ML1, the gate of the second multiplexed control transistor M2 is connected to the second multiplexed control line ML2, the gate of the third multiplexed control transistor M3 is connected to the third multiplexed control line ML3, the gate of the fourth multiplexed control transistor M4 is connected to the fourth multiplexed control line ML4, the gate of the fifth multiplexed control transistor M5 is connected to the fifth multiplexed control line ML5, the gate of the sixth multiplexed control transistor M6 is connected to the sixth multiplexed control line ML6, the gate of the seventh multiplexed control transistor M7 is connected to the seventh multiplexed control line ML7, the gate of the eighth multiplexed control transistor M8 is connected to the eighth multiplexed control line ML8, and the gate of the ninth multiplexed control transistor M9 is connected to the ninth multiplexed control line ML9.

[0111] In some examples, the first terminals of the nine multiplexed control transistors can all be connected to the same multiplexed data line SL. The second terminals of the nine multiplexed control transistors are respectively connected to different data lines in the display area. For example, the second terminal of the first multiplexed control transistor M1 is connected to the first data line DL1, the second terminal of the second multiplexed control transistor M2 is connected to the second data line DL2, the second terminal of the third multiplexed control transistor M3 is connected to the third data line DL3, the second terminal of the fourth multiplexed control transistor M4 is connected to the fourth data line DL4, the second terminal of the fifth multiplexed control transistor M5 is connected to the fifth data line DL5, the second terminal of the sixth multiplexed control transistor M6 is connected to the sixth data line DL6, the second terminal of the seventh multiplexed control transistor M7 is connected to the seventh data line DL7, the second terminal of the eighth multiplexed control transistor M8 is connected to the eighth data line DL8, and the second terminal of the ninth multiplexed control transistor M9 is connected to the ninth data line DL9. Each data line can be connected to at least one column of pixel circuits in the display area. A column of pixel circuits can include multiple pixel circuits arranged along a first direction D1. Nine multiplexed control lines can control multiple multiplexed circuits 31 to provide data signals to the corresponding column pixel circuits of the display area.

[0112] Figure 5 for Figure 1 A magnified view of a portion of the central region S1. Figure 6 for Figure 1 A magnified view of a portion of the central region S2. Figure 7 for Figure 1 A magnified view of a portion of the central region S3. Figure 5 The circuit structure layer is illustrated using a row (e.g., the nth row, where n is a positive integer) of the first display area A1, consisting of three columns of pixel circuits (e.g., including the jth column, the (j+1)th column, and the (j+2)th column, where j is a positive integer). The nth row of pixel circuits can be the last row of pixel circuits within the first display area A1. Figure 6 The circuit structure layer is illustrated using the two rows (e.g., the m-th row and the m+1-th row, where m can be an integer greater than 0 and less than n) and four columns (e.g., including the k-th column, the k+1-th column, the k+2-th column, and the k+3-th column, where k is an integer greater than 0 and less than j) of the pixel circuit near the first corner display area A1 close to the first corner display area A22a as an example. Figure 7 The circuit structure layer in the diagram is illustrated using a multiplexed circuit in the second display area A2 as an example.

[0113] In some examples, such as Figures 5 to 7As shown, the multiple light-emitting elements of the display area AA may include multiple light-emitting element groups, which can be arranged in an array along a first direction D1 and a second direction D2. A light-emitting element group may include a first light-emitting element EL1 emitting a first color light, a second light-emitting element EL2 emitting a second color light, and a third light-emitting element EL3 emitting a third color light. A light-emitting element group may correspond to one pixel unit. In a light-emitting element group, the first light-emitting element EL1 and the second light-emitting element EL2 may be aligned along the first direction D1 and located on the same side of the third light-emitting element EL3 along the second direction D2. For example, the first light-emitting element EL1 may be a red light-emitting element, the second light-emitting element EL2 may be a green light-emitting element, and the third light-emitting element EL3 may be a blue light-emitting element.

[0114] In some examples, the orthographic projections of the light-emitting areas of the first light-emitting element EL1, the second light-emitting element EL2, and the third light-emitting element EL3 onto the substrate can all be rectangular. The orthographic projection area of ​​the light-emitting area of ​​the second light-emitting element EL2 onto the substrate can be larger than that of the first light-emitting element EL1, and the orthographic projection area of ​​the light-emitting area of ​​the third light-emitting element EL3 onto the substrate can be larger than that of the second light-emitting element EL2. In this example, the light-emitting area of ​​the light-emitting element refers to the overlapping area of ​​the anode of the light-emitting element with the light-emitting functional layer and the cathode exposed by the pixel opening of the pixel definition layer.

[0115] In some examples, such as Figure 5 and Figure 6 As shown, within the first display area A1, the orthographic projections of the light-emitting elements and the connected pixel circuits onto the substrate can be offset along the first direction D1. The orthographic projection of the light-emitting elements onto the substrate can be located on the side of the orthographic projection of the connected pixel circuits onto the substrate closer to the second display area A2 along the first direction D1. The orthographic projections of the light-emitting areas of the light-emitting elements onto the substrate and the orthographic projections of the connected pixel circuits onto the substrate may partially overlap or may not overlap. For example, the orthographic projection of the light-emitting area of ​​the first light-emitting element EL1 onto the substrate may partially overlap with the orthographic projection of the connected pixel circuits onto the substrate, the orthographic projection of the light-emitting area of ​​the second light-emitting element E2 onto the substrate may not overlap with the orthographic projection of the connected pixel circuits onto the substrate, and the orthographic projection of the light-emitting area of ​​the third light-emitting element EL3 onto the substrate may not overlap with the orthographic projection of the connected pixel circuits onto the substrate.

[0116] In some examples, such as Figure 5 , Figure 6 and Figure 7As shown, within the second display area A2, the orthographic projection of the light-emitting area of ​​the light-emitting element onto the substrate may overlap with the orthographic projection of the multiplexing circuit onto the substrate. Multiple multiplexing control lines connected to the multiplexing circuit (e.g., including the first multiplexing control line ML1 to the ninth multiplexing control line ML9) may extend along the second direction D2 and be arranged along the first direction D1. For example, all multiple multiplexing control lines may be located in the first border area B1. In other examples, a portion of the multiple multiplexing control lines may be located in the second display area, while another portion may be located in the first border area B1.

[0117] The structure of a display substrate is illustrated below through an example of its fabrication process. The "patterning process" described in this disclosure, for metallic, inorganic, or transparent conductive materials, includes processes such as photoresist coating, mask exposure, development, etching, and photoresist stripping; for organic materials, it includes processes such as organic material coating, mask exposure, and development. Deposition can be performed using any one or more of sputtering, evaporation, and chemical vapor deposition; coating can be performed using any one or more of spraying, spin coating, and inkjet printing; etching can be performed using any one or more of dry etching and wet etching. This disclosure does not limit the methods used.

[0118] In this specification, "A and B are arranged in the same layer" means that A and B are formed simultaneously through the same patterning process, or that the surfaces of A and B closest to the substrate are substantially the same distance from the substrate, or that the surfaces of A and B closest to the substrate are in direct contact with the same film layer. The "thickness" of the film layer is its dimension in the direction perpendicular to the display substrate. In this specification, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A includes the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or that the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0119] In some exemplary embodiments, the fabrication process of the display substrate may include the following operations.

[0120] (1) Providing a substrate. In some examples, the substrate can be a rigid substrate or a flexible substrate. For example, a rigid substrate can be, but is not limited to, one or more of glass and quartz; a flexible substrate can be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers. In some examples, the flexible substrate may include a first flexible material layer, a first inorganic material layer, a second flexible material layer, and a second inorganic material layer stacked together. The materials of the first flexible material layer and the second flexible material layer may be polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer film, etc. The materials of the first inorganic material layer and the second inorganic material layer may be silicon nitride (SiNx, x>0) or silicon oxide (SiOy, y>0), etc., to improve the substrate's resistance to water and oxygen.

[0121] (2) Forming a first semiconductor layer. In some examples, a first semiconductor thin film is deposited on a substrate, and the first semiconductor thin film is patterned by a patterning process to form a first semiconductor layer disposed on the substrate. In some examples, the material of the first semiconductor layer may be amorphous silicon (a-Si), polycrystalline silicon (p-Si), hexathiophene, or polythiophene, etc.

[0122] Figure 8A for Figure 5 A schematic diagram of the first semiconductor layer in the process; Figure 8B for Figure 6 A schematic diagram of the first semiconductor layer in the process; Figure 8C for Figure 7 A schematic diagram of the first semiconductor layer. In some examples, such as... Figure 8A , Figure 8B and Figure 8C As shown, the first semiconductor layer of the display substrate may include: an active layer of multiple first-type transistors of multiple pixel circuits located in the first display area A1 (e.g., including the active layer T10 of the first transistor, the active layer T30 of the third transistor, the active layer T40 of the fourth transistor, the active layer T50 of the fifth transistor, the active layer T60 of the sixth transistor, the active layer T70 of the seventh transistor, and the active layer T80 of the eighth transistor), and an active layer of multiple multiplexing control transistors of multiple multiplexing circuits located in the second display area A2 (e.g., including the active layers M10 of the first multiplexing control transistor to the active layers M90 of the ninth multiplexing control transistor).

[0123] In some examples, such as Figure 8A and Figure 8BAs shown, the active layers T30 of the third transistor, T40 of the fourth transistor, T50 of the fifth transistor, T60 of the sixth transistor, and T70 of the seventh transistor in a pixel circuit can be an integral structure. The active layer T10 of the first transistor can be located on one side of the active layer T30 of the third transistor along the first direction D1, and the active layer T80 of the eighth transistor can be located on the other side of the active layer T30 of the third transistor along the first direction D1. The active layers T80 of the eighth transistor and T70 of the seventh transistor can be aligned along the second direction D2. The active layer T10 of the first transistor can be aligned with the active layer T60 of the sixth transistor along the first direction D1.

[0124] In some examples, such as Figure 8A and Figure 8B As shown, the orthographic projection of the active layer T10 of the first transistor, the active layer T40 of the fourth transistor, the active layer T60 of the sixth transistor, the active layer T70 of the seventh transistor, and the active layer T80 of the eighth transistor onto the substrate can be I-shaped, the orthographic projection of the active layer T30 of the third transistor onto the substrate can be S-shaped, and the orthographic projection of the active layer T50 of the fifth transistor onto the substrate can be T-shaped.

[0125] In some examples, the active layer of each transistor may include a first region, a second region, and a channel region located between the first and second regions. The semiconductor layer material may, for example, include polysilicon. The channel region may be undoped and possess semiconductor properties. The first and second regions may be doped regions on either side of the channel region and are doped with impurities, thus possessing conductivity. The impurities may vary depending on the type of transistor. In some examples, the doped regions of the active layer may be interpreted as the source or drain electrodes of the transistor. The portion of the active layer between transistors may be interpreted as doped wiring that can be used to electrically connect the transistors. This embodiment is not limited in this respect.

[0126] In some examples, such as Figure 8A and Figure 8B As shown, the second region of the active layer T30 of the third transistor can simultaneously serve as the first region of the active layer T60 of the sixth transistor. The second region of the active layer T60 of the sixth transistor can simultaneously serve as the second region of the active layer T70 of the seventh transistor. The first region of the active layer T30 of the third transistor can simultaneously serve as the second region of the active layer T40 of the fourth transistor and the second region of the active layer T50 of the fifth transistor. The first regions of the active layers T40, T70, and T50 of the fourth transistor can be set independently.

[0127] In some examples, such as Figure 8CAs shown, the active layers of the nine multiplexing control transistors in the multiplexing circuit (e.g., including the active layer M10 of the first multiplexing control transistor, the active layer M20 of the second multiplexing control transistor, the active layer M30 of the third multiplexing control transistor, the active layer M40 of the fourth multiplexing control transistor, the active layer M50 of the fifth multiplexing control transistor, the active layer M60 of the sixth multiplexing control transistor, the active layer M70 of the seventh multiplexing control transistor, the active layer M80 of the eighth multiplexing control transistor, and the active layer M90 of the ninth multiplexing control transistor) can be aligned along the second direction D2. The orthographic projection of the active layers M10 to M90 of the ninth multiplexing control transistor onto the substrate can be rectangular.

[0128] (3) Forming a first conductive layer. In some examples, a first insulating film and a first conductive film are sequentially deposited on the substrate on which the aforementioned structure is formed. The first conductive film is patterned using a patterning process to form a first insulating layer and a first conductive layer disposed on the first insulating layer. In some examples, the first insulating layer may also be referred to as a first gate insulating layer; the first conductive layer may also be referred to as a first gate metal layer.

[0129] Figure 9A for Figure 5 A schematic diagram of the display substrate after the first conductive layer has been formed; Figure 9B for Figure 9A A schematic diagram of the first conductive layer in the image. Figure 9C for Figure 6 A schematic diagram of the display substrate after the first conductive layer has been formed. Figure 9D for Figure 7 A schematic diagram of the display substrate after the first conductive layer has been formed.

[0130] In some examples, such as Figures 9A to 9DAs shown, the first conductive layer of the display substrate may include: gates of multiple first-type transistors (e.g., including the gates of the first transistor T1, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8) and the first electrode Cst-1 of multiple storage capacitors located in the first display area A1, multiple first scan lines (e.g., including the first scan lines GL1(n), GL1(m), and GL(m+1)), multiple first blocking electrodes 203, and multiple light-emitting control lines (e.g., including light-emitting control lines...). EML(n), EML(m), EML(m+1)), multiple first reset control lines (e.g., including first reset control lines RST1(n), RST1(m-1), RST1(m), RST1(m+1)), and multiple second reset control lines (e.g., including second reset control lines RST2(n), RST2(m), RST2(m+1)), the gates of multiple multiplexed control transistors of multiple multiplexed circuits located in the second display area A2 (e.g., including the gates M11 of the first multiplexed control transistor M1 to M91 of the ninth multiplexed control transistor M9), and multiple first auxiliary electrodes 201.

[0131] In some examples, such as Figure 9A and Figure 9B As shown, the first scan line GL1(n) can extend along the second direction D2. Multiple first blocking electrodes 203 can be connected to the side of the first scan line GL1(n) away from the third transistor T3. The orthographic projection of the first blocking electrode 203 onto the substrate can be rectangular. The orthographic projection of the first blocking electrode 203 onto the substrate can be located between the orthographic projections of the active layers T40 of the fourth transistor T4 of two adjacent pixel circuits in the same row onto the substrate. The overlapping portion of the first scan line GL1(n) and the active layer T40 of the fourth transistor T4 can serve as the gate of the fourth transistor T4.

[0132] In some examples, the orthographic projection of the first electrode Cst-1 of the storage capacitor onto the substrate can be rectangular. The first electrode Cst-1 of the storage capacitor can also serve as the gate of the third transistor T3.

[0133] In some examples, the orthogonal projection of the first reset control line RST1(n) onto the substrate can be a straight line extending along the second direction D2. The first reset control line RST1(n) can be located along the first direction D1 on the side of the first scan line GL1(n) away from the third transistor T3. The overlapping portion of the first reset control line RST1(n) with the active layer T10 of the first transistor T1 can serve as the gate of the first transistor T1.

[0134] In some examples, the orthogonal projection of the second reset control line RST2(n) onto the substrate can be a broken line extending along the second direction D2. The second reset control line RST2(n) can be located along the first direction D1 on the side of the third transistor T3 away from the first scan line GL1(n). The overlapping portion of the second reset control line RST2(n) with the active layer T70 of the seventh transistor T7 can serve as the gate of the seventh transistor T7, and the overlapping portion of the second reset control line RST2(n) with the active layer T80 of the eighth transistor T8 can serve as the gate of the eighth transistor T8.

[0135] In some examples, the orthogonal projection of the light-emitting control line EML(n) onto the substrate can be a broken line extending along the second direction D2. The light-emitting control line EML(n) can be located along the first direction D1 on the side of the second reset control line RST2(n) near the third transistor T3. The overlapping portion of the light-emitting control line EML(n) with the active layer of the sixth transistor T6 can serve as the gate of the sixth transistor T6, and the overlapping portion of the light-emitting control line EML(n) with the active layer of the fifth transistor T5 can serve as the gate of the fifth transistor T5.

[0136] In some examples, such as Figure 9D As shown, the gates M11 of the first multiplexed control transistor M1, M21 of the second multiplexed control transistor M2, M31 of the third multiplexed control transistor M3, M41 of the fourth multiplexed control transistor M4, M51 of the fifth multiplexed control transistor M5, M61 of the sixth multiplexed control transistor M6, M71 of the seventh multiplexed control transistor M7, M81 of the eighth multiplexed control transistor M8, and M91 of the ninth multiplexed control transistor M9 can be arranged sequentially along the second direction D2 and extend along the first direction D1, for example, extending to the first border region B1. The first auxiliary electrode 201 can be located on the side of the gate M11 of the first multiplexed control transistor M1 away from the gate M21 of the second multiplexed control transistor. The orthographic projection of the first auxiliary electrode 201 onto the substrate can be rectangular.

[0137] (4) Forming a second conductive layer. In some examples, a second insulating film and a second conductive film are sequentially deposited on the substrate on which the aforementioned structure is formed. The second conductive film is patterned using a patterning process to form a second insulating layer and a second conductive layer disposed on the second insulating layer. In some examples, the second insulating layer may also be referred to as a second gate insulating layer, and the second conductive layer may also be referred to as a second gate metal layer.

[0138] Figure 10A for Figure 5 A schematic diagram of the display substrate after the second conductive layer has been formed; Figure 10B for Figure 10A A schematic diagram of the second conductive layer in the image. Figure 10C for Figure 6 A schematic diagram of the display substrate after the second conductive layer has been formed. Figure 10D for Figure 7 A schematic diagram of the display substrate after the second conductive layer has been formed.

[0139] In some examples, such as Figures 10A to 10D As shown, the second conductive layer of the display substrate may include: the second electrode Cst-2 of the storage capacitor of the multiple pixel circuits located in the first display area A1, multiple first initial signal lines (e.g., including the first initial signal lines INIT1(n-1), INIT1(n), INIT1(m-1), INIT1(m)), multiple second scan auxiliary lines (e.g., including the second scan auxiliary lines GL2b(n), GL2b(m), GL2b(m+1)), multiple second auxiliary electrodes 202 located in the second display area A2, and multiplexed data lines SL.

[0140] In some examples, such as Figures 10A to 10C As shown, the second electrode Cst-2 of the storage capacitor may have a first cutout portion K0. The orthographic projection of the first cutout portion K0 onto the substrate may be located within the orthographic projection range of the first electrode Cst-1 of the storage capacitor onto the substrate. The orthographic projections of the second electrode Cst-2 and the first electrode Cst-1 of the storage capacitor onto the substrate overlap.

[0141] In some examples, the orthographic projection of the first initial signal line INIT1(n) onto the substrate can be a straight line extending along the second direction D2. The orthographic projection of the first initial signal line INIT1(n) onto the substrate can be located on the side of the first reset control line RST1(n) onto the substrate closer to the second display area A2.

[0142] In some examples, the orthographic projection of the second scan auxiliary line GL2b(n) onto the substrate can be a broken line extending along the second direction D2. The orthographic projection of the second scan auxiliary line GL2b(n) onto the substrate can be located between the orthographic projections of the first scan line GL1(n) and the first reset control line RST1(n) onto the substrate.

[0143] In some examples, such as Figure 10D As shown, the orthographic projection of the second auxiliary electrode 202 onto the substrate can be rectangular. The orthographic projection of the second auxiliary electrode 202 onto the substrate can be located between the orthographic projections of the gate M31 of the third multiplexed control transistor M3 and the gate M41 of the fourth multiplexed control transistor M4 onto the substrate.

[0144] In some examples, such as Figure 10DAs shown, the multiplexed data line SL can extend along the first direction D1 to the first border region B1. The orthographic projection of the multiplexed data line SL onto the substrate can be located between the orthographic projections of the gate M61 of the sixth multiplexed control transistor M6 and the gate M71 of the seventh multiplexed control transistor M7 onto the substrate.

[0145] (5) Forming a second semiconductor layer. In some examples, a third insulating film and a second semiconductor film are sequentially deposited on the substrate on which the aforementioned pattern is formed. The second semiconductor film is patterned using a patterning process to form a third insulating layer and a second semiconductor layer disposed on the third insulating layer. In some examples, the third insulating layer may also be referred to as a third gate insulating layer. For example, the material of the second semiconductor layer may be IGZO.

[0146] Figure 11A for Figure 5 A schematic diagram of the display substrate after the second semiconductor layer has been formed. Figure 11B for Figure 6 A schematic diagram of a display substrate after the second semiconductor layer has been formed. In some examples, such as... Figure 11A and Figure 11B As shown, the second semiconductor layer of the display substrate may include: an active layer of second-type transistors (e.g., an active layer T20 including second transistors) of a plurality of pixel circuits located in the first display area A1.

[0147] In some examples, such as Figure 11A and Figure 11B As shown, the active layer T20 of the second transistor may include: a channel region T20-0, a first region T20-1, and a second region T20-2. The active layer T20 of the second transistor may extend along a first direction D1. The orthographic projection of the second region T20-2 of the second transistor onto the substrate may be rectangular. The orthographic projection of the second region T20-2 of the second transistor onto the substrate may be located within the range of the orthographic projection of the first shielding electrode 203 onto the substrate.

[0148] (6) Forming a third conductive layer. In some examples, a fourth insulating film and a third conductive film are sequentially deposited on the substrate on which the aforementioned pattern is formed. The third conductive film is patterned using a patterning process to form a fourth insulating layer and a third conductive layer disposed on the fourth insulating layer. In some examples, the fourth insulating layer may also be referred to as a fourth gate insulating layer, and the third conductive layer may also be referred to as a third gate metal layer.

[0149] Figure 12A for Figure 5 A schematic diagram of the display substrate after the third conductive layer has been formed. Figure 12B for Figure 6 A schematic diagram of a display substrate after the formation of the third conductive layer. In some examples, such as... Figure 12A and Figure 12BAs shown, the third conductive layer of the display substrate may include: multiple second scan lines (e.g., including second scan lines GL2(n), GL2(m), GL2(m+1)) and multiple third initial signal lines (e.g., including third initial signal lines INIT3(n), INIT3(m), INIT3(m+1)) located in the first display area A1.

[0150] In some examples, such as Figure 12A and Figure 12B As shown, the orthographic projection of the second scan line GL2(n) onto the substrate can be a broken line extending along the second direction D2. The orthographic projection of the second scan line GL2(n) onto the substrate overlaps with the orthographic projection of the second scan auxiliary line GL2b(n) onto the substrate. The overlapping portion of the second scan line GL2(n) with the active layer T20 of the second transistor T2 can serve as the gate of the second transistor T2. The overlapping portion of the second scan auxiliary line GL2b(n) with the active layer T20 of the second transistor T2 can serve as the bottom gate of the second transistor T2. The second scan line GL2(n) and the second scan auxiliary line GL2b(n) can be configured to receive the same signal.

[0151] In some examples, such as Figure 12A and Figure 12B As shown, the orthographic projection of the third initial signal line INIT3(n) onto the substrate can be a broken line extending along the second direction D2. The orthographic projection of the third initial signal line INIT3(n) onto the substrate may overlap with the orthographic projection of the second reset control line RST2(n) onto the substrate.

[0152] (7) Forming a fifth insulating layer. In some examples, a fifth insulating film is deposited on the substrate on which the aforementioned pattern is formed, and the fifth insulating film is patterned by a patterning process to form a fifth insulating layer. In some examples, the fifth insulating layer may also be referred to as an interlayer insulating layer.

[0153] Figure 13A for Figure 5 A schematic diagram of the display substrate after the fifth insulating layer has been formed. Figure 13B for Figure 6 A schematic diagram of the display substrate after the fifth insulating layer has been formed. Figure 13C for Figure 7 A schematic diagram of the display substrate after the fifth insulating layer has been formed.

[0154] In some examples, such as Figures 13A to 13CAs shown, the fifth insulating layer of the display substrate can be provided with multiple vias, for example, it can include: first via V1 to twenty-seventh via V27. Specifically, the fifth, fourth, third, second, and first insulating layers within the first via V1 to twelfth via V12 can be removed, exposing a portion of the surface of the first semiconductor layer. The fifth, fourth, third, and second insulating layers within the thirteenth via V13 to seventeenth via V17 can be removed, exposing a portion of the surface of the first conductive layer. The fifth, fourth, and third insulating layers within the eighteenth via V18 and twenty-second via V22 can be removed, exposing a portion of the surface of the second conductive layer. The fifth and fourth insulating layers within the twenty-third via V23 to twenty-fourth via V24 can be removed, exposing a portion of the surface of the second semiconductor layer. The fifth insulating layer within the twenty-fifth via V25 and twenty-seventh via V27 can be removed, exposing a portion of the surface of the third conductive layer.

[0155] (8) Forming a fourth conductive layer. In some examples, a fourth conductive film is deposited on the substrate on which the aforementioned pattern is formed, and the fourth conductive film is patterned by a patterning process to form a fourth conductive layer on the fifth insulating layer. In some examples, the fourth conductive layer may also be referred to as a first source / drain metal layer.

[0156] Figure 14A for Figure 5 A schematic diagram of the display substrate after the fourth conductive layer has been formed; Figure 14B for Figure 14A A schematic diagram of the fourth conductive layer in the image. Figure 14C for Figure 6 A schematic diagram of the display substrate after the fourth conductive layer has been formed; Figure 14D for Figure 14C A schematic diagram of the fourth conductive layer in the image. Figure 14E for Figure 7 A schematic diagram of the display substrate after the fourth conductive layer has been formed.

[0157] In some examples, such as Figures 14A to 14EAs shown, the fourth conductive layer of the display substrate may include: a plurality of connection electrodes (e.g., first connection electrodes 301 to ninth connection electrodes 309) and a plurality of second initial signal lines (e.g., second initial signal lines INIT2(n), INIT2(n+1), INIT2(m), INIT2(m+1)) located in the first display area A1; a plurality of connection electrodes (e.g., eleventh connection electrodes 311 to fifteenth connection electrodes 315) and a first frame power line 33 located in the second display area A2; a first electrode and a second electrode of a plurality of multiplexed control transistors (e.g., first electrode M12 and second electrode M13 of the first multiplexed control transistor M1, and first electrode M82 and second electrode M83 of the eighth multiplexed control transistor M8); and a multiplexed connection electrode 34; and a plurality of multiplexed control lines (e.g., first multiplexed control lines ML1 to ninth multiplexed control lines ML9) located in the first frame area B1.

[0158] In some examples, such as Figure 14A and Figure 14B As shown, the orthogonal projection of the first connection electrode 301 onto the substrate can be a strip extending along the first direction D1. The first connection electrode 301 can be connected to the first region of the active layer T10 of the first transistor T1 through the tenth via V10, and can also be connected to the first initial signal line INIT1(n) through the nineteenth via V19.

[0159] In some examples, the orthographic projection of the second connection electrode 302 onto the substrate can be approximately L-shaped. One end of the second connection electrode 302 can be connected to the first region of the active layer T60 of the sixth transistor T6 through the third via V3, and the other end can be connected to the second region of the active layer T10 of the first transistor T1 through the ninth via V9. It can also be connected to the first region T20-1 of the active layer T20 of the second transistor T2 through the twenty-fourth via V24.

[0160] In some examples, the orthographic projection of the third connection electrode 303 onto the substrate can be a broken line extending along the first direction D1. The third connection electrode 303 can be connected to the gate T31 of the third transistor T3 through the thirteenth via V13, and can also be connected to the second region T20-2 of the active layer T20 of the second transistor T2 through the twenty-third via V23.

[0161] In some examples, the orthographic projection of the fourth connection electrode 304 onto the substrate can be a strip extending along a direction that intersects both the first direction D1 and the second direction D2. The fourth connection electrode 304 can be connected to the first region of the active layer T80 of the eighth transistor T8 through the fourth via V4, and can also be connected to the third initial signal line INIT3(n) through the twenty-seventh via V27.

[0162] In some examples, the orthographic projection of the fifth connection electrode 305 onto the substrate can be approximately rectangular. The fifth connection electrode 305 can be connected to the second region of the active layer T60 of the sixth transistor T6 via the second via V2.

[0163] In some examples, the orthographic projection of the sixth connection electrode 306 onto the substrate can be approximately L-shaped. The sixth connection electrode 306 can be connected to the second region of the active layer T80 of the eighth transistor T8 through the fifth via V5, and can also be connected to the second region of the active layer T50 of the fifth transistor T5 through the sixth via V6.

[0164] In some examples, the orthographic projection of the seventh connection electrode 307 onto the substrate can be approximately rectangular. The seventh connection electrode 307 can be connected to the first region of the active layer T40 of the fourth transistor T4 via the eighth via V8.

[0165] In some examples, the orthographic projection of the eighth connection electrode 308 onto the substrate can be approximately T-shaped. The eighth connection electrode 308 can be connected to the second electrode Cst-2 of the storage capacitor through two vertically arranged eighteenth vias V18, and can also be connected to the first region of the active layer T50 of the fifth transistor T5 through the seventh via V7. The eighth connection electrode 308 connected to a row of pixel circuits can be a single structure, thereby enabling the transmission of the first voltage signal along the second direction D2.

[0166] In some examples, the orthographic projection of the ninth connection electrode 309 onto the substrate can be a strip extending along the first direction D1. The ninth connection electrode 309 can be connected to the first region of the active layer T70 of the seventh transistor T7 through the first via V1.

[0167] In some examples, the second initial signal line INIT2(n) can be a straight line extending along the second direction D2. The second initial signal line INIT2(n) and the plurality of ninth connection electrodes 309 connected to a row (e.g., the nth row) of pixel circuit can be an integral structure. The orthographic projection of the second initial signal line INIT2(n) onto the substrate may overlap with the orthographic projection of the first reset control line RST1(n-1) onto the substrate.

[0168] In this example, multiple first initial signal lines can be located on the second conductive layer, multiple second initial signal lines can be located on the fourth conductive layer, and multiple third initial signal lines can be located on the third conductive layer. By setting the first, second, and third initial signal lines to be located on different conductive layers, it is beneficial to save the space occupied by the traces.

[0169] In some examples, such as Figure 14C and Figure 14DAs shown, the eleventh connecting electrode 311 to the fifteenth connecting electrode 315 can be located in the first corner display area A22a of the second display area. The orthographic projection of the eleventh connecting electrode 311 to the fifteenth connecting electrode 315 onto the substrate can all be approximately rectangular. The eleventh connecting electrode 311 can be connected to the end of the third initial signal line INIT3(m+1) extending to the first corner display area A22a through the twenty-fifth via V25. The twelfth connecting electrode 312 can be connected to the end of the light emission control line EML(m+1) extending to the first corner display area A22a through the sixteenth via V16. The thirteenth connecting electrode 313 can be integrated with the eighth connecting electrode 308 connected to the (m+1)th row pixel circuit. The fourteenth connecting electrode 314 can be connected to the end of the second scan line GL2(m+1) extending to the first corner display area A22a via the twenty-sixth via V26, and can also be connected to the end of the second scan auxiliary line GL2b(m+1) extending to the first corner display area A22a via the twenty-second via V22. The fifteenth connecting electrode 315 can be connected to the end of the first reset control line RST1(m+1) extending to the first corner display area A22a via the seventeenth via V17.

[0170] In some examples, such as Figure 14A and Figure 14E As shown, the first bezel power line 33 can be located in the second display area A2, and along the first direction D1, it can be located between the nth row pixel circuit and the row multiplexing circuit. The orthographic projection of the first bezel power line 33 onto the substrate can be a straight line extending along the second direction D2.

[0171] In some examples, such as Figures 14A to 14E As shown, the first terminal M12 of the first multiplexed control transistor M1 can be connected to the first region of the active layer M10 of the first multiplexed control transistor M1 through multiple (e.g., four) vertically arranged eleventh vias V11. The second terminal M13 of the first multiplexed control transistor M1 can be connected to the second region of the active layer M10 of the first multiplexed control transistor M1 through multiple (e.g., four) vertically arranged twelfth vias V12. The first terminal M82 of the eighth multiplexed control transistor M8 can be connected to the first region of the active layer M80 of the eighth multiplexed control transistor M8, and the second terminal M83 of the eighth multiplexed control transistor M8 can be connected to the second region of the active layer M80 of the eighth multiplexed control transistor M8.

[0172] In some examples, the multiplexing connection electrode 34 can be located on the side of the multiplexing circuit away from the first display area A1. The multiplexing connection electrode 34 and the first electrode of the first multiplexing control transistor M1 to the first electrode of the ninth multiplexing control transistor M9 of a multiplexing circuit can be an integral structure. In the sub-display area of ​​the second display area A2, the orthographic projection of the multiplexing connection electrode 34 onto the substrate can be a straight line extending along the second direction D2. The reset connection electrode 34 can be connected to the first auxiliary electrode 201 through the fourteenth via V14, to the second auxiliary electrode 202 through the twentieth via V20, and to the multiplexed data line SL through the twenty-first via V21.

[0173] In some examples, such as Figure 14E As shown, within the first sub-border area of ​​the first border area B1, multiple multiplexed control lines can extend along the second direction D2 and be arranged sequentially along the first direction D1. For example, the first multiplexed control line ML1 can be connected to the gate M11 of the first multiplexed control transistor M1 through the fifteenth via V15; the second multiplexed control line ML2 can be connected to the gate M21 of the second multiplexed control transistor M2; the third multiplexed control line ML3 can be connected to the gate M31 of the third multiplexed control transistor M3; the fourth multiplexed control line ML4 can be connected to the gate M41 of the fourth multiplexed control transistor M4; the fifth multiplexed control line ML5 can be connected to the gate M51 of the fifth multiplexed control transistor M5; the sixth multiplexed control line ML6 can be connected to the gate M61 of the sixth multiplexed control transistor M6; the seventh multiplexed control line ML7 can be connected to the gate M71 of the seventh multiplexed control transistor M7; the eighth multiplexed control line ML8 can be connected to the gate M81 of the eighth multiplexed control transistor M8; and the ninth multiplexed control line ML9 can be connected to the gate M91 of the ninth multiplexed control transistor M9.

[0174] (9) Forming a sixth insulating layer. In some examples, a sixth insulating film is coated on the substrate on which the aforementioned pattern is formed, and the sixth insulating film is patterned by a patterning process to form a sixth insulating layer. In some examples, the sixth insulating layer may also be referred to as a first planarization layer.

[0175] Figure 15A for Figure 5 A schematic diagram of the display substrate after the sixth insulating layer has been formed. Figure 15B for Figure 6 A schematic diagram of the display substrate after the formation of the sixth insulating layer. In some examples, such as... Figure 15A and Figure 15BAs shown, the sixth insulating layer of the display substrate may have multiple vias, for example, it may include: the thirty-first via V31 to the fortieth via V40. The sixth insulating layer within the thirty-first via V31 to the fortieth via V40 may be removed, exposing a portion of the surface of the fourth conductive layer.

[0176] (10) Forming the fifth conductive layer. In some examples, a fifth conductive film is deposited on the substrate on which the aforementioned pattern is formed, and the fifth conductive film is patterned by a patterning process to form the fifth conductive layer on the sixth insulating layer. In some examples, the fifth conductive layer may also be referred to as the second source / drain metal layer.

[0177] Figure 16A for Figure 5 A schematic diagram of the display substrate after the fifth conductive layer has been formed. Figure 16B for Figure 16A A schematic diagram of the fifth conductive layer. Figure 16C for Figure 6 A schematic diagram of the display substrate after the fifth conductive layer has been formed. Figure 16D for Figure 16C A schematic diagram of the fifth conductive layer. Figure 16E for Figure 7 A schematic diagram of the display substrate after the fifth conductive layer has been formed.

[0178] In some examples, such as Figures 16A to 16E As shown, the fifth conductive layer of the display substrate may include: multiple first power lines (e.g., including first power lines VDD(j), VDD(j+1), VDD(j+2), VDD(k), VDD(k+1), VDD(k+2), VDD(k+3)), multiple data lines (e.g., including first data line DL1, second data line DL2, third data line DL3, seventh data line DL7, eighth data line DL8 and ninth data line DL9), multiple first pads 51, multiple second pads 52, multiple first adapter electrodes (e.g., including first adapter electrodes 410a, 410b and 410c), and multiple connecting lines (e.g., including second connecting line 401, third connecting line 403, first connecting line 402, 404 and 405).

[0179] In some examples, such as Figures 16A to 16BAs shown, the first transition electrodes 410a, 410b, and 410c can extend along the first direction D1, allowing the orthogonal projections of the pixel circuit and the connected light-emitting element onto the substrate to be misaligned along the first direction D1. One end of the first transition electrode 410a can be connected to the fifth connection electrode 305 connecting the pixel circuit in the j-th column and n-th row via the thirty-first via V31, and the other end can be subsequently connected to the anode of the first light-emitting element EL1. One end of the first transition electrode 410b can be connected to the pixel circuit in the (j+1)-th column and n-th row, and the other end can be subsequently connected to the anode of the second light-emitting element EL2. One end of the first transition electrode 410c can be connected to the pixel circuit in the (j+2)-th column and n-th row, and the other end can be subsequently connected to the anode of the third light-emitting element EL3.

[0180] In some examples, multiple first power lines can extend along a first direction D1 and be arranged along a second direction D2. For example, the first power line VDD(j) can extend along the first direction D1 and from the first display area A1 to the second display area A2. The first power line VDD(j) in the first display area A1 can be connected to the eighth connection electrode 308 through the thirty-second via V32 to achieve electrical connection with the storage capacitor and the fifth transistor of the pixel circuit, and can also be connected to the first frame power line 33 in the second display area A2 through the thirty-fourth via V34.

[0181] In some examples, at least one first power line can be integrally formed with the first pad 51 located in the second display area A2. For example, the first pad 51 adjacent to the first multiplexed control transistor M1 can be integrally formed with the first power line VDD(j). The orthographic projection of the first pad 51 onto the substrate can be rectangular. The maximum length of the first pad 51 along the second direction D2 can be greater than the maximum length of the portion of the first power line VDD(j) within the second display area A2 along the second direction D2. The orthographic projection of the first pad 51 onto the substrate can be located on the side of the first multiplexed control transistor M1 away from the second multiplexed control transistor M2. In this example, by setting the first pad, it is beneficial to ensure the anode flatness of the light-emitting elements within the second display area A2.

[0182] In some examples, at least one first power line can be integrally formed with a second pad 52 located in the first display area A1. The orthographic projection of the second pad 52 onto the substrate can be rectangular, such as a square. For example, the first power line VDD(j) can be integrally formed with the second pad 52. The maximum length of the second pad 52 along the second direction D2 can be greater than or equal to the maximum length of the first power line VDD(j) along the second direction D2. In this example, the use of the second pad 52 helps to ensure the anode flatness of the light-emitting elements within the first display area A1.

[0183] In some examples, multiple data lines can extend along a first direction D1 and be arranged along a second direction D2. For example, the first data line DL1 can extend along the first direction D1 and from the first display area A1 to the second display area A2; the first data line DL1 in the first display area A1 can be connected to the seventh connection electrode 307 through the thirty-third via V33 to achieve connection with the fourth transistor of the pixel circuit; the first data line DL1 can also be connected to the second electrode M13 of the first multiplexing control transistor M1 in the second display area A2 through the thirty-fifth via V35.

[0184] In some examples, such as Figure 16C and Figure 16D As shown, multiple connecting lines (including, for example, second connecting line 401, third connecting line 403, first connecting line 402, 404 and 405) can extend from the first corner display area A22a to the third frame area, wherein the first connecting line connected to the gate line can realize the electrical connection between the gate driving circuit located in the third frame area. The second connecting line 401 can be connected to the eleventh connecting electrode 311 through the thirty-sixth via V36 to achieve electrical connection with the third initial signal line INIT3(m+1); the first connecting line 402 can be connected to the twelfth connecting electrode 312 through the thirty-seventh via V37 to achieve electrical connection with the light emission control line EML(m+1); the third connecting line 403 can be connected to the thirteenth connecting electrode 313 through the thirty-eighth via V38 to achieve electrical connection with the eighth connecting electrode connected to the (m+1)th row pixel circuit, thereby providing a first voltage signal along the second direction D2; the first connecting line 404 can be connected to the fourteenth connecting electrode 314 through the thirty-ninth via V39 to achieve electrical connection with the second scan line GL2(m+1) and the second scan auxiliary line GL2b(m+1); the first connecting line 405 can be connected to the fifteenth connecting electrode 315 through the fortieth via V40 to achieve electrical connection with the first reset control line RST1(m).

[0185] In some examples, within the first corner display area A22a, the orthographic projections of multiple connecting lines onto the substrate overlap with the orthographic projections of multiple multiplexed control transistors of the multiplexed circuit onto the substrate. This can help increase the flatness of the anode of the subsequently fabricated light-emitting element.

[0186] (11) Forming a seventh insulating layer. In some examples, a seventh insulating film is coated on the substrate on which the aforementioned pattern is formed, and the seventh insulating film is patterned by a patterning process to form a seventh insulating layer. In some examples, the seventh insulating layer may also be referred to as a second planarization layer.

[0187] Figure 17 for Figure 5A schematic diagram of the display substrate after the seventh insulating layer has been formed. In some examples, such as... Figure 17 As shown, the seventh insulating layer of the display substrate may have multiple vias, such as the forty-first via V41 to the forty-third via V43. The seventh insulating layer within the forty-first via V41 to the forty-third via V43 may be removed, exposing a portion of the surface of the fifth conductive layer.

[0188] At this point, the circuit structure layer of the display substrate is complete. The circuit structure layer in this example may include: a first semiconductor layer, a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, a third insulating layer, a second semiconductor layer, a fourth insulating layer, a third conductive layer, a fifth insulating layer, a fourth conductive layer, a sixth insulating layer, a fifth conductive layer, and a seventh insulating layer, sequentially disposed on the substrate.

[0189] In some examples, the first, second, third, fourth, and fifth conductive layers can be made of metallic materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or alloys of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). These can be single-layer structures or multi-layer composite structures, such as Mo / Cu / Mo. The first, second, third, fourth, and fifth insulating layers can be made of any one or more of silicon oxide (SiOx, x>0), silicon nitride (SiNy, y>0), and silicon oxynitride (SiON). These can be single-layer, multi-layer, or composite layers. The sixth and seventh insulating layers can be made of organic materials such as polyimide, acrylic, or polyethylene terephthalate. However, this embodiment is not limited in this regard.

[0190] (12) The light-emitting structure layer and the encapsulation structure layer are formed in sequence.

[0191] In some examples, an anode thin film is deposited on a substrate forming the aforementioned pattern, and the anode thin film is patterned using a patterning process to form an anode layer. Subsequently, a pixel definition film is coated, and a pixel definition layer is formed using a masking, exposure, and development process. The pixel definition layer may have multiple pixel openings exposing the anode layer. A light-emitting functional layer is formed within the aforementioned pixel openings, and the light-emitting functional layer is connected to the anode layer. For example, the pixel definition layer may be made of organic materials such as polyimide, acrylic, or polyethylene terephthalate. Subsequently, a cathode thin film is deposited, and the cathode thin film is patterned using a patterning process to form a cathode layer, and the cathode of the light-emitting element is connected to the light-emitting functional layer. Subsequently, an encapsulation layer is formed on the cathode layer, and the encapsulation layer may include a stacked structure of inorganic / organic / inorganic materials.

[0192] Figure 18A for Figure 5A schematic diagram of the display substrate after the anode layer has been formed. Figure 18B for Figure 18A A schematic diagram of the anode layer and the fifth conductive layer. Figure 18C for Figure 7 A schematic diagram of a display substrate after the anode layer has been formed. In some examples, such as... Figures 18A to 18C As shown, the anode layer of the display substrate may include: anodes of multiple light-emitting elements (e.g., anodes EL11 of the first light-emitting element EL1, anode EL21 of the second light-emitting element EL2, and anode EL31 of the third light-emitting element EL3), and multiple second transition electrodes (e.g., second transition electrodes 420a, 420b, and 420c).

[0193] In some examples, the second adapter electrode 420a is integrally formed with the anode EL11 of the first light-emitting element EL1. The second adapter electrode 420b is integrally formed with the anode EL21 of the second light-emitting element EL2. The second adapter electrodes 420a and 420b can extend along the first direction D1. The second adapter electrode 420a can be connected to the first adapter electrode 410a, and the second adapter electrode 420b can be connected to the first adapter electrode 410b. The second adapter electrode 420c can be integrally formed with the anode EL31 of the third light-emitting element EL3. This example, by setting the second adapter electrode, can ensure the electrical connection between the pixel circuit and the light-emitting element, and can also achieve a staggered arrangement of the pixel circuit and the connected light-emitting element along the first direction D1.

[0194] In some examples, such as Figure 18B As shown, within the second display area A2, the orthographic projection of the anode EL21 of the second light-emitting element EL2 onto the substrate and the orthographic projection of the first pad 51 onto the substrate can partially overlap to ensure the flatness of the anode of the second light-emitting element EL2.

[0195] In some examples, such as Figure 18B As shown, within the second display area A2, the orthographic projection of the anode EL31 of the third light-emitting element EL3 onto the substrate can have a first edge EL31-1 and a second edge EL31-2 extending along the first direction D1. The orthographic projection of the first edge EL31-1 onto the substrate can overlap with the orthographic projection of the first power line VDD(j+1) onto the substrate, for example, it can be located within the orthographic projection range of the first power line VDD(j+1) onto the substrate; similarly, the orthographic projection of the second edge EL31-2 onto the substrate can overlap with the orthographic projection of the first power line VDD(j+2) onto the substrate, for example, it can be located within the orthographic projection range of the first power line VDD(j+2) onto the substrate. This example ensures the flatness of the anode of the third light-emitting element EL3, which helps prevent defects such as color shift.

[0196] In some examples, the encapsulation structure layer may include a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer stacked together. The first and third encapsulation layers may be made of inorganic materials, while the second encapsulation layer may be made of organic materials. The second encapsulation layer may be disposed between the first and third encapsulation layers, forming an inorganic / organic / inorganic material stacked structure, which can ensure that external moisture cannot enter the light-emitting structure layer. In some possible implementations, the display substrate may also include other film layers, such as a touch structure layer, a color filter layer, etc., which are not limited in this embodiment.

[0197] The structure and fabrication process of the display substrate in this embodiment are merely illustrative. In some exemplary embodiments, the corresponding structure and patterning processes can be modified and added or reduced according to actual needs. The fabrication process of this exemplary embodiment can be implemented using currently mature fabrication equipment, is well compatible with existing fabrication processes, is simple to implement, easy to carry out, has high production efficiency, low production cost, and high yield.

[0198] The display substrate provided in this embodiment, by staggering the pixel circuits and light-emitting elements along a first direction, allows the multiplexing circuit to be positioned below some of the light-emitting elements. This reduces the space occupied by the multiplexing circuit in the bezel area, facilitating a narrower bezel design. For example, the reduced length of the first bezel area along the first direction D1 can be greater than or equal to the maximum length of a row of pixel circuits along the first direction D1.

[0199] Figure 19 This is a schematic diagram of a display device according to at least one embodiment of the present disclosure. In some examples, such as... Figure 19 As shown, the display device 91 may include a display substrate 910. The display substrate 910 may be an OLED display substrate. The display device 91 may be any product or component with display function, such as an OLED display device, mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator. However, this embodiment is not limited to this.

[0200] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0201] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application.

Claims

1. A display substrate, characterized in that, include: The substrate includes a display area and a first border area located on at least one side of the display area. The display area includes a first display area and a second display area disposed along a first direction, wherein the second display area is located between the first display area and the first border area along the first direction. A circuit structure layer is disposed on the substrate, the circuit structure layer comprising: a plurality of pixel circuits located in the first display area, a plurality of multiplexed circuits located in the second display area, and a plurality of data lines located in the display area; the plurality of data lines are connected to the plurality of pixel circuits and the plurality of multiplexed circuits; A light-emitting structure layer is disposed on the side of the circuit structure layer away from the substrate. The light-emitting structure layer includes: a plurality of light-emitting elements located in the display area; at least one pixel circuit of the plurality of pixel circuits is connected to at least one light-emitting element of the plurality of light-emitting elements, and the at least one light-emitting element and the connected pixel circuit are offset along the first direction in the orthographic projection of the at least one light-emitting element and the connected pixel circuit on the substrate; the orthographic projection of the plurality of multiplexing circuits on the substrate at least partially overlaps with the orthographic projection of the plurality of light-emitting elements located in the second display area on the substrate.

2. The display substrate according to claim 1, characterized in that, At least one of the plurality of light-emitting elements has its orthographic projection on the substrate located on the side of the orthographic projection of the connected pixel circuit on the substrate closer to the first border region.

3. The display substrate according to claim 1, characterized in that, The light-emitting area of ​​at least one of the plurality of light-emitting elements does not overlap with the orthographic projection of the connected pixel circuit onto the substrate.

4. The display substrate according to claim 1, characterized in that, The plurality of light-emitting elements includes: a plurality of light-emitting element groups, wherein the plurality of light-emitting element groups are arranged in an array along the first direction and the second direction, and the second direction intersects the first direction; At least one of the plurality of light-emitting element groups includes: a first light-emitting element emitting a first color light, a second light-emitting element emitting a second color light, and a third light-emitting element emitting a third color light; Within a single light-emitting element group, the first light-emitting element and the second light-emitting element are aligned along the first direction and located on the same side of the third light-emitting element along the second direction.

5. The display substrate according to claim 1, characterized in that, The at least one light-emitting element includes: a first electrode, a light-emitting functional layer, and a second electrode arranged sequentially along a direction away from the substrate; the first electrode is connected to the corresponding pixel circuit through a first adapter electrode; the first adapter electrode and the plurality of data lines are in the same layer structure, and the first adapter electrode extends along the first direction.

6. The display substrate according to claim 1, characterized in that, The circuit structure layer further includes: multiple first power lines located in the display area; the multiple first power lines extend along the first direction and are arranged along the second direction, the second direction intersecting the first direction; the multiple first power lines are connected to the multiple pixel circuits, and the multiple first power lines and the multiple data lines are in the same layer structure.

7. The display substrate according to claim 6, characterized in that, The circuit structure layer further includes: a first frame power line located in the second display area, the first frame power line being located along the first direction on the side of the plurality of multiplexed circuits close to the plurality of pixel circuits; the first frame power line extending along the second direction and connected to the plurality of first power lines.

8. The display substrate according to claim 7, characterized in that, The first frame power line is located on the side of the plurality of first power lines closest to the substrate.

9. The display substrate according to claim 6, characterized in that, The circuit structure layer further includes: a plurality of first pads located in the second display area, wherein the first pads and the first power line are integrally formed; The at least one light-emitting element includes: a first electrode, a light-emitting functional layer, and a second electrode arranged sequentially along a direction away from the substrate; the orthographic projection of the first electrode of the at least one light-emitting element onto the substrate at least partially overlaps with the orthographic projection of the first pad onto the substrate.

10. The display substrate according to claim 6, characterized in that, The at least one light-emitting element includes: a first electrode, a light-emitting functional layer, and a second electrode sequentially disposed along a direction away from the substrate; In the second display area, the first electrode of the at least one light-emitting element overlaps with the orthographic projection of the two first power lines on the substrate, and the orthographic projection of the edge of the first electrode extending along the first direction on the substrate at least partially overlaps with the orthographic projection of the two first power lines on the substrate.

11. The display substrate according to claim 1, characterized in that, The first border region includes: a first sub-border region extending along a second direction, and a first corner region and a second corner region located at both ends of the first sub-border region along the second direction; the second direction intersects the first direction; The second display area includes: a sub-display area extending along the second direction, and a first corner display area and a second corner display area located on both sides of the sub-display area along the second direction; the first corner display area is connected to the first corner area and the first display area, and the second corner display area is connected to the second corner area and the first display area.

12. The display substrate according to claim 11, characterized in that, The circuit structure layer further includes: multiple first signal lines connected to the multiple pixel circuits and extending along the second direction, and multiple connecting lines connected to the multiple first signal lines. The orthographic projection of the multiple multiplexed circuits located in the first corner display area and the second corner display area on the substrate overlaps with the orthographic projection of at least one of the multiple connecting lines on the substrate.

13. The display substrate according to claim 11, characterized in that, The circuit structure layer also includes: multiple multiplexed data lines; At least one of the plurality of multiplexing circuits includes: nine multiplexing control transistors, the gates of the nine multiplexing control transistors being connected to nine different multiplexing control lines, the first terminals of the nine multiplexing control transistors being connected to the same multiplexing data line, and the second terminals of the nine multiplexing control transistors being connected to different data lines among the plurality of data lines; In the sub-display area, the nine multiplexing control transistors of the at least one multiplexing circuit are arranged sequentially along the second direction.

14. The display substrate according to claim 1, characterized in that, At least one pixel circuit in the plurality of pixel circuits includes: a driving transistor, a compensation transistor, and a data writing transistor; The gate of the driving transistor is connected to the second terminal of the compensation transistor, the first terminal of the driving transistor is connected to the second terminal of the data writing transistor, and the second terminal of the driving transistor is connected to the first terminal of the compensation transistor. The first terminal of the data writing transistor is connected to the data line, the gate of the data writing transistor is connected to the first scan line, and the gate of the compensation transistor is connected to the second scan line. The compensation transistor has a different transistor type than the driving transistor and the data writing transistor.

15. The display substrate according to claim 14, characterized in that, The at least one pixel circuit further includes: a first reset transistor, a second reset transistor, and a third reset transistor; The gate of the first reset transistor is connected to the first reset control line, the first terminal of the first reset transistor is connected to the first initial signal line, and the second terminal of the first reset transistor is connected to the second terminal of the driving transistor. The gate of the second reset transistor is connected to the second reset control line, the first electrode of the second reset transistor is connected to the second initial signal line, and the second electrode of the second reset transistor is connected to the first electrode of the light-emitting element. The gate of the third reset transistor is connected to the second reset control line, the first terminal of the third reset transistor is connected to the third initial signal line, and the second terminal of the third reset transistor is connected to the first terminal of the driving transistor. The first reset control line and the second reset control line are in the same layer, while the first initial signal line, the second initial signal line and the third initial signal line are located in different conductive layers.

16. The display substrate according to claim 14, characterized in that, The at least one pixel circuit further includes: a first light-emitting control transistor and a second light-emitting control transistor; the gate of the first light-emitting control transistor and the gate of the second light-emitting control transistor are both connected to the light-emitting control line, the first electrode of the first light-emitting control transistor is connected to the first power supply line, the second electrode of the first light-emitting control transistor is connected to the first electrode of the driving transistor, the first electrode of the second light-emitting control transistor is connected to the second electrode of the driving transistor, and the second electrode of the second light-emitting control transistor is connected to the first electrode of the light-emitting element.

17. A display device, characterized in that, Includes the display substrate as described in any one of claims 1 to 16.

Images