Array substrate and display device

Abstract

An array substrate includes a first respective data line configured to provide a data signal to a first electrode of a data write transistor located in a first row of a same column of pixel driving circuits and adjacent two rows of pixel driving circuits, and a second respective data line configured to provide a data signal to a second electrode of a data write transistor located in a second row of the same column of pixel driving circuits and adjacent two rows of pixel driving circuits; and a second corresponding data line is configured to provide a data signal to a first electrode of a data write transistor located in the same column and a second row of the adjacent two rows of pixel driving circuits. The first respective data line and the second respective data line extend at least partially in the same column. The first respective data lines are electrically isolated from the first electrodes of the data write transistors located in the same column and the second row. The second respective data lines are electrically isolated from the first electrodes of the data write transistors located in the same column and the first row.

Description

Technical Field

[0001] The present invention relates to display technology, and in particular to an array substrate and a display device. Background Art

[0002] Organic light emitting diode (OLED) display is one of the hot spots in the field of flat panel display research today. Unlike thin film transistor-liquid crystal display (TFT-LCD) that uses a stable voltage to control brightness, OLED is driven by a driving current that needs to be kept constant to control brightness. The OLED display panel includes a plurality of pixel units, which are configured with pixel driving circuits arranged in multiple rows and columns. Each pixel driving circuit includes a driving transistor having a gate terminal connected to a gate line for each row and a drain terminal connected to a data line for each column. When the row in which the pixel unit is selected is turned on, the switching transistor connected to the driving transistor is turned on, and the data voltage is applied to the driving transistor from the data line via the switching transistor, so that the driving transistor outputs a current corresponding to the data voltage to the OLED device. The OLED device is driven to emit light of corresponding brightness. Summary of the invention

[0003] In one aspect, the present disclosure provides an array substrate, comprising a plurality of data lines; wherein the plurality of data lines comprise a first corresponding data line and a second corresponding data line, the first corresponding data line being configured to provide a data signal to a first electrode of a data write transistor located in a first row of a pixel drive circuit in the same column and two adjacent rows of pixel drive circuits; and the second corresponding data line being configured to provide a data signal to a first electrode of a data write transistor located in a second row of a pixel drive circuit in the same column and two adjacent rows of pixel drive circuits; the first corresponding data line and the second corresponding data line at least partially extend in the same column; the first corresponding data line is electrically isolated from the first electrode of the data write transistor located in the second row of the pixel drive circuit in the same column and two adjacent rows of pixel drive circuits; and the second corresponding data line is electrically isolated from the first electrode of the data write transistor located in the first row of the pixel drive circuit in the same column and two adjacent rows of pixel drive circuits.

[0004] Optionally, the orthographic projection of the same pixel driving circuit on the base substrate partially overlaps with the orthographic projection of the first corresponding data line on the base substrate, and partially overlaps with the orthographic projection of the second corresponding data line on the base substrate.

[0005] Optionally, the orthographic projection of the first corresponding data line on the base substrate partially overlaps with the first electrode of the driving transistor on the base substrate; and the orthographic projection of the second corresponding data line on the base substrate partially overlaps with the second electrode of the driving transistor on the base substrate.

[0006] Optionally, the array substrate also includes a plurality of first data signal connection pads and a plurality of second data signal connection pads located in the same column of pixel driving circuits; each of the plurality of first data signal connection pads connects the first corresponding data line to the first electrode of the data writing transistor in the first corresponding pixel driving circuit in the first row of the two adjacent rows of pixel driving circuits; each of the plurality of second data signal connection pads connects the second corresponding data line to the first electrode of the data writing transistor in the second corresponding pixel driving circuit in the second row of the two adjacent rows of pixel driving circuits; the plurality of first data signal connection pads do not exist in the first row of the two adjacent rows of pixel driving circuits; and the plurality of second data signal connection pads do not exist in the second row of the two adjacent rows of pixel driving circuits.

[0007] Optionally, a ratio of a total number of data lines to a total number of columns of pixel driving circuits in the array substrate is in a range of 1.6:1 to 2.4:1.

[0008] Optionally, the array substrate further includes a plurality of third reset signal lines and a plurality of fourth reset signal lines; wherein a first adjacent third reset signal line among the plurality of third reset signal lines is configured to provide a reset signal to a first electrode of a first reset transistor in two adjacent pixel driving circuits in a first row and a first column and a second column in two adjacent pixel driving circuits; a first adjacent fourth reset signal line among the plurality of fourth reset signal lines is configured to provide a reset signal to a first electrode of a second reset transistor in two adjacent pixel driving circuits in a first row and a first column and a second column in two adjacent pixel driving circuits; a second adjacent third reset signal line among the plurality of third reset signal lines is configured to provide a reset signal to a first reset transistor in two adjacent pixel driving circuits in a third column and a fourth column in two adjacent pixel driving circuits in the first row and a second column in two adjacent pixel driving circuits. a first electrode of a transistor; a second adjacent fourth reset signal line among the plurality of fourth reset signal lines is configured to provide a reset signal to the first electrode of the second reset transistor in the first row of the pixel driving circuits and the third column and the fourth column of the pixel driving circuits in the adjacent two columns; the second adjacent third reset signal line among the plurality of third reset signal lines is configured to provide a reset signal to the first electrode of the first reset transistor in the second row of the pixel driving circuits and the second column and the third column of the pixel driving circuits in the adjacent two columns; the first adjacent fourth reset signal line among the plurality of fourth reset signal lines is configured to provide a reset signal to the first electrode of the second reset transistor in the second row of the pixel driving circuits and the second column and the third column of the pixel driving circuits in the adjacent two columns.

[0009] Optionally, the first adjacent third reset signal line extends at least partially in the first column of the two adjacent columns of pixel driving circuits; the first adjacent fourth reset signal line extends at least partially in the second column of the two adjacent columns of pixel driving circuits; the second adjacent third reset signal line extends at least partially in the third column of the two adjacent columns of pixel driving circuits; the second adjacent fourth reset signal line extends at least partially in the fourth column of the two adjacent columns of pixel driving circuits; the first column, the second column, the third column, and the fourth column are arranged in sequence; and the first row and the second row are arranged in sequence.

[0010] Optionally, the array substrate further comprises a pixel driving circuit arranged in K columns and M rows, K and M are positive integers; the array substrate comprises K reset signal lines configured to provide a reset signal to a reset transistor in the array substrate; the K columns comprise a (4k-3)th column among the K columns, a (4k-2)th column among the K columns, a (4k-1)th column among the K columns, and a 4kth column among the K columns, k is a positive integer, 1≤k≤(K / 4); The M rows include the (2m-1)th row among the M rows and the 2mth row among the M rows, m is a positive integer, 1≤m≤(M / 2); the K reset signal lines include a plurality of third reset signal lines located in the (4k-3)th column among the K columns or in the (4k-1)th column among the K columns; and a plurality of fourth reset signal lines located in the (4k-2)th column among the K columns or in the (4k)th column among the K columns.

[0011] Optionally, the K reset signal lines include: a first adjacent third reset signal line among the plurality of third reset signal lines, which is configured to provide a reset signal to a first electrode of a first reset transistor in two adjacent pixel drive circuits in the pixel drive circuits in the (2m-1)th row and the pixel drive circuits in the (4k-3)th column and the (4k-2)th column, respectively; a first adjacent fourth reset signal line among the plurality of fourth reset signal lines, which is configured to provide a reset signal to a first electrode of a second reset transistor in two adjacent pixel drive circuits in the pixel drive circuits in the (2m-1)th row and the pixel drive circuits in the (4k-3)th column and the (4k-2)th column, respectively; a second adjacent third reset signal line among the plurality of third reset signal lines, which is configured to provide a reset signal to a first electrode of a second reset transistor in two adjacent pixel drive circuits in the pixel drive circuits in the (2m-1)th row and the pixel drive circuits in the (4k-1)th column and the (4k-2)th column, respectively. circuit; and a second adjacent fourth reset signal line among the plurality of fourth reset signal lines, which is configured to provide a reset signal to the first electrode of the second reset transistor in the pixel driving circuit located in the (2m-1)th row and the adjacent two pixel driving circuits in the pixel driving circuits in the (4k-1)th column and the (4k)th column, respectively; wherein the second adjacent third reset signal line is configured to provide a reset signal to the first electrode of the first reset transistor in the pixel driving circuit located in the (2m)th row and the adjacent two pixel driving circuits in the pixel driving circuits in the (4k-2)th column and the (4k-1)th column, respectively; and the first adjacent fourth reset signal line is configured to provide a reset signal to the first electrode of the second reset transistor in the pixel driving circuit located in the (2m)th row and the adjacent two pixel driving circuits in the pixel driving circuits in the (4k-2)th column and the (4k-1)th column, respectively.

[0012] Optionally, the first adjacent third reset signal line extends at least partially in the pixel driving circuit of the (4k-3)th column; the first adjacent fourth reset signal line extends at least partially in the pixel driving circuit of the (4k-2)th column; the second adjacent third reset signal line extends at least partially in the pixel driving circuit of the (4k-1)th column; and the second adjacent fourth reset signal line extends at least partially in the pixel driving circuit of the (4k)th column.

[0013] Optionally, the multiple third voltage supply lines do not exist in the (4k-2)th column and the (4k)th column; the multiple fourth voltage supply lines do not exist in the (4k-3)th column and the (4k-1)th column; the multiple third voltage supply lines exist in the (4k-3)th column or the (4k-1)th column; and the multiple fourth voltage supply lines exist in the (4k-2)th column or the (4k)th column.

[0014] Optionally, at least one corresponding layer of the pixel driving circuit located between the (4k-3)th column and the (4k-2)th column in the same row or multiple rows and at least one corresponding layer of the pixel driving circuit located between the (4k-1)th column and the (4k)th column have substantial mirror symmetry relative to each other.

[0015] Optionally, the first electrodes of the first reset transistors in the two adjacent pixel driving circuits located in the (2m-1)th row and the (4k-3)th column and the (4k-2)th column are respectively part of the first overall structure; the first electrodes of the second reset transistors in the two adjacent pixel driving circuits located in the (2m-1)th row and the (4k-3)th column and the (4k-2)th column are respectively part of the first overall structure; the first electrodes of the first reset transistors in the two adjacent pixel driving circuits located in the (2m-1)th row and the (4k-1)th column and the (4k-2)th column are respectively part of the second overall structure; -1) row R(2m-1) and the (4k-1)th column C(4k-1) and the (4k)th column C(4k) respectively form a part of the second overall structure; the first electrodes of the first reset transistors in the two adjacent pixel driving circuits located in the (2m)th row and the (4k-2)th column and the (4k-1)th column are respectively form a part of the third overall structure; and the first electrodes of the second reset transistors in the two adjacent pixel driving circuits located in the (2m)th row and the (4k-2)th column and the (4k-1)th column are respectively form a part of the third overall structure.

[0016] Optionally, the active layer, at least a portion of the first electrode, and at least a portion of the second electrode of the transistors in the two adjacent pixel driving circuits located in the (2m-1)th row and the (4k-3)th column and the (4k-2)th column are respectively part of the first overall structure; the active layer, at least a portion of the first electrode, and at least a portion of the second electrode of the transistors in the two adjacent pixel driving circuits located in the (2m-1)th row and the (4k-1)th column and the (4k)th column are respectively part of the second overall structure; and the active layer, at least a portion of the first electrode, and at least a portion of the second electrode of the transistors in the two adjacent pixel driving circuits located in the (2m)th row and the (4k-2)th column and the (4k-1)th column are respectively part of the third overall structure.

[0017] Optionally, the corresponding components of the first reset transistor in the two adjacent pixel driving circuits located in the same row and the (4k-3)th column and the (4k-2)th column have basic mirror symmetry; the corresponding components of the first reset transistor in the two adjacent pixel driving circuits located in the same row and the (4k-2)th column and the (4k-1)th column have basic mirror symmetry; the corresponding components of the first reset transistor in the two adjacent pixel driving circuits located in the same row and the (4k-1)th column and the (4k)th column have basic mirror symmetry; and the corresponding components of the second reset transistor in the two adjacent pixel driving circuits located in the same row and the (4k-2)th column and the (4k-1)th column have basic mirror symmetry.

[0018] Optionally, the corresponding components of the sixth transistor in the two adjacent pixel driving circuits located in the same row and the (4k-3)th column and the (4k-2)th column do not have mirror symmetry; and the corresponding components of the sixth transistor in the two adjacent pixel driving circuits located in the same row and the (4k-1)th column and the (4k)th column do not have mirror symmetry.

[0019] Optionally, the array substrate also includes a first reset signal network and a second reset signal network; wherein the first reset signal network includes a plurality of first reset signal lines and a plurality of third reset signal lines interconnected with each other; the second reset signal network includes a plurality of second reset signal lines and a plurality of fourth reset signal lines interconnected with each other; each first reset signal line among the plurality of first reset signal lines is connected to one or more third reset signal lines among the plurality of third reset signal lines; each third reset signal line among the plurality of third reset signal lines is connected to one or more first reset signal lines among the plurality of first reset signal lines; each second reset signal line among the plurality of second reset signal lines is connected to one or more fourth reset signal lines among the plurality of fourth reset signal lines; and each fourth reset signal line among the plurality of fourth reset signal lines is connected to one or more second reset signal lines among the plurality of second reset signal lines.

[0020] Optionally, the array substrate further includes a pixel driving circuit arranged in K columns and M rows, where K and M are positive integers; the K columns include the (4k-3)th column among the K columns, the (4k-2)th column among the K columns, the (4k-1)th column among the K columns, and the 4kth column among the K columns, k is a positive integer, 1≤k≤(K / 4); the M rows include the (2m-1)th row among the M rows and the 2mth row among the M rows, m is a positive integer, 1≤m≤(M / 2); the multiple third reset signal lines do not exist in the (4k-2)th column and the (4k)th column; the multiple fourth reset signal lines do not exist in the (4k-3)th column and the (4k-1)th column; the multiple first reset signal lines do not exist in the (2m)th row; and the multiple second reset signal lines do not exist in the (2m-1)th row.

[0021] Optionally, each of the multiple first reset signal lines located in the (2m-1)th row is connected to one or more third reset signal lines among the multiple third reset signal lines located in the (4k-3)th column or the (4k-1)th column; each of the multiple third reset signal lines located in the (4k-3)th column or the (4k-1)th column is connected to one or more first reset signal lines among the multiple first reset signal lines located in the (2m-1)th row; each of the multiple second reset signal lines located in the (2m)th row is connected to one or more fourth reset signal lines among the multiple fourth reset signal lines located in the (4k-2)th column or the (4k)th column; and each of the multiple fourth reset signal lines located in the (4k-2)th column or the (4k)th column is connected to one or more second reset signal lines among the multiple second reset signal lines located in the (2m)th row.

[0022] In another aspect, the present disclosure provides a display device including the array substrate and one or more integrated circuits connected to the array substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] According to various disclosed embodiments, the following drawings are examples only for illustration purposes and are not intended to limit the scope of the present invention.

[0024] Figure 1 is a plan view of an array substrate according to some embodiments of the present disclosure.

[0025] Figure 2A is a circuit diagram showing the structure of a pixel driving circuit in some embodiments according to the present disclosure.

[0026] Figure 2B is a circuit diagram showing the structure of a pixel driving circuit in some embodiments according to the present disclosure.

[0027] Figure 2C is a timing diagram illustrating the operation of a pixel driving circuit in some embodiments according to the present disclosure.

[0028] Figure 3A is a schematic diagram showing the structure of a portion of an array substrate in some embodiments of the present disclosure.

[0029] Figure 3B It is shown Figure 3A Schematic diagram of the arrangement of multiple pixel driving circuits in a portion of an array substrate shown in FIG.

[0030] Figure 3C It is shown Figure 3ASchematic diagram of the structure of a semiconductor material layer in a portion of an array substrate shown in FIG.

[0031] Figure 3D It is shown Figure 3A A schematic diagram of the structure of the first conductive layer in a portion of an array substrate is shown in FIG.

[0032] Figure 3E It is shown Figure 3A A schematic diagram of the structure of the second conductive layer in a portion of the array substrate shown in FIG.

[0033] Figure 3F It is shown Figure 3A A schematic diagram of the structure of an interlayer dielectric layer in a portion of an array substrate is shown in FIG.

[0034] Figure 3G It is shown Figure 3A Schematic diagram of the structure of the first signal line layer in a part of the array substrate shown in FIG.

[0035] Figure 3H It is shown Figure 3A Schematic diagram of the structure of the first planarization layer in a portion of the array substrate shown in FIG.

[0036] Fig. 3I It is shown Figure 3A A schematic diagram of the structure of a second signal line layer in a portion of an array substrate is shown in FIG.

[0037] Figure 4A is along Figure 3A Cross-sectional view along line A-A'.

[0038] Figure 4B is along Figure 3A Cross-sectional view along line BB'.

[0039] Figure 4C is along Figure 3A Cross-sectional view along line CC'.

[0040] Figure 4D is along Figure 3A Cross-sectional view along line D-D'.

[0041] Figure 5 It is shown Figure 3A Schematic diagram of the connection between some reset signal lines and corresponding transistors in the array substrate shown in FIG.

[0042] Figure 6 It is shown Figure 3A Schematic diagram of the structure of a semiconductor material layer in a portion of an array substrate shown in FIG.

[0043] Figure 7 It is shown Figure 3A Schematic diagram of the connection between data lines and corresponding transistors in an array substrate shown in FIG.

[0044] Figure 8 is a schematic diagram showing the structures of a first reset signal network and a second reset signal network in an array substrate according to some embodiments of the present disclosure.

[0045] Fig. 9 is a schematic diagram showing the layout of signal lines in a semiconductor material layer and a second conductive layer in a portion of an array substrate in some embodiments of the present disclosure.

[0046] Fig.10 is a schematic diagram showing the structure of an anti-interference block in some embodiments of the present disclosure. DETAILED DESCRIPTION

[0047] The present disclosure will now be described in more detail with reference to the following examples. It should be noted that the following description of some of the embodiments presented herein is for illustration and description purposes only. It is not intended to be exhaustive or limited to the precise form disclosed.

[0048] The present disclosure provides an array substrate and a display device, which substantially overcomes one or more problems caused by the limitations and shortcomings of the prior art. In one aspect, the present disclosure provides an array substrate. In some embodiments, the array substrate includes a plurality of data lines. Optionally, the plurality of data lines include a first corresponding data line and a second corresponding data line, the first corresponding data line being configured to provide a data signal to a first electrode of a data write transistor in a first row of a pixel drive circuit in the same column and two adjacent rows of pixel drive circuits; and the second corresponding data line being configured to provide a data signal to a first electrode of a data write transistor in a second row of a pixel drive circuit in the same column and two adjacent rows of pixel drive circuits. Optionally, the first corresponding data line and the second corresponding data line extend at least partially in the same column. Optionally, the first corresponding data line is electrically isolated from the first electrode of the data write transistor in the second row of the pixel drive circuit in the same column and two adjacent rows of pixel drive circuits. Optionally, the second corresponding data line is electrically isolated from the first electrode of the data write transistor in the first row of the pixel drive circuit in the same column and two adjacent rows of pixel drive circuits.

[0049] Various suitable pixel driving circuits can be used in the array substrate described in the present disclosure. Examples of suitable driving circuits include 3T1C, 2T1C, 4T1C, 4T2C, 5T2C, 6T1C, 7T1C, 7T2C, 8T1C and 8T2C. In some embodiments, each of the plurality of pixel driving circuits is a 7T1C driving circuit. Various suitable light-emitting elements can be used in the array substrate described in the present disclosure. Examples of suitable light-emitting elements include organic light-emitting diodes, quantum dot light-emitting diodes and micro light-emitting diodes. Optionally, the light-emitting element is a micro light-emitting diode. Optionally, the light-emitting element is an organic light-emitting diode including an organic light-emitting layer.

[0050] Figure 1 is a plan view of an array substrate in some embodiments of the present disclosure. Figure 1 , the array substrate includes an array of sub-pixels Sp. Each sub-pixel includes an electronic component, for example, a light-emitting element. In one example, the light-emitting element is driven by a corresponding pixel driving circuit PDC. The array substrate includes a plurality of gate lines GL, a plurality of data lines DL, and a plurality of second voltage supply lines Vdd (for example, a plurality of first voltage supply lines and / or a plurality of second voltage supply lines). Each sub-pixel Sp emits light driven by a corresponding pixel driving circuit PDC. In one example, a high voltage signal (for example, a VDD signal) is input to a corresponding pixel driving circuit PDC connected to an anode of a light-emitting element through a corresponding voltage supply line in a plurality of voltage supply lines Vdd; a low voltage signal (for example, a VSS signal) is input to a cathode of a light-emitting element through a low voltage supply line. The voltage difference between the high voltage signal (for example, a VDD signal) and the low voltage signal (for example, a VSS signal) is a driving voltage ΔV, which drives the light-emitting element to emit light.

[0051] Figure 2A is a circuit diagram showing the structure of a pixel driving circuit in some embodiments of the present disclosure. Figure 2AIn some embodiments, the pixel driving circuit includes a driving transistor Td; a storage capacitor Cst having a first capacitor electrode Ce1 and a second capacitor electrode Ce2; a first transistor T1 having a gate connected to a corresponding reset control signal line rstN of a current stage, a first electrode connected to a corresponding first reset signal line among a plurality of first reset signal lines Vint1, and a second electrode connected to the first capacitor electrode Ce1 of the storage capacitor Cst and the gate of the driving transistor Td; a second transistor T2 having a gate connected to a corresponding gate line among a plurality of gate lines GL, a first electrode connected to a corresponding data line among a plurality of data lines DL, and a second electrode connected to the first electrode of the driving transistor Td; a third transistor T3 having a gate connected to the corresponding gate line, a first electrode connected to the first capacitor electrode Ce1 of the storage capacitor Cst, and the gate of the driving transistor Td, and a second electrode connected to the second electrode of the driving transistor Td; a fourth transistor T4 having a gate connected to a corresponding light emitting control signal line among a plurality of light emitting control signal lines em, a first electrode connected to a corresponding voltage supply line among a plurality of voltage supply lines Vdd, and a second electrode connected to the first electrode of the driving transistor Td and the second electrode of the second transistor T2; a fifth transistor T5 having a gate connected to the corresponding light emitting control signal line, a first electrode connected to the second electrodes of the driving transistor Td and the third transistor T3, and a second electrode connected to the anode of the light emitting element LE; and a sixth transistor T6 having a gate connected to a reset control signal line rst(N+1) of the next stage, a first electrode connected to a second reset signal line among a plurality of second reset signal lines Vint2, and a second electrode connected to the second electrode of the fifth transistor and the anode of the light emitting element LE. The second capacitor electrode Ce2 is connected to the corresponding first voltage supply line and the first electrode of the fourth transistor T4.

[0052] In some embodiments, the pixel driving circuit includes a driving transistor Td, a data writing transistor (e.g., a second transistor T2), a compensation transistor (e.g., a third transistor T3), two light emitting control transistors (e.g., a fourth transistor T4 and a fifth transistor T5), and two reset transistors (e.g., a first transistor T1 and a sixth transistor T6).

[0053] Figure 2B is a circuit diagram showing the structure of a pixel driving circuit in some embodiments of the present disclosure. Figure 2BIn some embodiments, the third transistor T3 is a "dual-gate" transistor and the first transistor T1 is a "dual-gate" transistor. Optionally, in the "dual-gate" first transistor, the active layer of the first transistor crosses the corresponding reset control signal line twice (alternatively, the corresponding reset control signal line crosses the active layer of the first transistor T1 twice). Similarly, in the "dual-gate" third transistor, the active layer of the third transistor T3 crosses the corresponding first gate line of the plurality of first gate lines GL1 twice (alternatively, the corresponding gate line crosses the active layer of the third transistor T3 twice). The gate of the first transistor T1 is Figure 3D In the figure, it is represented as "G1", where the first transistor T1 is a "double-gate" transistor. The gate of the third transistor T3 is Figure 3D In the figure, it is represented as “G3”, where the third transistor T3 is a “dual-gate” transistor.

[0054] The pixel driving circuit also includes a first node N1, a second node N2, a third node N3 and a fourth node N4. The first node N1 is connected to the gate of the driving transistor Td, the first capacitor electrode Ce1 and the first electrode of the third transistor T3. The second node N2 is connected to the second electrode of the fourth transistor T4, the second electrode of the second transistor T2, and the first electrode of the driving transistor Td. The third node N3 is connected to the second electrode of the driving transistor Td, the second electrode of the third transistor T3, and the first electrode of the fifth transistor T5. The fourth node N4 is connected to the second electrode of the fifth transistor T5, the second electrode of the sixth transistor T6 and the anode of the light emitting element LE.

[0055] As used herein, a first electrode or a second electrode refers to one of a first terminal and a second terminal of a transistor, the first terminal and the second terminal being connected to an active layer of the transistor. The direction of the current flowing through the transistor can be configured to be from the first electrode to the second electrode, or from the second electrode to the first electrode. Therefore, depending on the direction of the current flowing through the transistor, in one example, the first electrode is configured to receive an input signal, and the second electrode is configured to output an output signal; in another example, the second electrode is configured to receive an input signal, and the first electrode is configured to output an output signal.

[0056] Figure 2C is a timing diagram showing the operation of the pixel driving circuit in some embodiments according to the present disclosure. FIG. 2A to FIG. 2CDuring one frame of image, the operation of the pixel driving circuit includes a reset sub-stage t1, a data writing sub-stage t2, and a light emitting sub-stage t3. In the initial sub-stage t0, a cut-off reset control signal is provided to the gate of the first transistor T1 through a corresponding reset control signal line among a plurality of reset control signal lines rst to cut off the first transistor T1. In the initial sub-stage t0, a corresponding gate line among a plurality of gate lines GL is provided with a cut-off signal, so that the second transistor T2 and the third transistor T3 are cut off.

[0057] In the reset sub-phase t1, the on-reset control signal is provided to the gate of the first transistor T1 through the corresponding reset control signal line in the plurality of reset control signal lines rst to turn on the first transistor T1; the initialization voltage signal from the corresponding first reset signal line in the plurality of first reset signal lines Vint1 is allowed to be transmitted from the first electrode of the first transistor T1 to the second electrode of the first transistor T1, and then to the first capacitor electrode Ce1 and the gate of the driving transistor Td. The gate of the driving transistor Td is initialized. The second capacitor electrode Ce2 receives a high voltage signal from the corresponding second voltage supply line in the plurality of second voltage supply lines Vdd2. As the voltage difference between the first capacitor electrode Ce1 and the second capacitor electrode Ce2 increases, the first capacitor electrode Ce1 is charged in the reset sub-phase t1. In the reset sub-phase t1, the corresponding gate line in the plurality of gate lines GL is provided with a cut-off signal, so that the second transistor T2 and the third transistor T3 are cut off. The corresponding light emitting control signal line in the plurality of light emitting control signal lines em is provided with a high voltage signal to cut off the fourth transistor T4 and the fifth transistor T5.

[0058] In the data writing sub-phase t2, the gate of the first transistor T1 is again provided with a cut-off reset control signal through the corresponding reset control signal line in the plurality of reset control signal lines rst to cut off the first transistor T1. The corresponding gate line GL in the plurality of gate lines GL is provided with a turn-on signal, so that the second transistor T2 is turned on with the third transistor T3. The second electrode of the driving transistor Td is connected to the second electrode of the third transistor T3. The gate of the driving transistor Td is electrically connected to the first electrode of the third transistor T3. Since the third transistor T3 is turned on in the data writing sub-phase t2, the gate of the driving transistor Td is connected to the second electrode and short-circuited, and only the PN junction between the gate and the first electrode of the driving transistor Td is effective, so that the driving transistor Td is in a diode connection mode. The second transistor T2 is turned on in the data writing sub-phase t2. The data voltage signal transmitted through the corresponding data line in the plurality of data lines DL is received by the first electrode of the second transistor T2 and sequentially transmitted to the first electrode of the driving transistor Td, which is connected to the second electrode of the second transistor T2. The node N2 connected to the first electrode of the driving transistor Td has the voltage level of the data voltage signal. Since only the PN junction between the gate of the driving transistor Td and the first electrode is effective, in the data writing sub-phase t2, the voltage level at the N1 node gradually rises to (Vdata+Vth), where Vdata is the voltage level of the data voltage signal and Vth is the voltage level of the threshold voltage Th of the PN junction. Because the voltage difference between the first capacitor electrode Ce1 and the second capacitor electrode Ce2 is reduced to a relatively small value, the storage capacitor Cst is discharged. The corresponding light emitting control signal line among the plurality of light emitting control signal lines em is provided with a high voltage signal to turn off the fourth transistor T4 and the fifth transistor T5.

[0059] In the data writing sub-phase t2, a turn-on reset control signal is provided to the gate of the sixth transistor T6 through a corresponding reset control signal line in the next adjacent stage among the plurality of reset control signal lines rst to turn on the sixth transistor T6; an initialization voltage signal from a corresponding second reset signal line among the plurality of second reset signal lines Vint2 is allowed to be transferred from the first electrode of the sixth transistor T6 to the second electrode of the sixth transistor T6; and sequentially to the node N4. The anode of the light emitting element LE is initialized.

[0060] In the light-emitting sub-stage t3, a cut-off reset control signal is again provided to the gate of the first transistor T1 through a corresponding reset control signal line among a plurality of reset control signal lines rst to cut off the first transistor T1. A corresponding gate line GL among a plurality of gate lines GL is provided with a cut-off signal, and the second transistor T2 and the third transistor T3 are cut off. A corresponding light-emitting control signal line among a plurality of light-emitting control signal lines em is provided with a low voltage signal to turn on the fourth transistor T4 and the fifth transistor T5. In the light-emitting sub-stage t3, the voltage level at the node N1 is maintained at (Vdata+Vth), and the driving transistor Td is turned on by the voltage level and operates in the saturation region. A path is formed through the fourth transistor T4, the driving transistor Td, and the fifth transistor T5 to the light-emitting element LE. The driving transistor Td generates a driving current for driving the light-emitting element LE to emit light. The voltage level at the node N3 connected to the second electrode of the driving transistor Td is equal to the light-emitting voltage of the light-emitting element LE.

[0061] In some embodiments, the array substrate includes a plurality of sub-pixels. In some embodiments, the plurality of sub-pixels include a corresponding first sub-pixel, a corresponding second sub-pixel, and a corresponding third sub-pixel. Optionally, the corresponding pixel of the array substrate includes a corresponding first sub-pixel, a corresponding second sub-pixel, and a corresponding third sub-pixel. The plurality of sub-pixels in the array substrate are arranged in an array. In one example, the array of the plurality of sub-pixels includes a S1-S2-S3 format repeating array, wherein S1 represents the corresponding first sub-pixel, S2 represents the corresponding second sub-pixel, and S3 represents the corresponding third sub-pixel. In another example, the S1-S2-S3 format is a C1-C2-C3 format, wherein C1 represents the corresponding first sub-pixel of the first color, C2 represents the corresponding second sub-pixel of the second color, and C3 represents the corresponding third sub-pixel of the third color. In another example, the C1-C2-C3 format is an RGB format, wherein the corresponding first sub-pixel is a red sub-pixel, the corresponding second sub-pixel is a green sub-pixel, and the corresponding third sub-pixel is a blue sub-pixel.

[0062] In another example, the array of multiple sub-pixels includes a repeating array of the S1-S2-S3-S4 format, wherein S1 represents the corresponding first sub-pixel, S2 represents the corresponding second sub-pixel, S3 represents the corresponding third sub-pixel, and S4 represents the corresponding fourth sub-pixel. In another example, the S1-S2-S3-S4 format is a C1-C2-C3-C4 format, wherein C1 represents the corresponding first sub-pixel of the first color, C2 represents the corresponding second sub-pixel of the second color, C3 represents the corresponding third sub-pixel of the third color, and C4 represents the corresponding fourth sub-pixel of the fourth color. In another example, the S1-S2-S3-S4 format is a C1-C2-C3-C2' format, wherein C1 represents the corresponding first sub-pixel of the first color, C2 represents the corresponding second sub-pixel of the second color, C3 represents the corresponding third sub-pixel of the third color, and C2' represents the corresponding fourth sub-pixel of the second color. In another example, the C1-C2-C3-C2′ format is an RGBG format, wherein the corresponding first subpixel is a red subpixel, the corresponding second subpixel is a green subpixel, the corresponding third subpixel is a blue subpixel, and the corresponding fourth subpixel is a green subpixel.

[0063] In some embodiments, the minimum repeating unit of the plurality of sub-pixels of the array substrate includes a corresponding first sub-pixel, a corresponding second sub-pixel, and a corresponding third sub-pixel. Optionally, each of the first sub-pixels, the second sub-pixels, and the third sub-pixels includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a driving transistor Td, and a storage capacitor Cst.

[0064] In an alternative embodiment, the minimum repeating unit of the plurality of sub-pixels of the array substrate includes a corresponding first sub-pixel, a corresponding second sub-pixel, a corresponding third sub-pixel, and a corresponding fourth sub-pixel. Optionally, each of the first sub-pixel, the second sub-pixel, the third sub-pixel, and the fourth sub-pixel includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a driving transistor Td, and a storage capacitor Cst.

[0065] Figure 3A is a schematic diagram showing the structure of an array substrate in some embodiments of the present disclosure. Figure 3B It is shown Figure 3A Schematic diagram of the arrangement of multiple pixel driving circuits in the array substrate shown in FIG. Figure 3A and Figure 3B A portion of an array substrate having eight pixel driving circuits (including PDC1 , PDC2 , PDC3 , PDC4 , PDC5 , PDC6 , PDC7 , and PDC8 ) is shown.

[0066] Figure 3C It is shown Figure 3A A schematic diagram of the structure of the semiconductor material layer in the array substrate is shown in FIG. Figure 3D It is shown Figure 3A A schematic diagram of the structure of the first conductive layer in the array substrate is shown in FIG. Figure 3E It is shown Figure 3A A schematic diagram of the structure of the second conductive layer in the array substrate is shown in FIG. Figure 3F It is shown Figure 3A A schematic diagram of the structure of the interlayer dielectric layer in the array substrate is shown in FIG. Figure 3G It is shown Figure 3A A schematic diagram of the structure of the first signal line layer in the array substrate is shown in FIG. Figure 3H It is shown Figure 3A A schematic diagram of the structure of the first planarization layer in the array substrate is shown in FIG. Fig. 3I It is shown Figure 3A A schematic diagram of the structure of the second signal line layer in the array substrate is shown in FIG. Figure 4A is along Figure 3A Cross-sectional view along line A-A'. Figure 4B is along Figure 3A Cross-sectional view along line BB'. Figure 4C is along Figure 3A Cross-sectional view along line C-C'. Figure 4D is along Figure 3A Cross-sectional view along line D-D'.

[0067] refer to FIG. 3A to FIG. 3I and FIG. 4A to FIG. 4D In some embodiments, the display panel includes a base substrate BS, a semiconductor material layer SML located on the base substrate BS, a gate insulating layer GI located on a side of the semiconductor material layer SML away from the base substrate BS, a first conductive layer CT1 located on a side of the gate insulating layer GI away from the semiconductor material layer SML, an insulating layer IN located on a side of the first conductive layer CT1 away from the gate insulating layer GI, a second conductive layer CT2 located on a side of the insulating layer IN away from the first conductive layer CT1, an interlayer dielectric layer ILD located on a side of the second conductive layer CT2 away from the insulating layer IN, a first signal line layer SL1 located on a side of the interlayer dielectric layer ILD away from the second conductive layer CT2, a first planarizing layer PLN1 located on a side of the first signal line layer SL1 away from the interlayer dielectric layer ILD, a second signal line layer SL2 located on a side of the first planarizing layer PLN1 away from the first signal line layer SL1, and a second planarizing layer PLN2 located on a side of the second signal line layer SL2 away from the first planarizing layer PLN1.

[0068] Reference Figure 2A , Figure 2B , Figure 3A and Figure 3C, each pixel driving circuit is marked with a number, and the number indicates the area corresponding to multiple transistors (including a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6 and a driving transistor Td) in each pixel driving circuit. Each pixel driving circuit is also marked with a number, and the number indicates the component of each of the multiple transistors in the pixel driving circuit. For example, the first transistor T1 includes an active layer ACT1, a first electrode S1 and a second electrode D1. The second transistor T2 includes an active layer ACT2, a first electrode S2 and a second electrode D2. The third transistor T3 includes an active layer ACT3, a first electrode S3 and a second electrode D3. The fourth transistor T4 includes an active layer ACT4, a first electrode S4 and a second electrode D4. The fifth transistor T5 includes an active layer ACT5, a first electrode S5 and a second electrode D5. The sixth transistor T6 includes an active layer ACT6, a first electrode S6 and a second electrode D6. The driving transistor Td includes an active layer ACTd, a first electrode Sd and a second electrode Dd. In one example, the active layers (ACT1, ACT2, ACT3, ACT4, ACT5, ACT6, and ACTd) of the transistors (T1, T2, T3, T4, T5, T6, and Td) in each pixel driving circuit are part of the overall structure. In another example, the active layers (ACT1, ACT2, ACT3, ACT4, ACT5, ACT6, and ACTd) of the transistors (T1, T2, T3, T4, T5, T6, and Td) in each pixel driving circuit, the first electrodes (S1, S2, S3, S4, S5, S6, and Sd), and the second electrodes (D1, D2, D3, D4, D5, D6, and Dd) are part of the overall structure. In another example, the active layers (ACT1, ACT2, ACT3, ACT4, ACT5, ACT6, and ACTd) of the transistors (T1, T2, T3, T4, T5, T6, and Td) are located on the same layer. In another example, the active layer (ACT1, ACT2, ACT3, ACT4, ACT5, ACT6 and ACTd), the first electrodes (S1, S2, S3, S4, S5, S6 and Sd) and the second electrodes (D1, D2, D3, D4, D5, D6 and Dd) of the transistors (T1, T2, T3, T4, T5, T6 and Td) are located on the same layer.

[0069] As used herein, an active layer refers to a component of a transistor including at least a portion of a semiconductor material layer, the orthographic projection of which on the substrate substrate overlaps with the orthographic projection of the gate on the substrate substrate. A first electrode refers to a component of a transistor connected to one side of the active layer, and a second electrode refers to a component of a transistor connected to the other side of the active layer. In the context of a dual-gate transistor (e.g., a third transistor T3), an active layer refers to a component of a transistor including a first portion of a semiconductor material layer, a second portion of a semiconductor material layer, and a third portion between the first portion and the second portion, wherein the orthographic projection of the first portion of the semiconductor material layer on the substrate substrate overlaps with the orthographic projection of the first gate on the substrate substrate, and the orthographic projection of the second portion of the semiconductor material layer on the substrate substrate overlaps with the orthographic projection of the second gate on the substrate substrate. In the context of a dual-gate transistor, a first electrode refers to a component of a transistor connected to a side of the first portion away from the third portion, and a second electrode refers to a component of a transistor connected to a side of the second portion away from the third portion.

[0070] Reference Figure 2A , Figure 2B , Figure 3A and Figure 3D In some embodiments, the first conductive layer includes a plurality of first reset control signal lines rst (including a reset control signal line rstN of the current stage and a reset control signal line rst(N+1) of the next stage), a plurality of light emitting control signal lines em, a plurality of gate lines GL, and a first capacitor electrode Ce1 of a storage capacitor Cst. Various suitable electrode materials and various suitable manufacturing methods can be used to manufacture the first conductive layer. For example, the conductive material can be deposited on a substrate and patterned by a plasma enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for manufacturing the first conductive layer include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloy, copper-molybdenum alloy, molybdenum-aluminum alloy, aluminum-chromium alloy, copper-chromium alloy, molybdenum-chromium alloy, copper-molybdenum-aluminum alloy, and the like. Optionally, the plurality of reset control signal lines rst, the plurality of light emitting control signal lines em, the plurality of gate lines GL, and the first capacitor electrode Ce1 of the storage capacitor Cst are located in the same layer.

[0071] As used herein, the term "same layer" refers to the relationship between layers formed simultaneously in the same step. In one example, when a plurality of gate lines GL and a first capacitor electrode Ce1 are formed due to one or more steps of the same patterning process performed in the same material layer, the plurality of gate lines GL and the first capacitor electrode Ce1 are located in the same layer. In another example, by simultaneously performing the steps of forming a plurality of gate lines GL and forming the first capacitor electrode Ce1, a plurality of gate lines GL and the first capacitor electrode Ce1 can be formed in the same layer. The term "same layer" does not always mean that the thickness of the layer or the height of the layer in the cross-sectional view is the same.

[0072] Reference Figure 2A , Figure 2B , Figure 3A and Figure 3E In some embodiments, the second conductive layer includes an anti-interference block IPB, a plurality of first reset signal lines Vint1, a plurality of second reset signal lines Vint2 and a second capacitor electrode Ce2 of a storage capacitor Cst. Various suitable conductive materials and various suitable manufacturing methods can be used to manufacture the second conductive layer. For example, the conductive material can be deposited on a substrate and patterned by a plasma enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for manufacturing the second conductive layer include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloy, copper-molybdenum alloy, molybdenum-aluminum alloy, aluminum-chromium alloy, copper-chromium alloy, molybdenum-chromium alloy, copper-molybdenum-aluminum alloy, etc. Optionally, the anti-interference block IPB, a plurality of first reset signal lines Vint1, a plurality of second reset signal lines Vint2 and a second capacitor electrode Ce2 of the storage capacitor Cst are located in the same layer.

[0073] Figure 3F A via extending through the interlayer dielectric layer ILD is shown in FIG.

[0074] Reference Figure 2A , Figure 2B , Figure 3A and Figure 3G In some embodiments, the first signal line layer includes a node connection line Cln, a plurality of second voltage supply lines Vdd2, an anode connection pad ACP, and a data signal connection pad DCP. In some embodiments, the first signal line layer further includes a plurality of third reset signal lines Vint3 and a plurality of fourth reset signal lines Vint4.

[0075] The node connection line Cln connects the first capacitor electrode Ce1 in each pixel driving circuit with the second electrode of the third transistor T3 and / or the second electrode of the first transistor T1. The data signal connection pad DCP is configured to connect the corresponding data line in the plurality of data lines to the first electrode of the second transistor T2. The anode contact pad ACP connects the fourth node N4 in each sub-pixel with the corresponding anode. The anode contact pad ACP is connected to the second electrodes of the fifth transistor T5 and the sixth transistor T6, and the corresponding anode in each sub-pixel is connected to the anode contact pad ACP.

[0076] A plurality of second voltage supply lines Vdd2 are connected to a plurality of first voltage supply lines in the second signal line layer and to a second capacitor electrode Ce2 of a storage capacitor in the second conductive layer. The second capacitor electrodes in the same row are interconnected as part of an overall structure. A plurality of overall structures of second capacitor electrodes in a plurality of rows, a plurality of second voltage supply lines Vdd2 and a plurality of first voltage supply lines form an interconnected voltage signal network. A corresponding second voltage supply line in a plurality of second voltage supply lines Vdd2 is connected to a first electrode of a fourth transistor T4 and to a second capacitor electrode Ce2 of a storage capacitor Cst. Optionally, a plurality of second voltage supply lines Vdd2 extend in a direction substantially parallel to a second direction DR2; a plurality of first voltage supply lines extend in a direction substantially parallel to a second direction DR2. Optionally, an overall structure including interconnected second capacitor electrodes in the same row extends in a direction substantially parallel to a first direction DR1. As used herein, the term "substantially parallel" refers to an angle in the range of 0 degrees to about 45 degrees, for example, 0 degrees to about 5 degrees, 0 degrees to about 10 degrees, 0 degrees to about 15 degrees, 0 degrees to about 20 degrees, 0 degrees to about 25 degrees, 0 degrees to about 30 degrees.

[0077] Various suitable conductive materials and various suitable manufacturing methods can be used to manufacture the first signal line layer. For example, the conductive material can be deposited on the substrate and patterned by a plasma enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for manufacturing the first signal line layer include, but are not limited to, titanium, aluminum, copper, molybdenum, chromium, aluminum-copper alloy, copper-molybdenum alloy, molybdenum-aluminum alloy, aluminum-chromium alloy, copper-chromium alloy, molybdenum-chromium alloy, copper-molybdenum-aluminum alloy, etc. In some embodiments, the first signal line layer includes a plurality of sublayers stacked together. In one example, the first signal line layer includes a stacked titanium / aluminum / titanium multilayer structure. In another example, the first signal line layer includes a stacked molybdenum / aluminum / molybdenum multilayer structure. Optionally, the node connection line Cln, a plurality of second voltage supply lines Vdd2, a data signal connection pad DCP, an anode connection pad ACP, a plurality of third reset signal lines Vint3, and a plurality of fourth reset signal lines Vint4 are located in the same layer.

[0078] Figure 3H Vias extending through the first planarization layer PLN1 are shown.

[0079] Reference Figure 2A , Figure 2B , Figure 3A and Fig. 3I In some embodiments, the second signal line layer includes a plurality of first voltage supply lines Vdd1 and a plurality of data lines DL. As described above, the plurality of first voltage supply lines Vdd1 are connected to a plurality of second voltage supply lines in the first signal line layer. Each of the plurality of data lines is electrically connected to the first electrode of the second transistor T2 through a data signal connection pad.

[0080] Various suitable conductive materials and various suitable manufacturing methods can be used to manufacture the second signal line layer. For example, the conductive material can be deposited on the substrate and patterned by a plasma enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for manufacturing the second signal line layer include, but are not limited to, titanium, aluminum, copper, molybdenum, chromium, aluminum-copper alloy, copper-molybdenum alloy, molybdenum-aluminum alloy, aluminum-chromium alloy, copper-chromium alloy, molybdenum-chromium alloy, copper-molybdenum-aluminum alloy, etc. In some embodiments, the second signal line layer includes a plurality of sublayers stacked together. In one example, the second signal line layer includes a stacked titanium / aluminum / titanium multilayer structure. In another example, the second signal line layer includes a stacked molybdenum / aluminum / molybdenum multilayer structure. Optionally, a plurality of first voltage supply lines Vdd1 and a plurality of data lines DL are located on the same layer.

[0081] Reference Figure 3A , Figure 3B , Figure 3E and Figure 3G , the array substrate includes two adjacent columns of pixel driving circuits, for example, a first column of pixel driving circuits including PDC1, and a second column of pixel driving circuits including PDC2. In some embodiments, a third reset signal line in a plurality of third reset signal lines Vint3 exists in a first column of pixel driving circuits in two adjacent columns, and the plurality of third reset signal lines Vint3 do not exist in a second column of pixel driving circuits in two adjacent columns. In some embodiments, a fourth reset signal line in a plurality of fourth reset signal lines Vint4 exists in a second column of pixel driving circuits in two adjacent columns, and the plurality of fourth reset signal lines Vint4 do not exist in a first column of pixel driving circuits in two adjacent columns.

[0082] In some embodiments, FIG. 3A to FIG. 3I As shown, each of the plurality of third reset signal lines Vint3 is configured to provide a reset signal to two adjacent pixel drive circuits in the first column and the second column of the pixel drive circuits in the same row and the adjacent two columns of the pixel drive circuits in two adjacent rows. In some embodiments, each of the plurality of fourth reset signal lines Vint4 is configured to provide a reset signal to two adjacent pixel drive circuits in the first column and the second column of the pixel drive circuits in the same row and the adjacent two columns of the pixel drive circuits in two adjacent rows.

[0083] Reference Figure 2A , Figure 2B , FIG. 3A to FIG. 3I as well as Figure 4AIn some embodiments, except for the hole region H where the second capacitor electrode Ce2 does not exist, the orthographic projection of the second capacitor electrode Ce2 on the substrate substrate BS completely covers and is larger than the orthographic projection of the first capacitor electrode Ce1 on the substrate substrate BS. In some embodiments, the first signal line layer includes a node connection line Cln, which is located on a side of the interlayer dielectric layer ILD away from the second capacitor electrode Ce2. The node connection line Cln is located in the same layer as at least one of the plurality of second voltage supply lines Vdd2, the anode connection pad ACP, the data signal connection pad DCP, the plurality of third reset signal lines Vint3, or the plurality of fourth reset signal lines Vint4.

[0084] In some embodiments, the first capacitor electrode Ce1 is located on a side of the gate insulating layer GI away from the base substrate BS. Optionally, the array substrate further includes a first via v1 and a second via v2. The first via v1 is located in the hole area H and extends through the interlayer dielectric layer ILD and the insulating layer IN. The second via v2 extends through the interlayer dielectric layer ILD, the insulating layer IN and the gate insulating layer GI. Optionally, the node connection line Cln is connected to the first capacitor electrode Ce1 through the first via v1, and the node connection line Cln is connected to the semiconductor material layer SML through the second via v2. Optionally, the node connection line Cln is connected to the second electrode D3 of the third transistor and / or the second electrode D1 of the first transistor, as shown in FIG. Figure 4A shown.

[0085] Reference Figure 2A , Figure 2B , FIG. 3A to FIG. 3I as well as Figure 4B In some embodiments, the array substrate further includes a third via hole v3 and a fourth via hole v4. The third via hole v3 extends through the interlayer dielectric layer ILD. The fourth via hole V4 extends through the interlayer dielectric layer ILD, the insulating layer IN, and the gate insulating layer GI. Optionally, a corresponding third reset signal line among the plurality of third reset signal lines Vint3 is connected to a first reset signal line among the plurality of first reset signal lines Vint1 through the third via hole v3. Optionally, a corresponding third reset signal line among the plurality of third reset signal lines Vint3 is connected to the first electrode S1 of the first transistor T1 through the fourth via hole v4.

[0086] Reference Figure 2A , Figure 2B , FIG. 3A to FIG. 3I as well as Figure 4CIn some embodiments, the array substrate further includes a fifth via hole v5 and a sixth via hole v6. The fifth via hole v5 extends through the interlayer dielectric layer ILD. The sixth via hole v6 extends through the interlayer dielectric layer ILD, the insulating layer IN, and the gate insulating layer GI. Optionally, a corresponding fourth reset signal line among the plurality of fourth reset signal lines Vint4 is connected to a second reset signal line among the plurality of second reset signal lines Vint2 through the fifth via hole v5. Optionally, a corresponding fourth reset signal line among the plurality of fourth reset signal lines Vint4 is connected to the first electrode S6 of the sixth transistor T6 through the sixth via hole v6.

[0087] Reference Figure 2A , Figure 2B , FIG. 3A to FIG. 3I as well as Figure 4D In some embodiments, the array substrate further includes a seventh via hole v7 and an eighth via hole v8. The seventh via hole v7 extends through the first planarization layer PLN1. The eighth via hole v8 extends through the interlayer dielectric layer ILD, the insulating layer IN, and the gate insulating layer GI. Optionally, a data line among the plurality of data lines DL is connected to the data signal connection pad DCP through the seventh via hole v7. Optionally, a data line among the plurality of data lines DL is connected to the first electrode S2 of the second transistor T2 through the eighth via hole v8.

[0088] Figure 5 It is shown Figure 3A Schematic diagram of the connection between some reset signal lines and corresponding transistors in the array substrate shown in FIG. Figure 3A , Figure 3C , Figure 3G and Figure 5 , the connection point between the reset signal line and the corresponding transistor is represented by a dotted circle. In some embodiments, the first adjacent third reset signal line Vint3-1 among the plurality of third reset signal lines is configured to provide a reset signal to the first electrode of the first transistor in the first row and the first column and the second column of the adjacent two pixel driving circuits respectively located in the first row of the adjacent two rows of pixel driving circuits and the adjacent two columns of pixel driving circuits; the first adjacent fourth reset signal line Vint4-1 among the plurality of fourth reset signal lines is configured to provide a reset signal to the first electrode of the sixth transistor in the first row and the first column and the second column of the adjacent two pixel driving circuits respectively located in the first row of the adjacent two rows of pixel driving circuits and the adjacent two columns of pixel driving circuits. Optionally, the first adjacent third reset signal line Vint3-1 at least partially extends in the first column of the adjacent two columns of pixel driving circuits (for example, extends through the first column); and the first adjacent fourth reset signal line Vint4-1 at least partially extends in the second column of the adjacent two columns of pixel driving circuits (for example, extends through the second column).

[0089] In some embodiments, the second adjacent third reset signal line Vint3-2 among the plurality of third reset signal lines is configured to provide a reset signal to the first electrode of the first transistor in the first row of the pixel driving circuits in the adjacent two rows and the third column and the fourth column of the pixel driving circuits in the adjacent two columns; the second adjacent fourth reset signal line Vint4-2 among the plurality of fourth reset signal lines is configured to provide a reset signal to the first electrode of the sixth transistor in the first row of the pixel driving circuits in the adjacent two rows and the third column and the fourth column of the pixel driving circuits in the adjacent two columns. Optionally, the second adjacent third reset signal line Vint3-2 at least partially extends in the third column of the pixel driving circuits in the adjacent two columns (for example, extends through the third column); and the second adjacent fourth reset signal line Vint4-2 at least partially extends in the fourth column of the pixel driving circuits in the adjacent two columns (for example, extends through the fourth column). Optionally, the first column, the second column, the third column and the fourth column are arranged in sequence. Alternatively, adjacent columns are separated by a first voltage supply line among the plurality of first voltage supply lines Vdd1 or a second voltage supply line among the plurality of second voltage supply lines Vdd2 .

[0090] In some embodiments, the second adjacent third reset signal line Vint3-2 among the plurality of third reset signal lines is configured to provide reset signals to the first electrodes of the first transistors in the second row of the pixel driving circuits in the adjacent two rows and the second column and the third column of the pixel driving circuits in the adjacent two columns; the first adjacent fourth reset signal line Vint4-1 among the plurality of fourth reset signal lines is configured to provide reset signals to the first electrodes of the sixth transistors in the second row of the pixel driving circuits in the adjacent two rows and the second column and the third column of the pixel driving circuits in the adjacent two columns. Optionally, the first row and the second row are arranged sequentially.

[0091] In some embodiments, the array substrate includes pixel driving circuits arranged in K columns and M rows, K and M are positive integers. The array substrate includes K reset signal lines configured to provide a reset signal to a reset transistor in the array substrate. In some embodiments, the K columns include the (4k-3)th column C(4k-3) among the K columns, the (4k-2)th column C(4k-2) among the K columns, the (4k-1)th column C(4k-1) among the K columns, and the 4kth column C(4k) among the K columns, k is a positive integer, 1≤k≤(K / 4). The M rows include the (2m-1)th row R(2m-1) among the M rows and the 2mth row R(2m) among the M rows, m is a positive integer, 1≤m≤(M / 2). In some embodiments, the K reset signal lines include a plurality of third reset signal lines located in the (4k-3)th column C(4k-3) among the K columns or in the (4k-1)th column C(4k-1) among the K columns; and a plurality of fourth reset signal lines located in the (4k-2)th column C(4k-2) among the K columns or in the (4k)th column C(4k) among the K columns. Optionally, adjacent columns are separated by a first voltage supply line among the plurality of first voltage supply lines Vdd1.

[0092] In some embodiments, the K reset signal lines include a first adjacent third reset signal line Vint3-1 in the (4k-3)th column C(4k-3) among the K columns, a second adjacent third reset signal line Vint3-2 in the (4k-1)th column C(4k-1) among the K columns, a first adjacent fourth reset signal line Vint4-1 in the (4k-2)th column C(4k-2) among the K columns, and a second adjacent fourth reset signal line Vint4-2 in the (4k)th column C(4k) among the K columns. The first adjacent third reset signal line Vint3-1, the first adjacent fourth reset signal line Vint4-1, the second adjacent third reset signal line Vint3-2, and the second adjacent fourth reset signal line Vint4-2 are arranged in sequence.

[0093] As used herein, the terms "column (4k-3)", "column (4k-2)", "column (4k-1)", and "column (4k)" are used in the context of K columns. The array substrate may or may not include additional columns before the first column of the K columns and / or additional columns after the last column of the K columns. In the context of the array substrate, the terms "column (4k-3)" or "column (4k-1)" do not necessarily mean an odd column, and the terms "column (4k-2)" or "column (4k)" do not necessarily mean an even column. In one example, the column (4k-3) is an odd column in the context of K columns, but may be an even column in the context of the array substrate. In another example, the column (4k-3) is an odd column in the context of K columns, and is also an odd column in the context of the array substrate. In one example, the column (4k-2) is an even column in the context of K columns, but may be an odd column in the context of the array substrate. In another example, the (4k-2)th column is an even column in the context of K columns, and is also an even column in the context of the array substrate. In one example, the (4k-1)th column is an odd column in the context of K columns, but may be an even column in the context of the array substrate. In another example, the (4k-1)th column is an odd column in the context of K columns, and is also an odd column in the context of the array substrate. In one example, the (4k)th column is an even column in the context of K columns, but may be an odd column in the context of the array substrate. In another example, the (4k)th column is an even column in the context of K columns, and is also an even column in the context of the array substrate.

[0094] As used herein, the term "row (2m-1)" and the term "row (2m)" are used in the context of M rows. The array substrate may or may not include additional rows before the first row of the M rows and / or additional rows after the last row of the M rows. In the context of the array substrate, the term "row (2m-1)" does not necessarily mean an odd row, and the term "row (2m)" does not necessarily mean an even row. In one example, the row (2m-1) is an odd row in the context of M rows, but may be an even row in the context of the array substrate. In another example, the row (2m-1) is an odd row in the context of M rows and is also an odd row in the context of the array substrate. In one example, the row (2m) is an even row in the context of M rows, but may be an odd row in the context of the array substrate. In another example, the row (2m) is an even row in the context of M rows and is also an even row in the context of the array substrate.

[0095] In some embodiments, the first adjacent third reset signal line Vint3-1 among a plurality of third reset signal lines is configured to provide a reset signal to the first electrode of the first transistor in two adjacent pixel driving circuits located in the pixel driving circuit of the (2m-1)th row R(2m-1) and the pixel driving circuit of the (4k-3)th column C(4k-3) and the pixel driving circuit of the (4k-2)th column C(4k-2); the first adjacent fourth reset signal line Vint4-1 among a plurality of fourth reset signal lines is configured to provide a reset signal to the first electrode of the sixth transistor in two adjacent pixel driving circuits located in the pixel driving circuit of the (2m-1)th row R(2m-1) and the pixel driving circuit of the (4k-3)th column C(4k-3) and the pixel driving circuit of the (4k-2)th column C(4k-2). Optionally, the first adjacent third reset signal line Vint3-1 extends at least partially in the pixel driving circuit of the (4k-3)th column C(4k-3) (e.g., extends through the column); and the first adjacent fourth reset signal line Vint4-1 extends at least partially in the pixel driving circuit of the (4k-2)th column C(4k-2) (e.g., extends through the column). Optionally, adjacent columns are separated by a first voltage supply line of the plurality of first voltage supply lines Vdd1 or a second voltage supply line of the plurality of second voltage supply lines Vdd2.

[0096] In some embodiments, the second adjacent third reset signal line Vint3-2 among the plurality of third reset signal lines is configured to provide the reset signal to the first electrode of the first transistor in the pixel driving circuit of the (2m-1)th row R(2m-1) and the pixel driving circuit of the (4k-1)th column C(4k-1) and the pixel driving circuit of the (4k)th column C(4k); the second adjacent fourth reset signal line Vint4-2 among the plurality of fourth reset signal lines is configured to provide the reset signal to the first electrode of the sixth transistor in the pixel driving circuit of the (2m-1)th row R(2m-1) and the pixel driving circuit of the (4k-1)th column C(4k-1) and the pixel driving circuit of the (4k)th column C(4k). Optionally, the second adjacent third reset signal line Vint3-2 extends at least partially in the pixel driving circuit of the (4k-1)th column C(4k-1) (e.g., extends through the column); and the second adjacent fourth reset signal line Vint4-2 extends at least partially in the pixel driving circuit of the (4k)th column C(4k) (e.g., extends through the column). Optionally, the (4k-3)th column C(4k-3), the (4k-2)th column C(4k-2), the (4k-1)th column C(4k-1) and the (4k)th column C(4k) are arranged in sequence. Optionally, adjacent columns are separated by a first voltage supply line among a plurality of first voltage supply lines Vdd1 or a second voltage supply line among a plurality of second voltage supply lines Vdd2.

[0097] In some embodiments, the second adjacent third reset signal line Vint3-2 among the plurality of third reset signal lines is configured to provide a reset signal to the first electrode of the first transistor in the pixel driving circuit of the (2m)th row R(2m) and the pixel driving circuit of the (4k-2)th column C(4k-2) and the pixel driving circuit of the (4k-1)th column C(4k-1), respectively; the first adjacent fourth reset signal line Vint4-1 among the plurality of fourth reset signal lines is configured to provide a reset signal to the first electrode of the sixth transistor in the pixel driving circuit of the (2m)th row R(2m) and the pixel driving circuit of the (4k-2)th column C(4k-2) and the pixel driving circuit of the (4k-1)th column C(4k-1), respectively. Optionally, the (2m-1)th row R(2m-1) and the (2m)th row R(2m) are arranged in sequence.

[0098] Reference FIG. 3A to FIG. 3I as well as Figure 5 In some embodiments, the corresponding layers of the pixel driving circuits located at the (4k-3)th column C(4k-3) and the (4k-2)th column C(4k-2) in the same row or multiple rows and the corresponding layers of the pixel driving circuits located at the (4k-1)th column C(4k-1) and the (4k)th column C(4k) in the same row or multiple rows, for example, have substantial mirror symmetry relative to each other with respect to a plane perpendicular to the main surface of the array substrate and substantially parallel to the multiple data lines DL, or the multiple first voltage supply lines Vdd1, or the multiple second voltage supply lines Vdd2.

[0099] As used herein, the term "corresponding layers of the pixel driving circuits in the (4k-3)th column C(4k-3) and the (4k-2)th column C(4k-2) and the corresponding layers of the pixel driving circuits in the (4k-1)th column C(4k-1) and the (4k)th column C(4k)" is not intended to include layers that are not part of the pixel driving circuits. For example, "corresponding layers of the pixel driving circuits in the (4k-3)th column C(4k-3) and the (4k-2)th column C(4k-2) and the corresponding layers of the pixel driving circuits in the (4k-1)th column C(4k-1) and the (4k)th column C(4k)" do not include an anode layer or a pixel defining layer. In some embodiments, "the corresponding layers of the pixel driving circuits in the (4k-3)th column C(4k-3) and the (4k-2)th column C(4k-2) and the corresponding layers of the pixel driving circuits in the (4k-1)th column C(4k-1) and the (4k)th column C(4k)" do not include the first signal line layer. In one example, "the corresponding layers of the pixel driving circuits in the (4k-3)th column C(4k-3) and the (4k-2)th column C(4k-2) and the corresponding layers of the pixel driving circuits in the (4k-1)th column C(4k-1) and the (4k)th column C(4k)" refers to at least one conductive layer of the pixel driving circuits in the (4k-3)th column C(4k-3), the (4k-2)th column C(4k-2), the (4k-1)th column C(4k-1) and the (4k)th column C(4k). In one specific example, the "corresponding layer" includes at least one of a first semiconductor material layer, a first gate metal layer, a second gate metal layer, a second semiconductor material layer, a third gate metal layer, a first signal line layer, or a second signal line layer. In another specific example, the "corresponding layer" also includes at least one of a gate insulating layer, an insulating layer, a first interlayer dielectric layer, a second interlayer dielectric layer, a passivation layer, a first planarization layer, or a second planarization layer. In another specific example, the "corresponding layer" includes a first semiconductor material layer, a first gate metal layer, a second gate metal layer, a second semiconductor material layer, a third gate metal layer, a first signal line layer, and a second signal line layer. In another specific embodiment, the "corresponding layer" also includes a gate insulating layer, an insulating layer, a first interlayer dielectric layer, a second interlayer dielectric layer, a passivation layer, a first planarization layer, and a second planarization layer.

[0100] See also Figure 3A , Figure 3G and Figure 5In some embodiments, the plurality of third voltage supply lines Vint3 do not exist in the (4k-2)th column C(4k-2) and the (4k)th column C(4k); the plurality of fourth voltage supply lines Vint4 do not exist in the (4k-3)th column C(4k-3) and the (4k-1)th column C(4k-1). Alternatively, the plurality of third voltage supply lines Vint3 exist in the (4k-3)th column C(4k-3) and the (4k-1)th column C(4k-1); and the plurality of fourth voltage supply lines Vint4 exist in the (4k-2)th column C(4k-2) and the (4k)th column C(4k).

[0101] Figure 6 It is shown Figure 3A Schematic diagram of the structure of a semiconductor material layer in a portion of an array substrate shown in FIG. Figure 3A , Figure 3C , Figure 5 and Figure 6 In some embodiments, the first electrodes of the first transistors in the two adjacent pixel driving circuits located in the (2m-1)th row R(2m-1) and the (4k-3)th column C(4k-3) and the (4k-2)th column C(4k-2) are respectively part of the first overall structure. In some embodiments, the first electrodes of the sixth transistors in the two adjacent pixel driving circuits located in the (2m-1)th row R(2m-1) and the (4k-3)th column C(4k-3) and the (4k-2)th column C(4k-2) are respectively part of the first overall structure. Optionally, the active layer, at least part of the first electrode and at least part of the second electrode of the transistors in the two adjacent pixel driving circuits located in the (2m-1)th row R(2m-1) and the (4k-3)th column C(4k-3) and the (4k-2)th column C(4k-2) are respectively part of the first overall structure. The inventors of the present disclosure have found that by providing a first overall structure including the first electrodes of the first transistors in two adjacent pixel driving circuits, only one via is needed to connect the reset signal line to the first electrodes of the first transistors in the two adjacent pixel driving circuits. This unique structure helps save layout space and reduce crosstalk between adjacent sub-pixels.

[0102] In some embodiments, the first electrodes of the first transistors in the two adjacent pixel driving circuits located in the (2m-1)th row R(2m-1) and the (4k-1)th column C(4k-1) and the (4k)th column C(4k) are respectively part of the second overall structure. In some embodiments, the first electrodes of the sixth transistors in the two adjacent pixel driving circuits located in the (2m-1)th row R(2m-1) and the (4k-1)th column C(4k-1) and the (4k)th column C(4k) are respectively part of the second overall structure. Optionally, the active layer, at least part of the first electrode and at least part of the second electrode of the transistors in the two adjacent pixel driving circuits located in the (2m-1)th row R(2m-1) and the (4k-1)th column C(4k-1) and the (4k)th column C(4k) are respectively part of the second overall structure. The inventors of the present disclosure have found that by providing a second overall structure including the first electrodes of the sixth transistors in two adjacent pixel driving circuits, only one via is needed to connect the reset signal line to the first electrodes of the sixth transistors in the two adjacent pixel driving circuits. This unique structure helps save layout space and reduce crosstalk between adjacent sub-pixels.

[0103] In some embodiments, the first electrodes of the first transistors in the two adjacent pixel driving circuits located in the (2m)th row R(2m) and the (4k-2)th column C(4k-2) and the (4k-1)th column C(4k-1) are respectively part of the third overall structure. In some embodiments, the first electrodes of the sixth transistors in the two adjacent pixel driving circuits located in the (2m)th row R(2m) and the (4k-2)th column C(4k-2) and the (4k-1)th column C(4k-1) are respectively part of the third overall structure. Optionally, the active layer, at least part of the first electrode and at least part of the second electrode of the transistors in the two adjacent pixel driving circuits located in the (2m)th row R(2m) and the (4k-2)th column C(4k-2) and the (4k-1)th column C(4k-1) are respectively part of the third overall structure.

[0104] Optionally, the first integral structure, the second integral structure and the third integral structure are spaced apart from each other.

[0105] Reference Figure 3A , Figure 3C , Figure 5 and Figure 6 In some embodiments, corresponding components of the first transistors in two adjacent pixel driving circuits located in the same row and two adjacent columns have substantial mirror symmetry, for example, with respect to a plane perpendicular to the main surface of the array substrate and substantially parallel to the plurality of data lines DL, or the plurality of first voltage supply lines Vdd1, or the plurality of second voltage supply lines Vdd2.

[0106] Optionally, corresponding components of the first transistors in two adjacent pixel driving circuits located in the same row and the (4k-3)th column C(4k-3) and the (4k-2)th column C(4k-2) have substantial mirror symmetry, for example, with respect to a first plane perpendicular to the main surface of the array substrate and substantially parallel to the plurality of data lines DL, or the plurality of first voltage supply lines Vdd1, or the plurality of second voltage supply lines Vdd2; corresponding components of the first transistors in two adjacent pixel driving circuits located in the same row and the (4k-2)th column C(4k-2) and the (4k-1)th column C(4k-1) have substantial mirror symmetry, for example, with respect to a first plane perpendicular to the main surface of the array substrate and substantially parallel to the plurality of data lines DL, or the plurality of first voltage supply lines Vdd1, or the plurality of second voltage supply lines Vdd2. A second plane perpendicular to the main surface of the array substrate and substantially parallel to the multiple data lines DL, or the multiple first voltage supply lines Vdd1, or the multiple second voltage supply lines Vdd2 has a substantial mirror symmetry; and corresponding components of the first transistors in two adjacent pixel driving circuits located in the same row and the (4k-1)th column C(4k-1) and the (4k)th column C(4k) have a substantial mirror symmetry, for example, with respect to a third plane perpendicular to the main surface of the array substrate and substantially parallel to the multiple data lines DL, or the multiple first voltage supply lines Vdd1, or the multiple second voltage supply lines Vdd2.

[0107] In some embodiments, corresponding components of the driving transistor, the second transistor, the third transistor, the fourth transistor, or the fifth transistor located in the same row and two adjacent columns have substantial translational symmetry along the row direction.

[0108] Optionally, corresponding components of the driving transistor, the second transistor, the third transistor, the fourth transistor or the fifth transistor located in the same row and the (4k-3)th column C(4k-3) and the (4k-2)th column C(4k-2) have basic translational symmetry along the row direction; corresponding components of the driving transistor, the second transistor, the third transistor, the fourth transistor or the fifth transistor located in the same row and the (4k-2)th column C(4k-2) and the (4k-1)th column C(4k-1) have basic translational symmetry along the row direction; and corresponding components of the driving transistor, the second transistor, the third transistor, the fourth transistor or the fifth transistor located in the same row and the (4k-1)th column C(4k-1) and the (4k)th column C(4k) have basic translational symmetry along the row direction.

[0109] In some embodiments, corresponding components of the sixth transistor in two adjacent pixel driving circuits located in the same row and (4k-2)th column C(4k-2) and (4k-1)th column C(4k-1) have substantial mirror symmetry, for example, with respect to a plane perpendicular to the main surface of the array substrate and substantially parallel to the plurality of data lines DL, or the plurality of first voltage supply lines Vdd1, or the plurality of second voltage supply lines Vdd2.

[0110] Optionally, the corresponding components of the sixth transistors in two adjacent pixel driving circuits located in the same row and the (4k-3)th column C(4k-3) and the (4k-2)th column C(4k-2) do not have mirror symmetry; and the corresponding components of the sixth transistors in two adjacent pixel driving circuits located in the same row and the (4k-1)th column C(4k-1) and the (4k)th column C(4k) do not have mirror symmetry.

[0111] Figure 7 It is shown Figure 3A Schematic diagram of the connection between the data lines and the corresponding transistors in the array substrate shown in FIG. Figure 3A , Figure 3C , Fig. 3I and Figure 7 In some embodiments, the plurality of data lines DL include a first corresponding data line RDL1, which is configured to provide a data signal to a first electrode of a second transistor in a first row of a pixel driving circuit in the same column and two adjacent rows; and a second corresponding data line RDL2, which is configured to provide a data signal to a first electrode of a second transistor in a second row of a pixel driving circuit in the same column and two adjacent rows. The first corresponding data line RDL1 and the second corresponding data line RDL2 extend at least partially in the same column (e.g., extend through the column). The first corresponding data line RDL1 is electrically isolated from a first electrode of a second transistor in a second row of a pixel driving circuit in the same column and two adjacent rows; and the second corresponding data line RDL2 is electrically isolated from a first electrode of a second transistor in a first row of a pixel driving circuit in the same column and two adjacent rows.

[0112] Reference Figure 3A , Figure 3C , Fig. 3I and Figure 7 In some embodiments, the plurality of data lines DL include a first corresponding data line RDL1 configured to provide a data signal to a first electrode of a second transistor in a pixel driving circuit located in the same column and the (2m-1)th row R(2m-1); and a second corresponding data line RDL2 configured to provide a data signal to a first electrode of a second transistor in a pixel driving circuit located in the same column and the (2m)th row R(2m). The first corresponding data line RDL1 and the second corresponding data line RDL2 extend at least partially in the same column (e.g., extend through the column). The first corresponding data line RDL1 is electrically isolated from a first electrode of a second transistor in a pixel driving circuit located in the same column and the (2m)th row R(2m); and the second corresponding data line RDL2 is electrically isolated from a first electrode of a second transistor in a pixel driving circuit located in the same column and the (2m-1)th row R(2m-1).

[0113] In some embodiments, the first corresponding data line RDL1 and the second corresponding data line RDL2 are located between adjacent two first voltage supply lines among the plurality of first voltage supply lines Vdd1 .

[0114] In some embodiments, the orthographic projections of active layers of driving transistors in the same column on the substrate separate the orthographic projections of the first corresponding data line RDL1 on the substrate from the orthographic projections of the second corresponding data line RDL2 on the substrate.

[0115] In some embodiments, the orthographic projection of the same pixel driving circuit on the base substrate partially overlaps with the orthographic projection of the first corresponding data line RDL1 on the base substrate, and partially overlaps with the orthographic projection of the second corresponding data line RDL2 on the base substrate.

[0116] In some embodiments, the orthographic projection of the semiconductor layer of the same pixel driving circuit on the base substrate partially overlaps with the orthographic projection of the first corresponding data line RDL1 on the base substrate, and partially overlaps with the orthographic projection of the second corresponding data line RDL2 on the base substrate.

[0117] In some embodiments, the orthographic projection of the first corresponding data line RDL1 on the substrate partially overlaps with the orthographic projection of the first electrode of the driving transistor on the substrate; the orthographic projection of the second corresponding data line RDL2 on the substrate partially overlaps with the orthographic projection of the second electrode of the driving transistor on the substrate.

[0118] In some embodiments, the array substrate includes a plurality of first data signal connection pads and a plurality of second data signal connection pads located in the same column of pixel driving circuits. Each first data signal connection pad RDCP1 connects a first corresponding data line RDL1 to a first electrode of a second transistor in a first corresponding pixel driving circuit in a first row of two adjacent rows of pixel driving circuits. Each second data signal connection pad RDCP2 connects a second corresponding data line RDL2 to a first electrode of a second transistor in a second corresponding pixel driving circuit in a second row of two adjacent rows of pixel driving circuits. There are no multiple first data signal connection pads in the first row of two adjacent rows of pixel driving circuits. There are no multiple second data signal connection pads in the second row of two adjacent rows of pixel driving circuits.

[0119] In some embodiments, the array substrate includes a plurality of first data signal connection pads and a plurality of second data signal connection pads located in the same column of pixel driving circuits. Each first data signal connection pad RDCP1 connects the first corresponding data line RDL1 to the first electrode of the second transistor in the first corresponding pixel driving circuit in the (2m-1)th row R(2m-1). Each second data signal connection pad RDCP2 connects the second corresponding data line RDL2 to the first electrode of the second transistor in the second corresponding pixel driving circuit in the (2m)th row R(2m). There are no plurality of first data signal connection pads in the (2m)th row R(2m). There are no plurality of second data signal connection pads in the (2m-1)th row R(2m-1).

[0120] In some embodiments, the ratio of the total number of data lines in the array substrate to the total number of columns of the pixel driving circuit is in the range of 1.6:1 to 2.4:1, for example, 1.6:1 to 1.7:1, 1.7:1 to 1.8:1, 1.8:1 to 1.9:1, 1.9:1 to 2.0:1, 2.0:1 to 2.1:1, 2.1:1 to 2.2:1, 2.2:1 to 2.3:1, or 2.3:1 to 2.4: 1. In one embodiment, the ratio of the total number of data lines in the array substrate to the total number of columns of the pixel driving circuit is 2:1.

[0121] In some embodiments, the ratio of the total number of data signal connection pads in the array substrate to the total number of pixel driving circuits is in the range of 0.8:1 to 1.2:1, for example, 0.8:1 to 0.9:1, 0.9:1 to 1.0:1, 1.0:1 to 1.1:1, or 1.1:1 to 1.2: 1. In one example, the ratio of the total number of data signal connection pads in the array substrate to the total number of pixel driving circuits is 1:1.

[0122] Figure 8 Schematic diagram showing the structure of a first reset signal network and a second reset signal network in an array substrate according to some embodiments of the present disclosure. Figure 8 In some embodiments, the first reset signal network includes a plurality of first reset signal lines Vint1 and a plurality of third reset signal lines Vint3 interconnected with each other. Optionally, the plurality of first reset signal lines Vint1 extend in a direction substantially parallel to the first direction DR1. Optionally, the plurality of third reset signal lines Vint3 extend in a direction substantially parallel to the second direction DR2. Optionally, each of the plurality of first reset signal lines Vint1 is connected to one or more third reset signal lines in the plurality of third reset signal lines Vint3. Optionally, each of the plurality of third reset signal lines Vint3 is connected to one or more first reset signal lines in the plurality of first reset signal lines Vint1.

[0123] In one example, the plurality of first reset signal lines Vint1 are located in the second conductive layer. Optionally, the plurality of third reset signal lines Vint3 are located in the first signal line layer.

[0124] Reference Figure 8 In some embodiments, the second reset signal network includes a plurality of second reset signal lines Vint2 and a plurality of fourth reset signal lines Vint4 interconnected with each other. Optionally, the plurality of second reset signal lines Vint2 extend in a direction substantially parallel to the first direction DR1. Optionally, the plurality of fourth reset signal lines Vint4 extend in a direction substantially parallel to the second direction DR2. Optionally, each of the plurality of second reset signal lines Vint2 is connected to one or more fourth reset signal lines in the plurality of fourth reset signal lines Vint4. Optionally, each of the plurality of fourth reset signal lines Vint4 is connected to one or more second reset signal lines in the plurality of second reset signal lines Vint2.

[0125] In one example, the plurality of second reset signal lines Vint2 are located in the first signal line layer. Optionally, the plurality of fourth reset signal lines Vint4 are located in the first signal line layer.

[0126] In some embodiments, there are no multiple third reset signal lines Vint3 in the (4k-2)th column C(4k-2) and the (4k)th column C(4k); there are no multiple fourth reset signal lines Vint4 in the (4k-3)th column C(4k-3) and the (4k-1)th column C(4k-1). In some embodiments, there are no multiple first reset signal lines Vint1 in the (2m)th row R(2m); there are no multiple second reset signal lines Vint2 in the (2m-1)th row R(2m-1).

[0127] In some embodiments, each of the plurality of first reset signal lines Vint1 located in the (2m-1)th row R(2m-1) is connected to one or more third reset signal lines Vint3 located in the (4k-3)th column C(4k-3) or the (4k-1)th column C(4k-1). Optionally, each of the plurality of third reset signal lines Vint3 located in the (4k-3)th column C(4k-3) or the (4k-1)th column C(4k-1) is connected to one or more first reset signal lines Vint1 located in the (2m-1)th row R(2m-1).

[0128] In some embodiments, each of the plurality of second reset signal lines Vint2 located in the (2m)th row R(2m) is connected to one or more fourth reset signal lines among the plurality of fourth reset signal lines Vint4 located in the (4k-2)th column C(4k-2) or the (4k)th column C(4k). Optionally, each of the plurality of fourth reset signal lines Vint4 located in the (4k-2)th column C(4k-2) or the (4k)th column C(4k) is connected to one or more second reset signal lines among the plurality of second reset signal lines Vint2 located in the (2m)th row R(2m).

[0129] The inventors of the present disclosure have discovered that by providing the first reset signal network and the second reset signal network according to the present disclosure, high-resolution display and high display quality can be achieved.

[0130] Fig. 9 Schematic diagram showing the layout of the signal lines in the semiconductor material layer and the second conductive layer in a portion of the array substrate in some embodiments of the present disclosure. FIG. 3A to FIG. 3I as well as Fig. 9 , in some embodiments, the array substrate further comprises an anti-interference block IPB. Optionally, the anti-interference block IPB is located in the second conductive layer. Optionally, the anti-interference block IPB is located in the same layer as the second capacitor electrode Ce2. Optionally, the anti-interference block IPB is connected to a corresponding second voltage supply line in a plurality of second voltage supply lines Vdd2. Optionally, the anti-interference block IPB is configured to receive a first reference voltage signal. Optionally, the first reference voltage signal is a constant voltage signal, for example, a high reference voltage signal.

[0131] In some embodiments, the orthographic projection of the anti-interference block IPB on the substrate substrate at least partially overlaps with the orthographic projection of a portion of the semiconductor material layer between two active layer portions (e.g., two channel portions) of the third transistor T3 on the substrate substrate. The inventors of the present disclosure have found that this unique structure enhances the stability of the third transistor T3.

[0132] Fig.10 is a schematic diagram showing the structure of an anti-interference block in some embodiments of the present disclosure. Fig.10In some embodiments, the anti-interference block IPB includes a first portion P1 and a second portion P2. In some embodiments, the orthographic projection of the first portion P1 on the substrate substrate at least partially overlaps with the orthographic projection of a portion of the semiconductor material layer between two active layer portions (e.g., two channel portions) of the third transistor T3 in the first adjacent pixel driving circuit on the substrate substrate. In some embodiments, the orthographic projection of the second portion P2 on the substrate substrate at least partially overlaps with the orthographic projection of the second electrode D1 of the first transistor and / or the second electrode D3 of the third transistor in the second adjacent pixel driving circuit on the substrate substrate. Optionally, the first adjacent pixel driving circuit and the second adjacent pixel driving circuit are located in the same row and are adjacent to each other.

[0133] In some embodiments, the anti-interference block IPB further includes a third portion P3 connecting the first portion P1 with the second portion P2. In some embodiments, the orthographic projection of the third portion P3 on the substrate substrate at least partially overlaps with the orthographic projection of the first electrode S2 of the second transistor in the second adjacent pixel driving circuit on the substrate substrate.

[0134] In another aspect, the present invention provides a display device, comprising an array substrate as described herein or manufactured by the method described herein, and one or more integrated circuits connected to the array substrate. Examples of suitable display devices include, but are not limited to, electronic paper, mobile phones, tablet computers, televisions, monitors, notebook computers, digital photo albums, GPS, etc. Optionally, the display device is an organic light emitting diode display device. Optionally, the display device is a micro light emitting diode display device. Optionally, the display device is a mini light emitting diode display device.

[0135] On the other hand, the present disclosure provides a method for manufacturing an array substrate. In some embodiments, the method includes forming a plurality of data lines. Optionally, forming the plurality of data lines includes forming a first corresponding data line and forming a second corresponding data line, wherein the first corresponding data line is configured to provide a data signal to a first electrode of a data write transistor in a first row of a pixel drive circuit in the same column and two adjacent rows of pixel drive circuits; and the second corresponding data line is configured to provide a data signal to a first electrode of a data write transistor in a second row of a pixel drive circuit in the same column and two adjacent rows of pixel drive circuits. Optionally, the first corresponding data line and the second corresponding data line extend at least partially in the same column. Optionally, the first corresponding data line is electrically isolated from the first electrode of the data write transistor in the second row of the pixel drive circuit in the same column and two adjacent rows of pixel drive circuits. Optionally, the second corresponding data line is electrically isolated from the first electrode of the data write transistor in the first row of the pixel drive circuit in the same column and two adjacent rows of pixel drive circuits.

[0136] For the purpose of illustration and description, the above description of the embodiments of the present invention has been given. It is not exhaustive, nor is it intended to limit the present invention to the precise form or exemplary embodiments disclosed. Therefore, the foregoing description should be considered illustrative rather than restrictive. Obviously, many modifications and variations will be apparent to those skilled in the art. The embodiments are selected and described to explain the principles of the present invention and its best mode practical application, so that those skilled in the art can understand the various embodiments of the present invention and the various modifications suitable for the specific use or implementation under consideration. The scope of the present invention is intended to be defined by the appended claims and their equivalents, wherein all terms are meant to have the broadest reasonable meaning unless otherwise stated. Therefore, the term "the present invention" and the like do not necessarily limit the scope of the claims to a specific embodiment, and the reference to the exemplary embodiments of the present invention does not mean a limitation of the present invention, and such limitation should not be inferred. The present invention is limited only by the spirit and scope of the appended claims. In addition, these claims may involve the use of "first", "second", etc., followed by a noun or element. These terms should be understood as nomenclature, and should not be interpreted as limiting the number of elements modified by these nomenclatures, unless a specific number has been given. Any advantages and benefits described may not apply to all embodiments of the present invention. It should be understood that those skilled in the art may make changes to the described embodiments without departing from the scope of the present invention as defined by the appended claims. In addition, the elements and assemblies in this disclosure are not intended to be contributed to the public, regardless of whether the element or assembly is clearly described in the appended claims.

Claims

1. An array substrate comprising a plurality of data lines; in, The plurality of data lines include a first corresponding data line and a second corresponding data line, the first corresponding data line being configured to provide a data signal to a first electrode of a data write transistor located in a first row of a same column of pixel drive circuits and two adjacent rows of pixel drive circuits; and the second corresponding data line being configured to provide a data signal to a first electrode of a data write transistor located in a second row of a same column of pixel drive circuits and two adjacent rows of pixel drive circuits; The first corresponding data line and the second corresponding data line extend at least partially in the same column; The first corresponding data line is electrically isolated from the first electrode of the data writing transistor located in the second row of the same column of pixel driving circuits and the adjacent two rows of pixel driving circuits; and The second corresponding data line is electrically isolated from the first electrode of the data writing transistor located in the first row of the pixel driving circuits in the same column and the adjacent two rows.

2. The array substrate according to claim 1, wherein: The orthographic projection of the same pixel driving circuit on the base substrate partially overlaps with the orthographic projection of the first corresponding data line on the base substrate, and partially overlaps with the orthographic projection of the second corresponding data line on the base substrate.

3. The array substrate according to claim 1, wherein: The orthographic projection of the first corresponding data line on the base substrate partially overlaps with the first electrode of the driving transistor on the base substrate; And the orthographic projection of the second corresponding data line on the base substrate partially overlaps with the second electrode of the driving transistor on the base substrate.

4. The array substrate according to any one of claims 1 to 3, further comprising a plurality of first data signal connection pads and a plurality of second data signal connection pads located in the same column of pixel driving circuits; Each of the plurality of first data signal connection pads connects the first corresponding data line to a first electrode of a data writing transistor in a first corresponding pixel driving circuit in the first row of the two adjacent rows of pixel driving circuits; Each second data signal connection pad among the plurality of second data signal connection pads connects the second corresponding data line to a first electrode of a data writing transistor in a second corresponding pixel driving circuit in the second row of the two adjacent rows of pixel driving circuits; The plurality of first data signal connection pads do not exist in the first row of the two adjacent rows of pixel driving circuits; as well as There are no second data signal connection pads in the second row of the two adjacent rows of pixel driving circuits.

5. The array substrate according to any one of claims 1 to 4, wherein: A ratio of a total number of data lines to a total number of columns of pixel driving circuits in the array substrate is in a range of 1.6:1 to 2.4:

1.

6. The array substrate according to any one of claims 1 to 5, further comprising a plurality of third reset signal lines and a plurality of fourth reset signal lines; in, A first adjacent third reset signal line among the plurality of third reset signal lines is configured to provide a reset signal to first electrodes of first reset transistors in adjacent two pixel drive circuits located in a first row among two adjacent rows of pixel drive circuits and in a first column and a second column among two adjacent columns of pixel drive circuits, respectively; A first adjacent fourth reset signal line among the plurality of fourth reset signal lines is configured to provide a reset signal to first electrodes of second reset transistors in the first row of pixel drive circuits in two adjacent rows and in the first column and in the second column of pixel drive circuits in the two adjacent columns, respectively; A second adjacent third reset signal line among the plurality of third reset signal lines is configured to provide a reset signal to first electrodes of first reset transistors in adjacent two pixel drive circuits located in the first row among the adjacent two rows of pixel drive circuits and in the third column and the fourth column among the adjacent two columns of pixel drive circuits, respectively; A second adjacent fourth reset signal line among the plurality of fourth reset signal lines is configured to provide a reset signal to first electrodes of second reset transistors in the adjacent two pixel drive circuits in the third column and the fourth column of the pixel drive circuits in the first row of the adjacent two rows and the adjacent two columns, respectively; The second adjacent third reset signal line among the plurality of third reset signal lines is configured to provide reset signals to first electrodes of first reset transistors in adjacent two pixel drive circuits in a second row among the two adjacent rows of pixel drive circuits and in the second column and the third column among the two adjacent columns of pixel drive circuits, respectively; The first adjacent fourth reset signal line among the multiple fourth reset signal lines is configured to provide reset signals to the first electrodes of the second reset transistors in the second row of pixel driving circuits in two adjacent rows and the second column and the third column of pixel driving circuits in the adjacent two columns, respectively.

7. The array substrate according to claim 6, wherein: The first adjacent third reset signal line at least partially extends in the first column of the two adjacent columns of pixel driving circuits; The first adjacent fourth reset signal line at least partially extends in the second column of the two adjacent columns of pixel driving circuits; The second adjacent third reset signal line at least partially extends in the third column of the two adjacent columns of pixel driving circuits; The second adjacent fourth reset signal line at least partially extends in the fourth column of the two adjacent columns of pixel driving circuits; The first column, the second column, the third column, and the fourth column are arranged in sequence; as well as The first row and the second row are arranged in sequence.

8. The array substrate according to any one of claims 1 to 5, further comprising pixel driving circuits arranged in K columns and M rows, where K and M are positive integers; The array substrate comprises K reset signal lines configured to provide a reset signal to a reset transistor in the array substrate; The K columns include the (4k-3)th column among the K columns, the (4k-2)th column among the K columns, the (4k-1)th column among the K columns, and the 4kth column among the K columns, where k is a positive integer, 1≤k≤(K / 4); The M rows include the (2m-1)th row among the M rows and the 2mth row among the M rows, where m is a positive integer, 1≤m≤(M / 2); The K reset signal lines include a plurality of third reset signal lines located in the (4k-3)th column among the K columns or in the (4k-1)th column among the K columns; and a plurality of fourth reset signal lines located in the (4k-2)th column among the K columns or in the (4k)th column among the K columns.

9. The array substrate according to claim 8, wherein: The K reset signal lines include: a first adjacent third reset signal line among the plurality of third reset signal lines, configured to provide a reset signal to first electrodes of first reset transistors in two adjacent pixel drive circuits located in the pixel drive circuit in the (2m-1)th row and the pixel drive circuit in the (4k-3)th column and the (4k-2)th column, respectively; a first adjacent fourth reset signal line among the plurality of fourth reset signal lines, configured to provide a reset signal to first electrodes of second reset transistors in the adjacent two pixel drive circuits in the pixel drive circuit in the (2m-1)th row and the pixel drive circuit in the (4k-3)th column and the (4k-2)th column, respectively; a second adjacent third reset signal line among the plurality of third reset signal lines, configured to provide a reset signal to first electrodes of first reset transistors in adjacent two pixel drive circuits located in the pixel drive circuit in the (2m-1)th row and the pixel drive circuits in the (4k-1)th column and the (4kth column respectively; and a second adjacent fourth reset signal line among the plurality of fourth reset signal lines, configured to provide a reset signal to first electrodes of second reset transistors in the adjacent two pixel drive circuits in the pixel drive circuit in the (2m-1)th row and the pixel drive circuit in the (4k-1)th column and the (4kth column, respectively; wherein the second adjacent third reset signal lines are configured to provide reset signals to first electrodes of first reset transistors in two adjacent pixel driving circuits located in the pixel driving circuit in the (2m)th row and the pixel driving circuit in the (4k-2)th column and the (4k-1)th column, respectively; and The first adjacent fourth reset signal line is configured to provide a reset signal to the first electrodes of the second reset transistors in the two adjacent pixel driving circuits respectively located in the pixel driving circuit of the (2m)th row and the pixel driving circuits of the (4k-2)th column and the (4k-1)th column.

10. The array substrate according to claim 8, wherein: The first adjacent third reset signal line at least partially extends in the pixel driving circuit of the (4k-3)th column; The first adjacent fourth reset signal line at least partially extends in the pixel driving circuit of the (4k-2)th column; The second adjacent third reset signal line at least partially extends in the pixel driving circuit of the (4k-1)th column; as well as The second adjacent fourth reset signal line at least partially extends in the pixel driving circuit of the (4k)th column.

11. The array substrate according to claim 8, wherein: The plurality of third voltage supply lines do not exist in the (4k-2)th column and the (4kth column; The plurality of fourth voltage supply lines do not exist in the (4k-3)th column and the (4k-1)th column; The plurality of third voltage supply lines exist in the (4k-3)th column or the (4k-1)th column; as well as The plurality of fourth voltage supply lines exist in the (4k-2)th column or the (4k)th column.

12. The array substrate according to any one of claims 8 to 11, wherein: At least one corresponding layer of the pixel driving circuit located between the (4k-3)th column and the (4k-2)th column in the same row or multiple rows and at least one corresponding layer of the pixel driving circuit located between the (4k-1)th column and the (4k)th column have substantial mirror symmetry relative to each other.

13. The array substrate according to claim 8, wherein: The first electrodes of the first reset transistors in the two adjacent pixel driving circuits located in the (2m-1)th row and the (4k-3)th column and the (4k-2)th column are respectively part of the first integral structure; The first electrodes of the second reset transistors in the two adjacent pixel driving circuits located in the (2m-1)th row and the (4k-3)th column and the (4k-2)th column are respectively part of the first overall structure; The first electrodes of the first reset transistors in the two adjacent pixel driving circuits located in the (2m-1)th row and the (4k-1)th column and the (4kth column) are respectively part of the second overall structure; The first electrodes of the second reset transistors in the two adjacent pixel driving circuits located in the (2m-1)th row R(2m-1) and the (4k-1)th column C(4k-1) and the (4k)th column C(4k) are respectively part of the second overall structure; The first electrodes of the first reset transistors in the two adjacent pixel driving circuits located in the (2m)th row and the (4k-2)th column and the (4k-1)th column are respectively part of the third overall structure; as well as The first electrodes of the second reset transistors in the two adjacent pixel driving circuits located in the (2m)th row and the (4k-2)th column and the (4k-1)th column are respectively part of the third integral structure.

14. The array substrate according to claim 8, wherein: The active layer, at least part of the first electrode and at least part of the second electrode of the transistor in the two adjacent pixel driving circuits located in the (2m-1)th row and the (4k-3)th column and the (4k-2)th column are respectively part of the first integral structure; The active layer, at least part of the first electrode and at least part of the second electrode of the transistor in the two adjacent pixel driving circuits located in the (2m-1)th row and the (4k-1)th column and the (4kth column) are respectively part of the second overall structure; as well as The active layer, at least part of the first electrode and at least part of the second electrode of the transistors in the two adjacent pixel driving circuits located in the (2m)th row and the (4k-2)th column and the (4k-1)th column are respectively part of the third integral structure.

15. The array substrate according to claim 8, wherein: The corresponding components of the first reset transistors in the adjacent two pixel driving circuits located in the same row and the (4k-3)th column and the (4k-2)th column have substantial mirror symmetry; The corresponding components of the first reset transistors in the adjacent two pixel driving circuits located in the same row and the (4k-2)th column and the (4k-1)th column have substantial mirror symmetry; The corresponding components of the first reset transistors in the adjacent two pixel driving circuits located in the same row and the (4k-1)th column and the (4k)th column have substantial mirror symmetry; as well as The corresponding components of the second reset transistors in the two adjacent pixel driving circuits located in the same row and the (4k-2)th column and the (4k-1)th column have substantial mirror symmetry.

16. The array substrate according to claim 15, wherein: The corresponding components of the sixth transistors in the two adjacent pixel driving circuits located in the same row and the (4k-3)th column and the (4k-2)th column do not have mirror symmetry; as well as Corresponding components of the sixth transistors in two adjacent pixel driving circuits located in the same row and the (4k-1)th column and the (4k)th column do not have mirror symmetry.

17. The array substrate according to any one of claims 1 to 5, further comprising a first reset signal network and a second reset signal network; in, The first reset signal network includes a plurality of first reset signal lines and a plurality of third reset signal lines interconnected with each other; The second reset signal network includes a plurality of second reset signal lines and a plurality of fourth reset signal lines interconnected with each other; Each of the plurality of first reset signal lines is connected to one or more third reset signal lines of the plurality of third reset signal lines; Each of the plurality of third reset signal lines is connected to one or more first reset signal lines of the plurality of first reset signal lines; Each of the plurality of second reset signal lines is connected to one or more fourth reset signal lines of the plurality of fourth reset signal lines; and Each of the plurality of fourth reset signal lines is connected to one or more second reset signal lines of the plurality of second reset signal lines.

18. The array substrate according to claim 17, further comprising pixel driving circuits arranged in K columns and M rows, K and M are positive integers; The K columns include the (4k-3)th column among the K columns, the (4k-2)th column among the K columns, the (4k-1)th column among the K columns, and the 4kth column among the K columns, where k is a positive integer, 1≤k≤(K / 4); The M rows include the (2m-1)th row among the M rows and the 2mth row among the M rows, where m is a positive integer, 1≤m≤(M / 2); The plurality of third reset signal lines do not exist in the (4k-2)th column and the (4kth column; The plurality of fourth reset signal lines do not exist in the (4k-3)th column and the (4k-1)th column; The plurality of first reset signal lines do not exist in the (2m)th row; and The plurality of second reset signal lines do not exist in the (2m-1)th row.

19. The array substrate according to claim 18, wherein: Each of the plurality of first reset signal lines located in the (2m-1)th row is connected to one or more third reset signal lines of the plurality of third reset signal lines located in the (4k-3)th column or the (4k-1)th column; Each of the plurality of third reset signal lines located in the (4k-3)th column or the (4k-1)th column is connected to one or more first reset signal lines of the plurality of first reset signal lines located in the (2m-1)th row; each of the plurality of second reset signal lines located in the (2m)th row is connected to one or more fourth reset signal lines of the plurality of fourth reset signal lines located in the (4k-2)th column or the (4kth column); and Each of the plurality of fourth reset signal lines located in the (4k-2)th column or the (4k)th column is connected to one or more second reset signal lines of the plurality of second reset signal lines located in the (2m)th row.

20. A display device comprising the array substrate according to any one of claims 1 to 19 and one or more integrated circuits connected to the array substrate.

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