Package including first substrate, second substrate, and electrical device coupled to bottom surface of second substrate

Abstract

A package (301), comprising: a first substrate (102); a first integrated device (103) coupled to the first substrate; a second substrate (104) coupled to the first substrate by a first plurality of solder interconnects (360) such that the first integrated device is located between the first substrate and the second substrate, where the second substrate includes a first surface and a second surface; an electrical device (110) coupled to the second surface of the second substrate such that the electrical device is located between the first substrate and the second substrate; and an encapsulation layer (306) coupled to the first substrate and the second substrate. The encapsulation layer is located between the first substrate and the second substrate. The encapsulation layer encapsulates the first integrated device and the electrical device.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of non-provisional application S / N. 17 / 889,163 filed in the U.S. Patent Office on August 16, 2022, the entire contents of which are incorporated herein by reference as if fully set forth in its entirety below and for all applicable purposes.

[0003] field

[0004] Various features are directed to a package having a substrate and an integrated device.

[0005] background

[0006] A package may include a substrate and an integrated device. These components are coupled together to provide a package that can perform various electrical functions. There is a constant need to provide a package with better performance and to reduce the overall size of the package.

[0007] Overview

[0008] Various features are directed to a package having a substrate and an integrated device.

[0009] One example provides a package, which includes: a first substrate; a first integrated device coupled to the first substrate; a second substrate, the second substrate coupled to the first substrate through a first plurality of solder interconnects so that the first integrated device is located between the first substrate and the second substrate, wherein the second substrate includes a first surface and a second surface; an electrical device, the electrical device coupled to the second surface of the second substrate so that the electrical device is located between the first substrate and the second substrate; and an encapsulation layer, the encapsulation layer coupled to the first substrate and the second substrate. The encapsulation layer is located between the first substrate and the second substrate. The encapsulation layer encapsulates the first integrated device and the electrical device.

[0010] Another example provides a package, which includes: a first substrate; a first integrated device coupled to the first substrate; a second substrate, the second substrate coupled to the first substrate through a first plurality of solder interconnects so that the first integrated device is located between the first substrate and the second substrate, wherein the second substrate includes a first surface and a second surface; a passive device, the passive device coupled to the second surface of the second substrate so that the passive device is located between the first substrate and the second substrate; and an encapsulation layer, the encapsulation layer coupled to the first substrate and the second substrate. The encapsulation layer is located between the first substrate and the second substrate. The encapsulation layer encapsulates the first integrated device and the passive device.

[0011] Another example provides a package, comprising: a first substrate; a first integrated device coupled to the first substrate; a second substrate coupled to the first substrate through a first plurality of solder interconnects so that the first integrated device is located between the first substrate and the second substrate, wherein the second substrate comprises a first surface and a second surface; a second integrated device coupled to the second surface of the second substrate so that the second integrated device is located between the first substrate and the second substrate; and an encapsulation layer coupled to the first substrate and the second substrate. The encapsulation layer is located between the first substrate and the second substrate. The encapsulation layer encapsulates the first integrated device and the second integrated device.

[0012] Another example provides a method for manufacturing a package. The method provides a second substrate including a first surface and a second surface. The method couples an electrical device to the second surface of the second substrate. The method couples a first plurality of solder interconnects to the second surface of the second substrate. The method provides a first substrate and a first integrated device coupled to the first substrate. The method couples the second substrate to the first substrate via a first plurality of solder interconnects so that the first integrated device and the electrical device are located between the first substrate and the second substrate. The method forms an encapsulation layer between the first substrate and the second substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Various features, characteristics and advantages will become apparent when the detailed description set forth below is read in conjunction with the accompanying drawings in which like reference numerals designate corresponding features throughout.

[0015] Figure 1 An exemplary plan view of a substrate of a package is illustrated.

[0016] Figure 2 An exemplary plan view of another substrate of a package is illustrated.

[0017] Figure 3 An exemplary cross-sectional profile view of a package including a substrate and at least one electrical device is illustrated.

[0018] Figure 4 An exemplary cross-sectional profile view of a package including a substrate and at least one electrical device is illustrated.

[0019] Figures 5A-5C An exemplary process for fabricating a package including a substrate and at least one electrical device is illustrated.

[0020] Figure 6 An exemplary flow chart of a method for manufacturing a package including a substrate and at least one electrical device is illustrated.

[0021] Figure 7A-7B An exemplary process for manufacturing a substrate is illustrated.

[0022] Figure 8 An exemplary flow chart of a method for manufacturing a substrate is illustrated.

[0023] Fig. 9 Various electronic devices are illustrated into which the dies, electronic circuits, integrated devices, integrated passive devices (IPDs), passive components, packages, and / or device packages described herein may be integrated.

[0024] Detailed Description

[0025] In the following description, specific details are given to provide a thorough understanding of various aspects of the present disclosure. However, it will be understood by those of ordinary skill in the art that these aspects can be practiced without these specific details. For example, circuits may be shown with block diagrams to avoid burying these aspects in unnecessary details. In other examples, well-known circuits, structures, and techniques may not be shown in detail to avoid burying these aspects of the present disclosure.

[0026] The present disclosure describes a package, which includes: a first substrate; a first integrated device coupled to the first substrate; a second substrate, which is coupled to the first substrate through a first plurality of solder interconnects so that the first integrated device is located between the first substrate and the second substrate, wherein the second substrate includes a first surface and a second surface; an electrical device, which is coupled to the second surface of the second substrate so that the electrical device is located between the first substrate and the second substrate; and an encapsulation layer coupled to the first substrate and the second substrate. The encapsulation layer is located between the first substrate and the second substrate. The encapsulation layer encapsulates the first integrated device and the electrical device. The electrical device may include passive devices, active devices, chiplets, and / or integrated devices. As will be further described below, the positioning and location of the electrical device can help improve the performance of the package.

[0027] Exemplary package including a substrate and an electrical device

[0028] Figure 1 A plan view of a substrate 102 is illustrated. As will be further described below, the substrate 102 may be a bottom substrate (e.g., a first substrate) of a package. The substrate 102 includes at least one dielectric layer 120 and a plurality of interconnects 122. The plurality of interconnects 122 include a plurality of pad interconnects 130, a plurality of pad interconnects 160, and a plurality of pad interconnects 150. The plurality of pad interconnects 130 may be positioned along an edge of a periphery of the substrate 102 (e.g., a first edge of the substrate). The plurality of pad interconnects 160 may be positioned along an edge of a periphery of the substrate 102 (e.g., a second edge of the substrate). The second edge of the substrate 102 may be opposite to the first edge of the substrate 102.

[0029] Figure 1The integrated device 103, the electrical device 110, and the electrical device 112 are also illustrated. As will be further described below, when implemented within a package, the integrated device 103, the electrical device 110, and the electrical device 112 may vertically overlap the substrate 102. However, the integrated device 103, the electrical device 110, and the electrical device 112 may not vertically overlap the plurality of pad interconnects 130 and the plurality of pad interconnects 160. The plurality of pad interconnects 150 may vertically overlap the integrated device 103. The integrated device 103 may be configured to be coupled to the plurality of pad interconnects 150 of the substrate 102. As will be further described below, in some implementations, the plurality of pad interconnects 130 and the plurality of pad interconnects 160 may be configured to be coupled to a plurality of solder interconnects. Figure 1 The top metal layer of the bottom substrate of the package can be explained. That is, Figure 1 The interconnects and / or pad interconnects shown in illustrative examples may illustrate interconnects and / or pad interconnects that may be located on a top metal layer of substrate 102. The top metal of substrate 102 may represent a first metal layer (eg, M1) of substrate 102.

[0030] Figure 2 A plan view of substrate 104 is illustrated. As will be further described below, substrate 104 can be a top substrate (e.g., a second substrate) of a package. Substrate 104 includes at least one dielectric layer 140 and a plurality of interconnects 142. The plurality of interconnects 142 includes a plurality of interconnects 230, a plurality of interconnects 260, and at least one planar interconnect 250. The at least one planar interconnect 250 can be configured to provide an electrical path for grounding.

[0031] Figure 2 The metal layer of the top substrate of the package can be explained. For example, Figure 1 The interconnects shown in illustrative examples may be illustrated as interconnects that may be located on a bottom metal layer of substrate 104 or on an adjacent bottom metal layer of substrate 104 .

[0032] Figure 2 Also illustrated are integrated device 103, electrical device 110, and electrical device 112. As will be further described below, when implemented within a package, integrated device 103, electrical device 110, and electrical device 112 may vertically overlap substrate 104. However, integrated device 103, electrical device 110, and electrical device 112 may not vertically overlap the plurality of interconnects 230 and the plurality of interconnects 260. The at least one planar interconnect 250 may or may not vertically overlap integrated device 103.

[0033] Figure 3 1 illustrates a cross-sectional view of a package 300 including a substrate and at least one electrical device. The cross-sectional view shown may span Figure 1 and Figure 2AA cross section shown. Package 300 may include a package on package (PoP). Package 300 may include package 301 and package 302. Package 301 may be a first package. Package 301 may be a bottom package. Package 302 may be a second package. Package 302 may be a top package. Package 302 is coupled to package 301 via a plurality of solder interconnects 320. Package 300 is coupled to board 308 via a plurality of solder interconnects 390. Board 308 includes at least one board dielectric layer 380 and a plurality of board interconnects 382. Board 308 may include a printed circuit board (PCB). A plurality of solder interconnects 390 are coupled to a plurality of board interconnects 382 and a plurality of interconnects 122.

[0034] Package 302 includes substrate 107, integrated device 109, and encapsulation layer 192. Substrate 107 includes at least one dielectric layer 170 and a plurality of interconnects 172. Integrated device 109 is coupled to substrate 107. Adhesive 194 may be used to couple the back side of integrated device 109 to substrate 107. The back side of integrated device 109 faces substrate 107. The front side of integrated device 109 faces away from substrate 107. Integrated device 109 is configured to be electrically coupled to substrate 107 through a plurality of wire bonds 190. The plurality of wire bonds 190 are coupled to integrated device 109 and the plurality of interconnects 172. Encapsulation layer 192 encapsulates integrated device 109, the plurality of wire bonds, and adhesive 194. Encapsulation layer 192 may be coupled to integrated device 109, the plurality of wire bonds 190, and a surface of substrate 107.

[0035] Package 301 includes substrate 102, substrate 104, integrated device 103, electrical device 110, electrical device 112, and encapsulation layer 306. Substrate 102 includes at least one dielectric layer 120 and a plurality of interconnects 122. The plurality of interconnects 122 may include a plurality of pad interconnects 130, a plurality of pad interconnects 150, and a plurality of pad interconnects 160, such as at least Figure 1 The integrated device 103 is coupled to the substrate 102 through a plurality of solder interconnects 350. The integrated device 103 may be coupled to the substrate 102 through a plurality of solder pillar interconnects and a plurality of solder interconnects 350. The front side of the integrated device 103 faces the substrate 102. The back side of the integrated device 103 faces the substrate 104.

[0036] Substrate 104 includes at least one dielectric layer 140 and a plurality of interconnects 142. The plurality of interconnects 142 may include a plurality of interconnects 230, a plurality of interconnects 260, and at least one planar interconnect 250, such as at least Figure 2. The electrical device 110 is coupled to the substrate 104 via a plurality of solder interconnects 314. For example, the electrical device 110 may be coupled to the bottom side (e.g., bottom surface) of the substrate 104 via a plurality of solder interconnects 314. The electrical device 110 may include a front side and a back side. In some implementations, the front side of the electrical device 110 may face the substrate 104, and the back side of the electrical device 110 may face the substrate 102. For example, when the electrical device 110 is an integrated device or a core particle, the front side of the integrated device or core particle may face the substrate 104, and the back side of the integrated device or core particle may face the substrate 102. The electrical device 110 is coupled to the plurality of interconnects 142 via a plurality of solder interconnects 314. The electrical device 112 is coupled to the substrate 104 via a plurality of solder interconnects 316. For example, the electrical device 112 may be coupled to the bottom side (e.g., bottom surface) of the substrate 104 via a plurality of solder interconnects 316. The electrical device 112 may include a front side and a back side. In some implementations, the front side of the electrical device 112 may face the substrate 104, and the back side of the electrical device 112 may face the substrate 102. For example, when the electrical device 112 is an integrated device or die, the front side of the integrated device or die may face the substrate 104, and the back side of the integrated device or die may face the substrate 102. The electrical device 112 is coupled to the plurality of interconnects 142 through the plurality of solder interconnects 316.

[0037] The integrated device 103, the electrical device 110, and the electrical device 112 are located between the substrate 102 and the substrate 104. The encapsulation layer 306 encapsulates the integrated device 103, the electrical device 110, and the electrical device 112. The encapsulation layer 306 is located between the substrate 102 and the substrate 104. The encapsulation layer 306 is coupled to the substrate 102 and the substrate 104. For example, the encapsulation layer 306 may be coupled to a first surface (e.g., a top surface) of the substrate 102 and a second surface (e.g., a bottom surface) of the substrate 104. The encapsulation layer 306 may include a molding, a resin, and / or an epoxy resin. The encapsulation layer 306 may be a device for encapsulation. The encapsulation layer 306 may be provided by using a compression and transfer molding process, a sheet molding process, or a liquid molding process.

[0038] As follows, at least Figure 4 As further described in , the plurality of solder interconnects 330 and the plurality of solder interconnects 360 are coupled to the substrate 102 and the substrate 104. The plurality of solder interconnects 330 and the plurality of solder interconnects 360 may be located along the periphery of the package 300. The plurality of solder interconnects 330 and the plurality of solder interconnects 360 may be coupled to the plurality of interconnects 122 of the substrate 102 and the plurality of interconnects 142 of the substrate 104. The plurality of solder interconnects 330 and the plurality of solder interconnects 360 may be located in the encapsulation layer 306. Thus, the encapsulation layer 306 may encapsulate the plurality of solder interconnects 330 and the plurality of solder interconnects 360.

[0039] As described above, package 302 is coupled to package 301 through a plurality of solder interconnects 320. The plurality of solder interconnects 320 are located between substrate 104 and substrate 107. The plurality of solder interconnects 320 are coupled to the plurality of interconnects 172 of substrate 107 and the plurality of interconnects 142 of substrate 104.

[0040] The electrical device 110 and / or the electrical device 112 may include passive devices and / or active devices. For example, the electrical device 110 and / or the electrical device 112 may include a capacitor and / or an inductor. The electrical device 110 and / or the electrical device 112 may include a trench capacitor (e.g., a deep trench capacitor formed in a silicon die). The electrical device 110 and / or the electrical device 112 may include an integrated device and / or a core particle. The electrical device 110 and / or the electrical device 112 may include a silicon die. As mentioned above, the electrical device 110 and / or the electrical device 112 may be coupled to the substrate 104 so that the front side of the electrical device 110 and / or the front side of the electrical device 112 face the substrate 104. The electrical device 110 and / or the electrical device 112 may be configured to be electrically coupled to a power distribution network (PDN). The electrical device 110 and / or the electrical device 112 may be configured to be electrically coupled to a power supply and / or ground.

[0041] Figure 4 1 illustrates a cross-sectional view of a package 300 including a substrate and at least one electrical device. The cross-sectional view shown may span Figure 1 and Figure 2 BB cross section shown.

[0042] like Figure 4 As shown in FIG. 1 , package 300 may include package 301 and package 302. Package 301 includes substrate 102, substrate 104, integrated device 103, multiple solder interconnects 330, multiple solder interconnects 360, and encapsulation layer 306. Package 301 also includes at least Figure 3 The electrical device 110 and the electrical device 112 are shown and described in FIG.

[0043] The plurality of solder interconnects 330 may be configured to be coupled to the plurality of pad interconnects 130, such as Figure 1 The plurality of solder interconnects 360 may be configured to be coupled to the plurality of pad interconnects 160, such as Figure 1 As shown and described, the plurality of pad interconnects 130 and the plurality of pad interconnects 160 may be part of the plurality of interconnects 122 of the substrate 102 .

[0044] The integrated device 103 is configured to be electrically coupled to the electrical device 110 and / or the electrical device 112. For example, the integrated device 103 is configured to be electrically coupled to the electrical device 110 through at least one electrical path, the at least one electrical path including: (i) at least one solder interconnection in the plurality of solder interconnections 350, (ii) at least one interconnection in the plurality of interconnections 122, (iii) at least one solder interconnection in the plurality of solder interconnections 330, (iv) at least one interconnection in the plurality of interconnections 142, and (v) at least one solder interconnection in the plurality of solder interconnections 314.

[0045] In some implementations, the integrated device 103 is configured to be electrically coupled to the electrical device 110 via at least one electrical path that includes: (i) at least one solder interconnect in the plurality of solder interconnects 350, (ii) at least one interconnect in the plurality of interconnects 122, (iii) at least one solder interconnect in the plurality of solder interconnects 360, (iv) at least one interconnect in the plurality of interconnects 142, and (v) at least one solder interconnect in the plurality of solder interconnects 314.

[0046] In some implementations, the integrated device 103 is configured to be electrically coupled to the electrical device 112 via at least one electrical path that includes: (i) at least one solder interconnect in the plurality of solder interconnects 350, (ii) at least one interconnect in the plurality of interconnects 122, (iii) at least one solder interconnect in the plurality of solder interconnects 330, (iv) at least one interconnect in the plurality of interconnects 142, and (v) at least one solder interconnect in the plurality of solder interconnects 316.

[0047] In some implementations, the integrated device 103 is configured to be electrically coupled to the electrical device 112 via at least one electrical path that includes: (i) at least one solder interconnect in the plurality of solder interconnects 350, (ii) at least one interconnect in the plurality of interconnects 122, (iii) at least one solder interconnect in the plurality of solder interconnects 360, (iv) at least one interconnect in the plurality of interconnects 142, and (v) at least one solder interconnect in the plurality of solder interconnects 316.

[0048] In some implementations, the integrated device 103 is configured to be electrically coupled to the integrated device 109 via at least one electrical path that includes: (i) at least one solder interconnect of the plurality of solder interconnects 350, (ii) at least one interconnect of the plurality of interconnects 122, (iii) at least one solder interconnect of the plurality of solder interconnects 330, (iv) at least one interconnect of the plurality of interconnects 142, (v) at least one solder interconnect of the plurality of solder interconnects 320, (vi) at least one interconnect of the plurality of interconnects 172, and (vii) at least one wire bond of the plurality of wire bonds 190.

[0049] In some implementations, the integrated device 103 is configured to be electrically coupled to the integrated device 109 via at least one electrical path that includes: (i) at least one solder interconnect among the plurality of solder interconnects 350, (ii) at least one interconnect among the plurality of interconnects 122, (iii) at least one solder interconnect among the plurality of solder interconnects 360, (iv) at least one interconnect among the plurality of interconnects 142, (v) at least one solder interconnect among the plurality of solder interconnects 320, (vi) at least one interconnect among the plurality of interconnects 172, and (vii) at least one wire bond among the plurality of wire bonds 190.

[0050] In some implementations, electrical device 110 is configured to be electrically coupled to integrated device 109 via at least one electrical path that includes: (i) at least one solder interconnect among plurality of solder interconnects 314, (ii) at least one interconnect among plurality of interconnects 142, (iii) at least one solder interconnect among plurality of solder interconnects 320, (iv) at least one interconnect among plurality of interconnects 172, and (v) at least one wire bond among plurality of wire bonds 190.

[0051] In some implementations, electrical device 112 is configured to be electrically coupled to integrated device 109 via at least one electrical path that includes: (i) at least one solder interconnect from plurality of solder interconnects 316, (ii) at least one interconnect from plurality of interconnects 142, (iii) at least one solder interconnect from plurality of solder interconnects 320, (iv) at least one interconnect from plurality of interconnects 172, and (v) at least one wire bond from plurality of wire bonds 190.

[0052] Figure 1-Figure 4 The configuration shown in provides several advantages for the package. First, positioning the electrical device in a manner that couples the electrical device (e.g., 110, 112) to the bottom surface of the top substrate helps maintain the package form factor because the electrical device occupies space in the encapsulation layer that would not otherwise be used. Therefore, more capabilities and functionality can be added to the package, and / or the performance of the package can be improved while still maintaining the form factor of the package. Second, the location and positioning of the electrical device helps improve signal connectivity (e.g., input / output signal connectivity) with other integrated devices (e.g., 103, 109) because the electrical device can be located closer to the other integrated devices, thereby providing a shorter electrical path between the electrical device and the other integrated devices. Third, the location and positioning of the electrical device helps improve power delivery to the packaged integrated devices because the electrical device can be located closer to the integrated devices (e.g., 103, 109). Fourth, since the electrical device is located in the encapsulation layer, it is easy to detect whether the electrical device has been tampered with after the package is manufactured.

[0053] The integrated device (e.g., 103, 109) may include a die (e.g., a bare semiconductor die). The integrated device may include a power management integrated circuit (PMIC). The integrated device may include an application processor. The integrated device may include a modem. The integrated device may include a radio frequency (RF) device, a passive device, a filter, a capacitor, an inductor, an antenna, a transmitter, a receiver, an integrated device based on gallium arsenide (GaAs), a surface acoustic wave (SAW) filter, a bulk acoustic wave (BAW) filter, a light emitting diode (LED) integrated device, a silicon (Si)-based integrated device, a silicon carbide (SiC)-based integrated device, a memory, a power management processor, and / or a combination thereof. The integrated device (e.g., 103, 109) may include at least one electronic circuit (e.g., a first electronic circuit, a second electronic circuit, etc.). The integrated device may include a transistor. The integrated device may be an example of an electrical device and / or an electrical device. In some implementations, the integrated device may be a core particle. The core particles may be manufactured using a technology node. Different core particles may be manufactured using different technology nodes. A technology node may refer to a specific manufacturing process and / or technology used to manufacture an integrated device and / or a core particle. A technology node may specify the smallest possible size that can be manufactured (e.g., the size of a transistor, the width of a trace, the gap between two transistors). Different technology nodes may have different yield losses. Different technology nodes may have different costs. Technology nodes that produce components with fine details (e.g., traces, transistors) are more expensive and have higher yield losses than technology nodes that produce components with less fine details (e.g., traces, transistors). Different core particles may have different sizes and / or shapes. Different core particles may be configured to provide different functions. Different core particles may have different interconnect densities (e.g., interconnects with different widths and / or spacings). In some implementations, several core particles may be used to perform the functionality of one or more chips (e.g., one or more integrated devices). Relative to using a single chip to perform all functions of a package, using several core particles that perform several functions can reduce the overall cost of the package by optimizing the technology node to be used for a particular core particle. Thus, a core particle may be manufactured using a first technology node, while a second core particle may be manufactured using a second technology node. This situation may occur when a die does not necessarily need to be manufactured using the most advanced available technology node. Instead, putting all the functions of a package in an integrated device means using one technology node. Therefore, functions that could have been manufactured using a less advanced technology node are manufactured using a more expensive technology node with potentially higher yield losses, which increases the overall cost of the integrated device.

[0054] In one example, an integrated device configured to provide a computing application may be manufactured using a first technology node (e.g., the most advanced technology node), and at least one core configured to provide other functionality may be manufactured using a second technology node, wherein the second technology node is less expensive than the first technology node, and wherein the second technology node manufactures components (e.g., interconnects, traces, transistors) having a minimum size that is greater than the minimum size of components manufactured using the first technology node (e.g., interconnects, traces, and transistors). Examples of computing applications may include high performance computing and / or high performance processing, which may be achieved by manufacturing and packaging as many transistors as possible in the integrated device, which is why the integrated device configured for the computing application may be manufactured using the most advanced technology node available, while other cores may be manufactured using less advanced technology nodes because those cores may not require as many transistors to be manufactured in the core. Therefore, the combination of using different technology nodes (which may have different associated yield losses) for different integrated devices and / or cores may reduce the overall cost of the package compared to using a single integrated device to perform all functions of the package.

[0055] In some implementations, an integrated device (e.g., 103) may include a plurality of die interconnects having a first minimum spacing, and a core particle may include a plurality of interconnects having a second minimum spacing. In some implementations, an integrated device (e.g., 103) may include a first plurality of transistors having a first minimum spacing, and a core particle may include a second plurality of transistors having a second minimum spacing. In some implementations, the first minimum spacing is less than the second minimum spacing. A core particle may include a passive device or an active device.

[0056] The package (e.g., 300, 301, 302) may be implemented in a radio frequency (RF) package. The RF package may be a radio frequency front end (RFFE) package. The package (e.g., 300, 301, 302) may be configured to provide wireless fidelity (WiFi) communications and / or cellular communications (e.g., 2G, 3G, 4G, 5G). The package (e.g., 300, 301, 302) may be configured to support a global system for mobile communications (GSM), a universal mobile telecommunications system (UMTS), and / or long term evolution (LTE). The package (e.g., 100, 200) may be configured to transmit and receive signals having different frequencies and / or communication protocols.

[0057] Having described various interconnect dies, processes for fabricating the interconnect dies will now be described below.

[0058] Exemplary process for manufacturing a package including a substrate and an electrical device

[0059] In some implementations, manufacturing the package includes several processes. Figure 5A-5CExemplary processes for providing or manufacturing a package are described. In some implementations, Figures 5A-5C The process may be used to provide or manufacture package 300. However, Figures 5A-5C The process may be used to manufacture any package described in this disclosure.

[0060] It should be noted that Figures 5A-5C The process of one or more stages may be combined to simplify and / or clarify the process for providing or manufacturing a package. In some implementations, the order of the processes may be changed or modified. In some implementations, one or more processes may be replaced or substituted without departing from the scope of the present disclosure.

[0061] like Figure 5A As shown in FIG. 1 , stage 1 illustrates a state after providing a substrate 104. The substrate 104 includes at least one dielectric layer 140 and a plurality of interconnects 142. The substrate 104 may include a first surface (e.g., bottom surface, top surface) and a second surface (e.g., top surface, bottom surface). The substrate 104 may be formed using a substrate such as Figure 7A-7B In some implementations, a core substrate (eg, a substrate including a core layer) is provided.

[0062] Stage 2 illustrates a state after the electrical device 110 is coupled to the second surface (e.g., bottom surface) of the substrate 104. The electrical device 110 may be coupled to the substrate 104 via a plurality of solder interconnects 314. A solder reflow process may be used to couple the electrical device 110 to the substrate 104. Stage 2 also illustrates a state after the electrical device 112 is coupled to the second surface (e.g., bottom surface) of the substrate 104. The electrical device 112 may be coupled to the substrate 104 via a plurality of solder interconnects 316. A solder reflow process may be used to couple the electrical device 112 to the substrate 104.

[0063] Stage 3 illustrates a state after coupling a plurality of solder interconnects 330 to a second surface (e.g., bottom surface) of the substrate 104. The plurality of solder interconnects 330 may be coupled to the plurality of interconnects 142 of the substrate 104. A solder reflow process may be used to couple the plurality of solder interconnects 330 to the substrate 104. Stage 3 also illustrates a state after coupling a plurality of solder interconnects 360 to a second surface (e.g., bottom surface) of the substrate 104. The plurality of solder interconnects 360 may be coupled to the plurality of interconnects 142 of the substrate 104. A solder reflow process may be used to couple the plurality of solder interconnects 360 to the substrate 104.

[0064] like Figure 5BAs shown in FIG. 4 , stage 4 illustrates a state after providing a substrate 102 and an integrated device 103. The substrate 102 includes at least one dielectric layer 120 and a plurality of interconnects 122. The substrate 102 may include a first surface (e.g., bottom surface, top surface) and a second surface (e.g., top surface, bottom surface). The substrate 102 may be provided using a Figure 7A-7B 102. In some implementations, a core substrate (e.g., a substrate including a core layer) is provided. The integrated device 103 can be coupled to a first surface (e.g., a top surface) of the substrate 102. The integrated device 103 can be coupled to the substrate 102 via a plurality of solder interconnects 350. The integrated device 103 can be coupled to the substrate 102 via a plurality of solder pillar interconnects and a plurality of solder interconnects 350. A solder reflow process can be used to couple the integrated device 103 to the substrate 102.

[0065] Stage 5 illustrates a state after the substrate 104 is coupled to the substrate 102 through the plurality of solder interconnects 330 and the plurality of solder interconnects 360. A solder reflow process may be used to couple the substrate 104 to the substrate 102. After the substrate 104 is coupled to the substrate 102, the integrated device 103, the electrical device 110, and the electrical device 112 may be located between the substrate 102 and the substrate 104. The substrate 104 may be configured to be electrically coupled to the substrate 102 through the plurality of solder interconnects 330 and the plurality of solder interconnects 360.

[0066] Stage 6 illustrates a state after providing encapsulation layer 306 between substrate 102 and substrate 104. Encapsulation layer 306 can encapsulate integrated device 103, electrical device 110, and electrical device 112. Encapsulation layer 306 can be coupled to a first surface of substrate 102 and a second surface of substrate 104. Encapsulation layer 306 can include a molding, a resin, and / or an epoxy resin. Encapsulation layer 306 can be a device for encapsulation. Encapsulation layer 306 can be provided by using a compression and transfer molding process, a sheet molding process, or a liquid molding process. Stage 6 can illustrate package 301 as described above.

[0067] like Figure 5C , stage 7 illustrates a state after coupling package 302 to package 301. Package 302 includes substrate 107, integrated device 109, multiple wire bonds 190, and encapsulation layer 192. Substrate 107 includes at least one dielectric layer 170 and multiple interconnects 172. Package 302 is coupled to package 301 through multiple solder interconnects 320. A solder reflow process may be used to couple package 302 to package 301. Multiple solder interconnects 320 may be coupled to multiple interconnects 172 of substrate 107 and multiple interconnects 142 of substrate 104.

[0068] Stage 8 illustrates a state after coupling the plurality of solder interconnects 390 to the substrate 102. The plurality of solder interconnects 390 may be coupled to a second surface (e.g., a bottom surface) of the substrate 102. A solder reflow process may be used to couple the plurality of solder interconnects 390 to the plurality of interconnects 122 of the substrate 102. Stage 8 may illustrate a package 300 including a package 301 and a package 302.

[0069] Exemplary flow chart of a method for manufacturing a package including a substrate and an electrical device

[0070] In some implementations, manufacturing the package includes several processes. Figure 6 An exemplary flow chart of a method 600 for providing or manufacturing a package is illustrated. In some implementations, Figure 6 The method 600 may be used to provide or manufacture the package 300 described in the present disclosure. However, the method 600 may be used to provide or manufacture any package described in the present disclosure.

[0071] It should be noted that Figure 6 The method 600 may combine one or more processes to simplify and / or clarify the method for providing or manufacturing a package. In some implementations, the order of the processes may be changed or modified.

[0072] The method provides (at 605) a substrate (e.g., 104) including a first surface and a second surface. The substrate 104 may be a second substrate. The substrate 104 includes at least one dielectric layer 140 and a plurality of interconnects 142. The substrate 104 may include a first surface (e.g., bottom surface, top surface) and a second surface (e.g., top surface, bottom surface). The substrate 104 may be formed using a dielectric layer such as Figure 7A-7B In some implementations, a core substrate (eg, a substrate including a core layer) is provided. Figure 5A Stage 1 of the present invention illustrates and describes an example of a substrate having a first surface and a second surface.

[0073] The method (at 610) couples at least one electrical device and solder interconnects to the substrate. For example, the method may couple the electrical device 110, the electrical device 112, and a plurality of solder interconnects (e.g., 330, 360) to the second surface of the substrate 104. The electrical device may include a passive device and / or an active device. The electrical device may include an integrated device. The electrical device may include a passive integrated device. The electrical device may include a core particle. The electrical device may include a trench capacitor (e.g., a deep trench capacitor in a tube die). The electrical device 110 may be coupled to the substrate 104 via a plurality of solder interconnects 314. A solder reflow process may be used to couple the electrical device 110 to the substrate 104. The electrical device 112 may be coupled to the substrate 104 via a plurality of solder interconnects 316. A solder reflow process may be used to couple the electrical device 112 to the substrate 104.

[0074] A plurality of solder interconnects 330 may be coupled to a second surface (e.g., bottom surface) of the substrate 104. The plurality of solder interconnects 330 may be coupled to the plurality of interconnects 142 of the substrate 104. A solder reflow process may be used to couple the plurality of solder interconnects 330 to the substrate 104. A plurality of solder interconnects 360 may be coupled to a second surface (e.g., bottom surface) of the substrate 104. The plurality of solder interconnects 360 may be coupled to the plurality of interconnects 142 of the substrate 104. A solder reflow process may be used to couple the plurality of solder interconnects 360 to the substrate 104. Figure 5A Stages 2 and 3 illustrate and describe examples of an electrical device and multiple solder interconnects coupled to a substrate.

[0075] The method provides (at 615) another substrate with an integrated device. A substrate 102 and an integrated device 103 may be provided. The substrate 102 may be a first substrate. The substrate 102 includes at least one dielectric layer 120 and a plurality of interconnects 122. The substrate 102 may include a first surface (e.g., bottom surface, top surface) and a second surface (e.g., top surface, bottom surface). The substrate 102 may be formed using a dielectric layer such as Figure 7A-7B 102. In some implementations, a core substrate (e.g., a substrate including a core layer) is provided. The integrated device 103 can be coupled to a first surface (e.g., a top surface) of the substrate 102. The integrated device 103 can be coupled to the substrate 102 via a plurality of solder interconnects 350. The integrated device 103 can be coupled to the substrate 102 via a plurality of solder pillar interconnects and a plurality of solder interconnects 350. A solder reflow process can be used to couple the integrated device 103 to the substrate 102. Figure 5B Stage 4 illustrates and describes an example of providing a substrate and an integrated device.

[0076] The method couples the substrate to another substrate (at 620). For example, the substrate 104 may be configured to be coupled to the substrate 102 via a plurality of solder interconnects 330 and a plurality of solder interconnects 360. A solder reflow process may be used to couple the substrate 104 to the substrate 102. After the substrate 104 is coupled to the substrate 102, the integrated device 103, the electrical device 110, and the electrical device 112 may be located between the substrate 102 and the substrate 104. The substrate 104 may be configured to be electrically coupled to the substrate 102 via a plurality of solder interconnects 330 and a plurality of solder interconnects 360. Figure 5B Stage 5 of the present invention illustrates and describes an example of coupling a substrate to another substrate.

[0077] The method forms an encapsulation layer between the substrate and another substrate (at 625). For example, encapsulation layer 306 can be formed between substrate 102 and substrate 104. Encapsulation layer 306 can encapsulate integrated device 103, electrical device 110, and electrical device 112. Encapsulation layer 306 can be coupled to a first surface of substrate 102 and a second surface of substrate 104. Encapsulation layer 306 can include a molding, a resin, and / or an epoxy resin. Encapsulation layer 306 can be an encapsulation device. Encapsulation layer 306 can be provided by using a compression and transfer molding process, a sheet molding process, or a liquid molding process. Figure 5B Stage 6 illustrates and describes an example of an encapsulation layer provided between two substrates.

[0078] The method couples (at 630) an integrated device or package to another package. For example, the method may couple (at 630) package 302 to a first surface of substrate 104 of package 301. Package 302 includes substrate 107, integrated device 109, a plurality of wire bonds 190, and encapsulation layer 192. . Substrate 107 includes at least one dielectric layer 170 and a plurality of interconnects 172. Package 302 is coupled to package 301 via a plurality of solder interconnects 320. A solder reflow process may be used to couple package 302 to package 301. The plurality of solder interconnects 320 may be coupled to the plurality of interconnects 172 of substrate 107 and the plurality of interconnects 142 of substrate 104. Figure 5C Stage 7 illustrates and describes the state after the package is coupled to the substrate of another package.

[0079] The method couples (at 635) a plurality of solder interconnects to the substrate of the package. For example, a plurality of solder interconnects 390 may be coupled to a second surface (e.g., bottom surface) of the substrate 102 of the package 301. A solder reflow process may be used to couple the plurality of solder interconnects 390 to the plurality of interconnects 122 of the substrate 102. Figure 5C Stage 8 illustrates and describes an example of multiple solder interconnects coupled to a substrate.

[0080] In some implementations, several packages are manufactured simultaneously on a wafer. In such cases, the method may singulate the packages (eg, 300, 301, 302).

[0081] Exemplary Process for Making a Substrate

[0082] In some implementations, manufacturing the substrate includes several processes. Figure 7A-7B Exemplary processes for providing or manufacturing a substrate are described. In some implementations, Figure 7A-7B The process may be used to provide or manufacture the substrate 102. However, Figure 7A-7B The process may be used to manufacture any substrate (eg, 104, 107) described in the present disclosure.

[0083] It should be noted that Figure 7A-7B The process of one or more stages can be combined to simplify and / or illustrate the process for providing or manufacturing a substrate. In some implementations, the order of each process can be changed or modified. In some implementations, one or more processes can be replaced or substituted without departing from the scope of the present disclosure.

[0084] like Fig. 7A As shown in , stage 1 illustrates a state after providing a carrier 700. A seed layer 701 and an interconnect 702 may be located on the carrier 700. The interconnect 702 may be located on the seed layer 701. The interconnect 702 may be formed using a plating process and an etching process. In some implementations, the carrier 700 may be provided with a seed layer 701 and a metal layer that is patterned to form the interconnect 702. The interconnect 702 may represent at least some of the plurality of interconnects 122.

[0085] Stage 2 illustrates a state after a dielectric layer 720 is formed over the carrier 700, the seed layer 701, and the interconnect 702. The dielectric layer 720 may be formed using a deposition and / or lamination process. The dielectric layer 720 may include prepreg and / or polyimide. The dielectric layer 720 may include a photoimageable dielectric. However, different implementations may use different materials for the dielectric layer.

[0086] Stage 3 illustrates a state after a plurality of cavities 710 are formed in the dielectric layer 720. The plurality of cavities 710 may be formed using an etching process (eg, a photolithography process) or a laser process.

[0087] Stage 4 illustrates a state after interconnects 712 are formed in and over dielectric layer 720, including in and over plurality of cavities 710. For example, vias, pads, and / or traces may be formed. A plating process may be used to form the interconnects.

[0088] Stage 5 illustrates a state after dielectric layer 722 is formed over dielectric layer 720 and interconnect 712. Dielectric layer 722 may be formed using a deposition and / or lamination process. Dielectric layer 722 may include prepreg and / or polyimide. Dielectric layer 722 may include a photoimageable dielectric. However, different implementations may use different materials for the dielectric layer.

[0089] like Figure 7B , stage 6 illustrates a state after a plurality of cavities 730 are formed in the dielectric layer 722. The plurality of cavities 730 may be formed using an etching process (eg, a photolithography process) or a laser process.

[0090] Stage 7 illustrates a state after interconnects 714 are formed in and over dielectric layer 722, including in and over plurality of cavities 730. For example, vias, pads, and / or traces may be formed. A plating process may be used to form the interconnects.

[0091] Stage 8 illustrates a state after decoupling (e.g., separating, removing, grinding away) the carrier 700 from the at least one dielectric layer 120 and the seed layer 701, removing (e.g., etching away) portions of the seed layer 701, thereby leaving the substrate 102 including the at least one dielectric layer 120 and the plurality of interconnects 122. The at least one dielectric layer 120 may represent dielectric layer 720 and / or dielectric layer 722. The plurality of interconnects 122 may represent interconnects 702, 712, and / or 714.

[0092] Different implementations may use different processes to form the metal layer(s) and / or interconnects. In some implementations, the metal layer(s) may be formed using a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, a sputtering process, a spraying process, and / or a plating process.

[0093] Exemplary Flowchart of a Method for Manufacturing a Substrate

[0094] In some implementations, manufacturing the substrate includes several processes. Figure 8 An exemplary flow chart of a method 800 for providing or manufacturing a substrate is illustrated. In some implementations, Figure 8 The method 800 may be used to provide or manufacture the substrate(s) of the present disclosure. For example, Figure 8 The method 800 may be used to manufacture the substrate 102 .

[0095] It should be noted that Figure 8 The method 800 may combine one or more processes to simplify and / or clarify the method for providing or manufacturing a substrate. In some implementations, the order of the processes may be changed or modified.

[0096] The method provides (at 805) a carrier (e.g., 700). Different implementations may use different materials for the carrier 700. The carrier 700 may include a seed layer (e.g., 701). The seed layer 701 may include a metal (e.g., copper). The carrier may include a substrate, glass, quartz, and / or a carrier tape. Fig. 7A Stage 1 of the present invention illustrates and describes an example of a carrier provided with a seed layer.

[0097] The method forms (at 810) interconnects over the carrier 700 and the seed layer 701 and patterns them. The metal layer may be patterned to form the interconnects. A plating process may be used to form the metal layer and the interconnects. In some implementations, the carrier and the seed layer may include a metal layer. The metal layer is located over the seed layer, and the metal layer may be patterned to form the interconnects (e.g., 122). Fig. 7A Stage 1 of the present invention illustrates and describes an example of forming and patterning interconnects over a seed layer and a carrier.

[0098] The method forms / provides (at 815) a dielectric layer 720 over the seed layer 701, the carrier 700, and the interconnect 702. The dielectric layer 720 may be formed using a deposition and / or lamination process. The dielectric layer 720 may include prepreg and / or polyimide. The dielectric layer 720 may include a photoimageable dielectric. Forming the dielectric layer 720 may also include forming a plurality of cavities (e.g., 710) in the dielectric layer 720. The plurality of cavities may be formed using an etching process (e.g., photolithography) or a laser process. Fig. 7A Stages 2-3 of FIG. 1 illustrate and describe an example of forming a dielectric layer and forming a cavity in the dielectric layer.

[0099] The method forms (at 820) interconnects in and on the dielectric layer. For example, interconnect 712 may be formed in and on dielectric layer 720. A plating process may be used to form the interconnects. Forming the interconnects may include providing a patterned metal layer on and / or in the dielectric layer. Forming the interconnects may also include forming the interconnects in a cavity of the dielectric layer. Fig. 7A Stage 4 of the present invention illustrates and describes an example of forming interconnects in and above a dielectric layer.

[0100] The method forms / provides (at 825) a dielectric layer 722 over the dielectric layer 720 and the interconnect 712. The dielectric layer 722 may be formed using a deposition and / or lamination process. The dielectric layer 722 may include prepreg and / or polyimide. The dielectric layer 722 may include a photoimageable dielectric. Forming the dielectric layer 722 may also include forming a plurality of cavities (e.g., 730) in the dielectric layer 722. The plurality of cavities may be formed using an etching process (e.g., photolithography) or a laser process. Figure 7A-7B Stages 5-6 of FIG. 1 illustrate and describe an example of forming a dielectric layer and forming a cavity in the dielectric layer.

[0101] The method forms (at 830) interconnects in and on the dielectric layer. For example, interconnect 714 may be formed in and on dielectric layer 722. A plating process may be used to form the interconnects. Forming the interconnects may include providing a patterned metal layer on and / or in the dielectric layer. Forming the interconnects may also include forming the interconnects in a cavity of the dielectric layer. Figure 7B Stage 7 of illustrative embodiments illustrates and describes an example of forming interconnects in and over a dielectric layer.

[0102] The method decouples (at 835) the carrier (e.g., 700) from the seed layer (e.g., 701). The carrier 700 may be separated and / or ground away. The method may also remove (at 835) portions of the seed layer (e.g., 701). Portions of the seed layer 701 may be removed using an etching process. Figure 7B Stage 8 illustrates and describes an example of decoupling the carrier and seed layer removal.

[0103] Different implementations may use different processes to form the metal layer(s). In some implementations, the metal layer(s) may be formed using a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, a sputtering process, a spraying process, and / or a plating process.

[0104] Exemplary Electronic Devices

[0105] Fig. 9 Various electronic devices that may be integrated with any of the aforementioned devices, integrated devices, integrated circuit (IC) packages, integrated circuit (IC) devices, semiconductor devices, integrated circuits, dies, interposers, packages, package-on-package (PoP), system-in-package (SiP), or systems-on-chip (SoC) are illustrated. For example, a mobile phone device 902, a laptop computer device 904, a fixed location terminal device 906, a wearable device 908, or a motor vehicle 910 may include a device 900 as described herein. The device 900 may be, for example, any of the devices and / or integrated circuit (IC) packages described herein. Fig. 9 The devices 902, 904, 906, and 908, and the vehicle 910 illustrated in the figure are merely exemplary. Other electronic devices can also feature the device 900, including, but not limited to, a group of devices (e.g., electronic devices) including: mobile devices, handheld personal communication system (PCS) units, portable data units (such as personal digital assistants), devices enabled with a global positioning system (GPS), navigation devices, set-top boxes, music players, video players, entertainment units, fixed location data units (such as meter reading equipment), communication devices, smart phones, tablet computers, computers, wearable devices (e.g., watches, glasses), Internet of Things (IoT) devices, servers, routers, electronic devices implemented in motor vehicles (e.g., autonomous vehicles), or any other device that stores or retrieves data or computer instructions, or any combination thereof.

[0106] Figure 1-4 , 5A-5C, 6, 7A-7B and / or 8-9, one or more of the components, processes, features, and / or functions illustrated in the drawings may be rearranged and / or combined into a single component, process, feature, or function, or implemented in several components, processes, or functions. Additional elements, components, processes, and / or functions may also be added without departing from the present disclosure. It should also be noted that Figure 1-4 , 5A-5C, 6, 7A-7B, and 8-9 and their corresponding descriptions in this disclosure are not limited to die and / or IC. In some implementations, Figure 1-4, 5A-5C, 6, 7A-7B, and 8-9 and their corresponding descriptions may be used to manufacture, create, provide, and / or produce devices and / or integrated devices. In some implementations, the device may include a die, an integrated device, an integrated passive device (IPD), a die package, an integrated circuit (IC) device, a device package, an integrated circuit (IC) package, a wafer, a semiconductor device, a package-on-package (PoP) device, a heat sink, and / or an interposer.

[0107] Note that the drawings in this disclosure may represent actual representations and / or conceptual representations of various components, assemblies, objects, devices, packages, integrated devices, integrated circuits, and / or transistors. In some instances, the drawings may not be to scale. In some instances, for clarity, not all components and / or parts are shown. In some instances, the positioning, location, size, and / or shape of the various components and / or assemblies in the drawings may be exemplary. In some implementations, the various components and / or parts in the drawings may be optional.

[0108] The wording "exemplary" is used herein to mean "serving as an example, instance, or illustration". Any implementation or aspect described herein as "exemplary" is not necessarily to be interpreted as superior or superior to other aspects of the present disclosure. Likewise, the term "aspect" does not require that all aspects of the present disclosure include the features, advantages, or modes of operation discussed. The term "coupled" is used herein to refer to a direct or indirect coupling (e.g., mechanical coupling) between two objects. For example, if object A physically contacts object B, and object B contacts object C, objects A and C can still be considered to be coupled to each other - even if they are not in direct physical contact with each other. Object A coupled to object B may be coupled to at least a portion of object B. The term "electrically coupled" may mean that two objects are coupled together directly or indirectly so that an electric current (e.g., signal, power, ground) can be transferred between the two objects. Two electrically coupled objects may or may not have an electric current transfer between the two objects. The use of the terms "first", "second", "third", and "fourth" (and / or anything higher than the fourth) is arbitrary. Any component described may be a first component, a second component, a third component, or a fourth component. For example, the component referred to as the second component may be the first component, the second component, the third component, or the fourth component. The terms "encapsulate", "encapsulate" and / or any derivatives thereof refer to an object that may partially encapsulate or completely encapsulate another object. The terms "top" and "bottom" are arbitrary. A component located at the top may be located above a component located at the bottom. A top component may be considered a bottom component, and vice versa. As described in the present disclosure, a first component located "above" a second component may mean that the first component is located above or below the second component, depending on how the bottom or top is arbitrarily defined. In another example, a first component may be located above (e.g., above) a first surface of a second component, and a third component may be located above (e.g., below) a second surface of the second component, wherein the second surface is opposite to the first surface. Further note that the term "above" as used in the context of a component being located above another component in the present application may be used to indicate that a component is on and / or in another component (e.g., on the surface of a component or embedded in a component). Thus, for example, a first component being above a second component may mean: (1) the first component is above the second component, but not directly contacting the second component; (2) the first component is on the second component (e.g., on the surface of the second component); and / or (3) the first component is in the second component (e.g., embedded in the second component). A first component that is "in" a second component may be partially in the second component or completely in the second component. A value of about X-XX may mean a value between X and XX (inclusive). The value(s) between X and XX may be discrete or continuous. As used in the present disclosure, the term "about 'value X'" or "approximately value X" means within ten percent of 'value X'.For example, a value of about 1 or approximately 1 would mean a value in the range of 0.9-1.1.

[0109] In some implementations, interconnection is an element or component that allows or facilitates electrical connection between two points, elements and / or components in a device or package. In some implementations, interconnection may include traces (e.g., trace interconnection), through holes (e.g., through hole interconnection), pads (e.g., pad interconnection), solder pillars, metallization layers, redistribution layers, and / or under bump metallization (UBM) layers / interconnection. In some implementations, interconnection may include conductive materials that can be configured to provide electrical paths for signals (e.g., data signals), grounding and / or power. Interconnection may include more than one element or component. Interconnection may be defined by one or more interconnections. Interconnection may include one or more metal layers. Interconnection may be part of a circuit. Different implementations may use different processes and / or procedures to form interconnection. In some implementations, chemical vapor deposition (CVD) processes, physical vapor deposition (PVD) processes, sputtering processes, spraying, and / or electroplating processes may be used to form interconnection.

[0110] It should also be noted that the various disclosures contained herein may be described as processes depicted as flow charts, flow diagrams, structure diagrams, or block diagrams. Although a flow chart may describe an operation as a sequential process, many operations may be performed in parallel or concurrently. In addition, the order of the operations may be rearranged. A process terminates when its operations are completed.

[0111] Further examples are described below to facilitate understanding of the present disclosure.

[0112] Aspect 1: A package includes: a first substrate; a first integrated device coupled to the first substrate; a second substrate coupled to the first substrate through a first plurality of solder interconnects so that the first integrated device is located between the first substrate and the second substrate, wherein the second substrate includes a first surface and a second surface; an electrical device coupled to the second surface of the second substrate so that the electrical device is located between the first substrate and the second substrate; and an encapsulation layer coupled to the first substrate and the second substrate. The encapsulation layer is located between the first substrate and the second substrate. The encapsulation layer encapsulates the first integrated device and the electrical device.

[0113] Aspect 2: The package according to aspect 1, wherein the electrical device comprises a passive device or an active device.

[0114] Aspect 3: The package of aspect 2, wherein the passive device comprises an inductor or a capacitor.

[0115] Aspect 4: A package as in aspects 2 to 3, wherein the passive device comprises a silicon die.

[0116] Aspect 5: The package of aspects 2 to 4, wherein the passive device comprises a trench capacitor.

[0117] Aspect 6: The package of aspects 1 to 5, wherein the electrical device comprises a second integrated device

[0118] Aspect 7: A package as in aspects 1 to 6, wherein the electrical device is configured to be electrically coupled to the first integrated device through an electrical path, the electrical path comprising at least one interconnect from the second substrate, at least one solder interconnect from the first plurality of solder interconnects, and at least one interconnect from the first substrate.

[0119] Aspect 8: A package as in Aspects 1 to 7, further comprising a second electrical device coupled to a second surface of a second substrate, wherein the second electrical device is configured to be electrically coupled to the first integrated device via a second electrical path, the second electrical path comprising at least one second interconnect from the second substrate, at least one second solder interconnect from the first plurality of solder interconnects, and at least one second interconnect from the first substrate.

[0120] Aspect 9: The package of aspects 1 to 8, wherein the electrical device is coupled to the second surface of the second substrate via a second plurality of solder interconnects.

[0121] Aspect 10: The package of aspects 1 to 9, wherein the package is a package-on-package (PoP).

[0122] Aspect 11: A package comprising: a first substrate; a first integrated device coupled to the first substrate; a second substrate coupled to the first substrate via a first plurality of solder interconnects so that the first integrated device is located between the first substrate and the second substrate, wherein the second substrate comprises a first surface and a second surface; a passive device coupled to the second surface of the second substrate so that the passive device is located between the first substrate and the second substrate; and an encapsulation layer coupled to the first substrate and the second substrate. The encapsulation layer is located between the first substrate and the second substrate. The encapsulation layer encapsulates the first integrated device and the passive device.

[0123] Aspect 12: The package of aspect 11, wherein the passive device comprises a trench capacitor.

[0124] Aspect 13: The package of aspects 11 to 12, wherein the passive device comprises a silicon die.

[0125] Aspect 14: The package of aspects 11 to 13, wherein the passive device is configured to be electrically coupled to the first integrated device via an electrical path comprising at least one interconnect from the second substrate, at least one solder interconnect from the first plurality of solder interconnects, and at least one interconnect from the first substrate.

[0126] Aspect 15: A package as in Aspects 11 to 14, further comprising a second passive device coupled to the second surface of the second substrate, wherein the second passive device is configured to be electrically coupled to the first integrated device via a second electrical path, the second electrical path comprising at least one second interconnect from the second substrate, at least one second solder interconnect from the first plurality of solder interconnects, and at least one second interconnect from the first substrate.

[0127] Aspect 16: The package of Aspects 11 to 15, further comprising an active device coupled to the second surface of the second substrate, wherein the active device is configured to be electrically coupled to the first integrated device via a second electrical path, the second electrical path comprising at least one second interconnect from the second substrate, at least one second solder interconnect from the first plurality of solder interconnects, and at least one second interconnect from the first substrate.

[0128] Aspect 17: A package as in aspects 11 to 16, wherein

[0129] The package is implemented in a device selected from the group including: a music player, a video player, an entertainment unit, a navigation device, a communication device, a mobile device, a mobile phone, a smart phone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an Internet of Things (IoT) device, and a device in a motor vehicle.

[0130] Aspect 18: A package comprising: a first substrate; a first integrated device coupled to the first substrate; a second substrate coupled to the first substrate via a first plurality of solder interconnects such that the first integrated device is located between the first substrate and the second substrate, wherein the second substrate comprises a first surface and a second surface; a second integrated device coupled to the second surface of the second substrate such that the second integrated device is located between the first substrate and the second substrate; and an encapsulation layer coupled to the first substrate and the second substrate. The encapsulation layer is located between the first substrate and the second substrate. The encapsulation layer encapsulates the first integrated device and the second integrated device.

[0131] Aspect 19: The package of aspect 18, wherein the second integrated device is configured to be electrically coupled to the first integrated device via an electrical path comprising at least one interconnect from the second substrate, at least one solder interconnect from the first plurality of solder interconnects, and at least one interconnect from the first substrate.

[0132] Aspect 20: A method for manufacturing a package. The method provides a second substrate including a first surface and a second surface. The method couples an electrical device to the second surface of the second substrate. The method couples a first plurality of solder interconnects to the second surface of the second substrate. The method provides a first substrate and a first integrated device coupled to the first substrate. The method couples the second substrate to the first substrate via the first plurality of solder interconnects so that the first integrated device and the electrical device are located between the first substrate and the second substrate. The method forms an encapsulation layer between the first substrate and the second substrate.

[0133] Aspect 21: The method of aspect 20, wherein the electrical device comprises a passive device or an active device.

[0134] Aspect 22: The method of aspect 20, wherein the electrical device comprises a second integrated device.

[0135] The various features of the present disclosure described herein may be implemented in different systems without departing from the present disclosure. It should be noted that the above aspects of the present disclosure are merely examples and should not be construed as limiting the present disclosure. The description of the various aspects of the present disclosure is intended to be illustrative rather than limiting the scope of the appended claims. Thus, the teachings of the present disclosure may be readily applied to other types of devices, and many substitutions, modifications, and variations will be apparent to those skilled in the art.

Claims

1. A package comprising: a first substrate; a first integrated device coupled to the first substrate; a second substrate coupled to the first substrate via a first plurality of solder interconnects such that the first integrated device is located between the first substrate and the second substrate, wherein the second substrate includes a first surface and a second surface; an electrical device coupled to the second surface of the second substrate such that the electrical device is located between the first substrate and the second substrate; as well as an encapsulation layer coupled to the first substrate and the second substrate, wherein the encapsulation layer is located between the first substrate and the second substrate, and The encapsulation layer encapsulates the first integrated device and the electrical device.

2. The package of claim 1, wherein the electrical device comprises a passive device or an active device.

3. The package of claim 2, wherein the passive device comprises an inductor or a capacitor. The package of claim 2 , wherein the passive device comprises a silicon die.

5. The package of claim 2, wherein the passive device comprises a trench capacitor.

6. The package of claim 1, wherein the electrical device comprises a second integrated device.

7. The package of claim 1, wherein the electrical device is configured to be electrically coupled to the first integrated device via an electrical path comprising at least one interconnect from the second substrate, at least one solder interconnect from the first plurality of solder interconnects, and at least one interconnect from the first substrate.

8. The package of claim 1 , further comprising a second electrical device coupled to the second surface of the second substrate, wherein the second electrical device is configured to be electrically coupled to the first integrated device through a second electrical path, the second electrical path comprising at least one second interconnect from the second substrate, at least one second solder interconnect from the first plurality of solder interconnects, and at least one second interconnect from the first substrate.

9. The package of claim 1, wherein the electrical device is coupled to the second surface of the second substrate by a second plurality of solder interconnects.

10. The package of claim 1, wherein the package is a package-on-package (PoP).

11. A package comprising: a first substrate; a first integrated device coupled to the first substrate; a second substrate coupled to the first substrate via a first plurality of solder interconnects such that the first integrated device is located between the first substrate and the second substrate, wherein the second substrate includes a first surface and a second surface; a passive device coupled to the second surface of the second substrate such that the passive device is located between the first substrate and the second substrate; as well as an encapsulation layer coupled to the first substrate and the second substrate, wherein the encapsulation layer is located between the first substrate and the second substrate, and The encapsulation layer encapsulates the first integrated device and the passive device.

12. The package of claim 11 wherein the passive device comprises a trench capacitor.

13. The package of claim 11 wherein the passive device comprises a silicon die.

14. The package of claim 11, wherein the passive device is configured to be electrically coupled to the first integrated device through an electrical path, the electrical path comprising at least one interconnect from the second substrate, at least one solder interconnect from the first plurality of solder interconnects, and at least one interconnect from the first substrate.

15. The package of claim 11, further comprising a second passive device coupled to the second surface of the second substrate, wherein the second passive device is configured to be electrically coupled to the first integrated device through a second electrical path, the second electrical path comprising at least one second interconnect from the second substrate, at least one second solder interconnect from the first plurality of solder interconnects, and at least one second interconnect from the first substrate.

16. The package of claim 11, further comprising an active device coupled to the second surface of the second substrate, wherein the active device is configured to be electrically coupled to the first integrated device through a second electrical path, the second electrical path comprising at least one second interconnect from the second substrate, at least one second solder interconnect from the first plurality of solder interconnects, and at least one second interconnect from the first substrate.

17. A package as described in claim 11, wherein the package is implemented in a device selected from the group consisting of: a music player, a video player, an entertainment unit, a navigation device, a communication device, a mobile device, a mobile phone, a smart phone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an Internet of Things (IoT) device, and a device in a motor vehicle.

18. A package comprising: a first substrate; a first integrated device coupled to the first substrate; a second substrate coupled to the first substrate via a first plurality of solder interconnects such that the first integrated device is located between the first substrate and the second substrate, wherein the second substrate includes a first surface and a second surface; a second integrated device coupled to the second surface of the second substrate such that the second integrated device is located between the first substrate and the second substrate; as well as an encapsulation layer coupled to the first substrate and the second substrate, wherein the encapsulation layer is located between the first substrate and the second substrate, and The encapsulation layer encapsulates the first integrated device and the second integrated device.

19. The package of claim 18, wherein the second integrated device is configured to be electrically coupled to the first integrated device via an electrical path comprising at least one interconnect from the second substrate, at least one solder interconnect from the first plurality of solder interconnects, and at least one interconnect from the first substrate.

20. A method for manufacturing a package, comprising: providing a second substrate including a first surface and a second surface; coupling an electrical device to the second surface of the second substrate; coupling a first plurality of solder interconnects to the second surface of the second substrate; providing a first substrate and a first integrated device coupled to the first substrate; coupling the second substrate to the first substrate via the first plurality of solder interconnects such that the first integrated device and the electrical device are located between the first substrate and the second substrate; as well as An encapsulation layer is formed between the first substrate and the second substrate.

21. The method of claim 20, wherein the electrical device comprises a passive device or an active device.

22. The method of claim 20, wherein the electrical device comprises a second integrated device.

Images