Optoelectronic semiconductor component and method for producing at least one optoelectronic semiconductor component

Abstract

The invention relates to an optoelectronic semiconductor component (1), comprising: a semiconductor layer stack (2), which comprises a first semiconductor region (4), a second semiconductor region (6) and an active region (5), which is arranged between the first and second semiconductor regions (4, 6), the second semiconductor region (6) having a first semiconductor layer (7) and a second semiconductor layer (8), the second semiconductor layer (8) is arranged on the side of the first semiconductor layer (7) facing away from the active region (5),-at least one recess (19), which extends from the first main surface (2A) of the semiconductor layer stack (2) through the first semiconductor region (4) and the active region (5) and terminates at the second semiconductor layer (8), wherein the first semiconductor layer (7) comprises a first compound semiconductor material and the second semiconductor layer (8) comprises a second compound semiconductor material, and the first compound semiconductor material has a higher aluminum content than the second compound semiconductor material. The invention further relates to a method for producing such an optoelectronic semiconductor component (1).

Description

Technical Field

[0001] An optoelectronic semiconductor component and a method for producing at least one optoelectronic semiconductor component are provided. The optoelectronic semiconductor component is, for example, an InGaAlP-based semiconductor component. The optoelectronic semiconductor component can be designed to generate or emit electromagnetic radiation. Background Art

[0002] In radiation-emitting semiconductor components, for example based on InGaAlP compound semiconductor materials, there are different possibilities for electrical contacting. For example, a first electrode of a first polarity (for example a p-type electrode) can be arranged on the back side, and a second electrode of a second polarity (for example an n-type electrode) can be arranged on the front side. However, since the second electrode is arranged on the front side designed for radiation emission, absorption losses can occur there. An alternative design proposes a via that completely penetrates the semiconductor chip and extends to the front side. In this case, although the second electrode has a smaller size, it is also arranged on the front side and can also cause absorption losses. In addition, there is the possibility of electrically contacting the semiconductor region arranged on the front side from the back side by means of one or more vias that are led through the semiconductor chip. However, due to the relatively high tolerances when manufacturing the recessed portion (in which the via is produced), the semiconductor layer to be contacted by means of one or more vias must be formed as thick as possible, which in turn leads to relatively high absorption losses due to the thickness and the possible high doping. Summary of the invention

[0003] The object to be achieved is, in particular, to specify an optoelectronic semiconductor component with a higher efficiency. A further object to be achieved is, in particular, to specify a method for producing at least one optoelectronic semiconductor component with a higher efficiency.

[0004] This object is achieved in particular by an optoelectronic semiconductor component and a method for producing at least one optoelectronic semiconductor component having the features of the independent claims.

[0005] Further advantages and embodiments of the optoelectronic semiconductor component and of the method for producing an optoelectronic semiconductor component are the subject matter of the dependent claims.

[0006] According to at least one embodiment of the optoelectronic semiconductor component, the optoelectronic semiconductor component comprises a semiconductor layer stack having a first semiconductor region, a second semiconductor region and an active region arranged between the first and second semiconductor regions. The active region can be designed to generate or emit electromagnetic radiation, for example in the visible to infrared spectral range.

[0007] Furthermore, the active region can have a series of individual layers. By means of the individual layers, a quantum well structure, in particular a single quantum well structure (Single Quantum Well, SQW) or a multiple quantum well structure (Multiple Quantum Well, MQW) can be formed.

[0008] The first semiconductor region may have a first conductivity type, for example p-type conductivity. In addition, the second semiconductor region may have a second conductivity type, for example n-type conductivity. However, it is also possible that the second semiconductor region is a semiconductor region of p-type conductivity and the first semiconductor region is a semiconductor region of n-type conductivity. The first and second semiconductor regions may each have a sequence of monolayers, which may be partially undoped or slightly doped. The monolayers may be layers deposited epitaxially on a growth substrate.

[0009] According to at least one embodiment, the second semiconductor region comprises: a first semiconductor layer, which comprises a first compound semiconductor material; and a second semiconductor layer, which comprises a second compound semiconductor material different from the first compound semiconductor material. In this case, the first compound semiconductor material can have a higher aluminum content than the second compound semiconductor material. In the case of a suitable selection of an etchant with sufficient selectivity, the higher aluminum content in the first semiconductor layer leads to a higher etching rate than in the second semiconductor layer. As a result, the etching process of the second semiconductor layer can be stopped. It is thus possible to set the etching depth particularly accurately or to determine the vertical extension of the recess to be produced with relatively high accuracy.

[0010] In accordance with at least one embodiment, the second semiconductor layer is arranged on that side of the first semiconductor layer which faces away from the active zone.

[0011] According to at least one embodiment, the optoelectronic semiconductor component has at least one recess, which extends from a first main surface of the semiconductor layer stack through the first semiconductor region and the active region and ends at the second semiconductor layer. The first main surface can be a surface of the semiconductor layer stack that delimits the semiconductor layer stack on one side, which side faces the back side of the optoelectronic semiconductor component.

[0012] According to at least one embodiment, the optoelectronic semiconductor component has a first contact structure for electrically contacting the first semiconductor region and a second contact structure for electrically contacting the second semiconductor region. The first contact structure can be arranged at least partially on the first main surface. In addition, the second contact structure can be arranged locally on the first main surface and in at least one recess. With the help of the first and second contact structures, it is possible to electrically connect the optoelectronic semiconductor component from the outside on only one side of the semiconductor component, for example at the side edge. The first and second contact structures can achieve a uniform current distribution in the semiconductor layer stack, so that larger semiconductor devices can also be realized.

[0013] According to at least one embodiment of the optoelectronic semiconductor component, the optoelectronic semiconductor component comprises:

[0014] - A semiconductor layer stack comprising:

[0015] - a first semiconductor region,

[0016] - a second semiconductor region, and

[0017] an active region, which is arranged between a first and a second semiconductor region, wherein the second semiconductor region comprises a first semiconductor layer and a second semiconductor layer, and the second semiconductor layer is arranged on a side of the first semiconductor layer facing away from the active region,

[0018] at least one recess which extends from the first main face of the semiconductor layer stack through the first semiconductor region and the active zone and ends at the second semiconductor layer,

[0019] a first contact structure for electrically contacting the first semiconductor region, the first contact structure being arranged at least in places at the first main surface,

[0020] a second contact structure for electrically contacting the second semiconductor region, said second contact structure being arranged locally at the first main surface and in the at least one recess,

[0021] The first semiconductor layer includes a first compound semiconductor material and the second semiconductor layer includes a second compound semiconductor material, and the first compound semiconductor material has a higher aluminum content than the second compound semiconductor material.

[0022] For example, at least one recess or the contact area of ​​the second contact structure arranged in the recess has a three-dimensional shape with a constant cross section, such as a cylinder or a cuboid. However, it is also feasible that at least one recess or the contact area arranged in the recess has a three-dimensional shape with a variable cross section, such as a truncated cone or a truncated pyramid. Here, the cross section can become smaller as the depth increases. For example, the shape and size of the contact area are determined by the shape and size of the recess. The shape and size of the contact area can be at least approximately the same as the shape and size of the recess.

[0023] In the case of a plurality of recesses or contact regions, these may vary in their size and / or their spacing from one another, for example in order to compensate for contact resistance and / or sheet resistance in the second semiconductor region.

[0024] According to at least one embodiment or configuration, the first compound semiconductor material is a phosphide compound semiconductor material, that is, a semiconductor material having a phosphorus content. In addition, the second compound semiconductor material can also be a phosphide compound semiconductor material. InGaAlP is considered for the first and second phosphide compound semiconductor materials.

[0025] According to at least one embodiment or design, the first compound semiconductor material includes Al n Ga m In 1-n-m P, where 0.3≤n≤0.6, 0≤m≤0.2 and 0.4≤n+m≤0.6. The first semiconductor layer can have the function of a buffer layer. A suitable lattice constant can be achieved with an indium content of between 40% and 60%.

[0026] According to at least one embodiment or design, the second compound semiconductor material includes Al n Ga m In 1-n-m P, where 0<n<0.6, 0<m<0.6 and 0.4≤n+m≤0.6. The second semiconductor layer can, for example, have the function of a contact layer or have the function of a contact and current spreading layer. The second semiconductor layer can be formed thinner than the first semiconductor layer. For example, the second semiconductor layer can have a thickness between 10 nm and 500 nm, in particular between 20 nm and 100 nm, wherein a manufacturing tolerance of ±10% may occur. Due to the relatively small thickness, relatively few absorption losses occur in the second semiconductor layer or the contact layer.

[0027] According to at least one embodiment or design, the second semiconductor region has a third semiconductor layer, which is arranged on the side of the second semiconductor layer facing away from the first semiconductor layer. For the third semiconductor layer, as for the first and second semiconductor layers, phosphide compound semiconductor materials, in particular InGaAlP, are considered. The compound semiconductor materials of the second and third semiconductor layers can differ in their gallium content and / or their doping level. For example, the second semiconductor layer is a contact layer as already mentioned above, and the third semiconductor layer is a current spreading layer.

[0028] According to at least one embodiment or design, a second main surface of the semiconductor layer stack opposite the first main surface does not have a first and a second contact structure. The second main surface can be located at a front side of the optoelectronic semiconductor component designed for radiation emission. A major part of the radiation to be emitted can pass through the second main surface and can be partially absorbed at the contact structure arranged on the second main surface. This can be advantageously prevented by arranging the contact structure outside the second main surface.

[0029] According to at least one embodiment or design, at least one recess has a widened region between the active region and the second semiconductor layer. The widened region can be evaluated as an indication of a two-stage etching process for producing the at least one recess, as described in more detail below in conjunction with the production method.

[0030] For example, the widened region can have a depth or a vertical extension which corresponds at least approximately to at least 25% of the thickness of the first semiconductor layer and corresponds at most to the thickness of the first semiconductor layer. The vertical extension can here denote an extension along a vertical direction which, for example, runs antiparallel to the growth direction in which the semiconductor regions grow successively. Furthermore, the widened region can have a lateral extension which deviates by approximately 10% with a tolerance of ±10% from the expected lateral extension at the bottom of the depression 19 (which would be achieved if the original shape of the depression were continued). For example, values ​​between 5.5 μm and 7.5 μm with a tolerance of ±10% come into consideration for the lateral extension of the widened region.

[0031] According to at least one embodiment or design, the second contact structure has a connection layer. The connection layer can cover one or more surfaces of the semiconductor layer stack that bound the at least one recess. Suitable for the connection layer are material connections and / or layer stacks that are metallic. For example, Au or Pd are considered for the connection layer. The connection layer can have a dopant such as, for example, Ge.

[0032] According to at least one embodiment or design, a cavity is formed in the widened region of at least one recess between the semiconductor layer stack and the second contact structure. The cavity can be gas-filled or substantially unfilled, so that a vacuum exists therein. For example, the extension of the connecting layer and, if necessary, further layers applied to the semiconductor layer stack in the widened region continues to follow the original shape of the recess, which would have had the original shape in the continuation of the non-widened region. Since the second contact structure or the connecting layer and, if necessary, further layers can be applied non-uniformly to the semiconductor layer stack in the widened region of the recess, cavities can occur.

[0033] According to at least one embodiment or design, the optoelectronic semiconductor device comprises an insulating layer, which is arranged between the semiconductor layer stack and the connecting layer. The insulating layer may contain an electrically insulating material such as silicon oxide or silicon nitride or consist of these materials. For example, the insulating layer may be arranged on one or more surfaces of the semiconductor layer stack that laterally delimit the recess. The surface at the bottom of the recess may not be covered by the insulating layer, so that the second semiconductor layer can be contacted by the second contact structure or by the connecting layer.

[0034] According to at least one embodiment or design, the optoelectronic semiconductor component comprises a carrier on which the semiconductor layer stack is arranged. In this case, the first semiconductor region can be arranged on a side of the active region facing the carrier and the second semiconductor region can be arranged on a side of the active region facing away from the carrier. The carrier can contain a semiconductor material such as, for example, Ge or Si or contain a ceramic material such as, for example, SiN or consist thereof.

[0035] The method described below is suitable for producing at least one optoelectronic semiconductor component as described above. Features described in conjunction with the semiconductor component can therefore also be used for the method and vice versa.

[0036] According to at least one embodiment or configuration of the method for producing at least one optoelectronic semiconductor component, the method comprises the following steps, for example in the order specified:

[0037] - providing a semiconductor layer sequence for producing at least one semiconductor layer stack, wherein the semiconductor layer sequence comprises:

[0038] - a first semiconductor region,

[0039] - a second semiconductor region,

[0040] an active region, which is arranged between a first and a second semiconductor region, wherein the second semiconductor region comprises a first semiconductor layer and a second semiconductor layer, and the second semiconductor layer is arranged on a side of the first semiconductor layer facing away from the active region, and

[0041] - a first main surface,

[0042] - forming a first contact structure on the first main surface,

[0043] - producing at least one recess which extends from the first main surface through the first semiconductor region and the active zone and ends at the second semiconductor layer,

[0044] - forming a second contact structure, which is locally arranged on the first main surface and in at least one recess, wherein the at least one recess is produced by a two-stage etching process and the semiconductor layer sequence is etched into the first semiconductor layer in a first etching step and into the second semiconductor layer in a second etching step.

[0045] In contrast to a single-stage etching process, in which the end of the etching process or the etching depth can be controlled less precisely than in a two-stage etching process as described here, so that the semiconductor layer in which the etching process is to be stopped must be relatively thick, the second semiconductor layer can be relatively thin, for example, with a thickness between 10 nm and 500 nm, in particular between 20 nm and 100 nm, wherein typical manufacturing tolerances of ±10% may occur. In contrast, the first semiconductor layer in which the first etching step ends can be thicker than the second semiconductor layer. For example, values ​​between 0.4 μm and 0.6 μm with a tolerance of ±10% are considered for the thickness of the first semiconductor layer. The thickness of the first semiconductor layer takes into account, for example, thickness fluctuations and etching rate fluctuations that occur in the first etching step.

[0046] The semiconductor layer sequence corresponds, for example, with respect to its layer structure and its material composition to a semiconductor layer stack which is produced from the semiconductor layer sequence, so that the embodiments associated therewith apply accordingly to the semiconductor layer sequence. Preferably, the first semiconductor region of at least one semiconductor layer stack is formed by the first semiconductor region of the semiconductor layer sequence, the active region of at least one semiconductor layer stack is formed by the active region of the semiconductor layer sequence, and the second semiconductor region of at least one semiconductor layer stack is formed by the second semiconductor region of the semiconductor layer sequence. In particular, the first semiconductor layer of the second semiconductor region is formed from a first compound semiconductor material, for example InAlP, and the second semiconductor layer is formed from a second compound semiconductor material, for example InGaAlP, wherein the first compound semiconductor material has a higher aluminum content than the second compound semiconductor material.

[0047] A semiconductor layer sequence may be provided on a substrate, on which the semiconductor layer sequence is grown, for example epitaxially.

[0048] Furthermore, the first and second contact structures formed on the semiconductor layer sequence are designed such that first and second contact structures for at least one optoelectronic semiconductor device can be produced thereby. Therefore, the embodiments made in connection with the first and second contact structures of the optoelectronic semiconductor device, for example embodiments concerning the structure and suitable materials, apply accordingly. In particular, the second contact structure can have a connection layer, which is designed to produce a connection layer of the second contact structure of the at least one semiconductor device. The connection layer can cover one or more surfaces of the semiconductor layer sequence that delimit the at least one recess.

[0049] According to at least one embodiment or design, the first etching step comprises a dry etching process. In addition, the second etching step may comprise a wet chemical etching process. For the second etching step or the wet chemical etching process, in particular, an etchant with sufficient selectivity is used, which has a higher etching rate for the first semiconductor layer with a higher aluminum content than for the second semiconductor layer with a lower aluminum content. For example, the etching rate in the second semiconductor layer can be less than the etching rate in the first semiconductor layer by more than one order of magnitude. As a result, the etching process can be terminated in a targeted manner at the second semiconductor layer. As a result, the desired etching depth can be set in a targeted manner.

[0050] Suitable etchants include, for example, aqueous solvents such as dilute hydrochloric acid or dilute sulfuric acid.

[0051] According to at least one embodiment or configuration, a widened region of at least one recess is produced by means of a second etching step. The widened region is produced by etching downwards in the first semiconductor layer. The dimensions of the widened region apply as already stated in connection with the optoelectronic semiconductor component.

[0052] According to at least one embodiment or design, an insulating layer is formed between the semiconductor layer sequence and the termination layer, and the insulating layer is designed to produce an insulating layer in at least one semiconductor device. Therefore, the embodiments made in connection with the insulating layer of the optoelectronic semiconductor device, such as the embodiments involving the structure and suitable materials, apply accordingly. For example, the insulating layer can be applied to the semiconductor layer sequence as a closed layer, so that the surface bounding the recess or the first subregion of the recess is completely covered. Subsequently, the insulating layer can be partially removed, so that the surface of the semiconductor layer sequence arranged at the bottom of the recess or the first subregion of the recess is exposed.

[0053] According to at least one embodiment or design, an insulating layer is applied before performing the second etching step. In this case, the insulating layer can be etched down in the second etching step and have a distance from the semiconductor layer sequence. However, it is also feasible to apply the insulating layer after the second etching step. In this case, the insulating layer can be closer to the semiconductor layer sequence.

[0054] According to at least one embodiment or design, the active region has a quantum well structure, wherein mixing of the quantum well structure is performed in a region of the active region adjacent to the recess. In this case, the quantum wells and barrier layers are mixed so that a higher band gap is produced, which results in fewer charge carriers and surface recombination. The mixing can be performed before a layer, such as an insulating layer or a termination layer, is applied to the semiconductor layer sequence in the recess. It is also possible to perform the mixing before the recess is produced.

[0055] Optoelectronic semiconductor components are suitable, for example, for projection and lighting applications in the longer-wavelength spectral range, for example from the red to the infrared. BRIEF DESCRIPTION OF THE DRAWINGS

[0056] Further advantages, advantageous embodiments and developments result from the exemplary embodiments described below in conjunction with the drawings.

[0057] The accompanying drawings show:

[0058] Figures 1 to 11 schematic cross-sectional views showing different method steps of a method for producing an optoelectronic semiconductor component according to one embodiment; and

[0059] Fig.12 Shown is a schematic cross-sectional view of an optoelectronic semiconductor component in accordance with one exemplary embodiment.

[0060] In the exemplary embodiments and figures, identical, similar or identically functioning elements are each provided with identical or similar reference numerals which are distinguished from one another only by "'". The illustrated elements and their size ratios to one another are not necessarily to be regarded as true to scale; rather, individual elements may be illustrated exaggeratedly for better visibility and / or for better understanding. DETAILED DESCRIPTION

[0061] according to Figures 1 to 11 An exemplary embodiment of a method or a layer assembly 100 and possible variants of the exemplary embodiments are described, which are suitable for integrating an optoelectronic semiconductor component 1 as, for example, described below in conjunction with Fig.12 The dashed-line region in the drawing symbolically represents a further region of the layer composite 100 , in which, for example, a plurality of optoelectronic semiconductor components 1 can be produced.

[0062] The method comprises the step of providing a semiconductor layer sequence 2 ′ for producing at least one semiconductor layer stack 2 (see Fig.12 ), wherein a semiconductor layer sequence 2 ′ is provided on a substrate 3 (see Figure 1). The semiconductor layer sequence 2' can be formed from a semiconductor material based on a phosphide compound semiconductor. Furthermore, the substrate 3 can be formed from a semiconductor material based on an arsenide compound semiconductor. For example, GaAs is considered for the substrate 3. In particular, the substrate 3 is a growth substrate on which the semiconductor layer sequence 2' is epitaxially deposited.

[0063] The semiconductor layer sequence 2' comprises a first semiconductor region 4' of a first conductivity type, for example, p-type conductivity, a second semiconductor region 6' of a second conductivity type, for example, n-type conductivity, and an active region 5' arranged between the first and second semiconductor regions 4', 6'. Here, the first semiconductor region 4' is located on the side of the active region 5' facing away from the substrate 3, and the second semiconductor region 6' is located between the substrate 3 and the active region 5'.

[0064] The first and second semiconductor regions 4', 6' can respectively have a sequence of single layers, which can be doped, but can also be partially undoped or slightly doped. For example, the first semiconductor region 4' can have a confinement layer (not shown) near the active region 5'. In addition, the second semiconductor region 6' includes a first semiconductor layer 7' and a second semiconductor layer 8', which are arranged on the side of the first semiconductor layer 7' away from the active region 5'. The second semiconductor layer 8' can be constructed so that the second semiconductor layer assumes the functions of contact and current spreading layer. However, it is also feasible that different functions are realized by different layers. In the illustrated embodiment, the second semiconductor layer 8' has the function of a contact layer. For the function of the current spreading layer, a third semiconductor layer 9' is provided, which is located on the side of the second semiconductor layer 8' away from the first semiconductor layer 7'. In addition, the second semiconductor region 6' can have a radiation exit layer 10', which is arranged on the side of the semiconductor layer sequence 2' facing the substrate 3 and can be provided with a radiation coupling-out structure for improving the radiation emission in the manufactured semiconductor device.

[0065] Furthermore, the active region 5 ′ can have a sequence of monolayers. A quantum well structure, in particular a single quantum well structure (Single Quantum Well, SQW) or a multiple quantum well structure (Multiple Quantum Well, MQW) can be formed by means of the monolayers.

[0066] The first semiconductor layer 7' of the second semiconductor region 6' can be formed from a first phosphide compound semiconductor material and the second semiconductor layer 8' can be formed from a second phosphide compound semiconductor material, wherein the first compound semiconductor material has a higher aluminum content than the second compound semiconductor material. In particular, the first compound semiconductor material comprises Al n Ga m In 1-n-mP, where 0.3≤n≤0.6, 0≤m≤0.2 and 0.4≤n+m≤0.6. The first semiconductor layer 7' can have the function of a buffer layer. A suitable lattice constant can be achieved with an indium content between 40% and 60%. In addition, the second compound semiconductor material can have Al n Ga m In 1-n-m P, where 0<n<0.6, 0<m<0.6 and 0.4≤n+m≤0.6. The third semiconductor layer 9' can be formed, like the first and second semiconductor layers 7', 8', from a phosphide compound semiconductor material, in particular from InGaAlP, wherein the compound semiconductor materials of the second and third semiconductor layers 8', 9' differ in terms of the gallium content and / or its doping level.

[0067] The second semiconductor layer 8' can be formed thinner than the first semiconductor layer 7'. For example, the second semiconductor layer 8' can have a thickness d2 between 10 nm and 500 nm, in particular between 20 nm and 100 nm, wherein typical manufacturing tolerances of ±10% may occur. Due to the relatively small thickness d2, absorption losses can be reduced in the second semiconductor layer 8' or the contact layer. The thickness can represent the vertical extension along the vertical direction V, which extends, for example, parallel to the growth direction in which the semiconductor regions 6', 5', 4' grow successively.

[0068] The method further comprises the step of forming a first contact structure 11' on a first main surface 2A' of the semiconductor layer sequence 2', wherein the first main surface 2A' delimits the semiconductor layer sequence 2' toward the outside on a side facing away from the substrate (see Figure 1 ). The step of forming the first contact structure 11' can include producing a first expansion layer 12' on the first main surface 2A'. The first expansion layer 12' can be applied in direct contact with the first semiconductor region 4'. The first expansion layer 12' can be formed in a single layer or in multiple layers. For example, TCO (transparent conductive oxide) such as ITO, ZnO, InZnO or AlO is considered for the first expansion layer 12'.

[0069] Furthermore, the step of forming the first contact structure 11' comprises producing a second expansion layer 14', which is arranged on the side of the first expansion layer 12' facing away from the semiconductor layer sequence 2' and is electrically conductively connected to said side. In this case, the second expansion layer 14' can cover a larger area of ​​the first main surface 2A' than the first expansion layer 12'.

[0070] For example, the second expansion layer 14 ′ is a metal layer, which may be formed in a single layer or in multiple layers.

[0071] Furthermore, the step of forming the first contact structure 11' comprises producing a mirror layer 13' between the first and second expansion layers 12', 14', the mirror layer being formed of Ag, for example. Fig.12 ) During operation, a considerable portion of the radiation emitted by the active region 5', 5 can be transmitted through the first expansion layer 12', 12, while through the mirror layer 13', 13 it is possible to deflect the emitted radiation in the direction of the second main surface 2B', 2B opposite to the first main surface 2A', 2A and to shield the radiation from the second expansion layer 14, 14' which may cause absorption.

[0072] In order to achieve a favorable reflectivity at the back side of the finished semiconductor component, a reflective element 15' can be arranged on the first main surface 2A' (see Figure 1 ). The reflective element 15' can have layers with a higher and a lower refractive index arranged alternately. The layers can be dielectric layers, for which materials such as SiO, SiN, NbO or HfO come into consideration. For example, the reflective element 15' comprises a Bragg reflector. The reflective element 15' can cover the first main surface 2A' and thereby partially cover the first expansion layer 12'. The reflective element 15' can be provided with an opening 16, into which the second expansion layer 14' and, if necessary, the mirror layer 13' extend as far as the first expansion layer 12'.

[0073] Furthermore, openings 17 may be formed in the second expansion layer 14 ′ and, if appropriate, in the mirror layer 13 ′ at a lateral distance from the openings 16 .

[0074] An insulating layer 18' can be applied on the side of the second expansion layer 14' facing away from the semiconductor layer sequence 2', which insulating layer at least largely covers the first main surface 2A' and extends into the opening 17. The insulating layer 18' is designed to connect the first contact structure 11' and the second contact structure 21' (see Fig.10 ) are electrically isolated from each other.

[0075] As from Figure 2 and 6 As can be seen from FIG, the method further comprises the step of producing at least one recess 19 which extends from the first main face 2A′ through the first semiconductor region 4′ and the active area 5′ and ends at the second semiconductor layer 8′. The recess 19 may already start at the insulating layer 18′ and extend through the opening 17.

[0076] The depression 19 is produced by a two-stage etching process. In this case, the semiconductor layer sequence 2' is etched into the first semiconductor layer 7' in a first etching step. The first etching step comprises, for example, a dry etching process. The first region 19A of the depression 19 produced in this way is laterally delimited by one or more surfaces 2C' of the semiconductor layer sequence 2', which in cross section can each extend at an angle of 90°<α<180°, in particular 95°<α<115°, to a surface 2D' of the semiconductor layer sequence 2' delimiting the first region 19A at the bottom (see Figure 2 ). The first region 19A may have a shape of a truncated cone or a truncated pyramid.

[0077] In addition, the method, as in Figure 3 As indicated by arrows in the figure, a step of mixing the quantum well structure of the active region 5' in a region adjacent to the recess 19 or the first region 19A adjacent to the recess 19 can be included. In this case, the quantum well and barrier layers are mixed, for example, thermally, if necessary by introducing impurities, so that a higher band gap is generated, which leads to fewer charge carriers and surface recombination. The steps are performed, for example, when surface recombination in the recess 19 plays an important role. In particular, mixing is also carried out at an early stage, for example before the recess 19 is produced, so that higher temperatures are also feasible.

[0078] The method further comprises a step of producing the insulation layer 20 ′, which, as in the exemplary embodiment, is carried out before the second etching step. However, it is also possible for this step to be carried out after the second etching step.

[0079] As in Figure 4 As shown in FIG, an insulating layer 20' is applied to the semiconductor layer sequence 2', for example as a closing layer, so that the surfaces 2C', 2D' that bound the first region 19A of the recess 19 are completely covered. Subsequently, the insulating layer 20' is partially removed, so that a surface 2D' of the semiconductor layer sequence 2' arranged at the bottom of the first region 19A of the recess 19 is exposed (see FIG. Figure 5 ).

[0080] The insulating layer 20 ′ may be formed of an electrically insulating material such as, for example, silicon oxide or silicon nitride, or a combination of these materials.

[0081] After the insulating layer 20' is structured, as in Figure 6As shown in , a second etching step is performed, in which the semiconductor layer sequence 2' is etched to the second semiconductor layer 8'. For example, the second etching step comprises a wet chemical etching process. For the second etching step or the wet chemical etching process, in particular an etchant with sufficient selectivity is used, which has a higher etching rate for the first semiconductor layer 7' with a higher aluminum content than for the second semiconductor layer 8' with a lower aluminum content. For example, the etching rate in the second semiconductor layer 8' can be less than the etching rate in the first semiconductor layer 7' by more than one order of magnitude. As a result, the etching process can be terminated in a targeted manner at the second semiconductor layer 8', so that the desired etching depth can be set in a targeted manner. As an etchant, for example, an aqueous solvent, such as diluted hydrochloric acid or diluted sulfuric acid, comes into consideration.

[0082] In contrast to less precise single-stage etching processes in which the semiconductor layer to be contacted must be formed relatively thick due to higher tolerances, the second semiconductor layer 8' to be contacted can be formed relatively thinly with a thickness d2 of between 10 nm and 500 nm, in particular between 20 nm and 100 nm, wherein typical manufacturing tolerances of ±10% may occur.

[0083] The first semiconductor layer 7', in which the first etching step ends, can be formed thicker than the second semiconductor layer 8'. For the thickness d1 of the first semiconductor layer 7', for example, values ​​between 0.4 μm and 0.6 μm with a tolerance of ±10% are considered. The thickness d1 of the first semiconductor layer 7' takes into account, for example, thickness fluctuations and etching rate fluctuations that occur in the first etching step.

[0084] In the second etching step, a widened region 19B of the recess 19 is produced. The widened region 19B is produced by etching downwards in the first semiconductor layer 7 ′. In the second etching step, the insulation layer 20 ′ is etched downwards such that it is spaced apart from the semiconductor layer sequence 2 ′.

[0085] For example, the widened region 19B can have a depth or vertical extension h which corresponds at least approximately to at least 25% of the thickness d1 of the first semiconductor layer 7 ′ and corresponds at most to the thickness d1 . The vertical extension h can denote the extension along the vertical direction V here.

[0086] Furthermore, the widened region 19B can have a lateral extension b which deviates from the expected lateral extension at the bottom of the depression 19 by approximately 10% with a tolerance of ±10%, in the case of a continuation of the original shape of the depression 19 or in the case of the shape of the first region 19A of the depression 19 while maintaining the angle α (see Figure 2) will achieve the desired lateral expansion). For example, values ​​between 5.5 μm and 7.5 μm with a tolerance of ±10% are considered for the lateral expansion b of the widened region. The lateral expansion b can denote the expansion along a lateral direction L, which extends transversely to the direction V, for example perpendicularly.

[0087] The method further comprises the step of forming a second contact structure 21 ′, which is arranged locally at the first main face 2A′ and in the recess 19 (see Figures 7 to 9 ).

[0088] The step of forming the second contact structure 21' may include producing a termination layer 22' which covers one or more surfaces 2C', 2D' of the semiconductor layer sequence 2' which bound the recess 19 (see Figure 7 ). For example, the termination layer 22' can only cover the surface 2D' arranged at the bottom of the recess 19 or additionally cover the surface 2C'. The termination layer 22' is applied in particular so that the second semiconductor layer 8' can be electrically contacted via the termination layer. The termination layer 22' can be produced from one or more material compounds and / or layer sequences of materials, which are metallic. For example, the following materials or material compounds are considered for the termination layer 22', which contain Au or Pd and are doped with Ge, for example. Surface oxides can be removed before applying the termination layer 22'. After applying the termination layer 22', a so-called annealing process can be performed.

[0089] As from Figure 7 It is known from the figure that a cavity 23 is formed in the widened region 19B of the depression 19 between the semiconductor layer sequence 2' and the insulating layer 20' or the terminal layer 22', which cavity is, for example, substantially unfilled, so that a vacuum exists therein, or is gas-filled. The cavity can be formed in such a way that the insulating layer 20' or the terminal layer 22' in the widened region 19B also follows the original shape of the depression 19 or the shape of the first region 19A of the depression 19 in terms of its extension.

[0090] As from Figure 8 It is known from the figure that the step of forming the second contact structure 21' can also include: forming a solder barrier layer 24' and forming a first solder layer 25', wherein the solder barrier layer 24' is arranged between the semiconductor layer sequence 2' and the first solder layer 25'. The solder barrier layer 24' is designed to prevent the solder material from diffusing inwardly into the layers 2', 13', 18', 20', for example. The solder barrier layer 24' and the first solder layer 25' can cover the first main surface 2A' and also fill the recess 19. Suitable materials for the solder barrier layer 24' are, for example, WTi, Ti or Ta. For the first solder layer 25', for example, AuPt, Au or Ni are considered.

[0091] Furthermore, the step of forming the second contact structure 21' may include forming a second solder layer (not shown) on the first solder layer 25', the second solder layer being connected to the first solder layer 25' when bonded to the carrier 27', so that a connection layer 26' is formed (see Fig. 9 ). Suitable materials for the second solder layer are, for example, Sn and InSn, so that the connection layer 26' contains, for example, AuSn, AuInSn, NiSn or NiInSn. The carrier 27' can be formed from a semiconductor material such as, for example, Ge or Si or a ceramic material such as, for example, SiN. The carrier 27' is applied to the side of the semiconductor layer sequence 2' facing away from the substrate 3.

[0092] The method may further comprise the step of removing the substrate 3 (cf. Fig.10 ). In this case, the second main surface 2B' of the semiconductor layer sequence 2' can be exposed. For example, the substrate 3 can be removed by means of wet chemical etching. In addition, the method may include the step of forming a radiation coupling-out structure 28' in the radiation exit layer 10'. For example, the radiation coupling-out structure 28' can be produced by roughening the surface of the radiation exit layer 10' facing away from the carrier 27' or by roughening the second semiconductor region 6' at the second main surface 2B'. Roughening can be performed, for example, by means of photolithography and dry etching processes.

[0093] The method further comprises the step of structuring the semiconductor layer sequence 2 ′ (see Fig.10 ). For example, the structuring can be performed by means of dry etching. During the structuring, the edge region of the semiconductor layer sequence 2' can be removed, so that, for example, the second expansion layer 14' at least partially protrudes above the semiconductor layer sequence 2' and can make contact with the contact pad 29, for example, formed of Au, in the protruding region (see Fig.11 ). The semiconductor layer sequence 2 ′ can be structured in such a way that it has a mesa-like structure and the carrier 27 ′ projects above the semiconductor layer sequence 2 ′ on all sides in a plan view onto the semiconductor layer sequence 2 ′.

[0094] according to Fig.12 An exemplary embodiment of an optoelectronic semiconductor device 1 is described, which can be used in combination with Figures 1 to 11 The method described herein is used to produce Fig.11 After the step shown in , the optoelectronic semiconductor components 1 are singulated between the dashed areas by detaching from the layer composite 100 . Therefore, the features and relationships described in conjunction with the method apply correspondingly to the optoelectronic semiconductor components 1 and vice versa.

[0095] The optoelectronic semiconductor component 1 comprises a carrier 27 and a semiconductor layer stack 2 arranged thereon, wherein the carrier 27 of the optoelectronic semiconductor component 1 is separated from the carrier 27 ′ by a singulation process (see Fig.11) and the semiconductor layer stack 2 corresponds to the structured semiconductor layer sequence 2 ′ (see Fig.11 ).

[0096] The semiconductor layer stack 2 has, corresponding to the semiconductor layer sequence 2', a first semiconductor region 4, a second semiconductor region 6 and an active region 5, which is arranged between the first and second semiconductor regions 4, 6 and is designed to generate or emit electromagnetic radiation, for example in the visible to infrared spectral range. Correspondingly, the optoelectronic semiconductor component 1 can emit electromagnetic radiation, for example in the visible to infrared spectral range, during operation. In this case, the main part of the radiation can be emitted at the second main surface 2B of the semiconductor layer stack 2, which is arranged at the front side of the semiconductor component 1.

[0097] Advantageously, the second main surface 2B has no contact structure, so that no radiation loss due to shading occurs at the second main surface 2B. The optoelectronic semiconductor device 1 has a first contact structure 11 for electrically contacting the first semiconductor region 4, which is locally arranged at the first main surface 2A of the semiconductor layer stack 2. The first contact structure 11 can be, for example, combined with Figure 1 As explained, there is a first expansion layer 12 arranged on the first main surface 2A and a second expansion layer 14 arranged between the first expansion layer 12 and the carrier 27. A mirror layer 13 can be arranged between the first and second expansion layers 12, 14, which also forms part of the first contact structure 11 with good electrical conductivity.

[0098] Furthermore, the optoelectronic semiconductor component 1 has a second contact structure 21 for electrically contacting the second semiconductor region 6, which is arranged locally at the first main surface 2A and in the recess 19 of the semiconductor layer stack 2. Figures 7 to 10 As explained in detail, the second contact structure 21 can have a terminal layer 22 arranged in the recess 19 , a connection layer 26 adjoining the carrier 27 , and a solder barrier layer 24 which is arranged on that side of the connection layer 26 which faces the semiconductor layer stack 2 .

[0099] The first main face 2A, which can be formed, for example, by the surface of the first semiconductor region 4, and the second main face 2B, which can be formed, for example, by the surface of the second semiconductor region 6, are opposite and are arranged on the side of the semiconductor layer stack 2 facing the carrier 27. The first semiconductor region 4, for example, a p-conducting region, can be arranged on the side of the active region 5 facing the carrier 27. The second semiconductor region 6, for example, an n-conducting region, can be arranged on the side of the active region 5 facing away from the carrier 27.

[0100] If already combined Figure 1As described, the second semiconductor region 6 comprises a first semiconductor layer 7, which has a first compound semiconductor material with a higher aluminum content, and a second semiconductor layer 8, which has a second compound semiconductor material different from the first compound semiconductor material and with a lower aluminum content. The first and second compound semiconductor materials are, for example, phosphide compound semiconductor materials. By means of the different aluminum contents in the first and second semiconductor layers 7, 8, the two-stage etching process for producing the recess 19 can be precisely controlled so that the etching process stops in the second semiconductor layer 8, and the second semiconductor region 6 is electrically contacted by means of the second semiconductor layer. By relatively small thicknesses d1, d2 (see Figure 1 and Figure 6 Embodiments of the invention (the thickness of which can be achieved by means of a precise two-stage etching process), in particular due to lower absorption, can achieve a highly efficient semiconductor device 1. The first semiconductor layer 7 is arranged between the active region 5 and the second semiconductor layer 8.

[0101] The recess 19, in which the second contact structure 21 is partially arranged, extends from the first main surface 2A of the semiconductor layer stack 2 through the first semiconductor region 4 and the active region 5 and ends at the second semiconductor layer 8. For example, the recess 19 or the contact region 21A of the second contact structure 21 arranged in the recess 19 has a three-dimensional shape with a varying cross section, for example the shape of a truncated cone or a truncated pyramid. Here, the cross section can become smaller with increasing depth, wherein the depth can be determined parallel to the vertical direction V, along which the semiconductor regions 4, 5, 6 follow one another starting from the carrier 27. For example, the shape and size of the contact region 21A are determined by the shape and size of the recess 19. The shape and size of the contact region 21 can be at least approximately identical to the shape and size of the recess 19. It is possible that the semiconductor component 1 has more than one recess 19 or more than one contact region 21A in the case of excessively high contact resistance and / or surface resistance, wherein the plurality of recesses 19 or contact regions 21A can vary in their size and / or their mutual spacing.

[0102] The recess 19 has a widened region 19B between the active region 5 and the second semiconductor layer 8. The widened region 19B can be evaluated as an indication of a two-stage etching process. With regard to the vertical extension h and the lateral extension b of the widened region 19B, reference is made to the combined Figure 6 implementation plan.

[0103] In the widened region 19B, a cavity 23 is formed between the semiconductor layer stack 2 and the second contact structure 21, which cavity is, for example, substantially unfilled, so that a vacuum exists therein, or the cavity is filled with air. For example, the extension of the termination layer 22 and further layers applied to the semiconductor layer stack 2, such as, for example, the insulation layer 20, in the widened region 19B continues to follow the original shape of the recess 19, which would have had the original shape without the continuation of the widened region (see also Figure 2 implementation method).

[0104] By means of the first and second contact structures 11, 21, it is possible to electrically connect the optoelectronic semiconductor component 1 from the outside at only one side of the semiconductor component 1. For example, a first contact pad 29 of the first contact structure 11 serving as a first electrode of the semiconductor component 1 and a second contact pad (not shown) of the second contact structure 21 serving as a second electrode of the semiconductor component 1 are arranged laterally on a raised region of the carrier 27 of the semiconductor layer stack 2 and are designed for connection to a contact means, such as a bonding wire.

[0105] The first contact pad 29 is arranged on a region of the reflective element 15 which is locally arranged at the first main surface 2A and is not covered by the semiconductor layer stack 2 and extends through the opening of the reflective element 15 to the second expansion layer 14 of the first contact structure 11. Figure 1 As explained in detail, the second expansion layer 14 , like the mirror layer 13 , extends through the opening 16 in the reflective element 15 as far as the first expansion layer 12 .

[0106] By means of the insulating layer 20 (see Figures 4 to 6 ) and the insulating layer 18 (see Figure 1 ), the first contact structure 11 may be electrically insulated from the second contact structure 21.

[0107] The first and second contact structures 11 , 21 enable a uniform current distribution in the semiconductor layer stack 2 , so that even larger semiconductor components can be realized.

[0108] The invention is not restricted to the description based on the exemplary embodiments. Rather, the invention comprises any novel feature and any combination of features, which in particular includes any combination of features in the claims, even if the feature or the combination itself is not described in detail in the claims or exemplary embodiments.

[0109] This patent application claims the priority of German patent application 102022119108.7, the disclosure content of which is incorporated herein by reference.

[0110] Reference numerals list

[0111] 1 Optoelectronic semiconductor devices

[0112] 2 Semiconductor layer stacking

[0113] 2A First main surface

[0114] 2B Second main surface

[0115] 2C, 2D surface

[0116] 2' Semiconductor layer sequence

[0117] 2A' First main surface

[0118] 2B' Second main surface

[0119] 2C', 2D' surfaces

[0120] 2E, 2E' Side

[0121] 3 Substrate

[0122] 4, 4' first semiconductor region

[0123] 5, 5' active area

[0124] 6, 6' Second semiconductor region

[0125] 7, 7' First semiconductor layer

[0126] 8, 8' Second semiconductor layer

[0127] 9 Third semiconductor layer

[0128] 10, 10' Radiation exit layer

[0129] 11, 11' first contact structure

[0130] 12, 12' First expansion layer

[0131] 13, 13' mirror layer

[0132] 14, 14' Second expansion layer

[0133] 15, 15' reflective element

[0134] 16, 17 Opening

[0135] 18, 18' Insulation

[0136] 19 Depression

[0137] 19A First Area

[0138] 19B Widened second area

[0139] 20, 20' Insulation

[0140] 21, 21' Second contact structure

[0141] 21A Contact area

[0142] 22, 22' termination layer

[0143] 23 Cavity

[0144] 24, 24' Solder barrier layer

[0145] 25' First solder layer

[0146] 26, 26' connection layer

[0147] 27, 27' carrier

[0148] 28, 28' Radiative coupling output structure

[0149] 29 First contact plate

[0150] 100-layer composite

[0151] α Angle

[0152] b Horizontal expansion

[0153] d1, d2 thickness

[0154] H Depth, vertical extension

[0155] V vertical direction

[0156] L Horizontal direction

Claims

1. An optoelectronic semiconductor device (1), comprising: - a semiconductor layer stack (2), the semiconductor layer stack comprising: - a first semiconductor region (4), - a second semiconductor region (6), and an active region (5), said active region being arranged between said first semiconductor region and said second semiconductor region (4, 6), said second semiconductor region (6) comprising a first semiconductor layer (7) and a second semiconductor layer (8), and said second semiconductor layer (8) being arranged on a side of said first semiconductor layer (7) facing away from said active region (5), at least one recess (19), which extends from the first main surface (2A) of the semiconductor layer stack (2) through the first semiconductor region (4) and the active zone (5) and ends at the second semiconductor layer (8), a first contact structure (11) for electrically contacting the first semiconductor region (4), the first contact structure being arranged at least partially at the first main surface (2A), a second contact structure (21) for electrically contacting the second semiconductor region (6), the second contact structure being arranged locally at the first main surface (2A) and in the at least one recess (19), The first semiconductor layer (7) comprises a first compound semiconductor material and the second semiconductor layer (8) comprises a second compound semiconductor material, and the first compound semiconductor material has a higher aluminum content than the second compound semiconductor material. 2 . The optoelectronic semiconductor component ( 1 ) according to claim 1 , wherein the first compound semiconductor material and the second compound semiconductor material are each a phosphide compound semiconductor material.

3. The optoelectronic semiconductor device (1) according to claim 1, wherein the first compound semiconductor material comprises Al n Ga m In 1-n-m P, where 0.3≤n≤0.6, 0≤m≤0.2 and 0.4≤n+m≤0.

6.

4. The optoelectronic semiconductor device (1) according to claim 1, wherein the second compound semiconductor material comprises Al n Ga m In 1-n-m P, where 0<n<0.6, 0<m<0.6 and 0.4≤n+m≤0.

6. 5 . The optoelectronic semiconductor component ( 1 ) as claimed in claim 1 , wherein the second semiconductor layer ( 8 ) is thinner than the first semiconductor layer ( 7 ).

6. An optoelectronic semiconductor device (1) according to any of the above claims, wherein the second semiconductor region (6) has a third semiconductor layer (9), which is arranged on the side of the second semiconductor layer (8) facing away from the first semiconductor layer (7) and contains InGaAlP, wherein the compound semiconductor materials of the second semiconductor layer and the third semiconductor layer (8, 9) differ in their gallium content and / or their doping level.

7. The optoelectronic semiconductor component (1) according to claim 1, wherein a second main surface (2B) of the semiconductor layer stack (2) which is opposite the first main surface (2A) does not have the first contact structure and the second contact structure (11, 21).

8. The optoelectronic semiconductor component (1) as claimed in claim 1, wherein the recess (19) has a widened region (19B) between the active zone (5) and the second semiconductor layer (8).

9. An optoelectronic semiconductor device (1) according to any of the above claims, wherein the second contact structure (21) has a termination layer (22), and the termination layer (22) covers one or more surfaces (2C, 2D) of the semiconductor layer stack (2) that bound the at least one recess (19).

10. The optoelectronic semiconductor component (1) according to claim 1, wherein a cavity (23) is formed in the widened region (19B) between the semiconductor layer stack (2) and the second contact structure (21).

11. The optoelectronic semiconductor component (1) according to any one of the two preceding claims, comprising an insulation layer (20), wherein the insulation layer (20) is arranged between the semiconductor layer stack (2) and the termination layer (22).

12. A method for producing at least one optoelectronic semiconductor component (1), the method comprising: - providing a semiconductor layer sequence (2') for producing at least one semiconductor layer stack (2), wherein the semiconductor layer sequence (2') comprises: - a first semiconductor region (4'), - a second semiconductor region (6'), an active region (5'), said active region being arranged between said first semiconductor region and said second semiconductor region ((4', 6'), wherein said second semiconductor region (6') comprises a first semiconductor layer (7') and a second semiconductor layer (8'), and said second semiconductor layer (8') being arranged on a side of said first semiconductor layer (7') facing away from said active region (5'), and - a first main surface (2A'), - forming a first contact structure (11') on the first main surface (2A'), - producing at least one recess (19) which extends from the first main surface (2A') through the first semiconductor region (4') and the active zone (5') and ends in the second semiconductor layer (8'), - forming a second contact structure (21'), which is locally arranged at the first main surface (2A') and in the at least one recess (19), wherein the at least one recess (19) is produced by a two-stage etching process and the semiconductor layer sequence (2') is etched into the first semiconductor layer (7') in a first etching step and is etched into the second semiconductor layer (8') in a second etching step.

13. The method according to the preceding claim, wherein the first etching step comprises a dry etching process.

14. The method according to any of the two preceding claims, wherein the second etching step comprises a wet chemical etching process.

15. The method according to claim 12, wherein the first semiconductor layer (7') is formed by means of a first compound semiconductor material and the second semiconductor layer (8') is formed by means of a second compound semiconductor material, and the first compound semiconductor material has a greater aluminum content than the second compound semiconductor material.

16. The method according to claim 1, wherein an etchant is used for the wet-chemical etching process, which has a higher etching rate for the first semiconductor layer (7') with a higher aluminum content than for the second semiconductor layer (8') with a lower aluminum content.

17. The method according to any one of claims 12 to 16, wherein a widened region (19B) of the at least one recess (19) is produced by means of the second etching step.

18. The method according to claim 12, wherein the active region (5') has a quantum well structure and the mixing of the quantum well structure is carried out in a region of the active region (5') adjoining the at least one recess (19).

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