Flip MEMS pressure chip and preparation method thereof

Abstract

The flip MEMS pressure chip comprises an SOI substrate and a glass cover plate, and the top surface of the substrate is in bonding connection with the bottom surface of the cover plate; the top surface of the substrate is provided with four piezoresistors, the four piezoresistors are connected through a guide circuit to form a Wheatstone bridge, and four joints of the Wheatstone bridge are provided with electric connection discs; four through connecting holes are formed in the top surface of the cover plate, conductive materials are filled in the connecting holes, the bottom surfaces of the conductive materials are connected with the corresponding electric connecting discs, and a concave cavity is formed in the center of the bottom surface of the cover plate. According to the invention, the vertical connection of the circuit is realized through the cover plate, so that the chip can be directly inverted on the circuit board or the tube socket without lead bonding. In addition, the circuit structure is arranged in the front concave cavity, and the back of the chip is used for sensing pressure, so that silicone oil does not need to be filled to protect the circuit structure of the chip, and the performance and the stability of the chip are improved. After the silicone oil and the lead wire are removed from the core body, the size of the core body is greatly reduced, the working temperature area is improved, and the risk that the lead wire is broken or falls off to cause sensor failure is avoided.

Description

Technical Field

[0001] The present invention relates to the technical field of MEMS pressure sensors, and in particular to a flip-chip MEMS pressure chip and a preparation method thereof. Background Art

[0002] MEMS piezoresistive pressure sensor is the first mass-produced MEMS product and is widely used in many fields such as consumer electronics, automotive industry, aerospace, national defense and military.

[0003] The traditional silicon piezoresistive pressure chip has a simple structure and is made by bonding a glass base to the bottom of an etched silicon substrate. The packaging form of this type of chip is relatively simple. The silicon piezoresistive chip is attached to the tube shell by chip glue, and the pads on the chip are connected to the pins of the tube socket by wire bonding. Finally, the tube shell is filled with silicone oil and sealed with an isolation diaphragm. Because the pressure-sensing surface and the varistor are both located on the upper surface of the chip, oil filling can protect the chip from external influences. For example, corrosive measured gases may destroy the circuit structure on the front of the chip, but silicone oil will seriously affect the basic performance of the chip, especially in high and low temperature environments. In addition, wire bonding also poses challenges to the reliability of the sensor. Broken or falling wires will cause the sensor to fail. Summary of the invention

[0004] The present invention proposes a flip-chip MEMS pressure chip and a preparation method thereof, which solves the limitation that the packaging method of the silicon piezoresistive pressure chip in the prior art needs to fill oil in the tube shell and use wire bonding to connect the pads on the chip with the pins of the tube seat. The oil filling will seriously affect the performance and stability of the chip and greatly reduce the operating temperature range of the sensor. The wire bonding will cause the wire to break or fall off, resulting in sensor failure and other problems.

[0005] The technical solution of the present invention is achieved in this way: The first aspect of the present invention provides a flip-chip MEMS pressure chip, comprising an SOI substrate and a glass cover plate, wherein the top surface of the substrate is bonded to the bottom surface of the cover plate; four varistors are provided on the top surface of the substrate, and the four varistors are connected through a conductive path to form a Wheatstone bridge, and electrical connection pads are provided at the four joints of the Wheatstone bridge; four through-going connection holes are provided on the top surface of the cover plate, and the connection holes are filled with conductive material, and the bottom surface of the conductive material is connected to the corresponding electrical connection pads, and a concave cavity is provided in the center of the bottom surface of the cover plate.

[0006] The present invention realizes circuit connection through the cover plate, so that the chip can be inverted on the circuit board or the tube seat, and the pressure is sensed by the back of the chip. Since the circuit structure is in the front concave cavity, it is not necessary to fill silicone oil to protect the circuit structure of the chip, thereby improving the performance and stability of the chip. The pads on the chip are connected to the straight-insertion pins through conductive materials, and wire bonding is not required. The chip can be directly inserted into the required substrate or printed circuit board, reducing the size of the core body, and there is no problem of sensor failure due to broken or falling leads.

[0007] Specifically, the top surface of the cover plate is covered with a first insulating layer, a first opening is provided at a position on the top surface of the first insulating layer corresponding to the connection hole, a conductive bump is provided at the first opening, and the conductive bump is connected to the conductive material.

[0008] Furthermore, the top surface of the first insulating layer is covered with a passivation layer.

[0009] Specifically, a circle of supporting ring is provided on the edge of the top surface of the substrate, and the top surface of the supporting ring is bonded to the bottom surface of the cover plate.

[0010] Specifically, the top surface of the substrate is covered with a second insulating layer, and a second opening is provided at a position on the top surface of the second insulating layer corresponding to the electrical connection pad.

[0011] Specifically, a back cavity is provided on the bottom surface of the substrate.

[0012] Preferably, the substrate is made of SOI material, and the cover plate is made of glass.

[0013] A second aspect of the present invention provides a method for preparing a flip-chip MEMS pressure chip, comprising the following steps: Generating heavily doped regions and lightly doped regions on a device layer of an SOI substrate; A Wheatstone bridge and an edge support ring are etched on the device layer of the SOI substrate, wherein the Wheatstone bridge is composed of four lightly doped varistors connected to a heavily doped conductive path, and the Wheatstone bridge is insulated and isolated from the base of the SOI substrate by a buried oxide layer; A second insulating layer is formed on the top surface of the SOI substrate, and second openings are formed on the second insulating layer corresponding to four connection positions of the Wheatstone bridge; generating a conductive layer connected to the connector at the second opening, and etching an electrical connection pad on the conductive layer; A back cavity is etched on the bottom surface of the SOI substrate; Etching four blind holes corresponding to the electrical connection pads on the top surface of the cover plate, and filling the blind holes with conductive material; Generating a first insulating layer on the top surface of the cover plate, and opening a first opening on the first insulating layer at a position corresponding to the conductive material; Generating a conductive bump on the first opening by using a bump process, wherein the conductive bump is connected to the conductive material; The bottom surface of the cover plate is thinned and polished so that the conductive material is exposed on the bottom surface of the cover plate; Etching a cavity in the center of the bottom surface of the cover plate; The cover plate is placed on the top surface of the SOI substrate, the conductive material on the bottom surface of the cover plate is butted against the electrical connection pad on the top surface of the SOI substrate, and the cover plate is bonded to the SOI substrate to form a flip-chip MEMS pressure chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0015] Figure 1 This is a schematic diagram of the internal layered structure of a flip-chip MEMS pressure chip of the present invention; Figure 2 Schematic diagram of the arrangement structure of the Wheatstone bridge on the top surface of the substrate in an embodiment of the present invention; FIG3 (a) is a schematic diagram showing the structure of generating heavily doped regions and lightly doped regions on the top surface of the device layer of the substrate; FIG3 (b) is a schematic diagram showing the structure of etching the top surface of the device layer of the substrate to generate a Wheatstone bridge and an edge support ring; FIG3 (c) is a schematic diagram showing the structure of generating a second insulating layer on the top surface of the substrate and etching the second openings on the second insulating layer corresponding to the four joint positions of the Wheatstone bridge; FIG3 (d) is a schematic diagram showing the structure of generating a conductive layer connected to the joints at the second openings; FIG3 (e) is a schematic diagram showing the structure of etching the back cavity on the bottom surface of the substrate; FIG4 (a) is a schematic diagram showing a structure in which a blind hole is formed by etching on the top surface of a cover plate; FIG4 (b) is a schematic diagram showing a structure in which a conductive material is filled in the blind hole; FIG4 (c) is a schematic diagram showing a structure in which a first insulating layer is formed on the top surface of the cover plate, and a first opening is etched on the first insulating layer at a position corresponding to the conductive material; FIG4 (d) is a schematic diagram showing a structure in which a hemispherical conductive bump is formed on the first opening; FIG4 (e) is a schematic diagram showing a structure in which a thinning and polishing process is performed on the bottom surface of the cover plate so that the conductive material is exposed on the bottom surface of the cover plate; FIG4 (f) is a schematic diagram showing a structure in which a cavity is etched in the center of the bottom surface of the cover plate; In the figure: 1. substrate; 2. cover plate; 3. varistor; 4. guide path; 5. electrical connection plate; 6. conductive material; 7. cavity; 8. first insulating layer; 9. first opening; 10. conductive bump; 11. passivation layer; 12. support ring; 13. second insulating layer; 14. second opening; 15. back cavity; 16. device layer; 17. heavily doped region; 18. lightly doped region; 19. base; 20. buried oxide layer; 21. blind hole. DETAILED DESCRIPTION

[0016] The technical solution of the present invention will be clearly and completely described below in conjunction with the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0017] Reference Figure 1 , 2 In a first aspect, an embodiment of the present invention provides a flip-chip MEMS pressure chip, comprising a substrate 1 and a cover plate 2, wherein the top surface of the substrate 1 is bonded to the bottom surface of the cover plate 2; the top surface of the substrate 1 is provided with four piezoresistors 3, and the four piezoresistors 3 are connected through a conducting path 4 to form a Wheatstone bridge, and the four joints of the Wheatstone bridge are provided with electrical connection pads 5 (in this embodiment, the electrical connection pads 5 are copper pads, and materials with the same or similar properties may also be used instead in the specific implementation process); the top surface of the cover plate 2 is provided with four through-holes, and the connection holes are provided with It is filled with a conductive material 6 (in this embodiment, the conductive material 6 is copper, and a material with the same or similar properties can also be used instead during the specific implementation process), the bottom surface of the conductive material 6 is connected to the corresponding electrical connection plate 5, and a cavity 7 is opened in the center of the bottom surface of the cover plate 2. The cavity 7 can provide space for the compressive deformation of the substrate 1, and the compressive deformation of the substrate 1 can be controlled according to the depth of the cavity 7; in addition, compared with the traditional pressure chip that uses an isolation diaphragm to bear pressure, the present invention uses the cavity 7 as a stopping structure for diaphragm deformation, which greatly improves the chip's anti-overload performance.

[0018] The present invention realizes vertical connection of the circuit through the cover plate 2, so that the chip can be inverted on the circuit board or the tube seat, and the pressure is sensed by the back of the chip. Since the circuit structure is in the front cavity 7, it is not necessary to fill silicone oil to protect the circuit structure of the chip, thereby improving the performance and stability of the chip. The pads on the chip are connected to the straight-insertion pins through the conductive material 6, and wire bonding is not required. The chip can be directly inserted into the required substrate or printed circuit board, reducing the size of the core body, and there is no problem of sensor failure due to broken or falling leads.

[0019] In this embodiment, the substrate 1 is made of SOI (silicon on insulator) material, and the SOI substrate 1 includes a device layer 16 (silicon), a buried oxide layer 20 and a base 19 from top to bottom; the cover plate 2 is made of glass material; in the specific implementation process, the substrate 1 and the cover plate 2 can also be made of materials with the same or similar properties as the above materials.

[0020] Specifically, the top surface of the cover plate 2 is covered with a first insulating layer 8 (silicon dioxide), and a first opening 9 is provided at a position on the top surface of the first insulating layer 8 corresponding to the connection hole, and a conductive bump 10 is provided at the first opening 9 (in this embodiment, the conductive bump 10 is a copper bump, and a material with the same or similar properties can also be used instead during the specific implementation process), and the conductive bump 10 is connected to the conductive material 6.

[0021] Furthermore, the top surface of the first insulating layer 8 is covered with a passivation layer 11, and the passivation layer 11 can protect the first insulating layer 8 and play an anti-corrosion role.

[0022] Specifically, a circle of supporting ring 12 is provided on the edge of the top surface of the substrate 1 , and the top surface of the supporting ring 12 is bonded to the bottom surface of the cover plate 2 .

[0023] Specifically, the top surface of the substrate 1 is covered with a second insulating layer 13 , and a second opening 14 is provided at a position on the top surface of the second insulating layer 13 corresponding to the electrical connection pad 5 .

[0024] Specifically, a back cavity 15 is provided on the bottom surface of the substrate 1 .

[0025] A second aspect of an embodiment of the present invention provides a method for preparing a flip-chip MEMS pressure chip, comprising the following steps: SOI substrate 1 processing steps: a1. A heavily doped region 17 and a lightly doped region 18 are generated on the device layer 16 of the SOI substrate 1 by an ion implantation process, as shown in FIG3(a). The lightly doped region 18 is used to form a varistor 3, and the heavily doped region 17 is used to form a conductive path 4. In this embodiment, the doped particles and their concentrations can be flexibly adjusted according to actual conditions so as to be able to form a varistor and a conductive path.

[0026] a2. A Wheatstone bridge and an edge support ring 12 are etched on the device layer 16 of the SOI substrate 1 using reactive ion etching technology, as shown in FIG3 (b); the Wheatstone bridge is composed of four lightly doped varistors 3 and heavily doped conductive paths 4 connected to each other, and the Wheatstone bridge is insulated and isolated from the base 19 of the SOI substrate 1 by a buried oxide layer 20; in this step, all the redundant parts on the device layer 16 are etched away, leaving only the varistor 3, conductive path 4 and support ring 12, so that the varistor 3 is completely insulated from the base 19 by the buried oxide layer 20, thereby avoiding the PN junction leakage current generated by high temperature and greatly improving the working temperature range of the chip; the support ring 12 plays a role in subsequent bonding with the cover plate 2 on the one hand, and plays a role in sealing the cavity 7 on the other hand.

[0027] a3, using plasma enhanced chemical vapor deposition to form a second insulating layer 13 (silicon dioxide) on the top surface of the SOI substrate 1, and using a reactive ion etching process to etch the second insulating layer 13 at the four joint positions of the Wheatstone bridge to form a second opening 14 for subsequent metal deposition, as shown in FIG3 (c); a4, using a magnetron sputtering process to generate a conductive layer (copper in this embodiment) connected to the connector at the second opening 14, and using an ion beam to etch an electrical connection pad 5 on the conductive layer, as shown in FIG3 (d); a5, a back cavity 15 is etched on the bottom surface of the SOI substrate 1 by deep reactive ion etching process to form a back island structure, as shown in FIG3 (e). The measurement range of the chip can be changed by adjusting the size of the back island.

[0028] Cover plate 2 processing steps: b1, using a pulsed laser induced process to generate a continuous denatured zone on the top surface of the cover plate 2 and at four positions corresponding to the electrical connection pads 5, and then using a hydrofluoric acid solution to etch the denatured zone to form an inverted tapered blind hole 21, as shown in FIG4 (a); b2, using physical vapor deposition to deposit a seed layer in the blind hole 21, and then electroplating from the bottom up to fill the blind hole 21 with metal copper, and finally etching the desired pattern on its top surface, as shown in FIG4 (b); b3, using plasma enhanced chemical vapor deposition to form a first insulating layer 8 (silicon dioxide) on the top surface of the cover plate 2, and using an ion beam to etch a first opening 9 on the first insulating layer 8 at a position corresponding to the conductive material 6, as shown in FIG4 (c); b4, a hemispherical conductive bump 10 (copper bump in this embodiment) is generated on the first opening 9 by a bump process, and the conductive bump 10 is connected to the conductive material 6, as shown in FIG4 (d); the standard copper bump preparation process mainly includes repassivation, sputtering, etching, electroplating, reflow and other processes; b5, thinning and polishing the bottom surface of the cover plate 2 so that the conductive material 6 is exposed from the bottom surface of the cover plate 2, as shown in FIG4 (e); b6, a cavity 7 is etched in the center of the bottom surface of the cover plate 2 to form an absolute pressure cavity of the chip in cooperation with the SOI substrate 1, and to reserve a space for the chip to be compressed and deformed, as shown in FIG4(f).

[0029] Finally, the cover plate 2 is placed on the top surface of the SOI substrate 1, so that the conductive material 6 on the bottom surface of the cover plate 2 is connected to the electrical connection pad 5 on the top surface of the SOI substrate 1, and the cover plate 2 is bonded to the SOI substrate 1 to form a flip-chip MEMS pressure chip. Figure 1 shown.

[0030] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A flip-chip MEMS pressure chip, characterized in that: The invention comprises a substrate (1) and a cover plate (2), wherein the top surface of the substrate (1) is bonded to the bottom surface of the cover plate (2); four varistors (3) are arranged on the top surface of the substrate (1), the four varistors (3) are connected via a conducting path (4) to form a Wheatstone bridge, and four joints of the Wheatstone bridge are provided with electrical connection plates (5); four through-holes are provided on the top surface of the cover plate (2), the connection holes are filled with a conductive material (6), the bottom surface of the conductive material (6) is connected to the corresponding electrical connection plate (5), and a concave cavity (7) is provided in the center of the bottom surface of the cover plate (2).

2. A flip-chip MEMS pressure chip as claimed in claim 1, characterized in that: The top surface of the cover plate (2) is covered with a first insulating layer (8), a first opening (9) is provided at a position on the top surface of the first insulating layer (8) corresponding to the connection hole, a conductive bump (10) is provided at the first opening (9), and the conductive bump (10) is connected to the conductive material (6).

3. A flip-chip MEMS pressure chip as claimed in claim 2, characterized in that: The top surface of the first insulating layer (8) is covered with a passivation layer (11).

4. A flip-chip MEMS pressure chip as claimed in claim 1, characterized in that: A circle of supporting ring (12) is provided on the edge of the top surface of the substrate (1), and the top surface of the supporting ring (12) is bonded to the bottom surface of the cover plate (2).

5. The flip-chip MEMS pressure chip according to claim 1, characterized in that: The top surface of the substrate (1) is covered with a second insulating layer (13), and a second opening (14) is provided at a position on the top surface of the second insulating layer (13) corresponding to the electrical connection plate (5).

6. The flip-chip MEMS pressure chip according to claim 1, characterized in that: The bottom surface of the substrate (1) is provided with a back cavity (15).

7. The flip-chip MEMS pressure chip according to claim 1, characterized in that: The substrate (1) is made of SOI material, and the cover plate (2) is made of glass.

8. A method for preparing a flip-chip MEMS pressure chip, characterized in that: The following steps are involved: Generating a heavily doped region (17) and a lightly doped region (18) on a device layer (16) of an SOI substrate (1); A Wheatstone bridge and an edge support ring (12) are etched on a device layer (16) of an SOI substrate (1), wherein the Wheatstone bridge is formed by connecting four lightly doped varistors (3) and a heavily doped conducting path (4), and the Wheatstone bridge is insulated and isolated from a base (19) of the SOI substrate (1) by a buried oxide layer (20); A second insulating layer (13) is formed on the top surface of the SOI substrate (1), and second openings (14) are formed on the second insulating layer (13) at positions corresponding to four connections of the Wheatstone bridge; Generating a conductive layer connected to the joint at the second opening (14), and etching an electrical connection pad (5) on the conductive layer; Etching a back cavity (15) on the bottom surface of the SOI substrate (1); Etching four blind holes (21) corresponding to the electrical connection plates (5) on the top surface of the cover plate (2), and filling the blind holes (21) with conductive material (6); A first insulating layer (8) is formed on the top surface of the cover plate (2), and a first opening (9) is formed on the first insulating layer (8) at a position corresponding to the conductive material (6); A conductive bump (10) is generated on the first opening (9) using a bump process, wherein the conductive bump (10) is connected to the conductive material (6); The bottom surface of the cover plate (2) is thinned and polished so that the conductive material (6) is exposed on the bottom surface of the cover plate (2); Etching a cavity (7) in the center of the bottom surface of the cover plate (2); The cover plate (2) is placed on the top surface of the SOI substrate (1), the conductive material (6) on the bottom surface of the cover plate (2) is connected to the electrical connection pad (5) on the top surface of the SOI substrate (1), and the cover plate (2) is bonded to the SOI substrate (1) to form a flip-chip MEMS pressure chip.

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