A power management unit redundant reset system, an automobile chip and an automobile

Abstract

The application relates to a power management unit redundant reset system, an automobile chip and an automobile. The reset system comprises a voltage stabilizing module, a native power-on reset module, an internal redundant power-on reset module, a reset mode configuration module and a reset signal output module. The digital voltage is input into the native power-on reset module and the internal redundant power-on reset module through the voltage stabilizing module and converted into an analog voltage. In the process of voltage boosting, the native power-on reset module continuously detects the rising of the digital voltage and the analog voltage, and outputs a reset signal to the chip function system when the digital voltage reaches a first threshold value and the analog voltage reaches a second threshold value. The internal redundant power-on reset module also continuously detects the rising of the analog voltage, and outputs a reset signal to the chip function system when the analog voltage reaches a third threshold value, so that the reset signal can be provided when the native power-on reset module fails, and the running stability and reliability of the chip can be improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of chip startup stability, and particularly relates to a power management unit redundant reset system, an automobile chip and an automobile. BACKGROUND

[0002] In the startup process of a chip in the automobile industry, in order to ensure that the chip has a good running state after power-on, the chip must go through three stages of power-on, reset and normal working state. Reset is the basis for normal work. The reset process includes reset, clock initialization to ensure that the clock system of the chip works normally, memory initialization to clear the data in the memory of the chip, peripheral initialization of various peripherals on the chip (such as serial ports, network ports, etc.), and operating system startup to enter the application program execution stage. As a key action for chip power-on, reset mainly includes power reset, hardware reset and software reset. The corresponding reset sequence is that when the power management unit (PMU) receives an external initial voltage signal, the VDD voltage rises to a set power-on reset (POR) threshold value, reset is performed, and a hardware reset signal is output to each hardware functional module of the chip. Each hardware functional module of the chip performs reset, and software is loaded and executed to perform corresponding functions after successful hardware reset.

[0003] As a chip system reset pre-module, the reset accuracy and success rate of the power management unit are directly related to whether a chip can normally start and run. Therefore, the reset capability of the power management unit is a core capability of the chip function, especially for vehicle-grade chips. The chip failure rate is the failure probability of on-chip logic or memory based on the failure probability of a single transistor at a certain process node. The larger the area, the more transistors, and the greater the failure rate.

[0004] The power management unit is provided with a clock oscillation module, a POR detection module and a reset module. The POR module detects that the VCC access voltage rises. Once the voltage reaches the threshold value, the clock oscillation module starts to work, and the reset module controls the PMU reset. The POR detection module may have stability problems due to process factors during power-on, such as Figure 1 as shown in Figure 1 is a schematic diagram of an abnormal trigger voltage of PMU reset (wherein Vpor represents a normal reset signal output, Vpor1 represents a reset signal output when the input voltage does not reach the target threshold value, and Vpor2 represents a reset signal output when the input voltage exceeds the threshold value). The specific performance is that the input voltage (for example, 1.8V) has exceeded the target threshold value (for example, 1.2V+100mV) but still cannot output the reset signal, the input voltage does not reach the target threshold value and outputs the reset signal in advance, and PMU failure, voltage fluctuation exceeding the upper limit and negative voltage impact will also cause the reset signal to be unable to be output, affecting the overall function of the chip system.

[0005] Therefore, the prior art still needs to be improved and developed. SUMMARY

[0006] One of the purposes of the present application is to provide a power management unit redundant reset system to solve the problem that the power-on reset detection module of the PMU cannot output a reset signal due to process factors, thereby affecting the overall function of the chip system; the second purpose is to provide an automobile chip; the third purpose is to provide an automobile.

[0007] In order to achieve the above-mentioned purposes, the technical scheme adopted by the present application is as follows:

[0008] A power management unit redundant reset system connected with a chip function system, comprising: a voltage stabilizing module, a native power-on reset module, an internal redundant power-on reset module, a reset mode configuration module and a reset signal output module; wherein the voltage stabilizing module is connected with a digital voltage and connected with the native power-on reset module and the internal redundant power-on reset module respectively, for converting the digital voltage into an analog voltage and inputting the analog voltage into the native power-on reset module and the internal redundant power-on reset module respectively;

[0009] The native power-on reset module is connected with the digital voltage and the analog voltage and connected with the reset mode configuration module, for outputting a reset signal to the reset mode configuration module after the digital voltage reaches a first threshold value and the analog voltage reaches a second threshold value;

[0010] The internal redundant power-on reset module is connected with the analog voltage and connected with the voltage stabilizing module and the reset mode configuration module respectively, for outputting a reset signal to the reset mode configuration module when the analog voltage reaches a third threshold value;

[0011] The reset mode configuration module is connected with the native power-on reset module, the internal redundant power-on reset module, an external redundant power-on reset module and the reset signal output module respectively, for outputting a reset signal to the reset signal output module;

[0012] The reset signal output module is connected with the reset mode configuration module and the chip function system respectively, for outputting a reset signal to the chip function system.

[0013] According to the technical solution, the digital voltage is input to the native power-on reset module and the internal redundant power-on reset module through the voltage stabilizing module and converted into an analog voltage. During the process of voltage boosting, the native power-on reset module continuously detects the rising of the digital voltage and the analog voltage. After the digital voltage reaches a first threshold value and the analog voltage reaches a second threshold value, a reset signal can be output to the reset mode configuration module. Then, the reset signal is output to the reset signal output module through the reset mode configuration module, and the reset signal is output to the chip function system through the reset signal output module. The internal redundant power-on reset module also continuously detects the rising of the analog voltage. When the analog voltage reaches a third threshold value, a reset signal is output to the reset mode configuration module. Then, the reset signal is output to the reset signal output module through the reset mode configuration module, and the reset signal is output to the chip function system through the reset signal output module. Therefore, a reset signal can be provided when the native power-on reset module fails, thereby improving the running stability and reliability of the chip and avoiding the influence of the overall function of the chip system caused by the failure of the PMU.

[0014] Further, the internal redundant power-on module includes a current generating unit and a first comparison unit. The current generating unit is connected to the voltage stabilizing module and the first comparison unit, and is configured to output a reference current to the first comparison unit according to the analog voltage. The first comparison unit is connected to the current generating unit and the reset mode configuration module, and is configured to convert the reference current into a reference voltage and compare the reference voltage with a third threshold value. When the reference voltage reaches the third threshold value, a reset signal is output to the reset mode configuration module.

[0015] According to the technical solution, the current generating unit obtains the analog voltage from the voltage stabilizing module, and then generates a high-precision reference current and inputs the high-precision current to the first comparison unit. After receiving the reference current, the first comparison unit converts the reference current into a voltage signal, i.e., a reference voltage, and compares the reference voltage with a third threshold value. When the reference voltage exceeds the third threshold value, a reset signal is output to the reset mode configuration module, so that a reset signal can be output to the chip function system when the native power-on reset module fails.

[0016] Further, the current generating unit comprises a PMOS tube, an operational amplifier, a reference voltage source, a first resistor, a second resistor, a third resistor, a fourth resistor and a first capacitor; wherein the source of the PMOS tube is connected to the analog voltage, the drain of the PMOS tube is connected to the output of the current generating unit, and the gate of the PMOS tube is connected to the output of the operational amplifier; the non-inverting input of the operational amplifier is connected to one end of the first resistor and one end of the second resistor, and the inverting input of the operational amplifier is connected to the positive electrode of the reference voltage source; the other end of the first resistor is connected to the output of the current generating unit, and the other end of the second resistor is grounded; one end of the third resistor is connected to the output of the current generating unit, and the other end of the third resistor is grounded; the negative electrode of the reference voltage source is connected to one end of the fourth resistor, and the other end of the fourth resistor is grounded; the first capacitor is connected in parallel with the third resistor; and the first comparison unit is a Schmitt trigger.

[0017] According to the above technical solution, when the source of the PMOS tube is connected to the analog voltage provided by the voltage stabilizing module, the initial voltage of the common connection end of the first resistor and the second resistor is 0, at this time the output of the operational amplifier causes the gate potential of the PMOS tube to drop, and because the source voltage of the PMOS tube is unchanged, the output voltage of the current generating unit rises to the reference voltage output by the reference voltage source, so that a stable reference current can be obtained.

[0018] In addition, the first comparison unit adopts a Schmitt trigger, and the Schmitt trigger has a hysteresis characteristic, which can ensure that a slight change in the power supply voltage after power-on completion will not cause the reset signal to be incorrectly flipped.

[0019] Further, the power management unit redundancy reset system further comprises an external redundancy power-on reset module; the external redundancy power-on reset module is connected to the analog voltage, and is configured to output a reset signal to the reset mode configuration module when the output voltage of the external redundancy power-on reset module reaches a fourth threshold value.

[0020] According to the above technical solution, the external redundancy power-on reset module detects the connected analog voltage, and can output a reset signal to the reset mode configuration module when the output voltage of the external redundancy power-on reset module reaches a fourth threshold value, so that a reset signal can still be output to the chip function system when the native power-on reset module and the internal redundancy power-on reset module fail, further improving the startup stability and reliability of the chip.

[0021] Further, the external redundant power-on reset module comprises a fifth resistor, a second capacitor and a diode; one end of the fifth resistor is connected to the analog voltage, and the other end of the fifth resistor is connected to one end of the second capacitor; the cathode of the diode is connected to the analog voltage, and the anode of the diode is connected to one end of the second capacitor; the other end of the second capacitor is grounded; and the common connection end of the diode, the fifth resistor and the second capacitor is connected to the reset mode configuration module.

[0022] According to the above technical solution, the external redundant power-on reset module is composed of a fifth resistor, a second capacitor and a diode. Since it is an independent separate device, it has stronger anti-interference ability and is less affected by temperature and voltage fluctuations. The end of the fifth resistor connected to the voltage stabilizing module is a power supply end, which can obtain the analog voltage output by the voltage stabilizing module in real time. When the power supply is powered off, the diode discharges the second capacitor. According to the zero-state response characteristics of the circuit, when the voltage stabilizing module is powered on, the external redundant power-on reset module is also powered on, and the power supply end of the external redundant power-on reset module immediately reaches a stable value, and the voltage across the capacitor is 0V. Thereafter, the fifth resistor charges the second capacitor, and the voltage of the second capacitor gradually rises. When the voltage rises to the reset threshold voltage, i.e., the fourth threshold value, the external redundant power-on reset module can output a reset signal to the reset mode configuration module, thereby improving the running stability and reliability of the chip.

[0023] Further, the native power-on reset module comprises an input unit, a reference voltage generating unit, a second comparison unit and a reset signal generating unit; the input unit is connected to the digital voltage and the analog voltage and connected to the second comparison unit, for inputting the digital voltage and the analog voltage to the second comparison unit; the reference voltage generating unit is connected to the second comparison unit, for setting the reset voltage threshold of the digital voltage and setting the reset voltage threshold of the analog voltage; the second comparison unit is connected to the input unit, the reference voltage generating unit and the reset signal generating unit, for outputting a control signal to the reset signal generating unit after the digital voltage reaches a first threshold value and the analog voltage reaches a second threshold value; and the reset signal generating unit is connected to the second comparison unit and the reset mode configuration module, for outputting a reset signal to the reset signal output module after receiving the control signal.

[0024] According to the technical solution, the input unit receives an external digital voltage and an analog voltage output by the voltage stabilizing module. During the voltage boosting process, the input unit continuously detects the rising of the input digital voltage and the analog voltage, and transmits the rising voltage signal to the second comparison unit. The reference voltage generating unit can set a reset voltage threshold of the digital voltage and can set a reset voltage threshold of the analog voltage, allowing the millivolt level to float up and down. Then, the second comparison unit continuously compares the digital voltage input by the input unit, and when the digital voltage exceeds the set reset voltage threshold by a certain threshold, the reset signal generating unit is notified to output a reset signal. At the same time, the second comparison unit continuously compares the analog voltage input by the input module, and when the analog voltage exceeds the reset voltage threshold by a certain threshold, the reset signal generating unit is notified to output a reset signal. The above two conditions need to be met at the same time, and the reset signal generating unit outputs a reset signal to the chip function system to complete the normal start reset of the chip.

[0025] Further, the reset mode configuration module includes a first input pin and a second input pin; when the first input pin and the second input pin are configured as low level, the reset signal output by the native power-on reset module is a valid reset signal; when the first input pin is configured as high level and the second input pin is configured as low level, the reset signal output by the internal redundant power-on reset module is a valid reset signal; when the first input pin is configured as low level and the second input pin is configured as high level, the reset signal output by the external redundant power-on reset module is a valid reset signal; when the first input pin and the second input pin are configured as high level, the reset signals output by the native power-on reset module, the internal redundant power-on reset module, and the external redundant power-on reset module are all valid reset signals.

[0026] According to the technical solution, when the first input pin is configured as high level and the second input pin is configured as low level, the reset signal output by the internal redundant power-on reset module is a valid reset signal; when the first input pin is configured as low level and the second input pin is configured as high level, the reset signal output by the external redundant power-on reset module is a valid reset signal; when the first input pin and the second input pin are configured as high level, the reset signals output by the native power-on reset module, the internal redundant power-on reset module, and the external redundant power-on reset module are all valid reset signals. It can be seen that the application can select the reset mode by configuring the high and low levels of the two input pins of the reset mode configuration module, and realize full coverage of the reset signal.

[0027] Further, the chip function system comprises a kernel function module, a clock and reset function module, a power supply function module, a storage function module, a peripheral function module and a bus function module, and the kernel function module, the clock function module, the power supply function module, the reset function module, the storage function module and the peripheral function module are connected through the bus function module.

[0028] In the above technical solution, the power supply function module can provide a digital voltage, the clock and reset function module can provide a clock signal, and a reset signal output by a reset signal output module is acquired. After the reset signal is stable for a period of time, the clock module is reset and released, and the reset function module controls the chip system to reset. After all the clock modules are stable, the kernel function module reads a first instruction from the storage function module through the bus function module, runs user software, and uses peripherals through the peripheral function module to process signals or communicate.

[0029] An automobile chip comprises the power management unit redundant reset system.

[0030] According to the above technical solution, a digital voltage is input to a native power-on reset module and an internal redundant power-on reset module through a voltage stabilizing module and converted into an analog voltage. During the process of voltage boosting, the native power-on reset module continuously detects the rising of the digital voltage and the analog voltage. After the digital voltage reaches a first threshold value and the analog voltage reaches a second threshold value, a reset signal can be output to a reset mode configuration module. Then, the reset signal is output to a reset signal output module through the reset mode configuration module, and the reset signal is output to a chip function system through the reset signal output module. The internal redundant power-on reset module also continuously detects the rising of the analog voltage. When the analog voltage reaches a third threshold value, a reset signal is output to the reset mode configuration module. Then, the reset signal is output to the reset signal output module through the reset mode configuration module, and the reset signal is output to the chip function system through the reset signal output module. Therefore, a reset signal can be provided when the native power-on reset module fails, and the running stability and reliability of the chip can be improved. The influence of the failure of the PMU on the running of the overall function of the chip system is avoided, the single-point failure rate of the chip system meets the requirements of ISO26262, and the personal safety is ensured.

[0031] An automobile comprises the automobile chip.

[0032] The present application has the following advantages:

[0033] (1) by increasing the internal redundancy power-on reset module, continuously detecting the climbing of the analog voltage, outputting the reset signal to the reset mode configuration module when the analog voltage reaches the third threshold value, and then outputting to the reset signal output module through the reset mode configuration module, outputting the reset signal to the chip function system through the reset signal output module, so that the reset signal can be provided when the native power-on reset module fails, thereby improving the running stability and reliability of the chip, avoiding the influence of the overall function of the chip system after the PMU fails, ensuring that the single point failure rate of the chip system meets the requirements of ISO26262, and ensuring personal safety;

[0034] (2) by increasing the external redundancy power-on reset module, when the voltage rises to the reset threshold voltage, i.e. the fourth threshold, the external redundancy power-on reset module can output the reset signal to the reset mode configuration module, which can further improve the running stability and reliability of the chip. BRIEF DESCRIPTION OF DRAWINGS

[0035] Figure 1 is a schematic diagram of the PMU reset abnormal trigger voltage;

[0036] Figure 2 is a principle diagram of the native power-on reset module outputting the reset signal;

[0037] Figure 3 is a principle diagram of the native power-on reset module outputting the reset signal;

[0038] Figure 4 is a principle diagram of the native power-on reset module outputting the reset signal;

[0039] Figure 5 is a circuit principle diagram of the external redundancy power-on reset module;

[0040] Figure 6 is a circuit principle diagram of the current generating unit;

[0041] Figure 7 is a principle diagram of the chip function module.

[0042] Among them, 100, voltage stabilizing module; 200, native power-on reset module; 210, input unit; 220, reference voltage generating unit; 230, second comparison unit; 240, reset signal generating unit; 300, internal redundancy power-on reset module; 310, current generating unit; 320, first comparison unit; 400, reset mode configuration module; 500, reset signal output module; 600, chip function system; 700, external redundancy power-on reset module. DETAILED DESCRIPTION

[0043] The present application is described and explained with additional specificity and detail through the use of the accompanying drawings in which:

[0044] It is also to be understood that the following description is only illustrative of the present application and is not intended to limit the present application in any way such as by way of limitation of the scope of the present application.

[0045] The present embodiment provides a power management unit redundant reset system, as shown in Figure 2 The present embodiment provides a power management unit redundant reset system, as shown in

[0046] ISO26262 categorizes safety levels, with the most common being ASIL-B and ASIL-D. ASIL-B requires chips to cover 90% of single-point failure scenarios, while ASIL-D requires 99%. While the probability of a single transistor failing is low, a complex chip typically consists of hundreds of millions of transistors. Without proper protection, any single error could cause functional failure, resulting in a high failure rate.

[0047] In this embodiment, the voltage stabilizing module 100 may be an LDO chip, which receives an external 3.3V digital voltage and converts it into a 1.8V analog voltage.

[0048] During the voltage boost process, the native power-on reset module 200 continuously detects the rise of the digital voltage and the analog voltage. After the digital voltage reaches a first threshold and the analog voltage reaches a second threshold, it can output a reset signal to the reset mode configuration module 400. The reset signal is then output to the reset signal output module 500 through the reset mode configuration module 400, and the reset signal is then output to the chip functional system 600 through the reset signal output module 500. During this process, the internal redundant power-on reset module 300 can also continuously detect the rise of the analog voltage. When the analog voltage reaches a third threshold, it outputs a reset signal to the reset mode configuration module 400. The reset signal is then output to the reset signal output module 500 through the reset mode configuration module 400, and the reset signal is then output to the chip functional system 600 through the reset signal output module 500. This allows a reset signal to be provided even when the native power-on reset module 200 fails, thereby improving the operational stability and reliability of the chip and preventing the overall functional operation of the chip system from being affected by a PMU failure. In addition, the present invention can prevent the operation of the overall function of the chip system from being affected by a PMU failure, ensure that the single point failure rate of the chip system meets the requirements of ISO26262, and ensure personal safety.

[0049] It's important to note that the power-on reset ensures that analog and digital modules are initialized to a known state after power is applied. The power-on reset module generates an internal reset pulse to keep the device static, preventing the internal circuits from operating in an uncontrolled, erroneous state. This pulse remains in effect until the power supply voltage reaches a threshold that ensures normal operation. The reset signal is then released, allowing the chip to resume normal operation.

[0050] like Figure 3 As shown, Figure 3is a schematic diagram of the original power-on reset module outputting a reset signal, before the digital voltage VDD rises from low to high and crosses a specified voltage threshold (the stable working voltage of the chip function system, which can be 100mV, where min=1.8, typ=1.88, and max=1.96), the chip is kept in reset, and after a short period of time after crossing the voltage threshold (the reset hysteresis in Figure 3 is 100mV), the reset ends and the reset vector is taken, and the execution of instructions begins.

[0051] In some embodiments, as shown in Figure 2 , the power management unit redundant reset system further includes: an external redundant power-on reset module 700. The external redundant power-on reset module 700 is connected to the analog voltage and is connected to the voltage stabilizing module 100 and the reset mode configuration module 400, respectively, for outputting a reset signal to the reset mode configuration module 400 when the voltage at the output end of the external redundant power-on reset module 700 reaches a fourth threshold value.

[0052] In this embodiment, the external redundant power-on reset module 700 is an external circuit module. The external redundant power-on reset module 700 detects the analog voltage connected thereto. When the voltage at the output end of the external redundant power-on reset module 700 reaches a fourth threshold value, a reset signal can be output to the reset mode configuration module 400. Therefore, when the original power-on reset module 200 and the internal redundant power-on reset module 300 fail, a reset signal can still be output to the chip function system 600, further improving the startup stability and reliability of the chip.

[0053] In some embodiments, as shown in Figure 2 , the internal redundant power-on reset module 300 includes: a current generating unit 310 and a first comparison unit 320. The current generating unit 310 is connected to the analog voltage and is connected to the first comparison unit 320, for outputting a reference current to the first comparison unit 320 according to the analog voltage; the first comparison unit 320 is connected to the current generating unit 310 and the reset mode configuration module 400, respectively, for converting the reference current into a reference voltage and comparing the reference voltage with a third threshold voltage, and outputting a reset signal to the reset mode configuration module 400 when the reference voltage reaches the third threshold voltage.

[0054] In the embodiment, the current generating unit 310 obtains an analog voltage of 1.8V from the voltage stabilizing module 100, and then generates a high-precision reference current through an internal resistance-capacitance circuit, and inputs the high-precision current to the first comparison unit 320. After receiving the reference current, the first comparison unit 320 converts the reference current into a voltage signal, i.e., a reference voltage, and compares the reference voltage with a third threshold value. When the reference voltage exceeds the third threshold value, a reset signal is output to the reset mode configuration module 400, so that the reset signal can also be output to the chip function system 600 when the native power-on reset module 200 fails.

[0055] In some embodiments, as shown in Figure 2 With Figure 6 As shown in the figure, the current generating unit 310 includes a PMOS tube PMOS, an operational amplifier OP, a reference voltage source Vref, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, and a first capacitor C1. The source of the PMOS tube PMOS is connected to the analog voltage VCC, the drain of the PMOS tube PMOS is connected to the output of the current generating unit 310, and the gate of the PMOS tube PMOS is connected to the output of the operational amplifier OP. The non-inverting input of the operational amplifier OP is connected to one end of the first resistor R1 and one end of the second resistor R2, and the inverting input of the operational amplifier OP is connected to the positive electrode of the reference voltage source Vref. The other end of the first resistor R1 is connected to the output of the current generating unit 310, and the other end of the second resistor R2 is grounded. One end of the third resistor R3 is connected to the output of the current generating unit 310, and the other end of the third resistor R3 is grounded. The negative electrode of the reference voltage source Vref is connected to one end of the fourth resistor R4, and the other end of the fourth resistor R4 is grounded. The first capacitor C1 is connected in parallel with the third resistor R3.

[0056] In the embodiment, the first capacitor C1 is a filter capacitor, the first resistor R1 and the second resistor R2 are voltage dividing resistors, and the third resistor R3 is a current limiting resistor. After the source of the PMOS tube PMOS is connected to the analog voltage VCC provided by the voltage stabilizing module 100, the initial voltage of the common connection end A of the first resistor R1 and the second resistor R2 is 0. At this time, the output of the operational amplifier OP causes the gate potential of the PMOS tube PMOS to drop. Since the source voltage Vs of the PMOS tube PMOS does not change, the output end voltage Vout of the current generating unit 310 rises to the reference voltage output by the reference voltage source Vref, so that a stable reference current Iout can be obtained and output to the first comparison unit 320.

[0057] In some embodiments, the first comparison unit 320 is a Schmitt trigger. The first comparison unit 320 adopts a Schmitt trigger, and the Schmitt trigger has a hysteresis characteristic, which can ensure that a slight change in the power supply voltage after power-up completion will not cause an erroneous flip of the reset signal.

[0058] In some embodiments, as shown in FIG. 4, the reset mode configuration module 400 includes a sixth resistor R6, a third capacitor C3, and a diode D2. One end of the sixth resistor R6 is connected to the analog voltage VCC, and the other end of the sixth resistor R6 is connected to one end of the third capacitor C3. The cathode of the diode D2 is connected to the analog voltage VCC, and the anode of the diode D2 is connected to one end of the third capacitor C3. The other end of the third capacitor C3 is grounded. The common terminal VRST of the diode D2, the sixth resistor R6, and the third capacitor C3 is connected to the reset signal output terminal of the first comparison unit 320. Figure 2 Figure 5 In some embodiments, as shown in FIG. 7, the external redundant power-up reset module 700 includes a fifth resistor R5, a second capacitor C2, and a diode D1. One end of the fifth resistor R5 is connected to the analog voltage VCC, and the other end of the fifth resistor R5 is connected to one end of the second capacitor C2. The cathode of the diode D1 is connected to the analog voltage VCC, and the anode of the diode D1 is connected to one end of the second capacitor C2. The other end of the second capacitor C2 is grounded. The common terminal VRST of the diode D1, the fifth resistor R5, and the second capacitor C2 is connected to the reset mode configuration module 400.

[0059] In this embodiment, the external redundant power-up reset module 700 is composed of the fifth resistor R5, the second capacitor C2, and the diode D1. Since it is an independent separate device, it has stronger anti-interference capability and is less affected by temperature and voltage fluctuations. The end of the fifth resistor R5 connected to the voltage stabilization module 100 is a power supply end, which can obtain the analog voltage VCC output by the voltage stabilization module 100 in real time. When the power supply is powered off, the diode D1 discharges the second capacitor C2. According to the zero-state response characteristics of the circuit, when the voltage stabilization module 100 is powered on, the external redundant power-up reset module 700 is also powered on. The power supply end of the external redundant power-up reset module 700 immediately reaches a stable value, and the voltage across the second capacitor C2 is 0 V. Thereafter, the fifth resistor R5 charges the second capacitor C2, and the voltage of the second capacitor C2 gradually rises. When the voltage rises to the reset threshold voltage, that is, the fourth threshold, the external redundant power-up reset module 700 can output a reset signal to the reset mode configuration module 400, so as to improve the running stability and reliability of the chip.

[0060] In some embodiments, as shown in FIG. 8, the reset mode configuration module 800 includes a seventh resistor R7, a fourth capacitor C4, and a diode D3. One end of the seventh resistor R7 is connected to the analog voltage VCC, and the other end of the seventh resistor R7 is connected to one end of the fourth capacitor C4. The cathode of the diode D3 is connected to the analog voltage VCC, and the anode of the diode D3 is connected to one end of the fourth capacitor C4. The other end of the fourth capacitor C4 is grounded. The common terminal VRST of the diode D3, the seventh resistor R7, and the fourth capacitor C4 is connected to the reset signal output terminal of the first comparison unit 320. Figure 2 Figure 4 ​​As shown, the native power-on reset module 200 includes an input unit 210, a reference voltage generating unit 220, a second comparison unit 230, and a reset signal generating unit 240. The input unit 210 is connected to the second comparison unit 230 and inputs the digital voltage and the analog voltage to the second comparison unit 230. The reference voltage generating unit 220 is connected to the second comparison unit 230 and sets the reset voltage threshold of the digital voltage and the reset voltage threshold of the analog voltage. The second comparison unit 230 is connected to the input unit 210, the reference voltage generating unit 220, and the reset signal generating unit 240, and outputs a control signal to the reset signal generating unit 240 when the digital voltage reaches a first threshold and the analog voltage reaches a second threshold. The reset signal generating unit 240 is connected to the second comparison unit 230 and the reset mode configuration module 400, and outputs a reset signal to the reset signal output module 500 when receiving the control signal.

[0061] In this embodiment, the input unit 210 receives an external 3.3V digital voltage and a 1.8V analog voltage output by the voltage stabilizing module 100. During the voltage boosting process, the input unit 210 continuously detects the rising of the input digital voltage and the analog voltage, and transmits the rising voltage signal to the second comparison unit 230. The reference voltage generating unit 220 can set the reset voltage threshold of the digital voltage, for example, set the reset voltage threshold of the digital voltage to 1.8V, and can set the reset voltage threshold of the analog voltage, for example, set the reset voltage threshold of the analog voltage to 0.9V, allowing the millivolt level to float up and down. Then, the second comparison unit 230 continuously compares the digital voltage input by the input unit 210, and when the digital voltage exceeds the set reset voltage threshold by a certain threshold, i.e., reaches the first threshold, notifies the reset signal generating unit 240 to output a reset signal. At the same time, the second comparison unit 230 continuously compares the analog voltage input by the input module, and when the analog voltage exceeds the reset voltage threshold by a certain threshold, notifies the reset signal generating unit 240 to output a reset signal. The above two conditions need to be met at the same time, and the reset signal generating unit 240 outputs a reset signal to the chip function system 600 to complete the normal start reset of the chip.

[0062] In some embodiments, as Figure 7As shown, the chip function system 600 comprises a core function module, a clock function module, a power supply function module, a reset function module, a storage function module, a peripheral function module and a bus function module. The core function module, the clock function module, the power supply function module, the reset function module, the storage function module and the peripheral function module are connected through the bus function module.

[0063] In the embodiment, the core function module (CORE), the clock and reset function module (RCMU), the power supply function module, the storage function module (SRAM and ROM) and the peripheral function module are connected through the bus function module, wherein the bus function module comprises an AHB bus and an APB bus (such as APB1 and APB2 in Figure 7 When the power management unit is powered on, the power supply function module starts to work, and can provide a 3.3V digital voltage. The resistance-capacitance circuit inside the clock and reset function module also starts to work, and can provide a clock signal and obtain the reset signal output by the reset signal output module. After the reset signal is stable for a period of time, the clock module reset is released, and the reset function module controls the chip system reset. After all the clock modules are stable, the core function module reads the first instruction from the storage function module through the bus function module, runs the user software, and uses the peripherals through the peripheral function module to process signals or communicate. It should be noted that the specific component modules of the chip function system 600 are prior art, and thus will not be described here.

[0064] In some embodiments, as shown in Figure 2 When the first input pin set1 and the second input pin set2 are configured as low level, the reset signal output by the native power-on reset module 200 is a valid reset signal; when the first input pin set1 is configured as high level and the second input pin set2 is configured as low level, the reset signal output by the internal redundant power-on reset module 300 is a valid reset signal; when the first input pin set1 is configured as low level and the second input pin set2 is configured as high level, the reset signal output by the external redundant power-on reset module 700 is a valid reset signal; when the first input pin set1 and the second input pin set2 are configured as high level, the reset signals output by the native power-on reset module 200, the internal redundant power-on reset module 300 and the external redundant power-on reset module 700 are all valid reset signals.

[0065] In the embodiment, when the first input pin set1 is configured as high level and the second input pin set2 is configured as low level, the reset signal output by the internal redundant power-on reset module 300 is a valid reset signal; when the first input pin set1 is configured as low level and the second input pin set2 is configured as high level, the reset signal output by the external redundant power-on reset module 700 is a valid reset signal; when the first input pin set1 and the second input pin set2 are configured as high level, the reset signals output by the native power-on reset module 200, the internal redundant power-on reset module 300 and the external redundant power-on reset module 700 are all valid reset signals. It can be seen that, by configuring the high and low levels of the two input pins of the reset mode configuration module 400, the reset mode can be selected, and full coverage of the reset signal can be realized.

[0066] Taking the internal redundant power-on reset module 300 as an example, the first input pin set1 and the second input pin set2 are respectively configured as high level and low level, so that the reset signal output by the internal redundant power-on reset module 300 is used as a valid reset signal.

[0067] Firstly, the digital voltage of 3.3V is converted into the analog voltage of 1.8V by the voltage stabilizing module 100 and input into the internal redundant power-on reset module 300, and the input end of the reset mode configuration module 400 obtains the external digital power supply from the input end of the native power-on reset module 200. The input end of the current generating unit 310 obtains the analog voltage of 1.8V from the voltage stabilizing module 100, and generates a high-precision reference current through the circuit composed of internal resistance / capacitance, the first comparison unit 320 converts the reference current into a voltage signal and performs voltage threshold comparison, and outputs a reset signal when the threshold is exceeded. The reset mode configuration module 400 regards the reset signal output by the internal redundant power-on reset module 300 as a valid reset signal according to the first input pin set1 / second input pin set2 and outputs it to the reset signal output module 500, which is output to each module by the reset signal output module 500, completing the power-on reset of the chip and making the chip enter the normal working state.

[0068] Taking the external redundant power-on reset module 700 as an example, the first input pin set1 and the second input pin set2 are respectively configured as low level and high level, so that the reset signal output by the external redundant power-on reset module 700 is used as a valid reset signal.

[0069] The 3.3V digital voltage is converted into 1.8V analog voltage by the voltage stabilizing module 100, and is output to the external redundant power-on reset module 700 through the PAD pin of the chip. At the moment of power-on, the second capacitor C2 is charged, and the voltage formed by the charging current on the fifth resistor R5 is high. After a few milliseconds, the second capacitor C2 is fully charged, the current is 0, and the voltage on the fifth resistor R5 is low. The output end changes from high to low, and a low-level reset signal is generated. At this time, the external redundant power-on reset module 700 outputs a reset signal, and the reset mode configuration module 400 regards the reset signal output by the external redundant power-on reset module 700 as a valid reset signal according to the first input pin set1 and the second input pin set2, and outputs the reset signal to the reset signal output module 500. The reset signal output module 500 outputs the reset signal to each module, completes the POR reset of the chip, and makes the chip enter a normal working state.

[0070] In some embodiments, the application also provides an automotive chip comprising the power management unit redundant reset system described above.

[0071] In some embodiments, the application provides an automotive chip comprising the power management unit redundant reset system described above.

[0072] The application can provide a reset signal when the original power-on reset module fails by adding an internal redundant power-on reset module, continuously detecting the climbing of the analog voltage, outputting a reset signal to the reset mode configuration module when the analog voltage reaches the third threshold, and then outputting the reset signal to the reset signal output module through the reset mode configuration module, and outputting the reset signal to the chip function system through the reset signal output module. Thus, the running stability and reliability of the chip can be improved, the influence of the PMU failure on the running of the overall function of the chip system can be avoided, the single-point failure rate of the chip system can meet the requirements of ISO26262, and the personal safety can be ensured. In addition, the application further adds an external redundant power-on reset module. When the voltage rises to the reset threshold voltage, i.e., the fourth threshold, the external redundant power-on reset module can output a reset signal to the reset mode configuration module, and the running stability and reliability of the chip can be further improved.

[0073] The above embodiments are only preferred embodiments for fully illustrating the application, and the protection scope of the application is not limited thereto. Any equivalent replacement or transformation of the application made by those skilled in the art based on the application is within the protection scope of the application.

Claims

1. A power management unit redundant reset system, connected to a chip function system, characterized in that: include: Voltage regulator module, native power-on reset module, internal redundant power-on reset module, reset mode configuration module and reset signal output module; Among them, The voltage stabilizing module is connected to the digital voltage and is connected to the native power-on reset module and the internal redundant power-on reset module respectively, for converting the digital voltage into an analog voltage and inputting it into the native power-on reset module and the internal redundant power-on reset module respectively; The native power-on reset module is connected to the digital voltage and the analog voltage, and is connected to the reset mode configuration module, and is configured to output a reset signal to the reset mode configuration module after the digital voltage reaches a first threshold and after the analog voltage reaches a second threshold; The internal redundant power-on reset module is connected to the analog voltage and is respectively connected to the voltage stabilization module and the reset mode configuration module, and is configured to output a reset signal to the reset mode configuration module when the analog voltage reaches a third threshold; The reset mode configuration module is respectively connected to the native power-on reset module, the internal redundant power-on reset module, the external redundant power-on reset module and the reset signal output module, and is used to output a reset signal to the reset signal output module; The reset signal output module is connected to the reset mode configuration module and the chip function system respectively, and is used to output a reset signal to the chip function system; The system further comprises: an external redundant power-on reset module; the external redundant power-on reset module is connected to the analog voltage, and is configured to output a reset signal to the reset mode configuration module when the output terminal voltage of the external redundant power-on reset module reaches a fourth threshold; The external redundant power-on reset module includes: a fifth resistor, a second capacitor and a diode; wherein, One end of the fifth resistor is connected to the analog voltage, and the other end of the fifth resistor is connected to one end of the second capacitor; The cathode of the diode is connected to the analog voltage, and the anode of the diode is connected to one end of the second capacitor; The other end of the second capacitor is grounded; and a common end of the diode, the fifth resistor, and the second capacitor is connected to the reset mode configuration module.

2. The power management unit redundant reset system according to claim 1, wherein: The internal redundant power-on reset module includes: a current generating unit and a first comparing unit; wherein, The current generating unit is connected to the analog voltage and is connected to the first comparing unit, and is configured to output a reference current to the first comparing unit according to the analog voltage; The first comparison unit is connected to the current generating unit and the reset mode configuration module respectively, and is used to convert the reference current into a reference voltage and compare the reference voltage with a third threshold voltage. When the reference voltage reaches the third threshold voltage, a reset signal is output to the reset mode configuration module.

3. The power management unit redundant reset system according to claim 2, wherein: The current generating unit includes: a PMOS tube, an operational amplifier, a reference voltage source, a first resistor, a second resistor, a third resistor, a fourth resistor and a first capacitor; wherein, The source of the PMOS tube is connected to the analog voltage, the drain of the PMOS tube is connected to the output end of the current generating unit, and the gate of the PMOS tube is connected to the output end of the operational amplifier; The non-inverting input terminal of the operational amplifier is connected to one end of the first resistor and one end of the second resistor, and the inverting input terminal of the operational amplifier is connected to the positive electrode of the reference voltage source; The other end of the first resistor is connected to the output end of the current generating unit, and the other end of the second resistor is grounded; One end of the third resistor is connected to the output end of the current generating unit, and the other end of the third resistor is grounded; The negative electrode of the reference voltage source is connected to one end of the fourth resistor, and the other end of the fourth resistor is grounded; The first capacitor is connected in parallel with the third resistor; The first comparison unit is a Schmitt trigger.

4. The power management unit redundant reset system according to claim 1, wherein: The native power-on reset module includes: an input unit, a reference voltage generating unit, a second comparison unit and a reset signal generating unit; wherein, The input unit receives the digital voltage and the analog voltage and is connected to the second comparing unit, and is used to input the digital voltage and the analog voltage into the second comparing unit; The reference voltage generating unit is connected to the second comparing unit and is used to set a reset voltage threshold of the digital voltage and a reset voltage threshold of the analog voltage; The second comparing unit is connected to the input unit, the reference voltage generating unit and the reset signal generating unit respectively, and is configured to output a control signal to the reset signal generating unit after the digital voltage reaches a first threshold and after the analog voltage reaches a second threshold; The reset signal generating unit is connected to the second comparing unit and the reset mode configuration module respectively, and is configured to output a reset signal to the reset signal output module after receiving the control signal.

5. The power management unit redundant reset system according to claim 1, wherein: The reset mode configuration module includes a first input pin and a second input pin; When the first input pin and the second input pin are configured to be at a low level, the reset signal output by the native power-on reset module is a valid reset signal; When the first input pin is configured as a high level and the second input pin is configured as a low level, the reset signal output by the internal redundant power-on reset module is a valid reset signal; When the first input pin is configured as a low level and the second input pin is configured as a high level, the reset signal output by the external redundant power-on reset module is a valid reset signal; When the first input pin and the second input pin are configured to be at a high level, the reset signals output by the native power-on reset module, the internal redundant power-on reset module, and the external redundant power-on reset module are all valid reset signals.

6. The power management unit redundant reset system according to claim 1, wherein: The chip functional system includes: a core functional module, a clock and reset functional module, a power functional module, a storage functional module, a peripheral functional module and a bus functional module. The core functional module, the clock and reset functional module, the power functional module, the storage functional module and the peripheral functional module are connected through the bus functional module.

7. An automotive chip, characterized by: The invention comprises a power management unit redundant reset system as described in any one of claims 1 to 6.

8. An automobile, characterized in that: Comprising the automotive chip as claimed in claim 7.

Images