Control system upgrading method and control system

Abstract

The invention provides an upgrading method of a control system and the control system.The control system comprises an upper computer, a DSP processing unit, a master FPGA chip and at least one slave FPGA chip connected with the master FPGA chip which are connected in sequence, and the method comprises the steps that the upper computer is used for issuing a first upgrading instruction and an upgrading configuration file to the DSP processing unit; judging the content of the first upgrading instruction by utilizing the DSP processing unit, and when the first upgrading instruction is a self-upgrading instruction of the DSP processing unit, receiving the upgrading configuration file and carrying out self-upgrading according to the upgrading configuration file; when the first upgrading instruction is the upgrading instruction of the slave FPGA chip, issuing a second upgrading instruction to the master FPGA chip, receiving an upgrading configuration file, and sending the upgrading configuration file to the master FPGA chip; and sending the upgrading configuration file to the slave FPGA chip by utilizing the master FPGA chip according to the second upgrading instruction, so as to upgrade according to the upgrading configuration file by utilizing the slave FPGA chip. According to the method and the device, the upgrading operation difficulty of DSP + FPGA architecture equipment can be reduced, and the upgrading efficiency is improved.

Description

Technical Field

[0001] The present application relates to the technical field of program upgrade, and in particular to an upgrade method of a control system and a control system. Background Art

[0002] Currently, DSP+FPGA architecture is widely used in the field of industrial control. The common upgrade method for devices with this architecture is local upgrade. The local upgrade method requires opening the chassis, connecting the device to the computer through the download software and connection cable provided by the manufacturer to complete the upgrade. This upgrade method has certain limitations. When performing program upgrades and maintenance on DSP+FPGA architecture devices in complex environments, the operation is difficult and time-consuming overall.

[0003] Therefore, how to reduce the difficulty of upgrading DSP+FPGA architecture devices and improve the upgrading efficiency is a technical problem that needs to be solved urgently by those skilled in the art. Summary of the invention

[0004] To solve the above technical problems, the present application provides a control system upgrade method, which can reduce the upgrade operation difficulty of DSP+FPGA architecture equipment and improve the upgrade efficiency. The present application also provides a control system with the same technical effect.

[0005] The first objective of the present application is to provide a method for upgrading a control system.

[0006] The above-mentioned application objective 1 of the present application is achieved through the following technical solutions: A control system upgrade method, the control system comprising: a host computer, a DSP processing unit, a master FPGA chip, and at least one slave FPGA chip connected to the master FPGA chip, the method comprising: Using the host computer, issuing a first upgrade instruction and an upgrade configuration file to the DSP processing unit; Using the DSP processing unit, receiving the first upgrade instruction and determining the content of the first upgrade instruction, When the first upgrade instruction is a self-upgrade instruction of the DSP processing unit, using the DSP processing unit to receive the upgrade configuration file, and perform self-upgrade according to the upgrade configuration file; When the first upgrade instruction is an upgrade instruction of the slave FPGA chip, the DSP processing unit is used to issue a second upgrade instruction to the master FPGA chip, and the DSP processing unit is used to receive the upgrade configuration file, and the upgrade configuration file is sent to the master FPGA chip; The master FPGA chip is used to receive the second upgrade instruction and the upgrade configuration file, and according to the second upgrade instruction, the upgrade configuration file is sent to the slave FPGA chip, so as to use the slave FPGA chip to perform an upgrade according to the upgrade configuration file.

[0007] Preferably, in the upgrade method of the control system, the control system further includes a first memory connected to the main FPGA chip, and after the step of using the main FPGA chip to receive the upgrade configuration file, the method further includes: Using the main FPGA chip, storing the upgrade configuration file in the first memory; Accordingly, the step of using the master FPGA chip to send the upgrade configuration file to the slave FPGA chip according to the second upgrade instruction specifically includes: The master FPGA chip is used to send the upgrade configuration file stored in the first memory to the slave FPGA chip according to the second upgrade instruction.

[0008] Preferably, in the control system upgrade method, after the step of using the DSP processing unit to receive the upgrade configuration file, the method further includes: Using the DSP processing unit, performing a CRC check on the upgrade configuration file, if the check passes, storing the upgrade configuration file in a set storage area of ​​the DSP processing unit; After the step of using the main FPGA chip to receive the upgrade configuration file, the method further includes: The main FPGA chip is used to perform a CRC check on the upgrade configuration file. If the check passes, the upgrade configuration file is stored in the first memory.

[0009] Preferably, in the control system upgrade method, the control system further comprises a SelectMap control module and a SelectMap interface connected in sequence, and the master FPGA chip is connected to the slave FPGA chip through the SelectMap control module and the SelectMap interface; Accordingly, the step of using the master FPGA chip to send the upgrade configuration file to the slave FPGA chip according to the second upgrade instruction specifically includes: The master FPGA chip is used to send the upgrade configuration file to the slave FPGA chip through the SelectMap control module and the SelectMap interface according to the second upgrade instruction.

[0010] The second object of the present application is to provide a control system.

[0011] The second application objective of the present application is achieved through the following technical solutions: A control system, comprising: a host computer, a DSP processing unit, a master FPGA chip, and at least one slave FPGA chip connected to the master FPGA chip, wherein: The host computer is used to send a first upgrade instruction and an upgrade configuration file to the DSP processing unit; The DSP processing unit is configured to receive the first upgrade instruction, determine the content of the first upgrade instruction, and when the first upgrade instruction is a self-upgrade instruction of the DSP processing unit, receive the upgrade configuration file, and perform self-upgrade according to the upgrade configuration file; and when the first upgrade instruction is an upgrade instruction of the slave FPGA chip, issue a second upgrade instruction to the master FPGA chip, receive the upgrade configuration file, and send the upgrade configuration file to the master FPGA chip; The master FPGA chip is used to receive the second upgrade instruction and the upgrade configuration file, and send the upgrade configuration file to the slave FPGA chip according to the second upgrade instruction; The slave FPGA chip is used to receive the upgrade configuration file and perform an upgrade according to the upgrade configuration file.

[0012] Preferably, the control system further comprises a first memory connected to the main FPGA chip, and the main FPGA chip is further used to store the upgrade configuration file in the first memory after receiving the upgrade configuration file; Accordingly, when executing the second upgrade instruction to send the upgrade configuration file to the slave FPGA chip, the master FPGA chip is specifically used to: According to the second upgrade instruction, the upgrade configuration file stored in the first memory is sent to the slave FPGA chip.

[0013] Preferably, in the control system, the DSP processing unit is further used to perform a CRC check on the upgrade configuration file after receiving the upgrade configuration file, and if the check passes, store the upgrade configuration file in a set storage area of ​​the DSP processing unit; The main FPGA chip is further used to perform a CRC check on the upgrade configuration file after receiving the upgrade configuration file, and if the check passes, store the upgrade configuration file in the first memory.

[0014] Preferably, the control system further comprises a SelectMap control module and a SelectMap interface connected in sequence, and the master FPGA chip is connected to the slave FPGA chip through the SelectMap control module and the SelectMap interface; Accordingly, when the master FPGA chip executes the second upgrade instruction and sends the upgrade configuration file to the slave FPGA chip, it is specifically used to: According to the second upgrade instruction, the upgrade configuration file is sent to the slave FPGA chip through the SelectMap control module and the SelectMap interface.

[0015] Preferably, the control system further includes a second memory connected to the main FPGA chip, wherein: the second memory is used to store relevant program files of the main FPGA chip.

[0016] Preferably, the control system further comprises a debugger, and the host computer is connected to the DSP processing unit via the debugger.

[0017] In the above technical scheme, the control system includes: a host computer, a DSP processing unit, a main FPGA chip, and at least one slave FPGA chip connected to the main FPGA chip in sequence, and a first upgrade instruction and an upgrade configuration file are issued to the DSP processing unit through the host computer; the first upgrade instruction is received through the DSP processing unit, and the content of the first upgrade instruction is judged, when the first upgrade instruction is a self-upgrade instruction of the DSP processing unit, the upgrade configuration file is received, and self-upgrade is performed according to the upgrade configuration file; and when the first upgrade instruction is an upgrade instruction of the slave FPGA chip, a second upgrade instruction is issued to the main FPGA chip, the upgrade configuration file is received, and the upgrade configuration file is sent to the main FPGA chip; the second upgrade instruction and the upgrade configuration file are received through the main FPGA chip, and the upgrade configuration file is sent to the slave FPGA chip according to the second upgrade instruction, so as to be upgraded according to the upgrade configuration file through the slave FPGA chip.

[0018] To sum up, the above technical solution realizes the online upgrade of the DSP processing unit and the slave FPGA chip through the communication between the host computer, the DSP processing unit, the master FPGA chip and the slave FPGA chip. There is no need to disassemble the equipment for operation, which can reduce the upgrade operation difficulty of the DSP+FPGA architecture equipment and improve the upgrade efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0020] Figure 1 A flowchart of a control system upgrade method in an embodiment of the present application; Figure 2 This is a schematic diagram of the structure of a control system in an embodiment of the present application; Figure 3 This is another structural schematic diagram of a control system in an embodiment of the present application. DETAILED DESCRIPTION

[0021] In order to enable those skilled in the art to better understand the technical solutions in this application, the technical solutions in the embodiments of this application will be clearly and completely described below. Obviously, the described embodiments are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0022] In the embodiments provided in the present application, it should be understood that the disclosed methods and systems can be implemented in other ways. The system embodiments described below are merely schematic. For example, the division of units and modules is only a logical function division. There may be other division methods in actual implementation, such as: multiple units or modules can be combined, or can be integrated into another system, or some features can be ignored, or not executed. In addition, the coupling, direct coupling, or communication connection between the components shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or modules, which can be electrical, mechanical or other forms.

[0023] In addition, all functional units in the embodiments of the present application may be integrated into one processor, or each unit may be a separate device, or two or more units may be integrated into one device; each functional unit in the embodiments of the present application may be implemented in the form of hardware or in the form of hardware plus software functional units.

[0024] A person skilled in the art can understand that all or part of the steps of the following method embodiments can be completed by program instructions and related hardware. The aforementioned program instructions can be stored in a computer-readable storage medium. When the program instructions are executed, the steps of the following method embodiments are executed; and the aforementioned storage medium includes: a mobile storage device, a read-only memory (ROM), a magnetic disk or an optical disk, and other media that can store program codes.

[0025] It should be understood that the use of "system", "device", "unit" and / or "module" in this application is only a method for distinguishing different components, elements, parts, parts or assemblies at different levels. However, if other words can achieve the same purpose, the word can be replaced by other expressions.

[0026] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, "multiple" and "several" mean two or more, unless otherwise clearly and specifically defined.

[0027] If a flow chart is used in the present application, the flow chart is used to illustrate the operations performed by the system according to the embodiment of the present application. It should be understood that the preceding or following operations are not necessarily performed accurately in order. On the contrary, each step can be processed in reverse order or simultaneously. At the same time, other operations can also be added to these processes, or a certain step or several steps of operations can be removed from these processes.

[0028] It should also be noted that, in this article, terms such as "comprises", "includes" or any other variations thereof are intended to cover non-exclusive inclusion, so that an article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such articles or devices. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the article or device including the above elements.

[0029] The embodiments of the present application are written in a progressive manner.

[0030] like Figure 1 As shown, an embodiment of the present application provides a control system upgrade method, wherein the control system includes: a host computer, a DSP processing unit, a master FPGA chip connected in sequence, and at least one slave FPGA chip connected to the master FPGA chip, and the method includes: S101. Using the host computer, the first upgrade command and upgrade configuration file are issued to the DSP processing unit; In S101, specifically, the host computer can be any one or combination of a variety of upgrade entities such as a remote monitoring platform, a PC, a cloud platform, etc., and the DSP processing unit can be a chip that can implement digital signal processing technology; the host computer and the DSP processing unit can be connected through a CAN interface or a communication interface of other communication protocols; through the host computer, a first upgrade instruction and an upgrade configuration file can be issued to the DSP processing unit, wherein the first upgrade instruction can be a self-upgrade instruction of the DSP processing unit or an upgrade instruction from the FPGA chip, the self-upgrade instruction of the DSP processing unit can carry an identification mark of the DSP processing unit, and the upgrade instruction from the FPGA chip can carry an identification mark from the FPGA chip, specifically, the first upgrade instruction can be a Boot instruction, and the present application does not impose specific restrictions on this; accordingly, the upgrade configuration file can be a configuration file for self-upgrade of the DSP processing unit or a configuration file for upgrading from the FPGA chip.

[0031] S102. Using the DSP processing unit, receiving the first upgrade instruction, and determining the content of the first upgrade instruction, when the first upgrade instruction is a self-upgrade instruction of the DSP processing unit, executing S103; when the first upgrade instruction is an upgrade instruction from the FPGA chip, executing S104; In S102, specifically, after receiving the first upgrade instruction, the DSP processing unit may parse and determine the content of the first upgrade instruction, for example, according to the identification mark in the first upgrade instruction, determine whether the first upgrade instruction is a self-upgrade instruction of the DSP processing unit or an upgrade instruction from the FPGA chip.

[0032] S103. Using the DSP processing unit, receiving the upgrade configuration file, and performing self-upgrade according to the upgrade configuration file; In S103, specifically, when the first upgrade instruction is a self-upgrade instruction of the DSP processing unit, the DSP processing unit resets the program and enters the BOOT mode. In the BOOT mode, the DSP processing unit receives the upgrade configuration file sent by the host computer, and performs self-upgrade according to the upgrade configuration file. After the upgrade is completed, the upgrade process can be ended.

[0033] In some embodiments, after the step of receiving the upgrade configuration file by using the DSP processing unit, the method further includes: performing a CRC check on the upgrade configuration file by using the DSP processing unit, and if the check passes, storing the upgrade configuration file in a set storage area of ​​the DSP processing unit; Among them, CRC check (cyclic redundancy check) is a commonly used error detection technology, which is used to detect any errors in data transmission or storage. When the upgrade configuration file passes the CRC check, the upgrade configuration file can be loaded into the set storage area inside the DSP processing unit.

[0034] S104. Using the DSP processing unit, a second upgrade instruction is issued to the main FPGA chip, and using the DSP processing unit, an upgrade configuration file is received, and the upgrade configuration file is sent to the main FPGA chip; In S104, specifically, the DSP processing unit and the main FPGA chip can be connected via an SPI interface (Serial Peripheral Interface) or a communication interface of other communication protocols. When the first upgrade instruction is an upgrade instruction for the slave FPGA chip, the DSP processing unit generates a second upgrade instruction, wherein the second upgrade instruction can be an instruction with an identification mark of the slave FPGA chip, which is used to notify the main FPGA chip to determine the slave FPGA chip to be upgraded according to the identification mark. In addition, the DSP processing unit can also perform a CRC check on the received upgrade configuration file. When the check passes, the upgrade configuration file is stored in the set storage area of ​​the DSP processing unit, and then the second upgrade instruction and the upgrade configuration file stored in the set storage area are generated and sent to the main FPGA chip through the SPI interface.

[0035] S105. Using the master FPGA chip, receive the second upgrade instruction and the upgrade configuration file, and send the upgrade configuration file to the slave FPGA chip according to the second upgrade instruction, so as to use the slave FPGA chip to perform the upgrade according to the upgrade configuration file.

[0036] In S105, specifically, after receiving the second upgrade instruction, the master FPGA chip can determine the slave FPGA chip to be upgraded according to the second upgrade instruction, and send the upgrade configuration file to the corresponding slave FPGA chip, so that the corresponding slave FPGA chip loads the upgrade configuration file to complete the upgrade.

[0037] In some embodiments, the control system further includes a first memory connected to the main FPGA chip, wherein the first memory may be a FLASH memory, and the first memory may be used to store the upgrade configuration file, and may also be used to store other related program files of the slave FPGA chip. Specifically, after the step of receiving the upgrade configuration file using the main FPGA chip, the step may also include: using the main FPGA chip to store the upgrade configuration file in the first memory; correspondingly, using the main FPGA chip to send the upgrade configuration file to the slave FPGA chip according to the second upgrade instruction, specifically includes: using the main FPGA chip to send the upgrade configuration file stored in the first memory to the slave FPGA chip according to the second upgrade instruction.

[0038] In other embodiments, after the step of using the main FPGA chip to receive the upgrade configuration file, it also includes: using the main FPGA chip to perform CRC check on the upgrade configuration file. If the check passes, the upgrade configuration file is stored in the first memory to further detect whether an error occurs in the transmission or storage process of the upgrade configuration file.

[0039] In other embodiments, the control system further includes a SelectMap control module and a SelectMap interface connected in sequence, and the master FPGA chip is connected to the slave FPGA chip through the SelectMap control module and the SelectMap interface; Among them, SelectMap transmission is an interface technology provided by Xilinx FPGA for configuring and partially reconfiguring FPGA; SelectMap control module is used to write the upgrade configuration file into the slave FPGA chip through the SelectMap interface. Correspondingly, the step of using the master FPGA chip to send the upgrade configuration file to the slave FPGA chip according to the second upgrade instruction specifically includes: using the master FPGA chip to send the upgrade configuration file to the slave FPGA chip through the SelectMap control module and the SelectMap interface according to the second upgrade instruction. After receiving the upgrade configuration file, the slave FPGA chip can complete the upgrade according to the upgrade configuration file.

[0040] Specifically, the master FPGA chip loads the upgrade configuration file of the slave FPGA chip through the SelectMap interface. During the transmission process, the master FPGA chip first waits for the second upgrade instruction issued by the DSP processing unit. When the master FPGA chip receives the second upgrade instruction, the master FPGA chip starts the configuration timing of the master FPGA chip by pulling down the PROGRAM_B state signal, and then waits for the INIT state signal to be pulled low. The slave FPGA chip enters the configuration mode and transmits the upgrade configuration file to the slave FPGA chip through the data bus. When the upgrade configuration file is input into the slave FPGA chip, it can enter the start state. At this time, the slave FPGA chip completes the configuration. When the reset signal is stable and the DONE pin is at a high level, the slave FPGA chip enters the start state and can run the loaded program to complete the update.

[0041] In the above embodiment, the control system includes: a host computer, a DSP processing unit, a main FPGA chip, and at least one slave FPGA chip connected to the main FPGA chip in sequence, and a first upgrade instruction and an upgrade configuration file are issued to the DSP processing unit through the host computer; the first upgrade instruction is received through the DSP processing unit, and the content of the first upgrade instruction is judged, when the first upgrade instruction is a self-upgrade instruction of the DSP processing unit, the upgrade configuration file is received, and self-upgrade is performed according to the upgrade configuration file; and when the first upgrade instruction is an upgrade instruction of the slave FPGA chip, a second upgrade instruction is issued to the main FPGA chip, the upgrade configuration file is received, and the upgrade configuration file is sent to the main FPGA chip; the second upgrade instruction and the upgrade configuration file are received through the main FPGA chip, and the upgrade configuration file is sent to the slave FPGA chip according to the second upgrade instruction, so as to be upgraded according to the upgrade configuration file through the slave FPGA chip.

[0042] In summary, the above embodiment realizes the online upgrade of the DSP processing unit and the slave FPGA chip through communication between the host computer, the DSP processing unit, the master FPGA chip and the slave FPGA chip, without disassembling the equipment for operation, which can reduce the difficulty of the upgrade operation of the DSP+FPGA architecture equipment and improve the upgrade efficiency.

[0043] like Figure 2 , Figure 3 As shown, in another embodiment of the present application, a control system is also provided, comprising: a host computer 1, a DSP processing unit 2, a main FPGA chip 3 connected in sequence, and at least one slave FPGA chip 4 connected to the main FPGA chip 3, wherein: The host computer 1 is used to send a first upgrade instruction and an upgrade configuration file to the DSP processing unit 2; The DSP processing unit 2 is used to receive a first upgrade instruction and determine the content of the first upgrade instruction. When the first upgrade instruction is a self-upgrade instruction of the DSP processing unit 2, it receives an upgrade configuration file and performs self-upgrade according to the upgrade configuration file; and when the first upgrade instruction is an upgrade instruction from the FPGA chip 4, it issues a second upgrade instruction to the main FPGA chip 3, receives the upgrade configuration file, and sends the upgrade configuration file to the main FPGA chip 3; The master FPGA chip 3 is used to receive the second upgrade instruction and the upgrade configuration file, and send the upgrade configuration file to the slave FPGA chip 4 according to the second upgrade instruction; The slave FPGA chip 4 is used to receive the upgrade configuration file and perform the upgrade according to the upgrade configuration file.

[0044] The above control system can realize online upgrade of the DSP processing unit 2 and the slave FPGA chip 4 through communication between the host computer 1, the DSP processing unit 2, the master FPGA chip 3 and the slave FPGA chip 4, without disassembling the equipment for operation, which can reduce the upgrade operation difficulty of the DSP+FPGA architecture equipment and improve the upgrade efficiency.

[0045] In other embodiments of the present application, the control system further includes a first memory 5 connected to the main FPGA chip 3, and the main FPGA chip 3 is further used to store the upgrade configuration file in the first memory 5 after receiving the upgrade configuration file; Correspondingly, when the master FPGA chip 3 sends the upgrade configuration file to the slave FPGA chip 4 according to the second upgrade instruction, it is specifically used to: send the upgrade configuration file stored in the first memory 5 to the slave FPGA chip 4 according to the second upgrade instruction.

[0046] In other embodiments of the present application, in the above control system, the DSP processing unit 2 is further used to perform a CRC check on the upgrade configuration file after receiving the upgrade configuration file, and if the check passes, the upgrade configuration file is stored in the set storage area of ​​the DSP processing unit 2; The main FPGA chip 3 is also used to perform a CRC check on the upgrade configuration file after receiving the upgrade configuration file. If the check passes, the upgrade configuration file is stored in the first memory 5.

[0047] In other embodiments of the present application, the above control system further includes a SelectMap control module 6 and a SelectMap interface 7 connected in sequence, and the master FPGA chip 3 is connected to the slave FPGA chip 4 through the SelectMap control module 6 and the SelectMap interface 7; Correspondingly, when the master FPGA chip 3 executes the second upgrade instruction and sends the upgrade configuration file to the slave FPGA chip 4, it is specifically used to: send the upgrade configuration file to the slave FPGA chip 4 through the SelectMap control module 6 and the SelectMap interface 7 according to the second upgrade instruction.

[0048] In other embodiments of the present application, the control system further includes a second memory 8 connected to the main FPGA chip 3, wherein: the second memory 8 is used to store relevant program files of the main FPGA chip 3. The second memory 8 can be a FLASH memory, and the relevant program files can be program files executed by the main FPGA chip 3, and the present application does not impose any specific restrictions on this.

[0049] In other embodiments of the present application, the control system further includes a debugger 9, and a host computer 1 is connected to the DSP processing unit 2 through the debugger 9. The debugger 9 is a tool for testing and debugging programs, which allows developers to check and modify the behavior of programs while the programs are running. The host computer 1 can establish a connection with the debugger 9 through a physical interface, and the debugger 9 can establish a connection with the DSP processing unit 2 through a CAN interface. The host computer 1 can send a first upgrade instruction and an upgrade configuration file to the DSP processing unit 2 through the debugger 9.

[0050] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present application. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments shown herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A control system upgrade method, characterized in that: The control system comprises: a host computer, a DSP processing unit, a master FPGA chip, and at least one slave FPGA chip connected to the master FPGA chip in sequence, and the method comprises: Using the host computer, issuing a first upgrade instruction and an upgrade configuration file to the DSP processing unit; Using the DSP processing unit, receiving the first upgrade instruction and determining the content of the first upgrade instruction, When the first upgrade instruction is a self-upgrade instruction of the DSP processing unit, using the DSP processing unit to receive the upgrade configuration file, and perform self-upgrade according to the upgrade configuration file; When the first upgrade instruction is an upgrade instruction of the slave FPGA chip, the DSP processing unit is used to issue a second upgrade instruction to the master FPGA chip, and the DSP processing unit is used to receive the upgrade configuration file, and the upgrade configuration file is sent to the master FPGA chip; The master FPGA chip is used to receive the second upgrade instruction and the upgrade configuration file, and according to the second upgrade instruction, the upgrade configuration file is sent to the slave FPGA chip, so as to use the slave FPGA chip to perform an upgrade according to the upgrade configuration file.

2. The method according to claim 1, characterized in that The control system further includes a first memory connected to the main FPGA chip, and after the step of using the main FPGA chip to receive the upgrade configuration file, the control system further includes: Using the main FPGA chip, storing the upgrade configuration file in the first memory; Accordingly, the step of using the master FPGA chip to send the upgrade configuration file to the slave FPGA chip according to the second upgrade instruction specifically includes: The master FPGA chip is used to send the upgrade configuration file stored in the first memory to the slave FPGA chip according to the second upgrade instruction.

3. The method as claimed in claim 2, characterized in that After the step of receiving the upgrade configuration file by the DSP processing unit, the method further includes: Using the DSP processing unit, performing a CRC check on the upgrade configuration file, if the check passes, storing the upgrade configuration file in a set storage area of ​​the DSP processing unit; After the step of using the main FPGA chip to receive the upgrade configuration file, the method further includes: The main FPGA chip is used to perform a CRC check on the upgrade configuration file. If the check passes, the upgrade configuration file is stored in the first memory.

4. The method according to claim 1, characterized in that The control system further comprises a SelectMap control module and a SelectMap interface connected in sequence, and the master FPGA chip is connected to the slave FPGA chip through the SelectMap control module and the SelectMap interface; Correspondingly, the step of using the master FPGA chip to send the upgrade configuration file to the slave FPGA chip according to the second upgrade instruction specifically includes: The master FPGA chip is used to send the upgrade configuration file to the slave FPGA chip through the SelectMap control module and the SelectMap interface according to the second upgrade instruction.

5. A control system, characterized in that: include: A host computer, a DSP processing unit, a master FPGA chip, and at least one slave FPGA chip connected to the master FPGA chip, wherein: The host computer is used to send a first upgrade instruction and an upgrade configuration file to the DSP processing unit; The DSP processing unit is configured to receive the first upgrade instruction, determine the content of the first upgrade instruction, and when the first upgrade instruction is a self-upgrade instruction of the DSP processing unit, receive the upgrade configuration file, and perform self-upgrade according to the upgrade configuration file; and when the first upgrade instruction is an upgrade instruction of the slave FPGA chip, issue a second upgrade instruction to the master FPGA chip, receive the upgrade configuration file, and send the upgrade configuration file to the master FPGA chip; The master FPGA chip is used to receive the second upgrade instruction and the upgrade configuration file, and send the upgrade configuration file to the slave FPGA chip according to the second upgrade instruction; The slave FPGA chip is used to receive the upgrade configuration file and perform an upgrade according to the upgrade configuration file.

6. The control system as claimed in claim 5, characterized in that Also included is a first memory connected to the main FPGA chip, and the main FPGA chip is further used to store the upgrade configuration file in the first memory after receiving the upgrade configuration file; Accordingly, when executing the second upgrade instruction to send the upgrade configuration file to the slave FPGA chip, the master FPGA chip is specifically used to: According to the second upgrade instruction, the upgrade configuration file stored in the first memory is sent to the slave FPGA chip.

7. The control system as claimed in claim 6, characterized in that The DSP processing unit is further configured to perform a CRC check on the upgrade configuration file after receiving the upgrade configuration file, and if the check passes, store the upgrade configuration file in a set storage area of ​​the DSP processing unit; The main FPGA chip is further used to perform a CRC check on the upgrade configuration file after receiving the upgrade configuration file, and if the check passes, store the upgrade configuration file in the first memory.

8. The control system as claimed in claim 5, characterized in that It also includes a SelectMap control module and a SelectMap interface connected in sequence, and the master FPGA chip is connected to the slave FPGA chip through the SelectMap control module and the SelectMap interface; Accordingly, when the master FPGA chip executes the second upgrade instruction and sends the upgrade configuration file to the slave FPGA chip, it is specifically used to: According to the second upgrade instruction, the upgrade configuration file is sent to the slave FPGA chip through the SelectMap control module and the SelectMap interface.

9. The control system as claimed in claim 5, characterized in that It also includes a second memory connected to the main FPGA chip, wherein: the second memory is used to store relevant program files of the main FPGA chip.

10. The control system as claimed in claim 5, characterized in that It also includes a debugger, and the host computer is connected to the DSP processing unit through the debugger.

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