Prefetch parameter configuration and cache prefetch method, physical machine and processor

Abstract

The embodiment of the invention provides a prefetching parameter configuration and cache prefetching method, a physical machine and a processor. In the embodiment of the invention, the physical processor can perform hardware prefetching operation in the running process of the virtualization instance. Furthermore, the virtualization manager applies for a prefetch register access permission from a firmware program of the prefetch register, and the prefetch register is accessed under the condition that the prefetch register access permission is successfully applied; the operation of configuring the prefetching strategy parameter by the virtualization instance is perceived, and the prefetching strategy parameter is configured to a prefetching register in a physical processor to which the virtualization instance is scheduled instead of the virtualization instance, so that the configuration capability of the prefetching register is transmitted to the virtualization instance through a bottom layer virtualization technology; therefore, the prefetching strategy can be flexibly and dynamically configured for different virtualization instances according to the scheduling condition of the virtualization instances, and the problem that the performance of a plurality of applications cannot be considered due to the fact that the prefetching strategy cannot be flexibly and dynamically configured in the prior art is solved.

Description

Technical Field

[0001] The present application relates to the field of cloud storage technology, and in particular to a pre-fetch parameter configuration and cache pre-fetch method, a physical machine and a processor. Background Art

[0002] In modern processor design, a memory system with cache is usually introduced, and a hardware prefetch mechanism is supported. That is, the hardware prefetcher inside the central processing unit (CPU) reads instructions or data from a slower storage medium (such as memory) to a faster storage medium (such as cache) in advance, thereby reducing the time the CPU waits for instructions or data to be loaded and improving the CPU execution performance.

[0003] In some processor designs, multiple prefetchers may be included. The adjustable parameters involved in the prefetching process of each prefetcher are also diverse. Which hardware prefetcher is used and which parameter combinations are used by the hardware prefetcher in the prefetching process will form different prefetching strategies. The memory access mode and read-write rules of applications are different. Choosing different prefetching strategies will have different performance effects on the application. In the prior art, when the physical server is turned on, the firmware (Bios) generally provides an option menu for the CPU hardware prefetching strategy, and the user can select a fixed prefetching strategy according to the application characteristics.

[0004] However, when multiple applications are running on a physical server, the existing way of selecting prefetching strategies will lose sight of one thing while taking another into account, and cannot bring performance advantages to all applications. Especially in cloud computing scenarios, a physical server often runs multiple virtual machines of different tenants, and the applications running in these virtual machines are also different. Therefore, it is urgent to propose a new prefetching strategy configuration scheme that can take into account the performance advantages of various applications. Summary of the invention

[0005] Multiple aspects of the present application provide a prefetch parameter configuration and cache prefetch method, a physical machine and a processor, which are used to flexibly and dynamically configure a prefetch strategy for the CPU so that the prefetch strategy can take into account the performance advantages of various applications.

[0006] An embodiment of the present application provides a physical machine, wherein the hardware resources of the physical machine include at least at least one physical processor, and the physical processor includes a hardware prefetcher and a prefetch register for prefetching control of the hardware prefetcher; the software resources of the physical machine include at least a firmware program for reading and writing control of the prefetch register and a virtualization manager for creating and managing virtualization instances; the virtualization manager is further used to apply for prefetch register access rights from the firmware program, and when the prefetch register access rights are successfully applied for, in response to the operation of the virtualization instance to configure target prefetch policy parameters for the prefetch register, configure the target prefetch policy parameters to the prefetch register in the target physical processor to which the virtualization instance is scheduled, so as to realize dynamic configuration of the prefetch policy.

[0007] An embodiment of the present application provides a prefetch policy configuration method, which is applied to a virtualization manager on a physical machine for creating and managing virtualization instances. At least one physical processor of the physical machine includes a hardware prefetcher and a prefetch register for prefetching control of the hardware prefetcher. The method includes: applying for prefetch register access rights to a firmware program in the physical machine for reading and writing control of the prefetch register; in a case where the prefetch register access rights are successfully applied for, in response to an operation of the virtualization instance to configure a target prefetch policy parameter for the prefetch register, configuring the target prefetch policy parameter to the prefetch register in the target physical processor to which the virtualization instance is scheduled, so as to realize dynamic configuration of the prefetch policy.

[0008] An embodiment of the present application provides another prefetch policy configuration method, which is applied to a firmware program in a physical machine for reading and writing prefetch registers. The physical machine also includes a virtualization manager for creating and managing virtualization instances. The method includes: when the virtualization manager applies for prefetch register access rights, configuring an authorization register in at least one physical processor to a preset value representing authorization to open the prefetch register access rights to the virtualization manager; and returning authorization success structure information to the virtualization manager.

[0009] An embodiment of the present application provides another prefetch policy configuration method, which is applied to a virtualization instance created by a virtualization manager in a physical machine, wherein at least one physical processor of the physical machine includes a hardware prefetcher and a prefetch register for prefetching control of the hardware prefetcher; the method includes: in response to a prefetch policy configuration operation, obtaining a target prefetch policy parameter configured for the prefetch register; based on the ability of the virtualization instance configured by the virtualization manager to trap to the virtualization manager when configuring the target prefetch policy parameter for the prefetch register, trapping to the virtualization manager, so that the virtualization manager can intercept the target prefetch policy parameter and configure it to the prefetch register in the target physical processor to which the virtualization instance is scheduled, so as to realize dynamic configuration of the prefetch policy.

[0010] An embodiment of the present application provides a cache prefetch method, which is applied to a target physical processor in a physical machine, wherein the target physical processor includes a hardware prefetcher and a prefetch register for prefetching the hardware prefetcher, and the target prefetch policy parameters in the prefetch register are configured according to the above-mentioned prefetch policy configuration method; the method includes: reading the target prefetch policy parameters from the prefetch register; and performing data and / or instruction prefetch operations based on the target prefetch policy parameters during the operation of the scheduled virtualized instance.

[0011] An embodiment of the present application also provides a processor, which is responsible for running a virtualized instance. The processor includes a hardware prefetcher and a prefetch register for prefetching the hardware prefetcher. The target prefetch policy parameters in the prefetch register are configured according to the steps in the prefetch policy configuration method described above; the processor is used to execute a computer program to implement the steps in the cache prefetch method.

[0012] An embodiment of the present application also provides a computer-readable storage medium storing a computer program. When the computer program is executed by a processor, the processor implements the steps in any of the above methods.

[0013] In an embodiment of the present application, a virtualization manager for creating and managing virtualized instances is deployed on a physical machine, and the virtualized instance is scheduled to run on a physical processor of the physical machine. The physical processor includes a hardware prefetcher and a prefetch register for prefetching control of the hardware prefetcher, and can perform hardware prefetching operations during the operation of the virtualized instance. Further, in order to realize the dynamic configuration of the hardware prefetching strategy, the virtualization manager applies for the prefetch register access right to the firmware program of the prefetch register, and when the prefetch register access right is successfully applied for, the virtualized instance is sensed to configure the prefetching strategy parameters of the virtualized instance and configures the prefetching strategy parameters to the prefetch register in the physical processor to which the virtualized instance is scheduled on behalf of the virtualized instance, and then the configuration capability of the prefetch register is transparently transmitted to the virtualized instance through the underlying virtualization technology, so that the prefetching strategy can be flexibly and dynamically configured for different virtualized instances according to the scheduling of the virtualized instance, which solves the problem in the prior art that the prefetching strategy cannot be flexibly and dynamically configured, resulting in the inability to take into account the performance of multiple applications. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0015] Figure 1a A schematic diagram of an instruction pipeline of a processor core provided for an exemplary embodiment of the present application;

[0016] Figure 1b A schematic diagram of a register and its pre-fetch parameters provided for an exemplary embodiment of the present application;

[0017] Figure 2 A system framework diagram of the hardware and software structure of a physical machine provided for an exemplary embodiment of the present application;

[0018] Figure 3 A timing diagram of a pre-fetch strategy configuration method provided for an exemplary embodiment of the present application;

[0019] Figure 4 A flowchart of a pre-fetching strategy configuration method provided for an exemplary embodiment of the present application;

[0020] Figure 5 A flowchart of another pre-fetch strategy configuration method provided for an exemplary embodiment of the present application;

[0021] Figure 6 A flowchart of another pre-fetching strategy configuration method provided for an exemplary embodiment of the present application;

[0022] Figure 7 A schematic diagram of a flow chart of a cache pre-fetching method provided for an exemplary embodiment of the present application;

[0023] Figure 8 A schematic diagram of the structure of a pre-fetch strategy configuration device provided for an exemplary embodiment of the present application;

[0024] Fig. 9 A schematic diagram of the structure of another pre-fetch strategy configuration device provided by an exemplary embodiment of the present application;

[0025] Fig.10 A schematic diagram of the structure of another pre-fetch strategy configuration device provided by an exemplary embodiment of the present application;

[0026] Fig.11 A schematic diagram of the structure of a cache pre-fetching device provided for an exemplary embodiment of the present application;

[0027] Fig.12 A schematic diagram of the structure of a processor provided for an exemplary embodiment of the present invention. DETAILED DESCRIPTION

[0028] In order to make the purpose, technical solution and advantages of the present application clearer, the technical solution of the present application will be clearly and completely described below in combination with the specific embodiments of the present application and the corresponding drawings. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present application.

[0029] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with the relevant laws, regulations and standards of the relevant countries and regions, and provide corresponding operation entrances for users to choose to authorize or refuse.

[0030] In a cloud computing scenario, a user can purchase or deploy a virtualized instance, such as a virtual machine (VM) or a container. Each virtualized instance has an independent physical operating environment and independent resources, such as each virtualized instance has independent computing resources, storage resources, and network resources. In this embodiment, the computing resources of the virtualized instance include one or more physical CPU resources. This provides conditions for pre-fetching strategy configuration and cache pre-fetching control from the virtualized instance dimension. Further, considering that virtualized instances are usually scheduled according to the cluster dimension in cloud computing scenarios, on this basis, cache pre-fetching control of the physical CPU can be personalized or targeted from the dimension of the virtualized instance, so that the physical CPU can perform pre-fetching operations more reasonably during the operation of the virtualized instance, and pre-read data and / or instructions from the memory to the cache, or from the third-level cache to the second-level cache, or from the second-level cache to the first-level cache, to solve various problems encountered in the memory during the operation of the virtualized instance, such as low cache hit rate, insufficient memory bandwidth resources, memory contention, etc.

[0031] It is hereby explained that in the embodiments of the present application, the correspondence between the virtualization instance and the physical CPU is not limited. The same physical CPU can be assigned to a virtualization instance or dynamically assigned to different virtualization instances. Both cases are applicable to the embodiments of the present application. In addition, in the embodiments of the present application, one or more applications can be deployed in the virtualization instance. When the cache pre-fetch control of the physical CPU is personalized or targeted from the virtualization instance dimension, the physical CPU can be dynamically pre-fetched and cached according to the needs of each application in the virtualization instance.

[0032] In the embodiment of the present application, the cache system of the physical CPU is a multi-level system divided according to tasks. In addition, the implementation structure of the kernel cache system of processors with different architectures, different models, and different manufacturers will be different, which is not limited in the embodiment of the present application. Processors of various architectures, various models, and various scenarios are applicable to the embodiment of the present application as long as they support the hardware prefetching scheme and need to configure the value of the prefetch register for prefetching control. The following is an exemplary display of a processor core, such as Figure 1aAs shown, the instruction pipeline (InstructionPipeline) of the processor core includes but is not limited to the following stages: fetch and decode (Fetch&Decode) stage, execution (Execution) stage and commit and retire (Commit&Retire) stage.

[0033] Among them, the fetch and decode (Fetch & Decode) stage corresponds to the front-end sequential processing (In-Order FrontEnd) module, which includes but is not limited to the following hardware units: Branch Prediction Unit, Decode, Rename & Dispatch Unit, Level 1 Instruction-Cache (L1 I-Cache) Unit, Level 1 Instruction Translation Lookaside Buffer (L1-I-TLB) Unit. Among them, L1 I-Cache is used to store instructions; L1 D-Cache is used to store first-level cache data. L1-I-TLB is used to cache page table entries and determine the physical address of L1-level instructions.

[0034] The execution stage corresponds to the out-of-order back end module, which includes but is not limited to the following hardware units: issue queue, execution unit, load store unit, L1 data translation lookaside buffer (L1 data-TLB, L1 D-TLB) unit, L2 translation lookaside buffer (L2 TLB) unit and L1 data cache (Level 1 data-cache, L1 D-cache) unit. L2 TLB is used to cache page table entries and determine the physical address of L1 cache.

[0035] Among them, the Commit & Retire stage corresponds to the In-Order Instruction Retire module, which includes but is not limited to the following hardware units: Commit & Retire unit.

[0036] The fetch and decode (Fetch & Decode) stage and the execution (Execution) stage also correspond to the core interface (Core-Clure Interface) module, which includes a L2 cache (L2 Cache) unit. Figure 1a The last level cache (LLC) of the processor, also known as the third level cache, is not shown. For some processors, LLC is optional.

[0037] Among them, the branch prediction unit is used to predict the address of the next instruction, for example, predicting which address the CPU will go to to prefetch instructions; the decoding, renaming and scheduling unit is mainly used to obtain instructions from the L1 I-Cache according to the address predicted by the branch prediction unit, identify the type of instructions, and rename the instructions, and write the renamed instructions into the emission queue in sequence. The execution unit is used to execute the instructions in the emission queue, and the load storage unit provides the data required for the instructions in the emission queue. The commit and exit unit is used to commit the execution results and exit.

[0038] In order to improve the performance of the application, cache prefetching operations are involved in the above process. Figure 1a As shown in the figure, the cache prefetching situations can be summarized into the following two types: one is to read data from the low-end storage in advance and write it into the high-end cache, referred to as cache read data, mainly including from L2 Cache->L1 I-Cache / L1 D-Cache, indicating reading instructions from L2 Cache to L1 I-Cache or reading data from L2 Cache to L1 D-Cache, and from L2 TLB->L1I-TLB / L1D-TLB, indicating reading instruction mapping information from L2 TLB to L1 I-TLB or reading data mapping information from L2 TLB to L1 D-TLB; the other is to write dirty pages in high-end storage back to low-end storage in advance, referred to as dirty page writeback, mainly including from L1 D-Cache->L2 Cache, indicating writing dirty pages in L1 D-Cache back to L2Cache in advance, and from L1 I-TLB / L1 D-TLB->L2 TLB, indicating writing instruction mapping information in L1 I-TLB back to L2 in advance. TLB or write the data mapping information in L1 D-TLB back to L2 TLB in advance. In the embodiment of the present application, the main focus is on the case of cache reading data, that is, the case of pre-reading data from the low-end storage and writing it into the high-end cache.

[0039] In practical applications, there are two pre-fetching methods: software and hardware. Software pre-fetching can insert pre-fetch instructions into the program, use pre-fetch instructions to perform pre-fetching during coding, or use optimized compilation options during compilation, and use pre-fetch instructions to improve the execution efficiency of the program. Hardware pre-fetching is implemented by a dedicated hardware pre-fetcher inside the physical CPU. The hardware pre-fetcher is mainly used for data and / or instruction pre-fetching, that is, placing the data that may be used in the relevant cache in advance to wait for use in the relevant cache. In the embodiment of the present application, the hardware pre-fetching method is focused on. The physical CPU supports a variety of hardware pre-fetching algorithms, and different hardware pre-fetching algorithms are implemented by different hardware pre-fetchers. Which hardware pre-fetching algorithm (or hardware pre-fetcher) the physical CPU uses and how to perform data and / or instruction pre-fetching through the hardware pre-fetching algorithm (or hardware pre-fetcher) can be controlled by a pre-fetching register. Based on this, in the present embodiment, the physical CPU also includes: a plurality of pre-fetching registers for cache pre-fetching control of the physical CPU. The multiple prefetch registers in this embodiment refer to registers used to control cache prefetching of the physical CPU. It should be noted that the physical CPU will also include other registers, such as authorization registers, etc. Among them, each prefetch register is used to control a prefetch parameter, and different prefetch registers represent different prefetch parameters, that is, each prefetch register corresponds to a prefetch parameter, and a prefetch parameter has at least two values. For example, if the prefetch parameter corresponding to the prefetch register is represented by 1 bit, its value has two types: 0 and 1; if the prefetch parameter corresponding to the prefetch register is represented by 2 bits, its value has four types: 00, 01, 10 and 11. For the same prefetch register, different values ​​are mutually exclusive, indicating that at the same time, the value of the prefetch register can only be one of them. The value combination between multiple prefetch registers forms a plurality of prefetch parameter combinations, and each prefetch parameter combination represents a prefetch strategy. For example, the prefetch parameter combination may include but is not limited to: which prefetch algorithm the physical CPU uses, which data to prefetch, when to start prefetching, where the prefetched data is stored, etc. This information can be given by the values ​​of different prefetch registers.

[0040] Optionally, the multiple prefetch registers included in the physical CPU can be classified according to the prefetch parameters represented. Specifically, the multiple prefetch registers can be divided into two types. One is a prefetch register representing a prefetch algorithm selection parameter, which is mainly used to select whether to use a certain prefetch algorithm (i.e., a hardware prefetcher). It is explained here that the prefetch algorithm mentioned in the embodiment of the present application mainly refers to the hardware prefetch algorithm, that is, the prefetch algorithm implemented by the hardware prefetcher; the other is a prefetch register representing a prefetch operation execution control parameter, which is mainly used to control how the selected hardware prefetcher performs the prefetch process. There are multiple such registers, which are used to provide different prefetch operation execution control parameters for the hardware prefetcher, for example, determining which piece of data the hardware prefetcher prefetches, when to start prefetching data, the amount of prefetched data, the prefetch position, and the storage position of the prefetched data. Among them, the number of prefetch registers representing the prefetch algorithm selection parameter can be 1, and the number of prefetch registers representing the prefetch operation execution control parameter can be multiple, for example, 2, 3 or 10. Accordingly, a prefetch parameter combination, that is, a value combination of multiple prefetch registers, includes a set of values ​​corresponding to the prefetch algorithm selection parameters and the prefetch operation execution control parameters.

[0041] For example, in Figure 1b The schematic diagram of some prefetch registers included in the physical CPU is given in FIG. The CMC_MIN_WAY register belongs to the prefetch register representing the prefetch algorithm selection parameter, indicating whether to select the Correlated Miss Caching (CMC) algorithm. The CMC algorithm is a hardware prefetch algorithm and a type of temporal prefetcher. It uses part of the L2 cache space to store historical miss information and uses this part of the miss information as metadata (meta) information to prefetch data. If data is prefetched from the memory to the L2 cache, how many bits of the L2 cache need to be reserved for data and how many bits need to be reserved for instructions are controlled by the L2_DATA_PART register and the L2_INST_PART register respectively. The L2 cache data part (L2_DATA_PART) register and the L2 cache instruction part (L2_INST_PART) register belong to the prefetch register representing the prefetch operation execution control parameter. The value of the L2_DATA_PART register and the L2_INST_PART register can have multiple situations. Figure 1bIn the example, it is assumed that the parameters of the L2_DATA_PART register and the L2_INST_PART register are both represented by 3 bits, and each has 8 values; if the value of the L2_DATA_PART register is 000, it means that 0 bits are reserved for data in the L2 cache, which is a reset value; if the value of the L2_DATA_PART register is 001, it means that 1 bit is reserved for data in the L2 cache; if the value of the L2_INST_PART register is 111, it means that 7 bits are reserved for instructions in the L2 cache; if the value of the L2_INST_PART register is 101, it means that 5 bits are reserved for instructions in the L2 cache. Different combinations of values ​​of the L2_DATA_PART register and the L2_INST_PART register will form different prefetch strategies, and different prefetch strategies will produce different application performance during application operation.

[0042] In addition, different applications have different memory access modes and reading and writing rules, so different prefetching strategies need to be selected to ensure that different prefetching strategies can bring performance advantages to different applications. For example, in cloud computing scenarios, multiple virtualized instances of different tenants are often running on the same physical machine. The applications running in these virtualized instances are also different, and the prefetching strategies required by different applications are not the same. For example, in a cloud server product scenario, the product uses an ARM processor with an added hardware prefetcher, and database applications such as Relational Database Service (RDS) are deployed on the cloud server product. Other applications are also deployed. When using the prefetching strategy represented by a specific prefetching parameter combination, it can bring 15% or even higher performance improvement to database applications such as RDS, but it does not produce performance improvement for other applications and even brings negative performance benefits. It is further explained that different applications require different prefetching strategies, and the same prefetching strategy cannot bring performance improvements to all applications. Therefore, if the prefetching strategies can be flexibly and dynamically configured for different virtualization instances according to the scheduling of the virtualization instances, so that different virtualization instances use different prefetching strategies, and these prefetching strategies can bring performance advantages to different application scenarios, it becomes a technical problem that needs to be solved in the embodiments of the present application.

[0043] In view of the above, in an embodiment of the present application, a prefetch strategy configuration scheme is provided for cloud computing scenarios, which can flexibly and dynamically configure prefetch strategies for physical CPUs according to the scheduling of virtualized instances. That is, when the physical CPU runs virtualized instance A, a prefetch strategy adapted to virtualized instance A can be configured for the physical CPU, and when the physical CPU runs virtualized instance B, a prefetch strategy adapted to virtualized instance B can be configured for the physical CPU. Specifically, in a cloud computing scenario, a virtualization manager for creating and managing virtualized instances is deployed on the physical machine, and the virtualized instances are scheduled to run on the physical processors of the physical machine. In an embodiment of the present application, the physical processor includes a hardware prefetcher and a prefetch register for prefetching the hardware prefetcher. Under the control of the prefetch register, the prefetcher can perform hardware prefetch operations during the operation of the virtualized instance. The hardware prefetch operation can reduce the time the physical processor waits to read data or instructions, which is conducive to improving the execution efficiency of the physical processor, and then improving the running performance of the virtualized instance. Furthermore, in order to realize the dynamic configuration of hardware prefetch policy, in the embodiment of the present application, by expanding the function of the virtualization manager, the virtualization manager applies for the prefetch register access right to the firmware program of the prefetch register, and when the prefetch register access right is successfully applied, the virtualization manager senses the operation of configuring the prefetch policy parameters of the virtualization instance and configures the prefetch policy parameters to the prefetch register in the physical processor to which the virtualization instance is scheduled on behalf of the virtualization instance, and then transmits the configuration capability of the prefetch register to the virtualization instance through the underlying virtualization technology, so that the prefetch policy can be flexibly and dynamically configured for different virtualization instances according to the scheduling of the virtualization instance, which solves the problem in the prior art that the performance of multiple applications cannot be taken into account due to the inability to flexibly and dynamically configure the prefetch policy. At the same time, in the embodiment of the present application, the virtualization manager configures the prefetch policy for the prefetch register on behalf of the virtualization instance, which can ensure the security of the physical processor.

[0044] The technical solutions provided by various embodiments of the present application are described in detail below in conjunction with the accompanying drawings.

[0045] Figure 2 The following is a diagram of the hardware and software system architecture of a physical machine provided by an exemplary embodiment of the present application. Figure 2 As shown, the physical machine of this embodiment includes: hardware resources and software resources. Among them, hardware resources refer to the physical devices that can be seen and touched in the physical machine; software resources refer to the programs organized to facilitate the use of the physical machine and improve the efficiency of use, as well as the relevant documents used for development, use and maintenance.

[0046] In the embodiment of the present application, the hardware resources of the physical machine include at least one physical processor, memory, hard disk, network card, and some peripheral devices (display), etc. The hardware resources focused on in the embodiment of the present application are physical processors. Figure 2 The physical processor is highlighted in Figure 2 Multiple physical processors are shown in FIG. Figure 2 As shown, the physical processor of this embodiment includes at least one or more hardware prefetchers (Cache Prefetch) and multiple prefetch registers (Prefetch register) for prefetching control of the hardware prefetchers. The hardware prefetchers are used to perform prefetch operations under the control of the prefetch registers, and the prefetch registers are used to store prefetch parameters. Further, the physical processor of this embodiment can also Figure 1a The various components shown are not described in detail here.

[0047] In the embodiment of the present application, the software resources of the physical machine include at least a firmware program (Bios) for reading and writing control of the pre-fetch register and a virtualization manager for creating and managing virtualization instances; further, Figure 2 As shown, the software resources of the physical machine also include various virtualization instances created by the virtualization manager, and each virtualization instance includes its own operating system (OS). Relatively speaking, the physical machine acts as a host, and its operating system can be called the host operating system (Host OS), and the virtualization instance can act as a client, and its operating system can also be called the guest operating system (Guest OS). Figure 2 In the example of virtualization instance implementation as VM, the virtualization manager is not limited in the embodiment of the present application. For example, it can be a virtual machine monitor (Virtual Machine Monitor, VMM), which can also be called Hypervisor. Among them, Host OS is also a software resource of physical machine. Figure 2 It should be noted that the virtualization manager is a functional module in the Host OS. Figure 2 In the figure, each software resource is hierarchically illustrated based on the privilege level of each software resource, rather than from the dimension of inclusion or ownership relationship between software resources.

[0048] In an embodiment of the present application, the software resources of a physical machine have a privilege level. In some processor architectures, the privilege level is also called an exception level (EL). Different software resources may have different exception levels, and there may be multiple software resources under the same exception level. The privilege level or exception level provides a logical separation of execution permissions between software resources. Generally, the higher the privilege level or exception level, the greater the execution permission. In this embodiment, taking the processor architecture providing four exception levels as an example, it is assumed that the four exception levels are EL0, EL1, EL2, and EL3, EL0 is the level corresponding to the user application, EL1 is the level corresponding to the operating system kernel, EL2 is the level corresponding to the virtualization manager, and EL3 is the level corresponding to some firmware programs. Among them, the processor architecture that provides four exception levels can be but is not limited to the ARM architecture. The larger the number of the exception level, the higher the exception level, and the greater the corresponding execution permission. In this embodiment, if Figure 2 As shown, the virtual virtualization manager is in EL2, the firmware program of the pre-fetch register is in EL3, and the client operating system corresponding to the virtualization instance created by the virtualization manager is in EL1. Figure 2 The exception level of the host operating system is not limited. In different processor architectures, the exception level of the host operating system may be different. In some processor architectures, the host operating system is in EL2, and in some processor architectures, the host operating system may be in EL1.

[0049] In the processor architecture of this embodiment, for security reasons, the EL required for reading and writing prefetch registers is higher, allowing the firmware program at EL3 to read, write or modify it, while the virtualization manager at EL2 and the virtualization instance at EL1 do not have access rights to read and write prefetch registers, which can protect the security of the processor. However, in the embodiment of the present application, it is hoped that the prefetch strategy can be flexibly and dynamically configured for the physical processor according to the scheduling of the virtualization instance, which requires the prefetch strategy to be configured for the prefetch register from the dimension of the virtualization instance, that is, the virtualization instance needs to be able to read and write the prefetch register, which is contrary to the security of the processor architecture. To this end, in an embodiment of the present application, the access of the virtualization instance to the prefetch register is trapped to the virtualization manager, and the virtualization manager configures the prefetch policy for the prefetch register on behalf of the virtualization instance. While meeting the processor security requirements, the configuration capability of the prefetch register is transparently transmitted to the virtualization instance through the underlying virtualization technology, so that the prefetch policy can be flexibly and dynamically configured for different virtualization instances according to the scheduling status of the virtualization instance, which solves the problem in the prior art that the prefetch policy cannot be flexibly and dynamically configured, resulting in the inability to take into account the performance of multiple applications.

[0050] However, in the current processor architecture, the virtualization manager does not have access to the prefetch registers. In view of this, in the embodiments of the present application, the functions of the prefetch register firmware program, the virtualization manager and the virtualization instance are improved, and with the cooperation of the three, the virtualization manager has access to the prefetch registers and can pass the configuration capabilities of the prefetch registers to the virtualization instance, thereby being able to flexibly and dynamically configure prefetch strategies for different virtualization instances according to the scheduling conditions of the virtualization instances.

[0051] Specifically, on the one hand, it is necessary to re-implement the firmware program of the prefetch register and add an authorization function in the firmware program so that the firmware program can authorize the virtualization manager to access the prefetch register; on the other hand, the function of the virtualization manager is expanded so that it has the ability to apply for the prefetch register access permission from the firmware program of the prefetch register, and the ability to perceive the operation of the virtualization instance accessing the prefetch register to configure the target prefetch policy parameters and to configure the target prefetch policy parameters to the prefetch register in the target physical processor to which the virtualization instance is scheduled on behalf of the virtualization instance.

[0052] Based on the above, in addition to creating and managing virtualized instances, the virtualization manager in this embodiment is also used to apply for pre-fetch register access rights to the firmware program. When the pre-fetch register access rights are successfully applied for, in response to the operation of the virtualized instance configuring the target pre-fetch policy parameters for the pre-fetch register, the target pre-fetch policy parameters are configured to the pre-fetch register in the target physical processor to which the virtualized instance is scheduled, so as to realize the dynamic configuration of the pre-fetch policy. In the embodiment of the present application, the scheduling policy for scheduling the virtualized instance is not limited, but the virtualized instance is dynamically scheduled, and different physical processors may be assigned to the virtualized instance in different scheduling processes, or the same physical processor may be assigned to it, which is not limited. For the convenience of description and distinction, the physical processor to which the virtualized instance is scheduled after configuring the target pre-fetch policy parameters is called the target physical processor. Among them, the target pre-fetch policy parameters are the pre-fetch policy parameters that the virtualized instance needs to configure, and different virtualized instances can configure different pre-fetch policy parameters for the physical processor to which it is scheduled. In addition, in addition to configuring the pre-fetch configuration policy for the physical processor according to the scheduling situation of the virtualized instance, the physical processor also has a default pre-fetch policy parameter. It is to be noted that the pre-fetching strategy parameters of this embodiment are the “pre-fetching parameter combination” described above, which will not be described in detail here. For related explanations, please refer to the above text.

[0053] In an embodiment of the present application, in order to realize the dynamic configuration of the hardware prefetch policy, the virtualization manager applies for the prefetch register access right to the firmware program of the prefetch register, and when the prefetch register access right is successfully applied for, the virtualization instance is sensed to configure the prefetch policy parameter operation and configures the prefetch policy parameter to the prefetch register in the physical processor to which the virtualization instance is scheduled on behalf of the virtualization instance. This is equivalent to transparently transmitting the configuration capability of the prefetch register to the virtualization instance through the underlying virtualization technology, so that the prefetch policy can be flexibly and dynamically configured for different virtualization instances according to the scheduling of the virtualization instance. When the physical processor runs the virtualization instance A, the physical processor is configured with a prefetch policy adapted to the virtualization instance A, so that the prefetch policy brings performance improvement to the virtualization instance A. When the physical processor runs the virtualization instance B, the physical processor is configured with a prefetch policy adapted to the virtualization instance B, so that the prefetch policy brings performance improvement to the virtualization instance B, which solves the problem in the prior art that the performance of multiple applications cannot be taken into account due to the inability to flexibly and dynamically configure the prefetch policy.

[0054] In the embodiments of the present application, Figure 2 As shown, each physical processor also includes an authorization register, which is used to indicate whether to open the access right of the pre-fetch register to the virtualization manager through a preset value. Based on this, when the virtualization manager applies for the access right of the pre-fetch register, the firmware program can configure the authorization register in each physical processor to a preset value indicating authorization, so as to open the access right of the pre-fetch register to the virtualization manager. Among them, the implementation of the authorization register will also be different according to the different processor architectures, and this embodiment does not limit this. For example, taking the length of the authorization register as 1 bit as an example, and assuming that the preset value indicating authorization is "1", when the virtualization manager applies for the access right of the pre-fetch register to the firmware program, if the access right of the virtualization manager can be granted, the firmware program can configure the value of the authorization register in each physical processor to be "1", indicating that the access right of the pre-fetch register is opened to the virtualization manager, that is, the virtualization manager has the access right to access the pre-fetch registers in each physical processor. Of course, when the preset value indicating authorization is "1", the value of the authorization register is "0", which indicates that the access right of the pre-fetch register is not opened to the virtualization manager.

[0055] In an embodiment of the present application, the virtualization manager can apply to the firmware program for access rights to prefetch registers during the initialization process. The virtualization manager will perform an initialization process when it is loaded, and the situations in which the virtualization manager is loaded include but are not limited to the following two: one is when the physical machine is turned on, and the other is when the old version of the virtualization manager is replaced with the new version online. In an embodiment of the present application, the implementation method of the virtualization manager applying to the firmware program of the prefetch register for access rights to prefetch registers during the initialization process is not limited. The following examples are provided for illustration:

[0056] In an optional embodiment, in the processor architecture of the embodiment of the present application, a communication instruction is provided for the software resource in EL2 to interact with the software resource in EL3, and the communication instruction may include parameters, and different parameters represent different communication purposes between the software resource in EL2 and the software resource in EL3. Based on this, the developer can pre-agreed the parameters representing the virtualization manager to apply for the pre-fetch register access right to the firmware program, which are recorded as agreed parameters, so that the virtualization manager can use the existing communication instructions to apply for the pre-fetch register access right to the firmware program. That is, an implementation method of the virtualization manager applying for the pre-fetch register access right to the firmware program includes: the virtualization manager sends a communication instruction to the firmware program during the initialization process, and the communication instruction includes an agreed parameter indicating the application for the pre-fetch register access right; accordingly, the firmware program receives the communication instruction sent by the virtualization manager, and according to the agreed parameter included in the communication instruction, configures the authorization register in each physical processor to a preset value indicating authorization, so as to open the pre-fetch register access right to the virtualization manager, and returns the authorization success result information to the virtualization manager; accordingly, the virtualization manager receives the authorization success result information returned by the firmware program, indicating that the pre-fetch register access right has been successfully applied for.

[0057] For example, under the ARM (Advanced RISC Machines) processor architecture, the above communication instruction can be implemented as an SMC (Secure Monitor Call) instruction. Specifically, during the initialization process, the virtualization manager sends an SMC instruction to the firmware program. The SMC instruction contains an agreed parameter indicating the application for pre-fetch register access rights. After receiving the SMC instruction, the firmware program parses the agreed parameter contained in the SMC instruction, and configures the authorization register in each physical processor to "1" (assuming that "1" represents the preset value of authorization) according to the agreed parameter, so as to open the corresponding pre-fetch register access rights to the virtualization manager, and returns a default value to the virtualization manager, for example, returns "0" by default, and the default value indicates the authorization success result information. Under the ARM processing architecture, the authorization register can be implemented as ACTLR_EL3, which is an auxiliary control register used to control whether the pre-fetch register is authorized to the virtualization manager in EL2. Configuring ACTLR_EL3.ECTLREN=1 indicates that the pre-fetch register is authorized to the virtualization manager in EL2.

[0058] In another optional embodiment, a message for inter-process communication may be added between the virtualization manager and the firmware program of the pre-fetch register, and the virtualization manager may apply to the firmware program for the pre-fetch register access right through the message. The message has a specific format, and the specific format of the message may indicate that the virtualization manager applies to the firmware program for the pre-fetch register access right. Alternatively, a new instruction may be added between the virtualization manager and the firmware program of the pre-fetch register, and the virtualization manager may apply to the firmware program for the pre-fetch register access right through the new instruction.

[0059] It should be noted that no matter what method is used to apply for the prefetch register access rights from the firmware program, the prefetch register access rights applied for by the virtualization manager during the initialization process can always belong to the virtualization manager until the virtualization manager is restored to factory settings or reinitialized, at which time the virtualization manager stops using the prefetch register access rights, and during the reinitialization process, the virtualization manager can reapply to the firmware program for prefetch register access rights.

[0060] Furthermore, after the virtualization manager applies for access to the prefetch registers, in order to achieve dynamic configuration of the prefetch policy, it is also necessary to be able to perceive the operation of the virtualization instance to configure the target prefetch policy parameters for the prefetch registers, and intercept the target prefetch policy parameters configured by the virtualization instance for the prefetch registers, so as to replace the virtualization instance in configuring the target prefetch policy parameters to the prefetch registers in the target physical processor responsible for running the virtualization instance, and ultimately achieve the purpose of dynamically configuring the prefetch policy according to the scheduling situation of the virtualization instance. Based on this, when the virtualization manager responds to the operation of the virtualization instance configuring the target prefetch policy parameters for the prefetch registers, and configures the target prefetch policy parameters to the prefetch registers in the target physical processor to which the virtualization instance is scheduled to realize the dynamic configuration of the prefetch policy, it is specifically used for: during the initialization process, configuring the ability of the virtualization instance to trap out to the virtualization manager when configuring the target prefetch policy parameters for the prefetch registers, and "trapping out" can be understood as the switching of execution permissions, that is, switching from executing the virtualization instance in EL1 to executing the virtualization manager in EL2; further, when the virtualization instance traps out to the virtualization manager, the virtualization instance is executed, and at this time the virtualization instance can intercept the target prefetch policy parameters configured for the prefetch registers by the virtualization instance where the trap occurs, and store the target prefetch policy parameters in the software data structure of the virtualization instance; thereafter, configuring the target prefetch policy parameters to the prefetch registers in the target physical processor to which the virtualization instance where the trap occurs is scheduled to realize the dynamic configuration of the prefetch policy.

[0061] In the embodiments of the present application, Figure 2As shown, the hardware resources of the physical machine also include: an auxiliary authorization control register and a virtualization trap control register, which belong to the system registers. Among them, the auxiliary authorization control register is used to control whether to close the virtualization instance's direct access to the prefetch register, and the virtualization trap control register is used to control whether to allow the virtualization instance to trap out to the virtualization manager when configuring the target prefetch policy parameters for the prefetch register. Based on this, when the virtualization manager configures the ability of the virtualization instance to trap out to the virtualization manager when configuring the target prefetch policy parameters for the prefetch register, it is specifically used to: on the one hand, configure the auxiliary authorization control register to a preset value indicating that authorization is prohibited, so as to close the virtualization instance's direct access to the prefetch register; on the other hand, configure the virtualization trap register to a preset value indicating that trapping is allowed, so as to control the virtualization instance to trap out to the virtualization manager when configuring the target prefetch policy parameters for the prefetch register. In different processor architectures, the auxiliary authorization control register and the virtualization trap control register can have different implementations, which are not limited to this. For example, taking the ARM processor architecture as an example, the auxiliary authorization control register can be implemented as the ACTLR_EL2 register, which is an auxiliary control register used to assist in controlling whether to authorize the software resources in EL1 to access the prefetch register. For example, configuring ACTLR_EL2.ACTLREN=0 means closing or prohibiting the virtualization instance from directly accessing the prefetch register. Correspondingly, in the ARM processor architecture, the virtualization trap control register can be the HCR_EL2 register, which is also an auxiliary control register used to assist in controlling whether to allow the virtualization instance in EL1 to trap to the virtualization manager in EL2 when accessing the prefetch register. Configuring HCR_EL2.TIDCP=1 means allowing the virtualization instance to trap to the virtualization manager when configuring the target prefetch policy parameters for the prefetch register.

[0062] In an optional embodiment, after configuring the ability to instruct the virtualized instance to trap to the virtualized manager when configuring the target prefetch policy parameters for the prefetch register, the virtualized instance can be created according to the user's application requirements, and during the operation of the virtualized instance, it is monitored whether there is a virtualized instance trapping to the virtualized manager, and when it is detected that a virtualized instance has trapped, the target prefetch policy parameters configured for the prefetch register of the virtualized instance that has trapped are intercepted. More specifically, each virtualized instance has a unique identifier, and when the virtualized manager detects that the identifier of the virtualized instance appears locally, it determines that the virtualized instance traps to the virtualized manager, and intercepts the target prefetch policy parameters configured for the prefetch register of the virtualized instance that has trapped.

[0063] In an embodiment of the present application, a virtualization instance is created by a virtualization manager, and the virtualization manager and the virtualization instance belong to the same virtualization thread, which can be referred to as a virtual processor (Virtual Central Processing Unit, VCPU) thread. Before the virtualization instance is trapped, it can occupy physical processor resources, and the physical processor runs the virtualization instance. To facilitate the distinction from the target physical processor, the physical processor at this time is referred to as the first physical processor. During the period when the first physical processor runs the virtualization instance, the virtualization instance can initiate an operation to configure the target prefetch policy parameters for the prefetch register, for example, an operation to configure the target prefetch policy parameters for the prefetch register can be initiated according to the user's application requirements. It is explained here that the target prefetch policy parameters may not be applicable to the parameter configuration requirements of other virtualization instances for the prefetch register. When the virtualization instance initiates an operation to configure the target prefetch policy parameters for the prefetch register, based on the trapping capability configured above, the virtualization instance will trap to the virtualization manager, that is, the first physical processor will be preempted by the virtualization manager, and at this time, the first physical processor will run the virtualization manager. In order to facilitate other virtualized instances to use the first physical processor normally in the future, the prefetch registers in the first physical processor can be restored to the default prefetch policy parameters. Optionally, the default prefetch policy parameters can select relatively balanced prefetch policy parameters so as to be applicable to as many virtualized instances as possible. Based on this, the virtualization manager is also used to: when it is detected that a virtualized instance has fallen out of the virtualization manager, seize the first physical processor currently occupied by the virtualized instance that has fallen out, and restore the prefetch registers in the first physical processor to the default prefetch policy parameters; wherein the virtualization manager and the virtualized instance that has fallen out belong to different functional modules in the first virtualization thread, the first physical processor is scheduled to the first virtualization thread to be responsible for running different functional modules in the first virtualization thread, and at the same time, the first physical processor is responsible for running a functional module in the first virtualization thread.

[0064] In this embodiment, the virtualization manager does not limit the order between restoring the prefetch registers in the first physical processor to the default prefetch policy parameters and intercepting the target prefetch policy parameters configured for the prefetch registers by the virtualization instance where the trap occurs. Preferably, the prefetch registers in the first physical processor may be restored to the default prefetch policy parameters first, and then the target prefetch policy parameters configured for the prefetch registers by the virtualization instance where the trap occurs may be intercepted.

[0065] Furthermore, the virtualization manager is also used to: after intercepting the target prefetch policy parameters, set a scheduling point for the first physical processor to allow other threads on the physical machine to preempt the first physical processor, and wait for the first virtualized thread to be rescheduled when the first physical processor is preempted by other threads. Accordingly, when the virtualization manager configures the target prefetch policy parameters to the prefetch registers in the target physical processor to which the virtualized instance in which the trap occurs is scheduled to realize the dynamic configuration of the prefetch policy, it is specifically used to: when the first virtualized thread is rescheduled to the target physical processor, configure the target prefetch policy parameters to the prefetch registers in the target physical processor to realize the dynamic configuration of the prefetch policy. Among them, the target physical processor can be the first physical processor, or it can be another physical processor different from the first physical processor, such as the second physical processor. In some application scenarios, a binding relationship between each virtualized instance and the physical processor can be established, and when the virtualized instance is scheduled for execution, it can be assigned a physical processor with which it has a binding relationship. In some other application scenarios, it is also possible not to establish a binding relationship between the virtualized instance and the physical processor. When the virtualized instance is scheduled for execution, the physical processor can be randomly or according to a set resource allocation policy to be allocated to the virtualized instance, for example, physical processors with lighter loads are allocated preferentially. It is explained here that since the virtualization manager is being executed when the first physical processor is preempted by other threads, when the first virtualized thread is rescheduled to the target physical processor, it will continue to be executed from the virtualization manager. Therefore, the virtualization manager can configure the target prefetch policy parameters to the prefetch registers in the target physical processor when the first virtualized thread is rescheduled to the target physical processor. Further, after configuring the target prefetch policy parameters to the prefetch registers in the target physical processor, it can be switched back to the virtualized instance. At this time, the target physical processor can continue to run the virtualized instance, and in the process of running the virtualized instance, according to the target prefetch policy parameters stored in the prefetch registers, perform data and / or instruction prefetch operations.

[0066] Furthermore, the virtualization manager is further configured to restore the prefetch register in the target physical processor to the default prefetch policy parameters when the virtualization instance scheduled to the target physical processor is shut down or destroyed.

[0067] In an embodiment of the present application, the virtualization manager obtains the access rights of the prefetch registers of the physical processor and sets the access of the virtualization instance to the prefetch registers to the method of the virtualization manager, so that the prefetch registers can be simulated and transmitted to the virtualization instance through virtualization technology, so that the user of the virtualization instance can flexibly configure the prefetch policy, and can restore the prefetch policy on the corresponding physical processor to the default value after the user destroys the virtualization instance. The prefetch policy used by the physical processor where the virtualization instance is located can be configured separately for the virtualization instance, thereby improving the prefetch efficiency, and allowing the virtualization instances of different users on the physical machine to simultaneously obtain the performance improvement advantages brought by the prefetch policy when running different types of applications.

[0068] For ease of understanding, the following Figure 3 Taking the physical processor before and after the pre-fetch strategy configuration scheme as the same processor as an example, the pre-fetch strategy configuration scheme provided by the above embodiment is exemplarily described from the interaction process of the virtual machine instance, the virtualization manager, the firmware program and the physical processor. Figure 3 As shown, the dynamic configuration of the hardware prefetching strategy includes the following steps:

[0069] Step 1: Initialization of the virtualization manager. The initialization process of the virtualization manager mainly includes the following steps:

[0070] Step 11, the virtualization manager sends a communication instruction to the firmware program to apply for access rights to the pre-fetch register, so as to grant the firmware program access rights to the pre-fetch register;

[0071] Step 12: The firmware program configures the value of the authorization register in at least one physical processor to be a preset value indicating authorization according to the communication instruction sent by the virtualization manager for applying for the access right of the pre-fetch register;

[0072] Step 13: When the value of the authorization register is a preset value indicating authorization, return authorization success result information to the virtualization manager to open the pre-fetch register access right to the virtualization manager;

[0073] Step 2: The virtualization manager reads and saves the default prefetch strategy parameters of the prefetch register, referred to as default values;

[0074] Step 3: The virtualization manager configures the auxiliary authorization control register and the virtualization trap control register to achieve the ability of configuring the virtualization instance to trap to the virtualization manager when configuring the target prefetch policy parameters for the prefetch register;

[0075] Step 4: The virtualization manager creates a virtual machine instance, and the virtual machine instance starts running;

[0076] Step 5: The virtualized instance configures target prefetch policy parameters for the prefetch register and traps to the virtualization manager;

[0077] Step 6: The virtualization manager intercepts the target prefetch strategy parameters configured by the virtualization instance for the prefetch register;

[0078] Step 7: The virtualization manager configures the target prefetch policy parameters to the prefetch registers in the target physical processor to which the virtualization instance is scheduled, so as to realize dynamic configuration of the prefetch policy.

[0079] Step 8: The virtualization manager returns the virtualization instance so that the target physical processor continues to run the virtualization instance;

[0080] Step 9: When the virtualized instance is shut down or destroyed, the virtualization manager restores the prefetch register in the target physical processor to the default prefetch policy parameters and clears the relevant information of the virtualized instance.

[0081] At this point, the prefetch strategy configuration scheme has been executed, making it possible to flexibly and dynamically configure prefetch strategies for different virtualization instances according to the scheduling of virtualization instances, solving the problem in the prior art that the prefetch strategy cannot be flexibly and dynamically configured, resulting in the inability to take into account the performance of multiple applications.

[0082] Figure 4 A flowchart of a prefetch strategy configuration method provided by an exemplary embodiment of the present application. The method is applied to a virtualization manager for creating and managing virtualization instances on a physical machine, wherein at least one physical processor of the physical machine includes a hardware prefetcher and a prefetch register for prefetching control of the hardware prefetcher. Figure 4 As shown, the method includes:

[0083] 401. Apply for a prefetch register access permission from a firmware program in a physical machine for performing read and write control on the prefetch register;

[0084] 402. When the prefetch register access right is successfully applied for, in response to the operation of the virtualization instance to configure the target prefetch policy parameters for the prefetch register, the target prefetch policy parameters are configured to the prefetch register in the target physical processor to which the virtualization instance is scheduled, so as to realize dynamic configuration of the prefetch policy.

[0085] In an optional embodiment, applying for prefetch register access rights to a firmware program in a physical machine that is used to perform read and write control on prefetch registers includes: sending a communication instruction to the firmware program during an initialization process, the communication instruction including an agreed parameter indicating an application for prefetch register access rights, so that the firmware program configures an authorization register in at least one physical processor to a preset value indicating authorization, so as to open the prefetch register access rights to the virtualization manager; and receiving authorization success result information returned by the firmware program.

[0086] In an optional embodiment, in response to the operation of configuring the target prefetch policy parameters for the prefetch registers by the virtualization instance, the target prefetch policy parameters are configured to the prefetch registers in the target physical processor to which the virtualization instance is scheduled, so as to realize the dynamic configuration of the prefetch policy, including: during the initialization process, configuring the ability of the virtualization instance to trap out to the virtualization manager when configuring the target prefetch policy parameters for the prefetch registers; when the virtualization instance traps out to the virtualization manager, intercepting the target prefetch policy parameters configured for the prefetch registers by the virtualization instance that has trapped out; configuring the target prefetch policy parameters to the prefetch registers in the target physical processor to which the virtualization instance that has trapped out is scheduled, so as to realize the dynamic configuration of the prefetch policy.

[0087] In an optional embodiment, during the initialization process, the ability of the virtualized instance to trap out to the virtualization manager when configuring the target prefetch policy parameters for the prefetch register is configured, including: during the initialization process, configuring the auxiliary authorization control register of the physical machine to a preset value indicating that authorization is prohibited, so as to close the virtualized instance's direct access to the prefetch register; configuring the virtualization trap register of the physical machine to a preset value indicating that trap out is allowed, so as to control the virtualized instance to trap out to the virtualization manager when configuring the target prefetch policy parameters for the prefetch register.

[0088] Optionally, when a virtualization instance traps to the virtualization manager and before intercepting the target prefetch policy parameters, the method also includes: preempting the first physical processor currently occupied by the virtualization instance where the trap occurs, and restoring the prefetch registers in the first physical processor to default prefetch policy parameters; wherein the virtualization manager and the virtualization instance where the trap occurs belong to different functional modules in the first virtualization thread, and the first physical processor is scheduled to the first virtualization thread to be responsible for running different functional modules in the first virtualization thread.

[0089] Further optionally, after intercepting the target prefetch policy parameters, the method also includes: setting a scheduling point for the first physical processor, allowing other threads on the physical machine to preempt the first physical processor, and waiting for the first virtualization thread to be rescheduled when the first physical processor is preempted by other threads; wherein the target prefetch policy parameters are configured to the prefetch registers in the target physical processor to which the virtualization instance where the trap occurs is scheduled, so as to realize the dynamic configuration of the prefetch policy, including: when the first virtualization thread is rescheduled to the target physical processor, the target prefetch policy parameters are configured to the prefetch registers in the target physical processor, so as to realize the dynamic configuration of the prefetch policy.

[0090] Further optionally: when the virtualized instance scheduled to the target physical processor is shut down or destroyed, the prefetch register in the target physical processor is restored to the default prefetch policy parameters.

[0091] In the embodiment of the present application, the privilege level of the firmware program is higher than the privilege level of the virtualization manager, and the privilege level of the virtualization manager is higher than the privilege level of the virtualization instance.

[0092] Regarding the embodiments of the present application Figure 4 The detailed implementation and beneficial effects of each step in the method have been described in detail in the aforementioned embodiments and will not be elaborated here.

[0093] It should be noted that the execution subject of each step of the method provided in the above embodiment can be the same device, or the method can be executed by different devices. For example, the execution subject of step 401 to step 402 can be device A.

[0094] Figure 5 A flowchart of another prefetch strategy configuration method provided by an exemplary embodiment of the present application. The method is applied to a firmware program in a physical machine for reading and writing control of a prefetch register, and the physical machine also includes a virtualization manager for creating and managing virtualization instances. Figure 5 As shown, the method includes:

[0095] 501. When the virtualization manager applies for a pre-fetch register access right, configure an authorization register in at least one physical processor to a preset value indicating authorization, so as to open the pre-fetch register access right to the virtualization manager;

[0096] 502. Return authorization success structure information to the virtualization manager.

[0097] Regarding the embodiments of the present application Figure 5 The detailed implementation and beneficial effects of each step in the method have been described in detail in the aforementioned embodiments and will not be elaborated here.

[0098] It should be noted that the execution subject of each step of the method provided in the above embodiment can be the same device, or the method can be executed by different devices. For example, the execution subject of step 501 to step 502 can be device A.

[0099] Figure 6 A flowchart of another prefetch strategy configuration method provided by an exemplary embodiment of the present application. The method is applied to a virtualization instance created by a virtualization manager in a physical machine, wherein at least one physical processor of the physical machine includes a hardware prefetcher and a prefetch register for prefetching control of the hardware prefetcher. Figure 6 As shown, the method includes:

[0100] 601. In response to a prefetch strategy configuration operation, obtain target prefetch strategy parameters configured for a prefetch register;

[0101] 602. Based on the ability of the virtualization instance to trap to the virtualization manager when configuring target prefetch policy parameters for prefetch registers, the virtualization instance is instructed to trap to the virtualization manager so that the virtualization manager can intercept the target prefetch policy parameters and configure them to the prefetch registers in the target physical processor to which the virtualization instance is scheduled, so as to realize dynamic configuration of the prefetch policy.

[0102] Regarding the embodiments of the present application Figure 6 The detailed implementation and beneficial effects of each step in the method have been described in detail in the aforementioned embodiments and will not be elaborated here.

[0103] It should be noted that the execution subject of each step of the method provided in the above embodiment can be the same device, or the method can be executed by different devices. For example, the execution subject of step 601 to step 602 can be device A.

[0104] Figure 7 A flow chart of a cache prefetching method provided by an exemplary embodiment of the present application. The method is applied to a target physical processor in a physical machine, the target physical processor includes a hardware prefetcher and a prefetch register for prefetching control of the hardware prefetcher, and the target prefetching strategy parameter in the prefetch register is based on Figure 4 The configuration of each step in the method shown. Figure 7 As shown, the method includes:

[0105] 701. Read target prefetch strategy parameters from the prefetch register;

[0106] 702. During the running of the scheduled virtualized instance, perform data and / or instruction prefetch operations based on target prefetch policy parameters.

[0107] Regarding the embodiments of the present application Figure 7 The detailed implementation and beneficial effects of each step in the method have been described in detail in the aforementioned embodiments and will not be elaborated here.

[0108] It should be noted that the execution subject of each step of the method provided in the above embodiment can be the same device, or the method can be executed by different devices. For example, the execution subject of step 701 to step 702 can be device A; for another example, the execution subject of step 701 can be device A, and the execution subject of step 702 can be device B; and so on.

[0109] In addition, in some of the processes described in the above embodiments and the accompanying drawings, multiple operations that appear in a specific order are included, but it should be clearly understood that these operations may not be executed in the order in which they appear in this article or executed in parallel, and the sequence numbers of the operations such as 401, 402, 501, 502, 601, 602, 701, 702, etc. are only used to distinguish between different operations, and the sequence numbers themselves do not represent any execution order. In addition, these processes may include more or fewer operations, and these operations may be executed in sequence or in parallel. It should be noted that the descriptions of "first", "second", etc. in this article are used to distinguish different messages, devices, modules, etc., do not represent the order of precedence, and do not limit "first" and "second" to be different types.

[0110] Figure 8 A schematic diagram of a prefetch strategy configuration device provided in an exemplary embodiment of the present application. A virtualization manager for creating and managing virtualized instances on a physical machine, wherein at least one physical processor of the physical machine includes a hardware prefetcher and a prefetch register for prefetching the hardware prefetcher. Figure 8 As shown, the device comprises:

[0111] An authorization application module 81 is used to apply for a pre-fetch register access permission from a firmware program in a physical machine that is used to perform read and write control on the pre-fetch register;

[0112] The policy configuration module 82 is used to respond to the operation of the virtualization instance to configure the target prefetch policy parameters for the prefetch register when the prefetch register access right is successfully applied for, and configure the target prefetch policy parameters to the prefetch register in the target physical processor to which the virtualization instance is scheduled, so as to realize the dynamic configuration of the prefetch policy.

[0113] In an optional embodiment, when the authorization application module 81 is used to apply for prefetch register access rights to a firmware program in a physical machine that is used to perform read and write control on the prefetch register, it is specifically used to: send a communication instruction to the firmware program during the initialization process, and the communication instruction includes an agreed parameter indicating an application for prefetch register access rights, so that the firmware program configures the authorization register in the at least one physical processor to a preset value indicating authorization, so as to open the prefetch register access rights to the virtualization manager; and receive the authorization success result information returned by the firmware program.

[0114] In an optional embodiment, the policy configuration module 82 is used to respond to the operation of the virtualization instance configuring the target prefetch policy parameters for the prefetch registers, and configure the target prefetch policy parameters to the prefetch registers in the target physical processor to which the virtualization instance is scheduled to realize dynamic configuration of the prefetch policy. Specifically, it is used to: during the initialization process, configure the ability of the virtualization instance to trap out to the virtualization manager when the target prefetch policy parameters are configured for the prefetch registers; when the virtualization instance traps out to the virtualization manager, intercept the target prefetch policy parameters configured for the prefetch registers by the virtualization instance that has trapped out; configure the target prefetch policy parameters to the prefetch registers in the target physical processor to which the virtualization instance that has trapped out is scheduled to realize dynamic configuration of the prefetch policy.

[0115] Optionally, when the policy configuration module 82 is used to configure the ability of the virtualization instance to trap to the virtualization manager when configuring the target prefetch policy parameters for the prefetch register during the initialization process, it is specifically used to: during the initialization process, configure the auxiliary authorization control register of the physical machine to a preset value indicating that authorization is prohibited, so as to close the virtualization instance's direct access to the prefetch register; configure the virtualization trap register of the physical machine to a preset value indicating that trap is allowed, so as to control the virtualization instance to trap to the virtualization manager when configuring the target prefetch policy parameters for the prefetch register.

[0116] Optionally, when a virtualization instance traps to the virtualization manager and before the target prefetch policy parameters are intercepted, a preemption module and a recovery module are provided, wherein the preemption module is used to preempt the first physical processor currently occupied by the virtualization instance where the trap occurs, and the recovery module is used to restore the prefetch registers in the first physical processor to default prefetch policy parameters; wherein the virtualization manager and the virtualization instance where the trap occurs belong to different functional modules in the first virtualization thread, and the first physical processor is scheduled to the first virtualization thread to be responsible for running different functional modules in the first virtualization thread.

[0117] Further optionally, it also includes a setting module, which is used to set a scheduling point for the first physical processor after intercepting the target prefetch policy parameters, allowing other threads on the physical machine to preempt the first physical processor, and waiting for the first virtualization thread to be rescheduled when the first physical processor is preempted by other threads; wherein, the policy configuration module is used to configure the target prefetch policy parameters to the prefetch registers in the target physical processor to which the virtualization instance where the trap occurs is scheduled to realize dynamic configuration of the prefetch policy, and is specifically used to: when the first virtualization thread is rescheduled to the target physical processor, configure the target prefetch policy parameters to the prefetch registers in the target physical processor to realize dynamic configuration of the prefetch policy.

[0118] Further optionally, the recovery module is further configured to restore the prefetch register in the target physical processor to a default prefetch policy parameter when the virtualization instance scheduled to the target physical processor is shut down or destroyed.

[0119] In the embodiment of the present application, the privilege level of the firmware program is higher than the privilege level of the virtualization manager, and the privilege level of the virtualization manager is higher than the privilege level of the virtualization instance.

[0120] Regarding the embodiments of the present application Figure 8 The detailed implementation and beneficial effects of each module in the illustrated device have been described in detail in the aforementioned embodiments and will not be elaborated on in detail here.

[0121] Fig. 9 A schematic diagram of another prefetch strategy configuration device provided by an exemplary embodiment of the present application. A firmware program used in a physical machine for reading and writing prefetch registers, the physical machine also includes a virtualization manager for creating and managing virtualized instances. Fig. 9 As shown, the device comprises:

[0122] An authorization configuration module 91, configured to configure an authorization register in at least one physical processor to a preset value indicating authorization when the virtualization manager applies for a pre-fetch register access right, so as to open the pre-fetch register access right to the virtualization manager;

[0123] The authorization information returning module 92 is used to return authorization success structure information to the virtualization manager.

[0124] Regarding the embodiments of the present application Fig. 9 The detailed implementation and beneficial effects of each module in the illustrated device have been described in detail in the aforementioned embodiments and will not be elaborated on in detail here.

[0125] Fig.10A schematic diagram of the structure of another prefetch strategy configuration device provided by an exemplary embodiment of the present application. Applied to a virtualization instance created by a virtualization manager in a physical machine, at least one physical processor of the physical machine includes a hardware prefetcher and a prefetch register for prefetching control of the hardware prefetcher. Fig.10 As shown, the device comprises:

[0126] The parameter acquisition module 1001 is used to respond to the prefetch strategy configuration operation and acquire the target prefetch strategy parameters configured for the prefetch register;

[0127] The trap module 1002 is used to indicate the ability of the virtualized instance to trap to the virtualization manager when configuring the target prefetch policy parameters for the prefetch registers based on the configuration of the virtualization manager, and to trap to the virtualization manager so that the virtualization manager can intercept the target prefetch policy parameters and configure them to the prefetch registers in the target physical processor to which the virtualized instance is scheduled, so as to realize the dynamic configuration of the prefetch policy.

[0128] Regarding the embodiments of the present application Fig.10 The detailed implementation and beneficial effects of each module in the illustrated device have been described in detail in the aforementioned embodiments and will not be elaborated on in detail here.

[0129] Fig.11 A schematic diagram of a cache prefetching device provided as an exemplary embodiment of the present application. Applied to a target physical processor in a physical machine, the target physical processor includes a hardware prefetcher and a prefetch register for prefetching control of the hardware prefetcher, and the target prefetching strategy parameter in the prefetch register is based on Figure 4 The steps in the method shown are configured. Fig.11 As shown, the device comprises:

[0130] Parameter acquisition strategy 1101, used to read target prefetch strategy parameters from the prefetch register;

[0131] The prefetch operation execution module 1102 is used to execute data and / or instruction prefetch operations based on target prefetch policy parameters during the running of the scheduled virtualized instance.

[0132] Regarding the embodiments of the present application Fig.11 The detailed implementation and beneficial effects of each module in the illustrated device have been described in detail in the aforementioned embodiments and will not be elaborated on in detail here.

[0133] Fig.12A schematic diagram of the structure of a processor provided for an exemplary embodiment of the present application. The processor is responsible for running a virtualized instance, and includes a hardware prefetcher 1201 and a prefetch register 1202 for prefetching the hardware prefetcher. The target prefetch strategy parameter in the prefetch register is based on Figure 4 The steps in the method shown are configured; the processor is used to execute the computer program to implement Figure 7 The steps in the cache prefetching method are shown.

[0134] Regarding the embodiments of the present application Fig.12 The detailed implementation and beneficial effects of each module shown have been described in detail in the aforementioned embodiments and will not be elaborated here.

[0135] Further, if Fig.12 As shown, the electronic device also includes: a memory 1201b, a communication component 1201c, a display 1201d, a power supply component 1201e and other components. Fig.12 Only some components are shown schematically, which does not mean that the electronic device only includes Fig.12 In addition, Fig.12 The components in the dashed box are optional components, not mandatory components, and the specific components depend on the product form of the electronic device. The electronic device of this embodiment can be implemented as a terminal device such as a desktop computer, a laptop computer, a smart phone, or an IOT device, or a server device such as a conventional server, a cloud server, or a server array. If the electronic device of this embodiment is implemented as a terminal device such as a desktop computer, a laptop computer, a smart phone, etc., it can include Figure 6 If the electronic device of this embodiment is implemented as a server device such as a conventional server, a cloud server or a server array, it may not include Figure 6 Components within the dashed box.

[0136] The above-mentioned memory can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read only memory (EEPROM), erasable programmable read only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disk or optical disk.

[0137] The above-mentioned communication component is configured to facilitate wired or wireless communication between the device where the communication component is located and other devices. The device where the communication component is located can access a wireless network based on a communication standard, such as WiFi, 2G, 3G, 4G / LTE, 5G and other mobile communication networks, or a combination thereof. In an exemplary embodiment, the communication component receives a broadcast signal or broadcast-related information from an external broadcast management system via a broadcast channel. In an exemplary embodiment, the communication component also includes a near field communication (NFC) module to facilitate short-range communication. For example, the NFC module can be based on Radio Frequency Identification (RFID) technology, Infrared Data Association (IrDA) technology, Ultra Wide Band (UWB) technology, Bluetooth (BT) technology and other technologies.

[0138] The above-mentioned display includes a screen, and the screen may include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, the screen may be implemented as a touch screen to receive input signals from a user. The touch panel includes one or more touch sensors to sense touch, slide, and gestures on the touch panel. The touch sensor may not only sense the boundary of a touch or slide action, but also detect the duration and pressure associated with the touch or slide operation.

[0139] The power supply assembly provides power to various components of the device where the power supply assembly is located. The power supply assembly may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power to the device where the power supply assembly is located.

[0140] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application may adopt the form of a computer program product implemented in one or more computer-readable storage media (including but not limited to disk storage, compact disc read-only memory (Compact Disc Read-Only Memory, CD-ROM), optical storage, etc.) containing computer-usable program code.

[0141] The present application is described with reference to the flowchart and / or block diagram of the method, device (system) and computer program product according to the embodiment of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, and the combination of the process and / or box in the flowchart and / or block diagram can be realized by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device produce a device for realizing the function specified in one process or multiple processes in the flowchart and / or one box or multiple boxes in the block diagram.

[0142] These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer-readable memory produce a manufactured product including an instruction device that implements the functions specified in one or more processes in the flowchart and / or one or more boxes in the block diagram.

[0143] These computer program instructions may also be loaded onto a computer or other programmable data processing device so that a series of operational steps are executed on the computer or other programmable device to produce a computer-implemented process, whereby the instructions executed on the computer or other programmable device provide steps for implementing the functions specified in one or more processes in the flowchart and / or one or more boxes in the block diagram.

[0144] In a typical configuration, a computing device includes one or more processors (Central Processing Unit, CPU), input / output interface, network interface and memory.

[0145] Memory may include non-permanent storage in a computer-readable medium, random access memory (RAM) and / or non-volatile memory in the form of read-only memory (ROM) or flash RAM. Memory is an example of a computer-readable medium.

[0146] Computer readable media include permanent and non-permanent, removable and non-removable media that can be used to store information by any method or technology. Information can be computer-readable instructions, data structures, program modules or other data. Examples of computer storage media include, but are not limited to, phase-change random access memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, read-only compact disc read-only memory (CD-ROM), digital versatile disc (DVD) or other optical storage, magnetic cassettes, magnetic tape disk storage or other magnetic storage devices or any other non-transmission media that can be used to store information that can be accessed by a computing device. As defined herein, computer readable media does not include temporary computer readable media (transitory media), such as modulated data signals and carrier waves.

[0147] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0148] The above are only embodiments of the present application and are not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included within the scope of the claims of the present application.

Claims

1. A physical machine, characterized in that: The hardware resources of the physical machine include at least one physical processor, and the physical processor includes a hardware prefetcher and a prefetch register for prefetching control of the hardware prefetcher; the software resources of the physical machine include at least a firmware program for reading and writing control of the prefetch register and a virtualization manager for creating and managing virtualization instances; The virtualization manager is also used to apply for prefetch register access rights from the firmware program. When the prefetch register access rights are successfully applied for, the virtualization manager responds to the operation of configuring target prefetch policy parameters for the prefetch register by the virtualization instance, and configures the target prefetch policy parameters to the prefetch register in the target physical processor to which the virtualization instance is scheduled, so as to realize dynamic configuration of the prefetch policy.

2. The physical machine according to claim 1, characterized in that: The physical processor also includes a grant register; The firmware program is used to configure the authorization register in the at least one physical processor to a preset value indicating authorization when the virtualization manager applies for the pre-fetch register access right, so as to open the pre-fetch register access right to the virtualization manager.

3. The physical machine according to claim 1, characterized in that: The virtualization manager, in response to the operation of configuring the target prefetch policy parameters for the prefetch register of the virtualization instance, configures the target prefetch policy parameters to the prefetch register in the target physical processor to which the virtualization instance is scheduled to realize the dynamic configuration of the prefetch policy, specifically for: During initialization, configuring the instructing virtualized instance to trap to the virtualization manager when configuring target prefetch policy parameters for prefetch registers; When a virtualized instance is trapped into the virtualization manager, intercepting a target prefetch strategy parameter configured for a prefetch register of the virtualized instance where the trap occurs; The target prefetch policy parameters are configured to the prefetch register in the target physical processor to which the virtualized instance where the trap occurs is scheduled, so as to realize dynamic configuration of the prefetch policy.

4. The physical machine according to claim 3, characterized in that: The hardware resources of the physical machine also include: an auxiliary authorization control register and a virtualization trap control register; When configuring the virtualization instance to trap into the capability of the virtualization manager when configuring the target prefetch policy parameters for the prefetch register, the virtualization manager is specifically used to: Configuring the auxiliary authorization control register to a preset value indicating that authorization is prohibited, so as to close the virtualization instance's direct access rights to the prefetch register; The virtualization trap register is configured to a preset value indicating that trap is allowed, so as to control the virtualization instance to trap to the virtualization manager when configuring the target prefetch policy parameter for the prefetch register.

5. The physical machine according to claim 3 or 4, characterized in that: The virtualization manager is also used to: When a virtualized instance is trapped to the virtualization manager, preempting a first physical processor currently occupied by the virtualized instance where the trap occurs, and restoring a prefetch register in the first physical processor to a default prefetch policy parameter; The virtualization manager and the virtualization instance where the trap occurs belong to different functional modules in the first virtualization thread, and the first physical processor is scheduled to the first virtualization thread to be responsible for running the different functional modules in the first virtualization thread.

6. A pre-fetch strategy configuration method, characterized in that: A virtualization manager applied to a physical machine for creating and managing virtualization instances, wherein at least one physical processor of the physical machine includes a hardware prefetcher and a prefetch register for prefetching the hardware prefetcher, and the method includes: Apply for prefetch register access permission from a firmware program in the physical machine that is used to perform read and write control on the prefetch register; When the prefetch register access right is successfully applied for, in response to the operation of the virtualization instance configuring the target prefetch policy parameters for the prefetch register, the target prefetch policy parameters are configured to the prefetch register in the target physical processor to which the virtualization instance is scheduled, so as to realize the dynamic configuration of the prefetch policy.

7. The method according to claim 6, characterized in that Apply for the prefetch register access permission from the firmware program in the physical machine that is used to read and write the prefetch register, including: Sending a communication instruction to the firmware program during the initialization process, the communication instruction including an agreed parameter indicating an application for a pre-fetch register access right, so that the firmware program configures the authorization register in the at least one physical processor to a preset value indicating authorization, so as to open the pre-fetch register access right to the virtualization manager; Receive authorization success result information returned by the firmware program.

8. The method according to claim 6, characterized in that In response to the operation of configuring a target prefetch policy parameter for a prefetch register by the virtualization instance, the target prefetch policy parameter is configured to a prefetch register in a target physical processor to which the virtualization instance is scheduled, so as to implement dynamic configuration of the prefetch policy, including: During initialization, configuring the virtualized instance to trap into the virtualization manager when configuring target prefetch policy parameters for prefetch registers; When a virtualized instance is trapped into the virtualization manager, intercepting a target prefetch strategy parameter configured for a prefetch register of the virtualized instance where the trap occurs; The target prefetch policy parameters are configured to the prefetch register in the target physical processor to which the virtualized instance where the trap occurs is scheduled, so as to realize dynamic configuration of the prefetch policy.

9. The method according to claim 8, characterized in that During the initialization process, configuring the virtualized instance to break out to the virtualization manager's capability when configuring the target prefetch policy parameters for the prefetch registers includes: During the initialization process, the auxiliary authorization control register of the physical machine is configured to a preset value indicating that authorization is prohibited, so as to close the direct access right of the virtualized instance to the pre-fetch register; The virtualization trap register of the physical machine is configured to a preset value indicating that trapping is allowed, so as to control the virtualization instance to trap to the virtualization manager when configuring the target prefetch policy parameters for the prefetch register.

10. The method according to claim 8, characterized in that In the event that the virtualization instance is trapped into the virtualization manager, and before intercepting the target prefetching policy parameter, the method further includes: Preempting a first physical processor currently occupied by the virtualized instance in which the trap occurs, and restoring a prefetch register in the first physical processor to a default prefetch policy parameter; The virtualization manager and the virtualization instance where the trap occurs belong to different functional modules in the first virtualization thread, and the first physical processor is scheduled to the first virtualization thread to be responsible for running the different functional modules in the first virtualization thread.

11. The method according to any one of claims 6 to 10, characterized in that: Also includes: When the virtualized instance scheduled to the target physical processor is shut down or destroyed, the prefetch register in the target physical processor is restored to a default prefetch policy parameter.

12. A pre-fetch strategy configuration method, characterized in that: A firmware program applied to a physical machine for reading and writing a prefetch register, wherein the physical machine also includes a virtualization manager for creating and managing virtualization instances, and the method includes: When the virtualization manager applies for a pre-fetch register access right, configuring an authorization register in at least one physical processor to a preset value indicating authorization, so as to open the pre-fetch register access right to the virtualization manager; Return authorization success structure information to the virtualization manager.

13. A pre-fetch strategy configuration method, characterized in that: The method is applied to a virtualization instance created by a virtualization manager in a physical machine, wherein at least one physical processor of the physical machine includes a hardware prefetcher and a prefetch register for prefetching control of the hardware prefetcher; the method includes: In response to the prefetch strategy configuration operation, obtaining target prefetch strategy parameters configured for the prefetch register; Based on the ability of the virtualization instance to trap to the virtualization manager when configuring target prefetch policy parameters for prefetch registers, the virtualization instance is instructed to trap to the virtualization manager so that the virtualization manager can intercept the target prefetch policy parameters and configure them to the prefetch registers in the target physical processor to which the virtualization instance is scheduled, so as to realize dynamic configuration of the prefetch policy.

14. A cache prefetching method, characterized in that: A target physical processor applied to a physical machine, the target physical processor comprising a hardware prefetcher and a prefetch register for prefetching the hardware prefetcher, wherein a target prefetch strategy parameter in the prefetch register is configured according to a method according to any one of claims 1 to 8; the method comprising: Reading a target prefetch strategy parameter from the prefetch register; During the running of the scheduled virtualized instance, data and / or instruction prefetch operations are performed based on the target prefetch policy parameters.

15. A processor, characterized in that: The processor is responsible for running the virtualization instance, and the processor includes a hardware prefetcher and a prefetch register for prefetching control of the hardware prefetcher, and the target prefetch strategy parameters in the prefetch register are configured according to the method described in any one of claims 6-11; the processor is used to execute a computer program to implement the steps in the cache prefetch method described in claim 14.

16. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the processor is caused to implement the steps in the method according to any one of claims 6 to 11 and claims 12 to 14.

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