A method for embedding complex digital layout in analog layout

Abstract

The present invention discloses a method for embedding a complex digital layout in an analog layout, comprising the following steps: planning a TOP top-level layout in a Virtuoso tool, including planning the layout of an analog layout containing an analog module and a digital layout containing a digital module; making a digital layout model corresponding to the digital layout, and exporting the digital layout model as an intermediate file in a format that can be used by the Innovus tool; importing the intermediate file in the Innovus tool, making a digital layout according to the digital layout model obtained after the import, and verifying the digital layout after the production is completed, and generating a GDS file after the verification passes; importing the GDS file in the Virtuoso tool to replace the digital layout; making an analog layout and verifying it; and completing the connection between the digital layout and the analog layout. In the present invention, the GDS file corresponding to the digital layout can be directly plated after being imported back, thereby reducing the occurrence of layout mismatch.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit layout, and in particular to a method for embedding a complex digital layout in an analog layout. Background Art

[0002] Pure digital circuits can achieve automatic layout and routing and timing verification through P&R, but most chips today require a mix of digital and analog to achieve this. For mixed digital and analog circuits, especially for analog chips that require complex digital systems, the connection between digital and analog becomes a time-consuming and tedious project. The defects and shortcomings of the existing digital and analog hybrid layout are as follows:

[0003] Pure digital circuits can be automatically laid out and routed through digital software, analog circuits are completed manually by analog layout engineers, and in mixed digital and analog circuits, the key is to properly integrate the positions and connections of digital and analog modules. Only through manual communication between engineers, the efficiency is low and the error rate is high. When the digital system is complex and the control signal timing requirements are high, it takes a lot of time to communicate and adjust; when performing simulation verification, due to the large amount of data, the server or software itself cannot handle it, most of the calculations are done manually, and when the amount is large, the manual calculation progress is relatively rough and there are errors. Summary of the invention

[0004] The purpose of the present invention is to overcome the deficiencies of the prior art and provide a method for embedding a complex digital layout in an analog layout.

[0005] The objective of the present invention is achieved through the following technical solutions:

[0006] A first aspect of the present invention provides a method for embedding a complex digital layout in an analog layout, comprising the following steps:

[0007] Plan the TOP top-level layout in the Virtuoso tool, including planning the layout of the analog layout containing analog modules and the digital layout containing digital modules;

[0008] Creating a digital layout model corresponding to the digital layout in the Virtuoso tool, and exporting the digital layout model as an intermediate file in a format that can be used by the Innovus tool;

[0009] Import the intermediate file into the Innovus tool, make a digital layout based on the digital layout model obtained after the import, perform verification after the digital layout is completed, and generate a GDS file after the verification passes;

[0010] Importing the GDS file into the Virtuoso tool to replace the digital layout;

[0011] Create and verify the simulation layout in the Virtuoso tool;

[0012] Complete the wiring of digital and analog layouts in the Virtuoso tool.

[0013] Furthermore, the planning includes the layout of an analog layout of analog modules and a digital layout of digital modules, including: planning the shape, size and position of the analog modules, and planning the shape, size and position of the digital modules.

[0014] Furthermore, the planning includes the layout of the analog layout of the analog modules and the digital layout of the digital modules, and also includes: planning the pin positions of the analog modules and planning the pin positions of the digital modules.

[0015] Furthermore, the pin position of the analog module is set at the boundary of the analog module, and the pin position of the digital module is set at the boundary of the digital module.

[0016] Furthermore, the pin positions of the analog module and the pin positions of the digital module overlap and are both arranged at the boundary of the analog module.

[0017] Furthermore, the making of a digital layout model corresponding to the digital layout includes:

[0018] Create an empty total digital module DG_all, and create the digital modules in the planned digital layout in the total digital module DG_all according to their positions;

[0019] Place the pins in the corresponding positions.

[0020] Furthermore, the usable format of the intermediate file for exporting the digital layout model into a format usable by the Innovus tool is lef format.

[0021] Furthermore, the making of the digital layout model corresponding to the digital layout includes: adding a blocking layer to the non-digital module positions and the areas requiring routing in the digital layout model to form a digital layout model with constraints;

[0022] The exporting of the digital layout model into an intermediate file in a format usable by an Innovus tool includes: exporting the digital layout model with constraints into an intermediate file in a format usable by an external Innovus tool, wherein the usable format is a def format.

[0023] Furthermore, the digital layout model with constraints also includes digital standard cells not provided by a fab, including power ground lines, input-output cell structures IO cells, pads PADs, and registers.

[0024] Furthermore, the digital layout verification performed in the Innovus tool includes: timing verification using the STA tool and physical verification using calibre;

[0025] The simulation layout verification performed in the Virtuoso tool includes: DRC verification and LVS verification.

[0026] The beneficial effects of the present invention are:

[0027] In an exemplary embodiment of the present invention, when the TOP layout is completed, there are models of various digital modules and analog modules. After the digital module model is exported, the production of the digital module basically does not require complicated human communication. The GDS file corresponding to the digital layout produced strictly according to the model can be directly imported for platemaking, reducing the occurrence of layout mismatches; and the detailed production of analog modules and digital modules can be carried out simultaneously using Innovus tools and Virtuoso tools respectively, saving a lot of time. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 A flowchart of a method for embedding a complex digital layout in an analog layout provided in an exemplary embodiment of the present invention;

[0029] Figure 2 A schematic diagram of a TOP top-level layout provided in an exemplary embodiment of the present invention;

[0030] Figure 3 A schematic diagram of a digital layout model with constraints provided in an exemplary embodiment of the present invention. DETAILED DESCRIPTION

[0031] The technical solution of the present invention is described clearly and completely below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0032] In the description of the present invention, it should be noted that the directions or positional relationships indicated by "center", "up", "down", "left", "right", "vertical", "horizontal", "inside", "outside", etc. are directions or positional relationships based on the drawings, which are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance.

[0033] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, "installation", "connection" and "connection" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0034] In addition, the technical features involved in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0035] See also Figure 1 , Figure 1 A method for embedding a complex digital layout in an analog layout provided in an exemplary embodiment of the present invention is shown, characterized in that it includes the following steps:

[0036] S1: Plan the TOP top-level layout in the Virtuoso tool, including planning the layout of the analog layout containing analog modules and the digital layout containing digital modules;

[0037] S2: creating a digital layout model corresponding to the digital layout in the Virtuoso tool, and exporting the digital layout model into an intermediate file in a format that can be used by the Innovus tool;

[0038] S3: importing the intermediate file into the Innovus tool, making a digital layout according to the digital layout model obtained after the import, performing verification after the digital layout is completed, and generating a GDS file after passing the verification;

[0039] S4: importing the GDS file into the Virtuoso tool to replace the digital layout;

[0040] S5: Create the simulation layout in the Virtuoso tool and perform verification;

[0041] S6: Complete the connection between the digital layout and the analog layout in the Virtuoso tool.

[0042] Specifically, in this exemplary embodiment, first, step S1 performs TOP top-level layout, including planning the layout of the analog layout containing analog modules and the digital layout containing digital modules, such as Figure 2As shown, DG1~DG3 are digital modules, ANA1~ANA4 are analog modules, and each analog module contains multiple components (such as MOS tubes, resistors R, capacitors C, bipolar junction transistors BIP); when the TOP top-level layout is completed, the placement, shape, size and location of the interconnection interface of the low-level module components are automatically planned, that is, DG1~DG3 and ANA1~ANA4 in the steps. Because the top and low levels are retrieved and planned at the same time, there will be no mismatch. After the TOP top-level layout is completed, there are models of each module, so the TOP wiring and detailed production of the module can be carried out simultaneously, saving a lot of time.

[0043] The module generated in the above steps only contains the device, shape, size and port information, without specific connections inside the module. The final implementation of the digital layout requires the use of Cadence's Innovus tool, which only requires providing the module's shape, size, port information, and constraints (if any) to the digital engineer. The present invention can remove the device from DG1~DG3 generated in the above steps to extract the model diagram DG_mode1~3 containing only the shape, size and port information. Because the digital-analog layout is a different tool, the model DG_mode1~3 needs to be packaged. That is: step S2 produces a digital layout model corresponding to the digital layout, and the digital layout model is Figure 2 The digital layout model is used for subsequent import into the Innovus tool, so in step S2, the digital layout model is simultaneously exported as an intermediate file in a format that can be used by the Innovus tool.

[0044] At this time, in step S3, after the Innovus tool imports the intermediate file, it can make a digital layout. When the Innovus tool completes the digital layout, it verifies it and generates a GDS file after the verification passes. In step S4, the GDS file generated by the Innovus tool is imported into the Virtuoso tool to replace the digital layout, and then back to the TOP top-level layout, it can be seen that the digital module has been inserted into the corresponding position as expected and the GDS file is imported.

[0045] In step S5, the simulation layout is made and verified using the Virtuoso tool. Finally, in step S6, the digital layout and the simulation layout are connected.

[0046] Therefore, in this exemplary embodiment, there are the following advantages:

[0047] (1) In the prior art, the digital layout and the analog layout are completely separate and each provides interconnection ports at most. When they are combined, the module positions need to be determined through manual layout, and the ports are connected through manual routing. Since there is no detailed TOP top-level layout planning in advance, they will collide with each other and only simple interconnection can be achieved. That is, it is necessary to complete the low-level modules (including multiple digital modules and analog modules) first, and then perform TOP top-level layout. It is found that the shape, size and interconnection interface of the module are not suitable for the top level, and the layout cannot meet the requirements. Feedback is then given to the module for further modification; after the modification is completed, the TOP top level is laid out again. The modification method of the TOP top-level layout feedback may not necessarily meet the requirements of the module. This kind of mutual feedback through manual communication is troublesome and the accuracy is not high. The time cost and manpower of module production and TOP manual layout and wiring are relatively high.

[0048] In this exemplary embodiment, the lower-level module devices are automatically planned after the TOP top-level layout is completed. Because the top and lower levels are retrieved and planned at the same time, there will be no mismatch. When the TOP top-level layout is completed, there are models of various digital modules and analog modules. After the digital module model is exported, the production of the digital module basically does not require complex human communication. After the GDS file corresponding to the digital layout produced strictly according to the model is imported back, the layout can be directly assembled, reducing the occurrence of layout mismatch.

[0049] (2) In step S5 and step S3, the detailed production of the analog module and the digital module can be performed simultaneously using the Innovus tool and the Virtuoso tool, respectively, saving a lot of time.

[0050] (3) In the prior art, after the TOP top-level layout is produced (i.e., after step S4 and step S5), the amount of data after digital simulation is mixed is large. When performing simulation verification, the server or software itself cannot handle the large amount of data, so most of the calculations are done manually. When the amount is large, the manual calculation progress is rough and errors may occur.

[0051] In this exemplary embodiment, the digital layout is verified after it is made in the Innovus tool, and the analog layout is verified after it is made in the Virtuoso tool, thereby reducing the problem of large amount of data in mixed testing after digital and analog layout.

[0052] The following content will describe the preferred exemplary embodiments of each step:

[0053] More preferably, in an exemplary embodiment, the planning includes the layout of an analog layout of analog modules and a digital layout of digital modules, including: planning the shape, size and position of the analog modules, and planning the shape, size and position of the digital modules.

[0054] Specifically, in this exemplary embodiment, the TOP top-level layout includes planning for the shape, size and position of the analog module, as well as planning for the shape, size and position of the digital module. After the planning is completed, the placement, shape and size of each low-level device are also realized accordingly.

[0055] More preferably, in an exemplary embodiment, the planning includes the layout of an analog layout of analog modules and a digital layout of digital modules, and further includes: planning pin locations of analog modules, and planning pin locations of digital modules.

[0056] Specifically, in this exemplary embodiment, the TOP top-level layout includes not only the placement, shape, and size of each lower-level device, but also the location of the interconnection interface, i.e., the pins. The following two exemplary embodiments are used to illustrate the pin locations:

[0057] More preferably, in an exemplary embodiment, the pin position of the analog module is set at the boundary of the analog module, and the pin position of the digital module is set at the boundary of the digital module.

[0058] Specifically, in this exemplary embodiment, there are two situations in which the digital model is made in step S1. The first situation is the situation in this exemplary embodiment, where there are no special requirements for the routing between the digital module and the analog module (no special requirements for routing, low requirements for timing, etc., and small load). At this time, the pin position of the analog module is set at the boundary of the analog module, and the pin position of the digital module is set at the boundary of the digital module. At the same time, in this case, the usable format of the intermediate file that exports the digital layout model to a format that can be used by the Innovus tool is the lef format.

[0059] More preferably, in an exemplary embodiment, the pin positions of the analog module and the pin positions of the digital module overlap and are both arranged at the boundary of the analog module.

[0060] Specifically, in this exemplary embodiment, the second situation of making a digital model in step S1 is the situation in this exemplary embodiment, where the routing between the digital module and the analog module has strict timing and load requirements, such as the routing from DG1 to ANA1~ANA4 is particularly long and needs to ensure sufficient drive and consistent timing, etc. At this time, the digital and analog interconnection interfaces need to be close and the routing needs to be consistent. In this case, the pin position needs to be placed at the boundary of ANA1~ANA4, preferably overlapping with the corresponding connected analog module pin, and the routing to the analog can be completed in the digital layout model obtained in step S2, and the drive and timing can be verified in step S3.

[0061] It should be noted that:

[0062] In the prior art, the connection between digital and analog is realized after the digital and analog are mixed. When these connections are simulated and verified, the server or software required for the simulation will be overloaded due to the excessive amount of mixed data, resulting in failure to operate normally.

[0063] In this exemplary embodiment, special processing is performed for the timing and high driving requirements of the digital-analog interconnection lines. As mentioned above, the position of the digital layout interface can be specified so that it overlaps with the interface of the analog layout, so that the interconnection lines can be completed in the digital layout. The interconnection lines and the surrounding environment are also included when verifying the digital layout in step S3. In the subsequent step S5, the simulation verification on the TOP top-level planning only needs to simulate the analog part. In this way, there is no problem of being unable to carry the server or software, and the simulation is simplified, ensuring the reliability of the tape-out data. In other words, when the digital model is created, the port of the digital model is fixed at the boundary of the analog module and overlaps with the analog module, that is, the connection between the digital and analog is specified in the digital layout according to the constraint requirements. When the digital layout is completed with the simulation verification, the simulation verification of the connection between the digital and analog can be completed, avoiding the problem of inability to accurately simulate and verify due to the large amount of mixed data after the digital and analog layout.

[0064] More preferably, in an exemplary embodiment, the making of a digital layout model corresponding to the digital layout includes:

[0065] Create an empty total digital module DG_all, and create the digital modules in the planned digital layout in the total digital module DG_all according to their positions;

[0066] Place the pins in the corresponding positions.

[0067] Specifically, in this exemplary embodiment, an empty module DG_all and DG1 to DG3 are created, and DG1 to DG3 are set as Figure 2 Place the position shown in DG_all. Use prBondary to draw the position of the DG_all border to determine the size, and place the pins at the appropriate position according to the requirements. The position of the pins is selected according to the actual needs.

[0068] More preferably, in an exemplary embodiment, the making of the digital layout model corresponding to the digital layout includes: adding a blocking layer to the non-digital module positions and the areas requiring routing in the digital layout model to form a digital layout model with constraints;

[0069] The exporting of the digital layout model into an intermediate file in a format that can be used by the Innovus tool includes: exporting the digital layout model with constraints into an intermediate file in a format that can be used by an external Innovus tool, and the usable format is def format

[0070] Specifically, in this exemplary embodiment, when the routing between the digital module and the analog module has strict timing and load requirements, such as the routing from DG1 to ANA1~ANA4 is particularly long and needs to ensure sufficient drive and consistent timing, the digital and analog interconnection interfaces need to be close and the routing needs to be consistent. Therefore, constraints need to be added as required, such as generating a blocking layer to specify the routing area, such as Figure 3 As shown in the figure, the white blank area is the routing area, and the black virtual box is the area where the pins are placed.

[0071] It should be noted that for some small and medium-sized enterprises that do not have digital backend engineers, digital layout can only be outsourced. At this time, it is impossible to put the digital circuit in the desired position based on the given port information, and a lot of rework will occur. At the same time, the connection between digital and analog still needs to be manually connected by the engineer responsible for the TOP layout, which is time-consuming and labor-intensive. In this exemplary embodiment, a model with various constraints of the composite band can be provided, and the personnel using the Innovus tool can make the digital layout more accurately after getting it, and basically no complicated human communication is required.

[0072] More preferably, in an exemplary embodiment, the digital layout model with constraints also includes digital standard cells not provided by a fab, including power ground lines, input-output cell structures IO cells, pads PADs, and registers.

[0073] Specifically, in this exemplary embodiment, the digital layout model may also include digital standard units provided by non-fab manufacturers, including power ground lines, input-output unit structures IO cells, pads PADs, and registers. For example, in the case of IO cells and pads, the digital module has input and output signals at the chip layer in addition to interconnections with the analog, that is, external input and output of the chip. In the case of inserting standard digital units not provided by the fab, option options will be added to the digital units for the convenience of chip testing. For example, the input of a digital standard unit can be connected to high or low, and can be switched as needed during fib testing.

[0074] Here, the lef file and the def file are explained: after the digital layout model is completed in step S2, it is only necessary to export the model as an intermediate file, which is specifically an intermediate file of *.def or *.lef in the exemplary embodiment of the present invention. The def file can export all the data in the model, such as the added constraints. Depending on the situation, it is sometimes necessary to add power ground wires, input-output unit structure IO cell, pad PAD, and register. In short, everything in the model can be imported into *.def; while if it is exported as a *.lef file, only port information and shape and size information can be extracted. For example, the "first case, there is no special requirement for the routing between digital and analog" mentioned above does not need to add constraints and other information at this time, and it can be directly exported as *.lef. Exporting def and lef is a file that the digital layout tool Innovus can directly recognize and use.

[0075] More preferably, in an exemplary embodiment, the digital layout verification performed in the Innovus tool includes: using the STA tool for timing verification and calibre for physical verification;

[0076] The simulation layout verification performed in the Virtuoso tool includes: DRC verification and LVS verification.

[0077] Specifically, in this exemplary embodiment, after def or lef is imported into the Innovus tool, it is equivalent to having a main model of the digital layout, and the Innovus tool is used to make the digital layout in detail. Because the previously made digital layout model only provides an area or range according to the requirements, the digital layout engineer will use the Innovus tool to perform detailed layout and routing, and then use the STA tool for timing verification, calibre for physical verification, etc. After all are completed, the Innovus tool can directly export the gds data that can be used by Virtuoso (i.e., the GDS file in step S3).

[0078] At the same time, the simulation layout verification performed in the Virtuoso tool in step S5 includes DRC verification and LVS verification. Occasionally, a small number of errors may occur due to insufficient routing space, which need to be manually modified.

[0079] More preferably, in an exemplary embodiment, in step S5, the GDS file is imported into the Virtuoso tool, and when the digital layout is replaced, it is first determined whether the sizes of each module and the pin positions are consistent. If so, the digital layout is inserted and replaced.

[0080] Specifically, in this exemplary embodiment, in step S5, the GDS file is imported into the working library (the path for storing TOP production and simulation layout production, returning to TOP means returning to the top level), and called in DIG_all to check whether the imported GDS data is consistent with the size and pin position when the model was created before (normally it will be consistent), and then return to the top level of TOP, you can see that the digital module has been inserted into the corresponding position as expected.

[0081] For the connection in step S6, for the first case mentioned above, the TOP layer quickly completes the connection from the digital port to the analog port according to the circuit connection relationship. For the second case mentioned above, when the digital port and the analog port in the digital model coincide, there is no need to execute the automatic connection device (skill script), because the connection to the analog port has been completed in the digital layout, and the Top layer does not need to spend time simulating, because the signal between digital and analog has been simulated in the digital layout by the digital engineer.

[0082] More preferably, in an exemplary embodiment, the method further comprises:

[0083] S7: After completing the chip TOP routine operation and verification, you can tap out.

[0084] In summary, the above exemplary embodiment is aimed at the mixed digital and analog circuit. When laying out the TOP layout, according to the performance and functional requirements, constraints are added where the digital layout needs to be inserted, and then a constraint file that can be recognized by the digital layout production software is generated; after the digital layout is completed, the digital layout is imported into the TOP layout. At this time, the digital circuit is distributed in the position the engineer wants, and then the connection is completed to finally form a complete mixed digital and analog layout. This exemplary embodiment can easily solve the position conflict and connection conflict between the digital layout and the analog layout in the mixed digital and analog circuit, and can allow the digital module to be in a fixed position according to the needs of the TOP designer. DRC and LVS checks were performed before connection, which greatly improved work efficiency and reduced errors in human operation.

[0085] Obviously, the above embodiments are merely examples for clear explanation, and are not intended to limit the implementation methods. For ordinary technicians in the relevant field, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived from them are still within the protection scope of the invention.

Claims

1. A method for embedding a complex digital layout in an analog layout, characterized in that: The following steps are involved: Plan the TOP top-level layout in the Virtuoso tool, including planning the layout of the analog layout containing analog modules and the digital layout containing digital modules; The planning includes the layout of the analog layout of the analog module and the layout of the digital layout of the digital module, including: planning the shape, size, position and pin position of the analog module, and planning the shape, size, position and pin position of the digital module; the pin position of the analog module and the pin position of the digital module overlap and are both set at the boundary of the analog module; A digital layout model corresponding to the digital layout is produced in the Virtuoso tool, and the digital layout model is exported as an intermediate file in a format that can be used by the Innovus tool; the producing of the digital layout model corresponding to the digital layout includes: adding blocking layers to non-digital module positions and areas requiring routing in the digital layout model to form a digital layout model with constraints; the exporting of the digital layout model as an intermediate file in a format that can be used by the Innovus tool includes: exporting the digital layout model with constraints as an intermediate file in a format that can be used by an external Innovus tool, and the usable format is def format; Import the intermediate file into the Innovus tool, make the digital layout according to the digital layout model obtained after importing, verify after the digital layout is made, and generate the GDS file after the verification; wherein, the interconnection lines are made in the digital layout, and the interconnection lines and the surrounding environment are also included in the verification when verifying the digital layout; when the digital module is created, the port of the digital module is fixed at the boundary of the analog module and overlaps with the analog module, that is, the interconnection lines between the digital and analog are specified in the digital layout according to the constraint requirements, and the simulation verification of the connection lines between the digital and analog is completed when the digital layout is simulated and verified; Importing the GDS file into the Virtuoso tool to replace the digital layout; Creating and verifying the simulation layout in the Virtuoso tool; only verifying the simulation layout; Complete the wiring of digital and analog layouts in the Virtuoso tool.

2. The method for embedding a complex digital layout in an analog layout according to any one of claim 1, characterized in that: The step of making a digital layout model corresponding to the digital layout comprises: Create an empty total digital module DG_all, and create the digital modules in the planned digital layout in the total digital module DG_all according to their positions; Place the pins in the corresponding positions.

3. The method for embedding a complex digital layout in an analog layout according to claim 1, characterized in that: The digital layout model with constraints also includes digital standard cells provided by non-fab factories, including power ground lines, input-output cell structures IO cells, pads PADs, and registers.

4. The method for embedding a complex digital layout in an analog layout according to claim 1, characterized in that: Digital layout verification performed in Innovus tools, including: timing verification using STA tools and physical verification using calibre; The simulation layout verification performed in the Virtuoso tool includes: DRC verification and LVS verification.

Images