Automatic design method and device based on embedded chip

Abstract

The invention provides an automatic design method and device based on an embedded chip, and the method comprises the steps: obtaining a circuit signal flow, carrying out the analysis of a system board card function hardware circuit through the circuit signal flow, obtaining a self-test diagnosis circuit, and carrying out the automatic design according to the self-test diagnosis circuit. And generating a control function hardware test program of the embedded chip and a diagnosis program of the embedded chip, wherein the diagnosis program of the embedded chip is used for diagnosing the device to be tested. According to the scheme, the system board card function hardware circuit is analyzed, the self-test diagnosis circuit in the system board card function hardware circuit is extracted, and the control function hardware test program of the embedded chip and the diagnosis program of the embedded chip are automatically generated according to the self-test diagnosis circuit. Automatic development of self-test and self-diagnosis software of a system board card function hardware circuit is realized, so that the development efficiency of the self-test and self-diagnosis software in the system board card function hardware is improved, the design period is shortened, and the development cost is reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of chip testing, and in particular to an automatic design method and device based on embedded chips. Background Art

[0002] The research and development of self-testing and self-diagnosing software based on embedded chips not only depends on the implementation of self-testing and self-diagnosing hardware circuits in the system board functional hardware, but also depends on the experience of developers and their understanding of the functions of embedded chips.

[0003] With the development of integrated circuit technology, the functions on system boards are increasing, and the circuit scale and complexity are increasing, resulting in a significant increase in the difficulty, time and cost of developing self-testing and self-diagnostic software in the functional hardware of system boards, thereby reducing the development efficiency of self-testing and self-diagnostic software in the functional hardware of system boards.

[0004] Therefore, how to improve the development efficiency of self-testing and self-diagnostic software in the functional hardware of the system board is a problem that needs to be solved urgently in this application. Summary of the invention

[0005] In view of this, the present invention provides an automated design method and device based on embedded chips to realize the automation of self-testing and self-diagnostic software development of system board functional hardware circuits, thereby improving the development efficiency of self-testing and self-diagnostic software in system board functional hardware, shortening the design cycle and reducing development costs.

[0006] In order to achieve the above purpose, the disclosed technical solution is as follows:

[0007] The first aspect of the present application discloses an automated design method based on an embedded chip, the method comprising:

[0008] Get circuit signal flow;

[0009] By means of the circuit signal flow, the functional hardware circuit of the system board is analyzed to obtain a self-test diagnosis circuit;

[0010] According to the self-test diagnostic circuit, a control function hardware test program of the embedded chip and a diagnostic program of the embedded chip are generated; the diagnostic program of the embedded chip is used to diagnose the device to be tested.

[0011] Preferably, the process of analyzing the functional hardware circuit of the system board card through the circuit signal flow includes:

[0012] Determine the type of the circuit analysis starting point corresponding to the circuit signal flow;

[0013] If the type of the circuit analysis starting point is a type that uses an embedded chip as the circuit analysis starting point, the functional hardware circuit of the system board is analyzed through the circuit signal flow of the type that uses the embedded chip as the circuit analysis starting point;

[0014] If the circuit analysis starting point type is a type that uses the pins of the device under test as the circuit analysis starting point, the system board functional hardware circuit is analyzed through the circuit signal flow of the type that uses the pins of the device under test as the circuit analysis starting point.

[0015] Preferably, the process of determining the device under test includes:

[0016] If the type of the circuit analysis starting point is a type that uses an embedded chip as the circuit analysis starting point, determining a state control register connected to the output port according to an output port of the embedded chip;

[0017] According to the state control register, determining the analog multiplexer controlled by the state control register;

[0018] According to the analog multiplexer, determining an analog signal node connected to an input end of the analog multiplexer;

[0019] Determine a device connected to the analog signal node, and judge whether the device is a device to be tested;

[0020] If the device is a device under test, the device under test is determined as a device under test of a functional hardware circuit of a system board.

[0021] Preferably, the process of determining the device under test includes:

[0022] If the type of the circuit analysis starting point is a type that uses an embedded chip as the circuit analysis starting point, determining a state control register connected to the output port according to the embedded output port;

[0023] According to the state control register, determining a digital multiplexer controlled by the state control register;

[0024] According to the digital multiplexer, determining a digital signal node connected to an input end of the digital multiplexer;

[0025] Determine a device connected to the digital signal node, and judge whether the device is a device to be tested;

[0026] If the device is a device under test, the device under test is determined as a device under test of a functional hardware circuit of a system board.

[0027] Preferably, the circuit signal flow is used to analyze the system board function hardware circuit to obtain a self-test diagnostic circuit, including:

[0028] A self-test diagnostic circuit for obtaining the level of the analog signal node to be tested through the device to be tested connected to the analog signal node and a self-test diagnostic circuit for sampling and quantizing the level of the analog signal node to be tested;

[0029] A self-test diagnostic circuit for acquiring the logic level of the digital signal node to be tested and a self-test diagnostic circuit for sampling the logic level of the digital signal node to be tested are provided through the device to be tested connected with the digital signal node.

[0030] Preferably, it also includes:

[0031] According to the output terminal of the analog multiplexer, determining an analog-to-digital converter connected to the output terminal of the analog multiplexer;

[0032] Determine the input terminal of the embedded chip to which the output terminal of the analog-to-digital converter is connected;

[0033] According to the output end of the digital multiplexer, the input end of the embedded chip connected to the output end of the digital multiplexer is determined.

[0034] Preferably, it also includes:

[0035] According to the input end of the digital multiplexer, a level shift circuit connected to the output end of the digital multiplexer is determined.

[0036] Preferably, it also includes:

[0037] Determine the output of the amplifier connected to the input of the analog multiplexer and the programmable gain amplifier.

[0038] Preferably, it also includes:

[0039] Obtaining the quantized value of the analog signal node under test corresponding to the pin of the device under test;

[0040] The quantized value of the node to be tested of the analog signal is calculated by using a pre-built diagnostic model to obtain a calculation result;

[0041] Whether the device under test is normal is determined according to the calculation result.

[0042] The second aspect of the present application discloses an automatic design device based on an embedded chip, the device comprising:

[0043] A first acquisition unit, used for acquiring a circuit signal flow;

[0044] An analysis unit, used to analyze the functional hardware circuit of the system board through the circuit signal flow to obtain a self-test diagnosis circuit;

[0045] The generating unit is used to generate a control function hardware test program of the embedded chip and a diagnostic program of the embedded chip according to the self-test diagnostic circuit; the diagnostic program of the embedded chip is used to diagnose the device to be tested.

[0046] Through the above technical scheme, it can be known that the present application discloses an automated design method and device based on embedded chips, which obtains a circuit signal flow, analyzes the system board function hardware circuit through the circuit signal flow, obtains a self-test diagnostic circuit, generates a control function hardware test program of the embedded chip and a diagnostic program of the embedded chip according to the self-test diagnostic circuit, and the diagnostic program of the embedded chip is used to diagnose the device under test. Through the above scheme, there is no need to rely on the experience of the developer, only the system board function hardware circuit needs to be analyzed, the self-test diagnostic circuit therein is extracted, and the control function hardware test program of the embedded chip and the diagnostic program of the embedded chip are automatically generated according to the self-test diagnostic circuit, so as to realize the automation of the self-test and self-diagnosis software development of the system board function hardware circuit, thereby improving the development efficiency of the self-test and self-diagnosis software in the system board function hardware, shortening the design cycle, and reducing the development cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying creative work.

[0048] Figure 1 A method flow chart of an automated design method based on an embedded chip provided by an embodiment of the present invention;

[0049] Figure 2 A circuit analysis flow chart of an automated design method based on an embedded chip provided by an embodiment of the present invention;

[0050] Figure 3 Another circuit analysis flow chart of an automated design method based on an embedded chip provided by an embodiment of the present invention;

[0051] Figure 4 Another circuit analysis flow chart of an automated design method based on an embedded chip provided by an embodiment of the present invention;

[0052] Figure 5 Another circuit analysis flow chart of an automated design method based on an embedded chip provided by an embodiment of the present invention;

[0053] Figure 6Another circuit analysis flow chart of an automated design method based on an embedded chip provided by an embodiment of the present invention;

[0054] Figure 7 A device structure diagram of an automated design device based on an embedded chip provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0055] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0056] In this application, relational terms such as first and second, etc. are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. The terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of more restrictions, the elements defined by the sentence "comprise one..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0057] The present invention can be used in many general or special computing device environments or configurations, such as personal computers, server computers, handheld or portable devices, tablet devices, multi-processor devices, distributed computing environments including any of the above devices or devices, etc.

[0058] The embodiment of the present invention provides an automated design method based on embedded chips. The method can be applied to a variety of system platforms. The execution subject can be a processor of a computer terminal or various mobile devices. The method flow chart of the method is as follows: Figure 1 As shown, specifically including:

[0059] S101: Acquire circuit signal flow.

[0060] In S101, a circuit signal flow existing in a functional hardware circuit of a board of an automatic analysis system is obtained.

[0061] For each circuit component included in the hardware circuit, each circuit component includes but is not limited to an embedded chip, a state control register, an analog multiplexer / digital multiplexer, multiple analog / digital signal nodes, multiple application devices, an analog-to-digital converter (ADC), an amplifier, and a programmable gain amplifier (PGA).

[0062] S102: Analyze the system board function hardware circuit through the circuit signal flow to obtain a self-test diagnosis circuit.

[0063] In S102, a self-test diagnostic circuit for the level of the analog signal node to be tested and a self-test diagnostic circuit for sampling and quantizing the level of the analog signal node to be tested are obtained through the device to be tested connected through the analog signal node; a self-test diagnostic circuit for the logic level of the digital signal node to be tested and a self-test diagnostic circuit for sampling the logic level of the digital signal node to be tested are obtained through the device to be tested connected through the digital signal node.

[0064] Analyze the system board functional hardware circuit, extract the self-test diagnostic circuit, and automatically generate the embedded chip control function hardware test program and the embedded chip diagnostic program according to the self-test diagnostic circuit to realize the automation of self-test and self-diagnosis software development of the system board functional hardware circuit, thereby improving the development efficiency of the self-test and self-diagnosis software in the system board functional hardware, shortening the design cycle and reducing development costs.

[0065] Specifically, the process of analyzing the functional hardware circuit of the system board through the circuit signal flow to obtain the self-test diagnosis circuit is shown in A1-A3.

[0066] A1: Determine the type of circuit analysis starting point corresponding to the circuit signal flow.

[0067] Automatically analyze the functional hardware circuit of the system board card, using the embedded chip as the starting point to automatically analyze the functional hardware circuit of the system board card based on the signal flow, or using the pins of the device under test as the starting point to automatically analyze the functional hardware circuit of the system board card based on the signal flow, or a combination of the above two.

[0068] It should be noted that the developer needs to preset a netlist including various circuit components and the component logical relationships corresponding to each circuit component, and can determine the starting point of each circuit analysis according to the component logical relationships corresponding to each circuit component.

[0069] Optionally, in the method provided in the embodiment of the present invention, a preset netlist is determined, and each circuit analysis starting point and each specific circuit component in the target hardware circuit are determined based on the netlist. Starting from the circuit analysis starting point, the target hardware circuit is analyzed along the flow direction of the circuit signal flow existing in the target hardware circuit, so as to determine the connection relationship between each circuit component corresponding to each circuit analysis starting point. Among them, the hardware circuit, that is, the target hardware circuit, is pre-designed, and the preset netlist can be called and read in the hardware circuit to determine the various circuit information corresponding to the hardware circuit, such as determining each circuit analysis starting point and each circuit component in the hardware circuit.

[0070] Based on the above, according to the netlist, specific circuit components can be used as the starting point of circuit analysis, such as the pins of the embedded chip and each application device as the starting point of circuit analysis.

[0071] It should be noted that the application device, i.e., the device included in the application circuit, is usually taken as the object to be tested.

[0072] A2: If the type of the circuit analysis starting point is a type that uses an embedded chip as the circuit analysis starting point, the functional hardware circuit of the system board is analyzed through the circuit signal flow of the type that uses the embedded chip as the circuit analysis starting point.

[0073] A3: If the type of circuit analysis starting point is the type that takes the pins of the device under test as the circuit analysis starting point, the functional hardware circuit of the system board is analyzed through the circuit signal flow of the type that takes the pins of the device under test as the circuit analysis starting point.

[0074] Analyzing the functional hardware circuit of the system board means analyzing the content of the functional hardware circuit of the system board, starting from each pin of the embedded chip and / or the component to be tested, and autonomously analyzing the functional hardware circuit of the system board according to the flow direction of the circuit signal flow to determine the circuit to be tested corresponding to the component to be tested, and further, the component to be tested in the circuit to be tested can be determined.

[0075] It should be noted that the connection mentioned in the present invention includes a direct (physical) connection or a connection on a signal flow.

[0076] S103: Generate a control function hardware test program of the embedded chip and a diagnostic program of the embedded chip according to the self-test diagnostic circuit; the diagnostic program of the embedded chip is used to diagnose the device to be tested.

[0077] The process of determining the device under test is shown in B1-B5 and C1-C5.

[0078] B1: If the type of the circuit analysis starting point is a type that uses an embedded chip as the circuit analysis starting point, determine the state control register connected to the output port according to the output port of the embedded chip.

[0079] In B1, according to the output port of the embedded chip, the state control register connected to it is searched, thereby determining the state control register connected to the output port.

[0080] B2: According to the status control register, determine the analog multiplexer controlled by the status control register.

[0081] In B2, the analog multiplexer controlled by the state control register is searched according to the state control register searched.

[0082] B3: According to the analog multiplexer, determine the analog signal node connected to the input end of the analog multiplexer.

[0083] B4: Determine the device connected to the analog signal node and judge whether the device is the device under test.

[0084] In B4, based on the above content, that is, after determining each circuit component included in the hardware circuit, it is necessary to further determine whether each circuit component is a device under test.

[0085] Optionally, in a specific implementation, a technician may prepare a query table for components to be tested in advance, and determine whether the circuit component is the component to be tested by querying whether the circuit component exists in the query table for components to be tested. When the circuit component is the component to be tested, it means that the component to be tested exists in each circuit component, that is, check whether there is any application circuit device in the query table. If so, the application circuit device is the circuit device to be tested, and then execute step S103. If not, the application circuit device is not the circuit device to be tested, and there is no point in continuing to the next step.

[0086] It should be noted that in a hardware circuit, there may be multiple components to be tested (components to be tested are also called devices to be tested).

[0087] B5: If the device is a device under test, the device under test is determined as a device under test of a functional hardware circuit of a system board.

[0088] If the component to be tested exists in each of the circuit components, determining the circuit to be tested corresponding to the component to be tested according to each of the circuit components and the connection relationship between the circuit components;

[0089] Wherein, each component to be tested has a preset diagnosis model. The diagnosis model of the component to be tested is a preset diagnosis model, which can be used as a calculation function for calculation and can be obtained from a device library or a diagnosis model library.

[0090] Optionally, in a specific implementation, if there are one or more components to be tested in each circuit component, after determining the embedded chip and each component to be tested, determine the circuit components corresponding to the embedded chip and each component to be tested and the connection relationship between each circuit component; based on these circuit components and the connection relationship between these circuit components, determine the circuit to be tested corresponding to each embedded chip and each component to be tested.

[0091] Optionally, the process of analyzing the hardware circuit using the embedded chip as the starting point for circuit analysis is shown in (1)-(4):

[0092] (1) According to the output port of the embedded chip, find the state control register connected to the output port;

[0093] (2) according to the output port of the state control register, find the analog multiplexer connected to the output port;

[0094] (3) determining an input port of the analog multiplexer and finding an analog signal node connected to the input port;

[0095] (4) Determine the input port of the analog signal node and find the application circuit device connected to the input port.

[0096] Optionally, the process of analyzing the target hardware circuit using the pins of the device under test as the starting point of the circuit analysis is shown in 1)-4):

[0097] 1) Take the pin of the device under test as the input port and find the digital signal node connected to the output port;

[0098] 2) according to the signal output port of the digital signal node, searching for the digital multiplexer connected to the output port;

[0099] 3) Determine the input port of the digital multiplexer and find the digital signal node connected to the input port;

[0100] 4) Determine the input port of the digital signal node and find the application circuit device connected to the input port.

[0101] C1: According to the output port of the embedded chip, find the status control register to which it is connected.

[0102] C2: Based on the status control register being searched, find the digital multiplexer it controls.

[0103] C3: Based on the digital multiplexer being searched, find the digital signal node connected to its digital signal input terminal.

[0104] C4: Find other devices connected to the digital signal node you are looking for.

[0105] C5: For other devices found, determine whether they are devices to be tested, so as to analyze the devices to be tested in the functional hardware circuit of the system board.

[0106] It should be noted that the connection described in the present invention includes a direct connection or an indirect connection in the signal flow.

[0107] The process of determining whether the device under test is normal is as follows:

[0108] First, the quantized value of the analog signal node to be tested corresponding to the pin of the device to be tested is obtained.

[0109] Then, the quantized value of the node to be tested of the analog signal is calculated by using the pre-built diagnostic model to obtain a calculation result.

[0110] Finally, determine whether the device under test is normal based on the calculation results.

[0111] In the process of automatically analyzing the functional hardware circuit of the system board card with the embedded chip as the starting point (that is, the type of the circuit analysis starting point is the type of circuit analysis starting point with the embedded chip as the starting point), the analog-to-digital converter connected to the output end of the analog multiplexer is determined according to the output end of the analog multiplexer; the input end of the embedded chip connected to the output end of the analog-to-digital converter is determined; and the input end of the embedded chip connected to the output end of the digital multiplexer is determined according to the output end of the digital multiplexer.

[0112] Specifically, based on the output end of the analog multiplexer being searched, the analog-to-digital converter connected thereto is searched, and further the input end of the embedded chip connected to the output end of the analog-to-digital converter is searched; and / or based on the output end of the digital multiplexer being searched, the input end of the embedded chip connected thereto is searched.

[0113] Determine the output of the amplifier connected to the input of the analog multiplexer and the programmable gain amplifier (PDA).

[0114] Optional, see Figure 2 , Figure 2 1 is a flow chart of an automated design method based on an embedded chip provided by an embodiment of the present invention, specifically a circuit analysis flow chart for analyzing the hardware circuit involved in the method. Figure 2 As shown, the various circuit components involved include: an embedded chip, a digital multiplexer, various digital signal nodes (1, 2...n), an application device 1, an analog multiplexer, various analog signal nodes (1, 2...n), an application device 2 and an analog-to-digital converter.

[0115] Based on the above, Figure 2The connection relationships corresponding to the various circuit components include: the output end of the embedded chip is respectively connected to the input end of the digital multiplexer and the analog multiplexer, the input end of the embedded chip is respectively connected to the output end of the digital multiplexer and the analog-to-digital converter, the input end of the analog-to-digital converter is connected to the output end of the analog multiplexer, the input end of the digital multiplexer is respectively connected to the output end of each digital signal node, each input end of each digital signal node is respectively connected to each output pin of the application device 1, the input end of the analog multiplexer is connected to each output end of each analog signal node, and each input end of each analog signal node is connected to each output pin of the application device 2.

[0116] Figure 2 The process may include:

[0117] 1. Send control signal;

[0118] The embedded chip sends a control signal corresponding to the selected digital signal frequency to the digital multiplexer through the state control register.

[0119] 2. Send out digital signal frequency;

[0120] The application device 1 sends each digital signal frequency to each digital signal node, and then transmits each digital signal frequency to the digital multiplexer through each digital signal node. It should be noted that operation 1 can be performed synchronously with the current operation 2.

[0121] 3. Transmit digital signal frequency;

[0122] Each digital signal node (ie, digital signal nodes 1 to n) receives each digital signal frequency sent by the application device 1 and transmits each digital signal frequency to the digital multiplexer.

[0123] 4. Receive digital signals;

[0124] When the digital multiplexer receives the control signal sent by the embedded chip, it selects the digital signal with the maximum transmitted frequency in each digital signal node and sends the digital signal to the embedded chip. Because the digital signal frequencies of multiple digital signal nodes to be tested are different, it is necessary to select the digital signal frequency of the node with the highest signal frequency through the digital multiplexer.

[0125] 5. Send control signals;

[0126] The embedded chip sends a control signal corresponding to the selected digital signal frequency to the analog multiplexer through the state control register.

[0127] 6. Send out analog signal frequency;

[0128] The application device 2 sends each analog signal frequency to each analog signal node, and then transmits each analog signal frequency to the analog multiplexer through each analog signal node. It should be noted that operation 5 can be performed synchronously with the current operation 7.

[0129] 7. Transmit analog signal frequency;

[0130] Each analog signal node (ie, analog signal nodes 1 to n) receives each analog signal frequency sent by the application device 2 and transmits each analog signal frequency to the analog multiplexer.

[0131] 8. Receive maximum analog signal;

[0132] When the analog multiplexer receives the control signal sent by the embedded chip, it selects the analog signal with the maximum frequency from among the analog signal frequencies through each analog signal node, and sends the analog signal to the analog-to-digital converter, which is consistent with operation 4. Because the analog signal frequencies of multiple analog signal nodes to be tested are different, it is necessary to select the analog signal frequency of the node with the highest signal frequency through the analog multiplexer.

[0133] 9. Receive digital signals.

[0134] When the analog-to-digital converter receives the analog signal of the maximum frequency sent by the analog multiplexer, it converts the analog signal into a digital signal and sends the digital signal to the embedded chip.

[0135] It should be noted that, according to the above content, when the embedded chip sends control signals for obtaining digital signals to the digital multiplexer and the analog multiplexer respectively, operation 1 can be performed synchronously with operation 5, and correspondingly, operation 2 can be performed synchronously with operation 6, operation 3 can be performed synchronously with operation 7, and operation 1 can also be performed synchronously with operation 2.

[0136] Optionally, automatically analyzing the hardware circuit with the embedded chip as the starting point also includes: searching for the analog-to-digital converter connected to the output of the analog multiplexer being searched, and further searching for the input of the embedded chip connected to the output of the analog-to-digital converter; and / or searching for the input of the embedded chip connected to the output of the digital multiplexer being searched, based on the output of the digital multiplexer being searched.

[0137] Finding analog signal multiplexers includes finding parallel analog signal multiplexers and / or hierarchical analog signal multiplexers.

[0138] A level shift circuit (LS) connected to an output terminal of the digital multiplexer is determined according to an input terminal of the digital multiplexer.

[0139] Finding digital signal multiplexers includes finding parallel digital signal multiplexers and / or hierarchical digital signal multiplexers.

[0140] Optional, see Figure 3 , Figure 3 1 is a flow chart of an automated design method based on an embedded chip provided by an embodiment of the present invention, specifically another analysis flow chart for analyzing the hardware circuit involved in the method. Figure 3 As shown, the circuit components involved and the corresponding connection relationships of the circuit components can be referred to Figure 2 The contents of the embodiment shown will not be repeated here, but it should be noted that Figure 2 On the basis of Figure 3 Amplifiers are also provided between the analog multiplexer and each analog signal node, that is, the output end of each analog signal node is connected to the input end of each amplifier, and the output end of each amplifier is connected to the input end of the analog multiplexer.

[0141] Likewise, Figure 3 The process can be referred to Figure 2 The corresponding process is Figure 2 On the basis of Figure 3 Amplifiers are also arranged between the analog multiplexer and each analog signal node. Therefore, when each analog signal node transmits each analog signal frequency to the analog multiplexer, each analog signal frequency needs to pass through each amplifier. Each amplifier enhances the intensity and quality corresponding to each analog signal frequency, and then sends each enhanced analog signal frequency to the analog multiplexer, making it easier for the analog multiplexer to select the analog signal with the maximum frequency among the analog signal frequencies.

[0142] Optional, see Figure 4 , Figure 4 1 is a flow chart of an automated design method based on an embedded chip provided by an embodiment of the present invention, specifically another analysis flow chart for analyzing the hardware circuit involved in the method. Figure 4 As shown, the circuit components involved and the corresponding connection relationships of the circuit components can be referred to Figure 2 The contents of the embodiment shown will not be repeated here, but it should be noted that Figure 2 On the basis of Figure 4Each level shift circuit (i.e., LS1 to LSn) is also provided between the digital multiplexer and each analog signal node, that is, the output end of each analog signal node is connected to the input end of each level shift circuit, and the output end of each level shift circuit is connected to the input end of the analog multiplexer, and a gain controllable amplifier (i.e., programmable gain amplifier) ​​is also provided between the analog multiplexer and the analog-to-digital converter, that is, the output end of the analog multiplexer is connected to the input end of the gain controllable amplifier, the output end of the gain controllable amplifier is connected to the input end of the analog-to-digital converter, and the input end of the gain controllable amplifier is connected to the output end of the embedded chip.

[0143] Likewise, Figure 4 The process can be referred to Figure 2 The corresponding process is Figure 2 On the basis of Figure 4 Each level shift circuit is also arranged between the digital multiplexer and each analog signal node. Therefore, when each digital signal node transmits each digital signal frequency to the digital multiplexer, each digital signal frequency needs to pass through each level shift circuit. Each level shift circuit converts the level corresponding to each digital signal frequency, and then sends each digital signal frequency after level conversion to the digital multiplexer; and a gain controllable amplifier is also arranged between the analog multiplexer and the analog-to-digital converter. Therefore, if the embedded chip sends a gain control signal to the gain controllable amplifier, the gain controllable amplifier will receive the analog signal of the maximum frequency selected by the analog multiplexer, and the gain controllable amplifier will amplify the analog signal according to the gain control signal, and then send the amplified gain analog signal to the analog-to-digital converter, convert the gain analog signal into a digital signal, and then send it to the embedded chip.

[0144] Optionally, the system board functional hardware circuit is automatically analyzed with the embedded chip as the starting point, and also includes: searching for an amplifier connected to the output end of the analog signal multiplexer according to the input end; and / or searching for a programmable gain amplifier (gain controllable amplifier) ​​connected to the input end of the analog signal multiplexer according to the output end of the analog signal multiplexer.

[0145] Optionally, the programmable gain amplifier controlled by the status register is searched based on the output terminal of the status register.

[0146] Optionally, automatically analyzing the functional hardware circuit of the system board card with the embedded chip as the starting point also includes: searching, according to the input end of the searched digital signal multiplexer, a level shift circuit (LS) connected to the output end.

[0147] Optionally, the controlled clock circuit is searched according to the output terminal of the state register. The clock circuit may sample a clock signal and provide the clock signal to an analog-to-digital converter.

[0148] Optional, see Figure 5 , Figure 5 1 is a flow chart of an automated design method based on an embedded chip provided by an embodiment of the present invention, specifically another analysis flow chart for analyzing the hardware circuit involved in the method. Figure 5 As shown, the various circuit components involved include: an embedded chip, an analog multiplexer 1, an analog multiplexer 2, an analog multiplexer 3, various analog signal nodes (1, 2...n), an application device 1, an application device 2 and an analog-to-digital converter.

[0149] Based on the above, Figure 5 The connection relationships corresponding to the various circuit components include: the output end of the embedded chip is connected to the input end of the analog multiplexer 1, the analog multiplexer 2 and the analog multiplexer 3 respectively, the input end of the embedded chip is connected to the output end of the analog-to-digital converter, the input end of the analog-to-digital converter is connected to the output end of the analog multiplexer 1, the input end of the analog multiplexer 1 is connected to the output ends of the analog multiplexer 2 and the analog multiplexer 3 respectively, the input end of the analog multiplexer 2 is connected to the output ends of each analog signal node (11, 12...1n), the input end of each analog signal node (11, 12...1n) is connected to each output pin of the application device 1, and accordingly, the input end of the analog multiplexer 3 is connected to each output end of each analog signal node (21, 22...2n), and the input end of each analog signal node (21, 22...2n) is connected to each output pin of the application device 2. It should be noted that the analog multiplexer 2 and the analog multiplexer 3 are parallel analog multiplexers, and the analog multiplexer 1 and the analog multiplexer 2 or the analog multiplexer 3 are analog multiplexers at different levels.

[0150] Likewise, Figure 5 The process can be referred to Figure 2 Part of the process, and Figure 2 The difference between the flowchart is that Figure 5 There is no digital multiplexer but multiple analog multiplexers, that is, both parallel analog multiplexers and analog multiplexers at different levels. Therefore, in Figure 5In the embodiment, the embedded chip needs to send control signals to analog multiplexer 1, analog multiplexer 2 and analog multiplexer 3 at the same time. Analog multiplexer 2 selects analog signal 2 with the maximum frequency from various analog signal frequencies transmitted by various analog signal nodes (11, 12...1n) through the control signal, and sends the analog signal 2 to analog multiplexer 1. Analog multiplexer 3 selects analog signal 3 with the maximum frequency from various analog signal frequencies transmitted by various analog signal nodes (21, 22...2n) through the control signal, and sends the analog signal 3 to analog multiplexer 1. Analog multiplexer 3 selects the analog signal with the maximum frequency between analog signal 2 and analog signal 3 as the selected analog signal, and transmits the selected analog signal to the analog-to-digital converter. After the analog signal is selected by the analog-to-digital converter and converted into a digital signal, the digital signal is sent to the embedded chip.

[0151] Optionally, searching for an analog signal multiplexer includes searching for a parallel analog signal multiplexer and / or a hierarchical analog signal multiplexer.

[0152] Optional, see Figure 6 , Figure 6 1 is a flow chart of an automated design method based on an embedded chip provided by an embodiment of the present invention, specifically another analysis flow chart for analyzing the hardware circuit involved in the method. Figure 6 As shown, the various circuit components involved include: an embedded chip, a digital multiplexer 1, a digital multiplexer 2, a digital multiplexer 3, various digital signal nodes (1, 2...n), an application device 1 and an application device 2.

[0153] Based on the above, Figure 6The connection relationship corresponding to each circuit component includes: the output end of the embedded chip is connected to the input end of the digital multiplexer 1, the digital multiplexer 2 and the digital multiplexer 3 respectively, the input end of the embedded chip is connected to the output end of the digital multiplexer 1, the input end of the digital multiplexer 1 is connected to the output end of the digital multiplexer 2 and the digital multiplexer 3 respectively, the input end of the digital multiplexer 2 is connected to the output end of each digital signal node (11, 12...1n), and each input end of each digital signal node (11, 12...1n) is connected to each output pin of the application device 1. Correspondingly, the input end of the digital multiplexer 3 is connected to each output end of each digital signal node (21, 22...2n), and each input end of each digital signal node (21, 22...2n) is connected to each output pin of the application device 2. Correspondingly, the digital multiplexer 2 and the digital multiplexer 3 are parallel digital multiplexers, and the digital multiplexer 1 and the digital multiplexer 2 or the digital multiplexer 3 are digital multiplexers at different levels.

[0154] Likewise, Figure 6 The process can be referred to Figure 5 Some of the processes will not be repeated here, but it should be noted that Figure 6 and Figure 5 The difference between the flowchart is that Figure 6 There are only respective digital multiplexers that can directly select the digital signal of the maximum frequency and send the digital signal to the embedded chip without passing through an analog-to-digital converter to convert the analog signal into a digital signal.

[0155] Optionally, searching for a digital signal multiplexer includes searching for a parallel digital signal multiplexer and / or a hierarchical digital signal multiplexer.

[0156] It should be noted that the above Figures 2 to 6 In the flowchart, each step of the operation is numbered only to facilitate the distinction between the operations. There is no sequential relationship between the numbering. The specific operation sequence is based on the text description.

[0157] Based on various preset extraction strategies, multiple sub-circuits to be tested are extracted from the circuit to be tested.

[0158] Among them, each extraction strategy can be determined and preset by a preset netlist, and each desired sub-circuit to be tested can be extracted from the circuit to be tested according to each extraction strategy. Before extracting each sub-circuit to be tested, each first component to be tested must be extracted from all circuit components according to each extraction strategy, and the sub-circuit to be tested corresponding to each extraction strategy is determined by extracting these first components to be tested.

[0159] Based on the above content, optionally, the circuit to be tested is a self-test circuit for an analog signal node to be tested, and the sub-circuit to be tested extracted from the self-test circuit includes: (1) a self-test control circuit for obtaining the level of the analog signal node to be tested; and (2) a self-test sampling and quantization path for obtaining the level of the analog signal node to be tested.

[0160] (1) A self-test control circuit for obtaining the level of the node to be tested of the analog signal, including but not limited to:

[0161] Based on the extraction strategy corresponding to the self-test control circuit, it is determined that the first components to be tested corresponding to the self-test circuit include: an embedded chip, a state control register, an analog signal multiplexer and an analog-to-digital converter, etc., and can further include a programmable gain amplifier. By extracting these first components to be tested from various circuit components, the self-test control circuit of the analog signal node level to be tested can be determined.

[0162] (2) A self-test sampling and quantization path for obtaining the level of the node to be tested of the analog signal, including but not limited to:

[0163] Correspondingly, based on the corresponding extraction strategy, the analog signal multiplexer and analog-to-digital converter are extracted from each circuit component. Furthermore, the analog signal amplifier or programmable gain amplifier (PGA) can be extracted. Further, the current detection resistor connected in series on the pin of the device to be tested can be extracted, so as to determine the self-test sampling and quantization path of the analog signal node level to be tested.

[0164] It should be noted that the self-test control circuit for obtaining the level of the node to be tested of the analog signal includes a plurality of state control registers and a plurality of analog signal multiplexers organized in parallel or in a hierarchical manner.

[0165] Optionally, the circuit to be tested is a self-test circuit for a digital signal node to be tested, and the sub-circuit to be tested extracted from the self-test circuit includes: (1) a self-test control circuit for obtaining the logic level of the digital signal node to be tested; and (2) a self-test sampling path for obtaining the logic level of the digital signal node to be tested.

[0166] (1) A self-test control circuit for obtaining the logic level of a node to be tested of a digital signal, including but not limited to:

[0167] Accordingly, based on the corresponding extraction strategy, the embedded chip, the state control register and the digital signal multiplexer are extracted from each circuit component, and the self-test control circuit of the logic level of the digital signal node to be tested can be determined.

[0168] It should be noted that the state control register and the analog-to-digital converter may be circuit components inside the embedded chip.

[0169] (2) A self-test sampling path for obtaining the logic level of a digital signal node to be tested, including but not limited to:

[0170] Accordingly, based on the corresponding extraction strategy, the digital signal multiplexer is extracted from each circuit component, and further, the logic level shift circuit can be extracted to determine the self-test sampling path of the logic level of the digital signal node to be tested.

[0171] It should be noted that the self-test control circuit for obtaining the logic level of the node to be tested of the digital signal includes a plurality of state control registers and a plurality of digital signal multiplexers organized in parallel or in a hierarchical manner.

[0172] A test processing program corresponding to each sub-circuit to be tested is generated.

[0173] Before generating a test processing program corresponding to each sub-circuit to be tested, a technician needs to write a test program code for the specified component to be tested (the component to be tested is the second component to be tested) in each sub-circuit to be tested according to the test expectations, so that the component to be tested can achieve the expected operating effect, and then the sub-circuit to be tested can achieve the expected operating effect.

[0174] Specifically, each test program code implements a different effect, that is, each test program code has different code attributes. Therefore, the second component to be tested that matches any code attribute can be found through the component attributes corresponding to each first component to be tested in the sub-circuit to be tested, and the test program code that matches the second component to be tested can be written to generate a test program corresponding to the sub-circuit to be tested.

[0175] Based on the above content, optionally, a test processing program corresponding to the sub-circuit to be tested is generated, that is, a program for hardware testing of the embedded chip control function is generated, including: (1) generating a control program for a self-test control circuit for obtaining the level of the analog signal node to be tested; (2) generating a reading program for the quantized value of the level of the analog signal node to be tested; and or (3) generating a control program for a self-test control circuit for obtaining the logic level of the digital signal node to be tested; (4) generating a reading program for the logic value of the level of the digital signal node to be tested.

[0176] (1) Generate a control program for a self-test control circuit for obtaining the level of a node to be tested of an analog signal, including but not limited to:

[0177] Determine the test processing program corresponding to its self-test control circuit, that is, the program code for controlling the state value of the analog signal channel selection. After determining that the second component to be tested is the state control register that controls the analog signal multiplexer, write the program code for controlling the state value of the analog signal channel selection into the state control register to generate a control program for the self-test control circuit that obtains the level of the analog signal node to be tested.

[0178] Optionally, generating a control program for a self-test control circuit for acquiring the level of a node to be tested of an analog signal also includes writing a program code for controlling a state value of the gain of a programmable gain amplifier into a turntable register of the programmable gain amplifier.

[0179] Optionally, the code of the control value can be written into the state register of the sampling clock signal of the control clock circuit and the state register of the control programmable gain amplifier. Specifically, the state register of the control clock circuit sampling clock signal determines the sampling frequency according to the signal frequency on the node to be measured, and then determines the state register control value required for dividing or multiplying the input clock signal to generate the required output clock signal to control the sampling circuit in combination with the input signal frequency provided by the clock circuit, thereby determining the written control value, and for the state register controlling the programmable gain amplifier, the amplification factor of the programmable gain amplifier is calculated according to the signal amplitude on the node to be measured and the maximum amplitude of the signal received by the analog signal input end of the analog-to-digital converter, and the amplification factor corresponds to the control value written into the state register controlling the programmable gain amplifier.

[0180] (2) Generate a program for reading the quantized value of the node level of the analog signal to be tested, including but not limited to:

[0181] The number of bytes of the signal between the embedded chip and the analog signal test node read by the reading program is determined according to the number of bits of the analog-to-digital converter used in the path, which can be 1, 2, or 3 bytes.

[0182] (3) Generate a control program for a self-test control circuit for obtaining the logic level of a node to be tested of a digital signal, including but not limited to:

[0183] Correspondingly, when determining the self-test sampling and quantization path corresponding to the level of the analog signal node to be tested, that is, the program code for controlling the state value of the digital signal channel selection, and determining that the second component to be tested is the state control register of the digital signal multiplexer, the program code for controlling the state value of the digital signal channel selection is written to the state control register to generate a reading program for the quantization value of the level of the analog signal node to be tested.

[0184] (4) Generate a program for reading the logic value of the node level of the digital signal to be tested, including but not limited to:

[0185] The reading program reads one or more digital signal node level logic values ​​to be tested at one time. The multiple digital signal node level logic values ​​to be tested can be organized into one or more bytes to be read.

[0186] It should be noted that the program for automatically generating the hardware test of the embedded chip control function also includes generating the code for resetting the relevant status control register.

[0187] It should also be noted that the program for automatically generating hardware tests for embedded chip control functions also includes a time interval generation program, which is used to perform a read operation on the logic level of the digital signal node to be tested at an appropriate time point. The time interval is determined by the aforementioned circuit analysis part based on the signal frequency of the node to be tested according to the Nyquist sampling theorem.

[0188] The circuit to be tested is run using each of the test processing programs to obtain test data corresponding to the circuit to be tested.

[0189] Based on the above content, the data to be tested includes but is not limited to the number of bytes corresponding to each analog signal between the embedded chip and the analog signal node to be tested, the level logic value of the digital signal node to be tested, the quantized value (sequence) of the analog signal node to be tested and multiple quantized values ​​of the digital signal node to be tested, etc.

[0190] It should be noted that the multiple quantized values ​​of the analog signal nodes to be tested are obtained from a time series, that is, the quantized values ​​of the level signals measured at various time points on a specific pin of a specific component to be tested naturally have a sequence relationship on the time axis. The analog signal nodes to be tested here can be one or more analog signal nodes to be tested on the device to be tested.

[0191] The data to be tested is input into the diagnostic model, and the diagnostic model is used to output the diagnostic results corresponding to the component to be tested.

[0192] Optionally, calculation is performed based on the quantized value of the acquired analog signal node under test and the diagnostic model of the component under test, i.e., the quantized value is input into the diagnostic model corresponding to the circuit under test, and the diagnostic model is used to calculate to obtain a diagnostic result corresponding to the component under test corresponding to the circuit under test.

[0193] Optionally, the calculation is performed based on the acquired logic value of the digital signal node to be tested and the diagnostic model of the device to be tested, that is, the calculation is performed based on multiple quantized values ​​(sequences) of the digital signal node to be tested acquired in the time series and the diagnostic model of the device to be tested, and the calculation result is used to determine whether the device to be tested corresponding to the corresponding circuit to be tested is normal. The digital signal node to be tested here can be one or more digital signal nodes to be tested on the device to be tested.

[0194] Optionally, calculation is performed based on the acquired logic value of the digital signal node to be tested and the diagnostic model of the device to be tested, and calculation is performed based on multiple quantized values ​​(sequences) of the digital signal node to be tested acquired in a time series and the diagnostic model of the device to be tested, so as to obtain a diagnostic result corresponding to the component to be tested corresponding to its corresponding circuit to be tested.

[0195] By applying the method provided in the embodiment of the present invention, if there is a component to be tested in each circuit component, the circuit to be tested corresponding to the component to be tested is determined according to the determined connection relationship between each circuit component and each circuit component, and then each sub-circuit to be tested is extracted from the circuit to be tested, and a test processing program corresponding to each sub-circuit to be tested is autonomously generated, the circuit to be tested is run by using the test processing program to obtain each test data, and each test data is calculated by a diagnostic model to determine whether the component to be tested in the circuit to be tested has an abnormality. By using this method, not only can the self-test and self-diagnosis programs of the system be autonomously generated, but also the self-test and self-diagnosis programs can be used to autonomously test whether the component to be tested in the hardware circuit has an abnormality, thereby reducing the test time and test cost.

[0196] In the embodiment of the present application, a circuit signal flow is obtained, and the system board function hardware circuit is analyzed through the circuit signal flow to obtain a self-test diagnostic circuit, and a control function hardware test program of an embedded chip and a diagnostic program of an embedded chip are generated according to the self-test diagnostic circuit, and the diagnostic program of the embedded chip is used to diagnose the device under test. Through the above scheme, there is no need to rely on the experience of developers, and only the system board function hardware circuit needs to be analyzed to extract the self-test diagnostic circuit therein, and the control function hardware test program of the embedded chip and the diagnostic program of the embedded chip are automatically generated according to the self-test diagnostic circuit, so as to realize the automation of self-test and self-diagnosis software development of the system board function hardware circuit, thereby improving the development efficiency of self-test and self-diagnosis software in the system board function hardware, shortening the design cycle, and reducing development costs.

[0197] Further, based on the method provided in the above embodiment, in the method provided in the embodiment of the present invention, the step S101 of determining the circuit components contained in the target hardware circuit (i.e., the hardware circuit of the existing circuit signal) and the connection relationship between the circuit components includes:

[0198] Based on the preset netlist, determine each circuit analysis starting point and each circuit component in the target hardware circuit;

[0199] Starting from each circuit analysis starting point, along the flow direction corresponding to the circuit signal flow, the flow order corresponding to the circuit signal flow flowing through each circuit component in the hardware circuit is determined in turn;

[0200] According to the flow order, the connection relationship between each circuit component corresponding to each circuit analysis starting point is determined.

[0201] Further, based on the method provided in the above embodiment, in the method provided in the embodiment of the present invention, the step of determining whether there is a component to be tested in each of the circuit components mentioned in B4 includes:

[0202] Calling a preset query table of components to be tested;

[0203] Querying whether each circuit component exists in the component-to-be-tested query table;

[0204] If it is found that any circuit component exists in the query table of components to be tested, it is determined that there is a component to be tested in each circuit component.

[0205] Further, on the basis of the method provided in the above embodiment, in the method provided in the embodiment of the present invention, the above-mentioned extraction of multiple sub-circuits to be tested in the circuit to be tested based on the preset extraction strategy includes:

[0206] In the circuit to be tested, extracting each first component to be tested corresponding to each preset extraction strategy;

[0207] Each sub-circuit to be tested is determined according to each first component to be tested.

[0208] Further, based on the method provided in the above embodiment, in the method provided in the embodiment of the present invention, the above-mentioned generating of the test processing program corresponding to each of the sub-circuits to be tested includes:

[0209] Determine each preset test program code and the code attribute corresponding to each test program code;

[0210] Determine, among the first components to be tested included in each of the sub-circuits to be tested, a second component to be tested that matches any test program code;

[0211] A test program code matching each second component to be tested is written into the component to generate a test program corresponding to each sub-circuit to be tested.

[0212] Further, based on the method provided in the above embodiment, in the method provided in the embodiment of the present invention, determining the second component to be tested that matches any of the test program codes includes:

[0213] Determine component properties corresponding to each second component to be tested;

[0214] According to the attributes of each component, in each test program code, a second component to be tested that matches the code attribute corresponding to any program code is searched.

[0215] Based on the above embodiments Figure 1 The disclosed embodiment of the present invention also discloses an automatic design method based on an embedded chip, and the embodiment of the present invention also discloses an automatic design device based on an embedded chip, such as Figure 7 As shown, the automatic design device based on embedded chip includes a first acquisition unit 701 , an analysis unit 702 and a generation unit 703 .

[0216] The first acquisition unit 701 is used to acquire a circuit signal flow.

[0217] The analysis unit 702 is used to analyze the functional hardware circuit of the system board through the circuit signal flow to obtain a self-test diagnosis circuit.

[0218] The generating unit 703 is used to generate a control function hardware test program of the embedded chip and a diagnostic program of the embedded chip according to the self-test diagnostic circuit; the diagnostic program of the embedded chip is used to diagnose the device under test.

[0219] Furthermore, the analysis unit 702 of the process of analyzing the system board function hardware circuit through the circuit signal flow includes:

[0220] The first determination module is used to determine the type of the circuit analysis starting point corresponding to the circuit signal flow.

[0221] The first analysis module is used to analyze the system board function hardware circuit through the circuit signal flow of the type with the embedded chip as the circuit analysis starting point if the type of the circuit analysis starting point is the type with the embedded chip as the circuit analysis starting point.

[0222] The second analysis module is used to analyze the system board functional hardware circuit through the circuit signal flow of the type with the pins of the device under test as the starting point of the circuit analysis if the type of the circuit analysis starting point is the type with the pins of the device under test as the starting point of the circuit analysis.

[0223] Furthermore, the generation unit 703 of the determination process of the device under test includes:

[0224] The second determining module is used to determine a state control register connected to an output port of the embedded chip if the type of the circuit analysis starting point is a type that uses an embedded chip as the circuit analysis starting point.

[0225] The third determination module is used to determine the analog multiplexer controlled by the state control register according to the state control register.

[0226] The fourth determining module is used to determine the analog signal node connected to the input end of the analog multiplexer according to the analog multiplexer.

[0227] The fifth determination module is used to determine the device connected to the analog signal node and judge whether the device is a device to be tested.

[0228] The sixth determination module is used to determine the device under test as a device under test of a system board functional hardware circuit if the device is a device under test.

[0229] Furthermore, the generation unit 703 of the determination process of the device under test includes:

[0230] The seventh determination module is used to determine the state control register connected to the output port according to the embedded output port if the type of the circuit analysis starting point is the type of using the embedded chip as the circuit analysis starting point.

[0231] The eighth determination module is used to determine the digital multiplexer controlled by the state control register according to the state control register.

[0232] The ninth determination module is used to determine the digital signal node connected to the input end of the digital multiplexer according to the digital multiplexer.

[0233] The tenth determination module is used to determine the device connected to the digital signal node and judge whether the device is a device to be tested.

[0234] The eleventh determination module is used to determine the device under test as a device under test of a functional hardware circuit of a system board if the device is a device under test.

[0235] Furthermore, the analysis unit 702 includes:

[0236] The first acquisition module is used to acquire the self-test diagnosis circuit of the analog signal node level and the self-test diagnosis circuit of the sampling quantization of the analog signal node level through the device to be tested connected with the analog signal node.

[0237] The second acquisition module is used to acquire the logic level self-test diagnosis circuit of the digital signal node to be tested and the logic level sampling self-test diagnosis circuit of the digital signal node to be tested through the device to be tested connected to the digital signal node.

[0238] Furthermore, the automated design device based on the embedded chip also includes:

[0239] The first determining unit is used to determine the analog-to-digital converter connected to the output end of the analog multiplexer according to the output end of the analog multiplexer.

[0240] The second determining unit is used to determine the input end of the embedded chip to which the output end of the analog-to-digital converter is connected.

[0241] The third determining unit is used to determine the input terminal of the embedded chip connected to the output terminal of the digital multiplexer according to the output terminal of the digital multiplexer.

[0242] Furthermore, the automated design device based on the embedded chip also includes:

[0243] The fourth determining unit is used to determine the level shift circuit connected to the output end of the digital multiplexer according to the input end of the digital multiplexer.

[0244] Furthermore, the automated design device based on the embedded chip also includes:

[0245] The fifth determining unit is used to determine the output end of the amplifier connected to the input end of the analog multiplexer and the programmable gain amplifier.

[0246] Furthermore, the automated design device based on the embedded chip also includes:

[0247] A second acquisition unit, used to acquire a quantized value of a node under test of an analog signal corresponding to a pin of the device under test;

[0248] A calculation unit, used to calculate the quantized value of the node to be tested of the analog signal through a pre-built diagnostic model to obtain a calculation result;

[0249] The judging unit is used to judge whether the device under test is normal according to the calculation result.

[0250] In the device provided by the embodiment of the present invention, a circuit signal flow is obtained, and the system board function hardware circuit is analyzed through the circuit signal flow to obtain a self-test diagnostic circuit, and a control function hardware test program of an embedded chip and a diagnostic program of an embedded chip are generated according to the self-test diagnostic circuit, and the diagnostic program of the embedded chip is used to diagnose the device under test. Through the above scheme, there is no need to rely on the experience of developers, and only the system board function hardware circuit needs to be analyzed to extract the self-test diagnostic circuit therein, and the control function hardware test program of the embedded chip and the diagnostic program of the embedded chip are automatically generated according to the self-test diagnostic circuit, so as to realize the automation of self-test and self-diagnosis software development of the system board function hardware circuit, thereby improving the development efficiency of self-test and self-diagnosis software in the system board function hardware, shortening the design cycle, and reducing development costs.

[0251] Each embodiment in this specification is described in a progressive manner, and the same or similar parts between the embodiments can refer to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the system or system embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can refer to the partial description of the method embodiment. The system and system embodiments described above are merely schematic, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. Ordinary technicians in this field can understand and implement it without creative work.

[0252] Those skilled in the art may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein may be implemented by electronic hardware, computer software, or a combination of both.

[0253] In order to clearly illustrate the interchangeability of hardware and software, the above description has generally described the components and steps of each example according to function. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the present invention.

[0254] The above description of the disclosed embodiments enables one skilled in the art to implement or use the present invention. Various modifications to these embodiments will be apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An automated design method based on embedded chips, characterized in that: The method comprises: Get circuit signal flow; By means of the circuit signal flow, the functional hardware circuit of the system board is analyzed to obtain a self-test diagnosis circuit; According to the self-test diagnostic circuit, a control function hardware test program of the embedded chip and a diagnostic program of the embedded chip are generated; the diagnostic program of the embedded chip is used to diagnose the device to be tested.

2. The method according to claim 1, characterized in that The process of analyzing the functional hardware circuit of the system board through the circuit signal flow includes: Determine the type of the circuit analysis starting point corresponding to the circuit signal flow; If the type of the circuit analysis starting point is a type that uses an embedded chip as the circuit analysis starting point, the functional hardware circuit of the system board is analyzed through the circuit signal flow of the type that uses the embedded chip as the circuit analysis starting point; If the circuit analysis starting point type is a type that uses the pins of the device under test as the circuit analysis starting point, the system board functional hardware circuit is analyzed through the circuit signal flow of the type that uses the pins of the device under test as the circuit analysis starting point.

3. The method according to claim 2, characterized in that The process of determining the device under test includes: If the type of the circuit analysis starting point is a type that uses an embedded chip as the circuit analysis starting point, determining a state control register connected to the output port according to an output port of the embedded chip; According to the state control register, determining the analog multiplexer controlled by the state control register; According to the analog multiplexer, determining an analog signal node connected to an input end of the analog multiplexer; Determine a device connected to the analog signal node, and judge whether the device is a device to be tested; If the device is a device under test, the device under test is determined as a device under test of a functional hardware circuit of a system board.

4. The method according to claim 2, characterized in that: The process of determining the device under test includes: If the type of the circuit analysis starting point is a type that uses an embedded chip as the circuit analysis starting point, determining a state control register connected to the output port according to the embedded output port; According to the state control register, determining a digital multiplexer controlled by the state control register; According to the digital multiplexer, determining a digital signal node connected to an input end of the digital multiplexer; Determine a device connected to the digital signal node, and judge whether the device is a device to be tested; If the device is a device under test, the device under test is determined as a device under test of a functional hardware circuit of a system board.

5. The method according to claim 1, characterized in that The circuit signal flow is used to analyze the functional hardware circuit of the system board to obtain a self-test diagnostic circuit, including: A self-test diagnostic circuit for obtaining the level of the analog signal node to be tested through the device to be tested connected to the analog signal node and a self-test diagnostic circuit for sampling and quantizing the level of the analog signal node to be tested; A self-test diagnostic circuit for acquiring the logic level of the digital signal node to be tested and a self-test diagnostic circuit for sampling the logic level of the digital signal node to be tested are provided through the device to be tested connected with the digital signal node.

6. The method according to claim 4, characterized in that Also includes: According to the output terminal of the analog multiplexer, determining an analog-to-digital converter connected to the output terminal of the analog multiplexer; Determine the input terminal of the embedded chip to which the output terminal of the analog-to-digital converter is connected; According to the output end of the digital multiplexer, the input end of the embedded chip connected to the output end of the digital multiplexer is determined.

7. The method according to claim 4, characterized in that Also includes: According to the input end of the digital multiplexer, a level shift circuit connected to the output end of the digital multiplexer is determined.

8. The method according to claim 7, characterized in that Also includes: Determine the output of the amplifier connected to the input of the analog multiplexer and the programmable gain amplifier.

9. The method according to claim 1, characterized in that: Also includes: Obtaining the quantized value of the analog signal node under test corresponding to the pin of the device under test; The quantized value of the node to be tested of the analog signal is calculated by using a pre-built diagnostic model to obtain a calculation result; Whether the device under test is normal is determined according to the calculation result.

10. An automated design device based on embedded chips, characterized in that: The device comprises: A first acquisition unit, used for acquiring a circuit signal flow; An analysis unit, used to analyze the functional hardware circuit of the system board through the circuit signal flow to obtain a self-test diagnosis circuit; The generating unit is used to generate a control function hardware test program of the embedded chip and a diagnostic program of the embedded chip according to the self-test diagnostic circuit; the diagnostic program of the embedded chip is used to diagnose the device to be tested.

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