Power supply control system and display device

Abstract

This disclosure relates to the field of display technology, specifically to a power supply control system and a display device. The power supply control system includes a battery management chip and a display driver chip. The display driver chip includes a first pin and a second pin. The first pin is used to output at least a first control signal, and the second pin is used to output at least a second control signal. The first control signal enables the battery management chip to output a first voltage signal to the display driver chip, and the second control signal enables the battery management chip to output a second voltage signal to the display driver chip. The battery management chip includes a third pin and a fourth pin. The third pin is used to receive at least the first control signal, and the fourth pin is used to receive at least the second control signal. At least one first resistor is connected in series between the first pin and the third pin, and / or at least one first resistor is connected in series between the second pin and the fourth pin. The first resistor is disposed adjacent to the display driver chip. This disclosure effectively improves product yield.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to a power supply control system and display device. Background Technology

[0002] Currently, the display module's illumination is primarily powered by the battery management module (PMIC). The voltage output and adjustment of the PMIC are controlled by the display driver chip (DDIC) within the display module. The DDIC controls the PMIC to output the required voltage based on screen and brightness information.

[0003] However, the pins of display driver chips are prone to static electricity, which can cause electrostatic discharge (ESD) damage to the display driver chip and reduce product yield. Summary of the Invention

[0004] In order to solve the above-mentioned technical problems, or at least partially solve the above-mentioned technical problems, this disclosure provides a power supply control system and display device, which effectively improves product yield.

[0005] This disclosure provides a power supply control system, including: a battery management chip and a display driver chip; the display driver chip includes a first pin and a second pin, the first pin being used to output at least a first control signal, and the second pin being used to output at least a second control signal, the first control signal being used to enable the battery management chip to output a first voltage signal to the display driver chip, and the second control signal being used to enable the battery management chip to output a second voltage signal to the display driver chip; the battery management chip includes a third pin and a fourth pin, the third pin being used to receive at least the first control signal, and the fourth pin being used to receive at least the second control signal; at least one first resistor is connected in series between the first pin and the third pin, and / or at least one first resistor is connected in series between the second pin and the fourth pin; the first resistor is disposed adjacent to the display driver chip.

[0006] This disclosure also provides a display device, which includes a power supply control system and a display panel that are electrically connected, wherein the power supply control system is the aforementioned power supply control system.

[0007] The technical solution provided in this disclosure has the following advantages compared with the prior art:

[0008] In the power supply control system provided in this disclosure, at least one first resistor is connected in series between the first pin and the third pin, and / or at least one first resistor is connected in series between the second pin and the fourth pin. The first resistor is arranged adjacent to the display driver chip, that is, the first resistor is arranged on the side closer to the display driver chip. Thus, the static charge generated during electrostatic testing and use can first pass through the first resistor and then through the first pin or the second pin. That is, the static charge first passes through the first resistor. The first resistor plays a current limiting role, thereby reducing the peak value of the instantaneous current, thereby effectively reducing the static charge passing through the display driver chip, effectively reducing the risk of the display driver chip being electrostatically damaged, and improving the product yield.

[0009] Correspondingly, the display device provided in this disclosure also has the above-mentioned technical effects. Attached Figure Description

[0010] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure.

[0011] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0012] Figure 1 This is a schematic diagram of the structure of a power supply control system provided in this disclosure;

[0013] Figure 2 This is a schematic diagram of another power supply control system provided in this disclosure;

[0014] Figure 3 This is a schematic diagram of another power supply control system provided in this disclosure;

[0015] Figure 4 This is a schematic diagram of another power supply control system provided in this disclosure;

[0016] Figure 5 This is a schematic diagram of another power supply control system provided in this disclosure;

[0017] Figure 6 This is a schematic diagram of another power supply control system provided in this disclosure;

[0018] Figure 7 This is a schematic diagram of another power supply control system provided in this disclosure;

[0019] Figure 8This is a circuit diagram of a negative feedback circuit provided in this disclosure;

[0020] Figure 9 This is a schematic diagram of the structure of a display device provided in this disclosure. Detailed Implementation

[0021] To better understand the above-mentioned objectives, features, and advantages of this disclosure, the solutions disclosed herein will be further described below. It should be noted that, unless otherwise specified, the embodiments and features described herein can be combined with each other.

[0022] Numerous specific details are set forth in the following description in order to provide a full understanding of this disclosure, but this disclosure may also be implemented in other ways different from those described herein; obviously, the embodiments in the specification are only some, and not all, of the embodiments of this disclosure.

[0023] Figure 1 This is a schematic diagram of a power supply control system provided in this disclosure, for reference. Figure 1 This embodiment provides a power supply control system, which includes a battery management integrated circuit (PMIC) 10 and a display driver integrated circuit (DDIC) 20.

[0024] The display driver chip 20 includes a first pin Swire1 and a second pin Swire2. The first pin Swire1 is used to output at least a first control signal, and the second pin Swire1 is used to output at least a second control signal. The first control signal Swire1 is used to enable the battery management chip 10 to output a first voltage signal to the display driver chip 20, and the second control signal Swire2 is used to enable the battery management chip 10 to output a second voltage signal to the display driver chip 20.

[0025] The battery management chip 10 includes a third pin Swire3 and a fourth pin Swire4. The third pin Swire1 is used to receive at least a first control signal, and the fourth pin Swire4 is used to receive at least a second control signal.

[0026] At least one first resistor 30 is connected in series between the first pin Swire1 and the third pin Swire3, and / or at least one first resistor 30 is connected in series between the second pin Swire2 and the fourth pin Swire4;

[0027] The first resistor 30 is positioned adjacent to the display driver chip 20.

[0028] Specifically, the power supply control system provided in this embodiment includes a battery management chip 10 and a display driver chip 20. The battery management chip 10 is used to provide the display driver chip 20 with the voltage required for display, so that the display driver chip 20 can provide the display panel with the voltage required for display, thereby enabling the display panel to display.

[0029] The display driver chip 20 includes a first pin Swire1, and the battery management chip 10 includes a third pin Swire3. The first pin Swire1 and the third pin Swire3 are connected. The first pin Swire1 is used to output at least a first control signal, and correspondingly, the third pin Swire1 is used to receive at least the first control signal. The first control signal is an enable signal, which enables the battery management chip 10 to emit a first voltage signal. The first voltage signal can be a positive voltage signal PVDD or a negative voltage signal PVEE. The voltage obtained by the display driver chip 20 based on the first voltage signal is the positive voltage signal and the negative voltage signal of the light-emitting component in the display panel.

[0030] The display driver chip 20 includes a second pin Swire2, and the battery management chip 10 includes a fourth pin Swire4. The second pin Swire2 and the fourth pin Swire4 are connected. The second pin Swire2 is used to output at least a second control signal, and correspondingly, the fourth pin Swire4 is used to receive at least the second control signal. The second control signal is an enable signal, which enables the battery management chip 10 to output a second voltage signal AVDD. The voltage obtained by the display driver chip 20 based on the second voltage signal AVDD is the operating voltage of the display driver chip 20.

[0031] At least one first resistor 30 is connected in series between the first pin Swire1 and the third pin Swire3. The first resistor 30 is arranged adjacent to the display driver chip 20, that is, the first resistor 30 is arranged on the side closer to the display driver chip 20. Thus, the static charge generated during electrostatic testing and use can first pass through the first resistor 30 and then through the first pin Swire1. In other words, the static charge first passes through the first resistor 30. The first resistor 30 plays a current-limiting role, thereby reducing the peak value of the instantaneous current, effectively reducing the static charge passing through the display driver chip 20, effectively reducing the risk of the display driver chip 20 being electrostatically damaged, and improving the product yield.

[0032] Similarly, refer to Figure 2 , Figure 2This is a schematic diagram of another power supply control system provided in this disclosure. At least one first resistor 30 is connected in series between the second pin Swire2 and the fourth pin Swire4. The first resistor 30 is arranged adjacent to the display driver chip 20, that is, the first resistor 30 is arranged on the side closer to the display driver chip 20. Thus, the static charge generated during electrostatic testing and use can first pass through the first resistor 30 and then through the second pin Swire2. That is, the static charge first passes through the first resistor 30. The first resistor 30 plays a current limiting role, thereby reducing the peak value of the instantaneous current, thereby effectively reducing the static charge passing through the display driver chip 20, effectively reducing the risk of the display driver chip 20 being electrostatically damaged, and improving the product yield.

[0033] Similarly, refer to Figure 3 , Figure 3 This is a schematic diagram of another power supply control system provided in this disclosure. At least one first resistor 30 is connected in series between the first pin Swire1 and the third pin Swire3, and at least one first resistor 30 is connected in series between the second pin Swire2 and the fourth pin Swire4. The first resistor 30 is arranged adjacent to the display driver chip 20, that is, the first resistor 30 is arranged on the side closer to the display driver chip 20. Thus, the static charge generated during electrostatic testing and use can first pass through the first resistor 30 and then through the first pin Swire1 and the second pin Swire2. That is, the static charge first passes through the first resistor 30. The first resistor 30 plays a current limiting role, thereby reducing the peak value of the instantaneous current, thereby effectively reducing the static charge passing through the display driver chip 20, effectively reducing the risk of the display driver chip 20 being electrostatically damaged, and improving the product yield.

[0034] It should be noted that, Figure 1 and Figure 3 The example shows a first resistor 30 connected in series between the first pin Swire1 and the third pin Swire3. Figure 2 and Figure 3 The example shows a first resistor 30 connected in series between the second pin Swire2 and the fourth pin Swire4. In other embodiments of this disclosure, two or more first resistors 30 may be connected in series between the first pin Swire1 and the third pin Swire3, and two or more first resistors 30 may be connected in series between the second pin Swire2 and the fourth pin Swire4. These will not be described in detail here.

[0035] Continue to refer to Figure 1In some optional embodiments, the first pin Swire1 and the second pin Swire2 are arranged along the first direction X, and the distance between the first pin Swire1 and the center of the display driver chip 20 is greater than the distance between the second pin Swire2 and the center of the display driver chip 20.

[0036] At least one first resistor 30 is connected in series between the first pin Swire1 and the third pin Swire2.

[0037] Specifically, the first pin Swire1 and the second pin Swire2 are arranged along the first direction X. Along the first direction X, the distance between the first pin Swire1 and the center of the display driver chip 20 is greater than the distance between the second pin Swire2 and the center of the display driver chip 20. That is, along the first direction X, the first pin Swire1 and the second pin Swire2 are located on the same side of the display driver chip 20, and the first pin Swire1 is located on the side of the second pin Swire2 away from the center of the display driver chip 20. That is, relative to the second pin Swire2, the first pin Swire1 is located at the edge of the display driver chip 20, and the first pin Swire1 is more likely to introduce static charge.

[0038] A first resistor 30 is connected in series between the first pin Swire1 and the third pin Swire3. Therefore, the static charge generated during electrostatic testing and use can first pass through the first resistor 30 and then through the first pin Swire1. That is, the static charge first passes through the first resistor 30, which acts as a current limiter, thereby reducing the peak value of the instantaneous current and effectively reducing the static charge introduced by the first pin Swire1. This effectively reduces the static charge passing through the display driver chip 20, effectively reduces the risk of the display driver chip 20 being electrostatically damaged, and improves the product yield.

[0039] Figure 4 This is a schematic diagram of another power supply control system disclosed herein, for reference. Figure 4 In some optional embodiments, the display driver chip 20 further includes a first control circuit 21, a second control circuit 22 and a third control circuit 23. The first control circuit 21 and the third control circuit 23 are both used to generate a first control signal, and the second control circuit 22 is used to generate a second control signal.

[0040] The first pin Swire1 is electrically connected to the first control circuit 21, and the second pin Swire2 is electrically connected to the second control circuit 22 and the third control circuit 23.

[0041] The battery management chip 10 also includes a first identification circuit 11, a second identification circuit 12 and a third identification circuit 13. The first identification circuit 11 is electrically connected to the third pin Swire3 and is used to identify the first control signal generated by the first control circuit 21.

[0042] Both the second identification circuit 12 and the third identification circuit 13 are electrically connected to the fourth pin Swire4. The second identification circuit 12 is used to identify the second control signal generated by the second control circuit 22, and the third identification circuit 13 is used to identify the first control signal generated by the third control circuit 23.

[0043] Specifically, the display driver chip 20 also includes a first control circuit 21, with the first pin Swire1 electrically connected to the first control circuit 21. The first control circuit 21 is used to generate a first control signal. The battery management chip 10 also includes a first identification circuit 11, with the first identification circuit 11 electrically connected to the third pin Swire3. The first identification circuit 11 can identify the first control signal generated by the first control circuit 21, thereby enabling the battery management chip 10 to emit a first voltage signal through the first control signal.

[0044] The display driver chip 20 also includes a second control circuit 22, with the second pin Swire2 electrically connected to the second control circuit 22. The second control circuit 22 is used to generate a second control signal. The battery management chip 10 also includes a second identification circuit 12, with the second identification circuit 12 electrically connected to the fourth pin Swire4. The second identification circuit 12 is used to identify the second control signal generated by the second control circuit 22, thereby enabling the battery management chip 10 to emit a second voltage signal AVDD through the second control signal.

[0045] A first resistor 30 is connected in series between the first pin Swire1 and the third pin Swire3, which effectively reduces the static charge passing through the display driver chip 20, thereby reducing the risk of electrostatic discharge (ESD) damage to the display driver chip 20 and improving product yield. However, the first resistor 30 is susceptible to ESD damage. If the first resistor 30 is damaged by ESD, its resistance will increase, causing the first control signal received by the battery management chip 10 to fail to trigger a logic high level, resulting in the inability to send the first voltage signal and the display panel failing to light up.

[0046] The display driver chip 20 also includes a third control circuit 23. The second pin Swire2 is electrically connected to the third control circuit 23, which generates a first control signal. The battery management chip 10 also includes a third identification circuit 13, which is electrically connected to a fourth pin Swire4. The third identification circuit 13 can identify the first control signal generated by the third control circuit 23, thereby enabling the battery management chip 10 to emit a first voltage signal. Therefore, after the first resistor 30 connected in series between the first pin Swire1 and the third pin Swire3 is electrostatically broken down, the first control signal can be transmitted from the second pin Swire2 to the fourth pin Swire4, thereby enabling the battery management chip 10 to emit a first voltage signal.

[0047] Continue to refer to Figure 4 In some optional embodiments, when the second control signal generated by the second control circuit 22 is a high voltage signal, the second control signal is used to enable the battery management chip 10 to output the second voltage signal AVDD to the display driver chip 20.

[0048] When the first control signal generated by the third control circuit 23 is a pulse signal, the first control signal is used to enable the battery management chip 10 to output a first voltage signal to the display driver chip 20.

[0049] Specifically, after the first resistor 30, which is connected in series between the first pin Swire1 and the third pin Swire3, is electrostatically broken down, the first control signal can be transmitted from the second pin Swire2 to the fourth pin Swire4, thereby enabling the battery management chip 10 to issue a first voltage signal through the first control signal. First, a second control signal is generated by the second control circuit 22. The second control signal is a high-voltage signal and is transmitted to the fourth pin Swire4. After the second identification circuit 12 identifies the second control signal, it enables the battery management chip 10 to output a second voltage signal AVDD to the display driver chip 20. During the time between the second control circuit 22 generating the high-voltage second control signal and the display driver chip 20 receiving the second voltage signal AVDD, the third control circuit 23 generates a first control signal as a pulse signal and transmits it to the fourth pin Swire4. After the third identification circuit 13 identifies the first control signal, it enables the battery management chip 10 to output a first voltage signal to the display driver chip 20. Thus, the battery management chip 10 outputs the first voltage signal without affecting the output of the second voltage signal AVDD.

[0050] It should be noted that this embodiment exemplifies a communication logic in which the second pin Swire2 outputs a first control signal and a second control signal after the first resistor 30 connected in series between the first pin Swire1 and the third pin Swire3 is electrostatically broken down. In other embodiments of this disclosure, the second pin Swire2 can also output the first control signal and the second control signal through other communication logic settings, which will not be elaborated here.

[0051] Optionally, a judgment module can be set between the second pin Swire2 and the receiving pin of the first voltage signal. When the display driver chip 20 does not receive the first voltage signal after outputting the first control signal, it can be determined that the first resistor 30 connected in series between the first pin Swire1 and the third pin Swire3 has been electrostatically broken down, thereby outputting the first control signal and the second control signal through the second pin Swire2. When the display driver chip 20 outputs the first control signal and receives the first voltage signal, the second pin Swire2 outputs the second control signal. Optionally, the judgment module can be an inverter.

[0052] Figure 5 This is a schematic diagram of another power supply control system disclosed herein, for reference. Figure 5 In some alternative embodiments, at least one first resistor 30 is connected in series between the second pin Swire2 and the fourth pin Swire4.

[0053] Specifically, at least one first resistor 30 is connected in series between the second pin Swire2 and the fourth pin Swire4. The first resistor 30 is arranged adjacent to the display driver chip 20, that is, the first resistor 30 is arranged on the side closer to the display driver chip 20. Thus, the static charge generated during electrostatic testing and use can first pass through the first resistor 30 and then through the second pin Swire2. In other words, the static charge first passes through the first resistor 30. The first resistor 30 plays a current-limiting role, thereby reducing the peak value of the instantaneous current, effectively reducing the static charge passing through the display driver chip 20, effectively reducing the risk of the display driver chip 20 being electrostatically damaged, and improving the product yield.

[0054] Figure 6 This is a schematic diagram of another power supply control system disclosed herein, for reference. Figure 6 In some alternative embodiments, the display driver chip 20 further includes a fourth control circuit 24, which is electrically connected to the first pin Swire1 and is used to generate a second control signal.

[0055] The battery management chip 10 also includes a fourth identification circuit 14, which is electrically connected to the third pin Swire3. The fourth identification circuit 14 is used to identify the second control signal generated by the fourth control circuit 24.

[0056] Specifically, the display driver chip 20 also includes a fourth control circuit 24, which is electrically connected to the first pin Swire1. The fourth control circuit 24 is used to generate a second control signal. The battery management chip 10 also includes a fourth identification circuit 14, which is electrically connected to the third pin Swire3. The fourth identification circuit 14 is used to identify the second control signal generated by the fourth control circuit 24, thereby enabling the battery management chip 10 to emit a second voltage signal AVDD through the second control signal. Therefore, after the first resistor 30 connected in series between the second pin Swire2 and the fourth pin Swire4 is electrostatically broken down, the second control signal can be transmitted from the first pin Swire1 to the third pin Swire3, thereby enabling the battery management chip 10 to emit the second voltage signal AVDD through the second control signal.

[0057] Continue to refer to Figure 6 In some optional embodiments, when the first control signal generated by the first control circuit 21 is a pulse signal, the first control signal is used to enable the battery management chip 10 to output a first voltage signal to the display driver chip 20.

[0058] When the second control signal generated by the fourth control circuit 24 is a high voltage signal, the second control signal is used to enable the battery management chip 10 to output the second voltage signal AVDD to the display driver chip 20.

[0059] Specifically, after the first resistor 30, which is connected in series between the second pin Swire2 and the fourth pin Swire4, is electrostatically broken down, a second control signal can be transmitted from the first pin Swire1 to the third pin Swire3, thereby enabling the battery management chip 10 to issue a second voltage signal AVDD through the second control signal. First, a second control signal is generated by the fourth control circuit 24. The second control signal is a high-voltage signal and is transmitted to the third pin Swire3. After the fourth identification circuit 14 identifies the second control signal, it enables the battery management chip 10 to output a second voltage signal AVDD to the display driver chip 20. During the time between the generation of the high-voltage second control signal by the fourth control circuit 24 and the receipt of the second voltage signal AVDD by the display driver chip 20, the first control circuit 21 generates a first control signal as a pulse signal and transmits it to the third pin Swire3. After the first identification circuit 11 identifies the first control signal, it enables the battery management chip 10 to output a first voltage signal to the display driver chip 20. Thus, the battery management chip 10 outputs the second voltage signal AVDD without affecting the output of the first voltage signal.

[0060] It should be noted that this embodiment exemplifies a communication logic in which the first control signal and the second control signal are output from the first pin Swire1 after the first resistor 30 connected in series between the second pin Swire2 and the fourth pin Swire4 is electrostatically broken down. In other embodiments of this disclosure, the output of the first control signal and the second control signal from the first pin Swire1 can also be achieved by setting other communication logic, which will not be described in detail here.

[0061] Optionally, a judgment module can be set between the first pin Swire1 and the receiving pin of the second voltage signal AVDD. If the display driver chip 20 does not receive the second voltage signal AVDD after outputting the second control signal, it can be determined that the first resistor 30 connected in series between the second pin Swire2 and the fourth pin Swire4 has been electrostatically broken down. This allows the first and second control signals to be output through the first pin Swire1. When the display driver chip 20 outputs the second control signal and receives the second voltage signal AVDD, the first pin Swire1 outputs the first control signal. Optionally, the judgment module can be an inverter.

[0062] Figure 7 This is a schematic diagram of another power supply control system disclosed herein, for reference. Figure 7 In some alternative embodiments, the power supply control system further includes a negative feedback circuit 40, which is electrically connected to an external power supply 50.

[0063] A negative feedback circuit 40 is connected between the first pin Swire1 and the third pin Swire3. The negative feedback circuit 40 is used to adjust the voltage value of the first control signal received by the third pin Swire3 through an external power supply 50.

[0064] Specifically, a negative feedback circuit 40 is connected between the first pin Swire1 and the third pin Swire3. The negative feedback circuit 40 is electrically connected to an external power supply 50. The negative feedback circuit 40 is used to adjust the voltage value of the first control signal received by the third pin Swire3 through the external power supply 50. When the first resistor 30 between the first pin Swire1 and the third pin Swire3 is not electrostatically broken down, the voltage value of the first control signal transmitted by the first pin Swire1 can be normally transmitted to the third pin Swire3. After the first resistor 30 between the first pin Swire1 and the third pin Swire3 is electrostatically broken down, the resistance value of the first resistor 30 will increase. At this time, the voltage value of the first control signal received by the third pin Swire3 can be adjusted by the external power supply 50, so that the first control signal received by the battery management chip 10 can normally trigger the logic high level, thereby the battery management chip 10 can send a first voltage signal to the display driver chip 20.

[0065] Figure 8 This is a circuit diagram of a negative feedback circuit provided in this disclosure, for reference. Figure 7 and Figure 8 In some optional embodiments, the negative feedback circuit 40 includes an operational amplifier A, the positive input terminal UP of the operational amplifier A is electrically connected to an external power supply 50, the inverting input terminal UN of the operational amplifier A is electrically connected to the output terminal UO of the operational amplifier A, and the output terminal UO of the operational amplifier A is electrically connected to one end of the first resistor 30 and the first pin Swire1.

[0066] Specifically, the positive input terminal UP of operational amplifier A is electrically connected to the external power supply 50. The voltage of the positive input terminal UP of operational amplifier A remains unchanged. After the first resistor 30 between the first pin Swire1 and the third pin Swire3 is electrostatically broken down, the resistance of the first resistor 30 will increase. The voltage at the end where the first resistor 30 is electrically connected to the first pin Swire1 will increase, that is, the voltage at the output terminal UO of operational amplifier A will increase. Then the voltage at the inverting input terminal UN of operational amplifier A will inevitably increase, causing the voltage at the output terminal UO of operational amplifier A to decrease, thereby achieving the purpose of negative feedback. The first control signal received by the battery management chip 10 can normally trigger the logic high level.

[0067] It should be noted that this embodiment exemplarily shows one circuit structure of the negative feedback circuit 40. In other embodiments of this disclosure, the negative feedback circuit 40 may also adopt other circuit settings, which will not be described in detail here.

[0068] like Figure 9 As shown, Figure 9 This is a schematic diagram of the structure of a display device provided in this disclosure. This embodiment provides a display device including a power supply control system 100 and a display panel 200 electrically connected. The power supply control system 100 is the power supply control system provided in this disclosure embodiment. It is understood that the display device provided in this disclosure embodiment can be any electronic product with display function, including but not limited to the following categories: mobile phones, televisions, laptops, desktop monitors, tablet computers, digital cameras, smart bracelets, smart glasses, vehicle displays, medical devices, industrial control equipment, touch interactive terminals, etc. This disclosure embodiment does not impose any special limitations on these categories.

[0069] The display device provided in this embodiment has the same technical features as the power supply control system provided in the above embodiment, so it can also solve the same technical problems and achieve the same technical effects.

[0070] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0071] The above description is merely a specific embodiment of this disclosure, enabling those skilled in the art to understand or implement it. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this disclosure. Therefore, this disclosure is not to be limited to the embodiments described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A power supply control system, characterized in that, include: Battery management chip and display driver chip; The display driver chip includes a first pin and a second pin. The first pin is used to output at least a first control signal, and the second pin is used to output at least a second control signal. The first control signal is used to enable the battery management chip to output a first voltage signal to the display driver chip, and the second control signal is used to enable the battery management chip to output a second voltage signal to the display driver chip. The battery management chip includes a third pin and a fourth pin, wherein the third pin is used to receive at least the first control signal, and the fourth pin is used to receive at least the second control signal; At least one first resistor is connected in series between the first pin and the third pin; The first resistor is disposed adjacent to the display driver chip; The display driver chip further includes a first control circuit, a second control circuit, and a third control circuit. The first control circuit and the third control circuit are both used to generate the first control signal, and the second control circuit is used to generate the second control signal. The first pin is electrically connected to the first control circuit, and the second pin is electrically connected to the second control circuit and the third control circuit. The battery management chip further includes a first identification circuit, a second identification circuit, and a third identification circuit. The first identification circuit is electrically connected to the third pin and is used to identify the first control signal generated by the first control circuit. Both the second and third identification circuits are electrically connected to the fourth pin. The second identification circuit is used to identify the second control signal generated by the second control circuit, and the third identification circuit is used to identify the first control signal generated by the third control circuit.

2. The power supply control system according to claim 1, characterized in that, The first pin and the second pin are arranged along a first direction, and along the first direction, the distance between the first pin and the center of the display driver chip is greater than the distance between the second pin and the center of the display driver chip.

3. The power supply control system according to claim 2, characterized in that, When the second control signal generated by the second control circuit is a high voltage signal, the second control signal is used to enable the battery management chip to output a second voltage signal to the display driver chip; When the first control signal generated by the third control circuit is a pulse signal, the first control signal is used to enable the battery management chip to output a first voltage signal to the display driver chip.

4. The power supply control system according to claim 2, characterized in that, At least one of the first resistors is connected in series between the second pin and the fourth pin.

5. The power supply control system according to claim 4, characterized in that, The display driver chip further includes a fourth control circuit, which is electrically connected to the first pin and is used to generate the second control signal. The battery management chip also includes a fourth identification circuit, which is electrically connected to the third pin and is used to identify the second control signal generated by the fourth control circuit.

6. The power supply control system according to claim 5, characterized in that, When the first control signal generated by the first control circuit is a pulse signal, the first control signal is used to enable the battery management chip to output a first voltage signal to the display driver chip. When the second control signal generated by the fourth control circuit is a high voltage signal, the second control signal is used to enable the battery management chip to output a second voltage signal to the display driver chip.

7. The power supply control system according to claim 2, characterized in that, The power supply control system also includes a negative feedback circuit, which is electrically connected to an external power source. The negative feedback circuit is connected between the first pin and the third pin. The negative feedback circuit is used to adjust the voltage value of the first control signal received by the third pin through the external power supply.

8. The power supply control system according to claim 7, characterized in that, The negative feedback circuit includes an operational amplifier, the positive input terminal of which is electrically connected to the external power supply, the inverting input terminal of which is electrically connected to the output terminal of which, and the output terminal of which is electrically connected to the end of the first resistor and the first pin.

9. A display device, characterized in that, The display device includes a power supply control system and a display panel that are electrically connected, wherein the power supply control system is the power supply control system according to any one of claims 1-8.

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