A dynamic acceleration driving circuit and method for a high-resolution, high-refresh-rate TFT-LCD display screen

Abstract

This invention discloses a dynamic acceleration drive control circuit for a high-resolution, high-refresh-rate TFT-LCD display. A first-channel load (31) and a second-channel load (32) are controlled by a polarity-switching circuit (2) to alternately display positive and negative polarity voltages. The input of the polarity-switching circuit (2) is connected to a source amplifier circuit (1), and the output of the polarity-switching circuit (2) is connected to the inputs of the first-channel load (31) and the second-channel load (32), respectively. The polarity-switching circuit (2) includes at least a second selector (MUX2) for selecting the voltages of the positive polarity path intermediate nodes EX_P1 and EX_P2 to be sent to the positive source amplifier (11) as feedback voltage, and a fourth selector (MUX4) for selecting the voltages of the negative polarity path intermediate nodes EX_N1 and EX_N2 to be sent to the negative source amplifier (12) as feedback voltage. A corresponding control method is also provided. This invention can quickly drive the display screen and is simple and efficient.

Description

Technical Field

[0001] This invention belongs to the field of chips, specifically the field of display driver chips, particularly for TFT-LCD displays, specifically for high-resolution, high-refresh-rate TFT-LCD displays, and specifically for a dynamic acceleration drive control circuit and control method for high-resolution, high-refresh-rate TFT-LCD displays. Background Technology

[0002] In TFT-LCD screen display driving, the Source circuit typically drives the channel load voltage to the corresponding gamma grayscale voltage. The Source mainly consists of an operational amplifier buffer circuit driving the channel load. Generally, the driving time per row of pixels is relatively long for small to medium resolution screens, and a traditional operational amplifier (OP) can meet the driving speed requirements. However, in driving high-resolution, high-refresh-rate screens, the driving time per row of pixels becomes very short, making it difficult for general operational amplifiers to meet the driving speed requirements. To improve driving speed, the industry commonly uses the following methods:

[0003] (1) Improve the slew rate and bandwidth of the op-amp: In the initial stage of the amplifier (OP) enable, the tail current is increased by 2 to 4 times to improve the slew rate (SR) of the op-amp and speed up the large signal settling time of the amplifier (OP); increase the overall power consumption and area of ​​the amplifier (OP) to improve the small signal bandwidth of the OP and enable the amplifier (OP) to have a shorter small signal settling time.

[0004] (2) Power acceleration drive technology connects a MOS switch to the output terminal of the amplifier (OP) and the power supply terminal. The channel load is directly driven by the switch and the power supply. The principle is to drive the channel load voltage to near the middle gray level by controlling the conduction time of the switch. Then the amplifier (OP) drives the channel load voltage to a stable voltage. This acceleration technology does not consider the gray level voltage difference between the up and down rows, nor does it consider the voltage difference between different channel loads in the same row. It uniformly drives all channel load voltages of the same polarity to the corresponding power supply voltage range, which is actually difficult to achieve a good driving effect.

[0005] Existing technologies have many shortcomings, such as:

[0006] (1) Improve the slew rate and bandwidth of the op-amp: This solution sacrifices area and power consumption to reduce driving time, which not only increases chip cost, but also has limited ability to improve driving speed. Especially in high refresh rate and high resolution display driving applications, the working time of the buffer is limited to a very short time. Even if this high power consumption and large area solution is adopted, it is difficult to meet the demanding requirements of driving speed.

[0007] (2) Power-driven acceleration technology: This approach accelerates the drive by controlling the on-time of the switching transistors. The source circuit consists of thousands of amplifiers (OPs) driving thousands of channel loads. Since the magnitude and direction of the grayscale voltage changes between the upper and lower rows of each channel load are different, the magnitude and direction of the driving voltage between the channel loads vary greatly during the refresh process. The aforementioned technology cannot achieve independent and precise charging and discharging control, resulting in limited acceleration effects. This simplistic and crude acceleration method increases the power consumption of the driver chip, making it difficult to achieve high speeds in some applications with high driving speed requirements. Furthermore, when accelerating the charging and discharging of the channel loads using power supplies and switching transistors, the slope of the channel load voltage changes very rapidly, making it difficult to control the acceleration time and often leading to acceleration drive failure.

[0008] In some high refresh rate and high resolution screen applications, the RC time constant of the channel load is close to the maximum drive time. This means that even if the source drive buffer is perfectly ideal and has a large slew rate and a large bandwidth, it is difficult to drive the channel load voltage to the corresponding grayscale voltage within the maximum drive time.

[0009] In view of the above-mentioned problems in the prior art, this patent proposes a new TFT-LCD display driving technology solution. Summary of the Invention

[0010] To address the technical deficiencies of existing technologies, the present invention aims to provide a dynamic acceleration drive control circuit for a high-resolution, high-refresh-rate TFT-LCD display screen. This circuit is used for driving a high-resolution, high-refresh-rate TFT-LCD display screen. Its key feature is that at least two adjacent first-channel loads 31 and second-channel loads 32 are used as a group of drive units. The first-channel loads 31 and second-channel loads 32 are controlled by a polarity switching circuit 2 to alternately display positive and negative polarity voltages. The input terminal of the polarity switching circuit 2 is connected to a source amplifier circuit 1. The source amplifier circuit 1 includes at least a positive source amplifier 11 and a negative source amplifier 12. The output terminal of circuit 2 is connected to the input terminals of the first channel load 31 and the second channel load 32, respectively. The polarity switching circuit 2 includes at least a second selector MUX2 for selecting the voltages of the positive polarity path intermediate nodes EX_P1 and EX_P2 to be sent to the positive source amplifier 11 as feedback voltage, and a fourth selector MUX4 for selecting the voltages of the negative polarity path intermediate nodes EX_N1 and EX_N2 to be sent to the negative source amplifier 12 as feedback voltage. The source amplifier employs a floating transconductance linear loop controlled Class AB rail-to-rail operational amplifier to improve the bandwidth and driving capability of the operational amplifier. The positive source amplifier 11... The inverting terminal of the positive source amplifier 11 is connected to the first selector MUX1, and the input terminal of the first selector MUX1 is connected to the output terminal of the positive source amplifier 11 and the output terminal of the second selector MUX2, respectively. The inverting terminal of the negative source amplifier 12 is connected to the third selector MUX3, and the input terminal of the third selector MUX3 is connected to the output terminal of the negative source amplifier 12 and the output terminal of the fourth selector MUX4, respectively. The voltage at the intermediate node EX_P1 of the positive polarity path is selected by the first selector MUX1 and the second selector MUX2 and sent to the positive source amplifier 11 as a feedback voltage, forming the positive source amplifier 11. An acceleration drive buffer is formed by selecting the voltage of the negative polarity path intermediate node EX_N1 as the feedback voltage by the third selector MUX3 and the fourth selector MUX4, thus forming an acceleration drive buffer for the negative source amplifier 12. Subsequently, the first selector MUX1 selects the output voltage OUT_P of the positive source amplifier 11 as the feedback voltage, thus forming a stable drive buffer for the positive source amplifier 11. The third selector MUX3 selects the output voltage OUT_N of the negative source amplifier 12 as the feedback voltage, thus forming a stable drive buffer for the negative source amplifier 12.

[0011] Preferably, the polarity switching circuit 2 selects driving paths of opposite polarities for the first channel load 31 and the second channel load 32 through a polarity control signal. When the first channel load 31 is selected as the positive polarity driving path, the second channel load 32 is selected as the negative polarity driving path, and vice versa.

[0012] Preferably, the polarities of the first channel load 31 and the second channel load 32 are periodically switched for display.

[0013] Preferably, the two input terminals of the second selector MUX2 are respectively connected to the two control circuits of the polarity switching control circuit 2, and the output terminal of the second selector MUX2 is used to connect to the positive source amplifier 11; the two input terminals of the fourth selector MUX4 are respectively connected to the two control circuits of the polarity control circuit 2, and the output terminal of the fourth selector MUX4 is used to connect to the negative source amplifier 12.

[0014] Preferably, it further includes at least a zero-adjustment resistor 4, with the input terminal of the polarity switching circuit 2 connected to one end of the zero-adjustment resistor 4, and the other end of the zero-adjustment resistor 4 connected to the output terminal of the positive source amplifier 11 and / or the negative source amplifier 12 circuit.

[0015] Preferably, it further includes at least a first discharge switch CS1 and a second discharge switch CS2. The first discharge switch CS1 is connected to the intermediate nodes EX_P1 and EX_P2 of the positive polarity path, and the second discharge switch CS2 is connected to the intermediate nodes EX_N1 and EX_N2 of the negative polarity path. The other end of the first discharge switch CS1 and the second discharge switch CS2 is grounded to GND for the first channel load 31 and the second channel load 32 to discharge to ground.

[0016] Preferably, each Source amplifier circuit 1 includes at least a PMOS output transistor current sampling and current limiting circuit 15 and an NMOS output transistor current sampling and current limiting circuit 16, used to increase the overshoot voltage sustaining time of the Source during the acceleration drive phase and suppress reverse discharge of the power transistor current. Each output transistor current sampling and current limiting circuit includes at least a sampling transistor, a current limiting transistor, and an enable transistor. The gate of the PMOS output transistor current sampling transistor is connected to the gate of the output PMOS power transistor of the Source amplifier circuit 1, and the drain of the PMOS current limiting transistor is connected to the source of the sampling transistor. The drain of the transistor is connected to the source of the enable transistor, and the drain of the enable transistor is connected to node B inside the OP, which is used to suppress the premature turn-on and reverse discharge of the NMOS output power transistor of the Source amplifier circuit 1; the gate of the NMOS output current sampling transistor is connected to the gate of the output NMOS power transistor of the Source amplifier circuit 1, the drain of the NMOS current limiting transistor is connected to the source of the sampling transistor, the drain of the sampling transistor is connected to the source of the enable transistor, and the drain of the enable transistor is connected to node A inside the OP, which suppresses the premature turn-on and reverse discharge of the PMOS output power transistor of the Source amplifier circuit 1.

[0017] Preferably, the Source amplifier circuit 1 does not have an internal Miller compensation capacitor, and a zero-adjustment resistor 4 is connected in series at the output of the Source amplifier circuit 1 to improve the small-signal bandwidth of the operational amplifier.

[0018] According to another aspect of the present invention, the present invention provides a dynamic acceleration driving method for a high-resolution, high-refresh-rate TFT-LCD display screen, which is used to perform dynamic acceleration driving according to the above-described dynamic acceleration driving control circuit, characterized in that it includes the following steps:

[0019] a. The polarity switching circuit 2 controls the selection of the corresponding voltage polarity drive path for the first channel load 31 and the second channel load 32;

[0020] b. After the Source amplifier circuit 1 is enabled, the positive Source amplifier 11 is configured as a positive Source acceleration drive buffer and the negative Source amplifier 12 is configured as a negative Source acceleration drive buffer by controlling the acceleration drive enable signal, so that the first channel load 31 and the second channel load 32 are quickly driven to near the stable voltage.

[0021] c. When the capacitor voltages on the first channel load 31 and the second channel load 32 are close to or slightly exceed the stable voltage, the positive source amplifier 11 is controlled to form a stable drive buffer for the positive source amplifier 11, and the negative source amplifier 12 is controlled to form a stable drive buffer for the negative source amplifier 12. The stable drive buffers are used to quickly drive the first channel load 31 and the second channel load 32 to the stable voltage.

[0022] Preferably, in step b, the acceleration drive phase is entered, and at least under the action of the large slew rate and persistent overcharge voltage of the acceleration drive buffer, the first channel load 31 and the second channel load 32 are rapidly driven to near the stable voltage.

[0023] Preferably, in step c, the system enters a stable driving phase, where a stable driving buffer, with its large small-signal bandwidth, rapidly drives the first channel load 31 and the second channel load 32 to a stable voltage. The above steps can be referenced. Figure 1 , Figure 2 As shown.

[0024] Preferably, in the first stage, i.e. the acceleration drive stage, the voltage of the positive polarity path intermediate node EX_P1 is selected by the first selector MUX1 and the second selector MUX2 and sent to the positive source amplifier 11 as a feedback voltage to form an acceleration drive buffer for the positive source amplifier 11, and the voltage of the negative polarity path intermediate node EX_N1 is selected by the third selector MUX3 and the fourth selector MUX4 and sent to the negative source amplifier 12 as a feedback voltage to form an acceleration drive buffer for the negative source amplifier 12. In the second stage, i.e. the stable drive stage, the output voltage OUT_P of the positive source amplifier 11 is selected by the first selector MUX1 as a feedback voltage to form a stable drive buffer for the positive source amplifier 11, and the output voltage OUT_N of the negative source amplifier 12 is selected by the third selector MUX3 as a feedback voltage to form a stable drive buffer for the negative source amplifier 12.

[0025] Preferably, during the acceleration drive process, the enable transistors in the output transistor current sampling and current limiting circuit 15 and the output transistor current sampling and current limiting circuit 16 are turned on, and during the stable drive process, the enable transistors in the output transistor current sampling and current limiting circuit 15 and the output transistor current sampling and current limiting circuit 16 are turned off.

[0026] Preferably, in the polarity switching circuit 2, the third switch PS3 and the fourth switch PS4 are open, and the first switch PS1 and the second switch PS2 are closed, selecting a negative polarity drive channel for the first channel load 31. In the polarity switching circuit 2, the seventh switch NS3 and the eighth switch NS4 are open, and the fifth switch NS1 and the sixth switch NS2 are closed, selecting a positive polarity drive channel for the second channel load 32. The EN enable signal of the Source amplifier circuit 1 changes from high to low, turning off the positive Source amplifier 11 and the negative Source amplifier 12, and the output terminals OUT_P and OUT_N of the Source amplifier circuit 1 are both in a high-impedance state. For detailed invention information, please refer to [link / reference]. Figure 2 .

[0027] Preferably, the first discharge switch CS1 and the second discharge switch CS2 of the polarity switching circuit 2 are turned on, and the negative charge on the capacitor of the first channel load 31 is discharged to GND through the eighth switch NS4 and the second discharge switch CS2, and the positive charge on the capacitor of the second channel load 32 is discharged to GND through the fourth switch PS4 and the first discharge switch CS1; after the first channel load 31 and the second channel load 32 have discharged to GND, the first discharge switch CS1 and the second discharge switch CS2 to ground are turned off, completing the discharge of the first channel load 31 and the second channel load 32 to ground. For detailed invention information, please refer to [reference needed]. Figure 2 .

[0028] Preferably, in the polarity switching circuit 2, the first switch PS1 and the second switch PS2 are open, and the output terminal of the positive source amplifier 11 is connected to the first channel load 31 through the zero-adjustment resistor, the first switch PS1, and the second switch PS2. The third switch PS3 and the fourth switch PS4 are closed, selecting a positive polarity drive channel for the first channel load 31. In the polarity switching circuit, the fifth switch NS1 and the sixth switch NS2 are open, and the output terminal of the negative source amplifier 12 is connected to the second channel load 32 through the zero-adjustment resistor, the fifth switch NS1, and the sixth switch NS2. The seventh switch NS3 and the eighth switch NS4 are closed, selecting a negative polarity drive channel for the second channel load 32. Simultaneously, the first selector MUX1 is controlled to connect the OUT_P signal to the inverting input terminal of the positive source amplifier 11, forming a positive drive buffer for the first channel load 31. The third selector MUX3 is controlled to connect the OUT_N signal to the inverting input terminal of the negative source amplifier 12, forming a negative drive buffer for the second channel load 32. For detailed invention information, please refer to [link to invention description]. Figure 2 .

[0029] Preferably, when the Source enable signal EN_OP changes from low to high, the positive Source amplifier 11 and the negative Source amplifier 12 begin to operate. At this time, the positive drive buffer and the negative drive buffer begin to initially drive the first channel load 31 and the second channel load 32. After a clock delay following the Source enable signal EN_OP changing from low to high, the current direction of the power transistors in the output stage of the positive Source amplifier 11 and the negative Source amplifier 12 is basically determined. The acceleration control signal TURBO changes from low to high, controlling the Source to enter the acceleration drive stage. For detailed invention information, please refer to [link / reference needed]. Figure 2 .

[0030] Preferably, the acceleration control signal TURBO changes from low to high level, controlling the first selector MUX1 and the second selector MUX2 to select the positive polarity channel node EX_P1 and connect it to the inverting input terminal of the positive source amplifier 11 to form a positive polarity acceleration drive buffer. The third selector MUX3 and the fourth selector MUX4 select the negative polarity channel node EX_N1 and connect it to the inverting input terminal of the negative source amplifier 12 to form a negative polarity acceleration drive buffer. Both the positive polarity acceleration drive buffer and the negative polarity acceleration drive buffer are in a phase-instantaneous state.

[0031] Preferably, during the acceleration drive phase, when the acceleration control signal TURBO changes from low to high, the power transistor current sampling and current limiting enable EN is turned on inside the positive Source amplifier 11 and negative Source amplifier 12 circuits. Due to the effect of the current limiting transistor, the power consumption of the Source amplifier remains basically unchanged. The sampling transistor current is injected into nodes A and B respectively, suppressing the premature reverse discharge of the power transistor. The overshoot voltage maintenance time generated by the Source acceleration drive buffer will be significantly longer, greatly enhancing the acceleration drive speed of the first channel load 31 and the second channel load 32. By adjusting the pulse width of the acceleration signal TURBO, when the channel load capacitor voltage approaches or slightly exceeds the stable voltage, the acceleration signal TURBO immediately changes from high to low, turning off the current sampling and current limiting circuit enable. The acceleration drive phase of the Source for the first channel load 31 and the second channel load 32 is completed. For detailed invention content, please refer to [reference needed]. Figure 3 , Figure 4 .

[0032] Preferably, after the Source acceleration drive phase is completed, TURBO becomes low, controlling the first selector MUX1 to connect the OUT_P signal to the inverting input of the positive Source amplifier 11, forming a positive polarity stable drive buffer; controlling the third selector MUX3 to connect the OUT_N signal to the inverting input of the negative Source amplifier 12, forming a negative polarity stable drive buffer. At this time, the Source enters the stable drive phase for driving the first channel load 31 and the second channel load 32. During this phase, both the Source positive polarity drive buffer and the Source negative polarity drive buffer are in a phase stable state. Due to the large small-signal bandwidth of zero-capacitance compensation, the stable drive buffer quickly drives the first channel load 31 and the second channel load 32 to a stable voltage, completing the stable drive phase of the Source for the first channel load 31 and the second channel load 32. For detailed invention content, please refer to [reference needed]. Figure 2 .

[0033] Those skilled in the art will understand that steps a to c above, and the corresponding subsequent steps, preferably constitute a complete technical solution for controlling dynamic acceleration drive, namely the control method protected by this invention. Based on the technical solution provided by this invention, the driving speed of the aforementioned channel load is increased by approximately 20% to 50%.

[0034] The source dynamic acceleration drive solution provided by this invention significantly improves the driving speed of the source circuit. Specifically, the solution alters the stability of the buffer by changing the feedback point of the amplifier (OP) circuit. Utilizing the high speed and large overshoot characteristics of the OP in its understability state, the OP output voltage is made significantly higher than the input voltage to accelerate the channel load. Furthermore, the sampling current of the output transistor is used to suppress the turning on of the other output transistor, allowing the overshoot voltage to be maintained for a sufficiently long time. This overcomes the abnormal power leakage caused by the overshoot voltage, achieving independent, precise, and dynamic acceleration drive for each channel load. The implementation of this invention does not increase the cost or size of existing circuits and consumes less power. The method of this invention is simple, cost-effective, and effectively solves the aforementioned technical problems, possessing significant commercial value. Attached Figure Description

[0035] Other features, objects, and advantages of the present invention will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings:

[0036] Figure 1 The circuit diagram illustrates a dynamic acceleration drive control circuit for a high-resolution, high-refresh-rate TFT-LCD display screen, according to a specific embodiment of the present invention.

[0037] Figure 2 A circuit diagram of a dynamic acceleration drive control circuit for a high-resolution, high-refresh-rate TFT-LCD display screen according to a first embodiment of the present invention is shown.

[0038] Figure 3 A circuit diagram of the first channel load 31 in the dynamic acceleration drive control circuit of a high-resolution, high-refresh-rate TFT-LCD display screen according to a first embodiment provided by the present invention is shown.

[0039] Figure 4 A circuit diagram of the Source amplifier circuit 1 in the dynamic acceleration drive control circuit of a high-resolution, high-refresh-rate TFT-LCD display screen according to the first embodiment of the present invention.

[0040] Figure 5 A timing diagram illustrating a control method for a dynamic acceleration drive control circuit applied to a high-resolution, high-refresh-rate TFT-LCD display, according to a specific embodiment of the present invention;

[0041] Figure 6 A timing diagram illustrating a control method for a dynamic acceleration drive control circuit applied to a high-resolution, high-refresh-rate TFT-LCD display, according to a specific embodiment of the present invention;

[0042] Figure 7 A timing diagram illustrating a control method for a dynamic acceleration drive control circuit applied to a high-resolution, high-refresh-rate TFT-LCD display, according to a specific embodiment of the present invention;

[0043] Figure 8 A timing diagram illustrating a control method for a dynamic acceleration drive control circuit applied to a high-resolution, high-refresh-rate TFT-LCD display, showing a specific embodiment of the present invention; and

[0044] Figure 9 A circuit diagram of a dynamic acceleration drive control circuit for a high-resolution, high-refresh-rate TFT-LCD display screen according to a second embodiment of the present invention is shown. Detailed Implementation

[0045] To better illustrate the technical solution of the present invention, the present invention will be further described below with reference to the accompanying drawings.

[0046] refer to Figure 4The illustrated embodiment shows a circuit diagram of the Source amplifier circuit 1. The Source amplifier circuit 1 employs a floating transconductance linear loop controlled Class AB rail-to-rail operational amplifier. To improve the small-signal bandwidth of the operational amplifier, the internal phase compensation capacitor is omitted, and a zero-adjustment resistor 4 is connected in series at the output of the operational amplifier for phase compensation. The Source amplifier circuit 1 drives the channel loads 31 and 32 through two steps: a first stage (acceleration drive stage) and a second stage (stabilization drive stage). The characteristic feature is that in the acceleration drive stage, the Source amplifier circuit 1 is in a phase-instable state, generating a large overshoot voltage during the drive process. This overshoot voltage is used to accelerate the drive of the channel loads. To increase the duration of the overshoot voltage and prevent excessive power consumption due to reverse discharge of the amplifier (OP) output stage caused by excessive overshoot voltage, current sampling and current limiting circuits are added to the two output transistors of the amplifier (OP). In the stabilization drive stage, the Source amplifier circuit 1 is in a phase-stable state. The zero-adjustment resistor compensation method, with its large bandwidth, enables the channel loads to quickly reach a stable voltage.

[0047] Those skilled in the art will understand that, in a preferred embodiment, a zero-adjustment compensation resistor is connected in series at the amplifier (OP) output: this is to allow the buffer during the stable drive phase to obtain a larger bandwidth and sufficient phase margin, and to allow the buffer during the accelerated drive phase to be in an unstable state, generating a larger overcharge voltage.

[0048] The polarity switching circuit selects the correct voltage polarity drive path for the first channel load 31 and the second channel load 32 via a polarity control signal. If one channel load is selected as the positive polarity drive path, the other must be selected as the negative polarity drive path. The polarities of the two channel loads 31 and 32 need to be periodically switched. When the first switch PS1, second switch PS2, fifth switch NS1, and sixth switch NS2 are open, and the third switch PS3, fourth switch PS4, seventh switch NS3, and eighth switch NS4 are closed, the first channel load 31 is selected as the positive polarity drive path. The positive source amplifier circuit 1 provides positive voltage drive to the first channel load 31 through the zero-adjustment resistor 4, the first switch PS1, and the second switch PS2. Simultaneously, the second channel load 32 is selected as the negative polarity drive path. The negative source amplifier circuit 1 provides positive voltage drive to the second channel load 32 through the zero-adjustment resistor, the fifth switch NS1, and the sixth switch NS2. When the third switch PS3, the fourth switch PS4, the seventh switch NS3, and the eighth switch NS4 are open, and the first switch PS1, the second switch PS2, the fifth switch NS1, and the sixth switch NS2 are closed, a negative polarity drive path is selected for the first channel load 31. The negative source amplifier circuit 1 provides a negative voltage drive to the first channel load S1 through the zero-adjustment resistor 4, the seventh switch NS3, and the eighth switch NS4. At the same time, a positive polarity drive path is selected for the second channel load 32. The positive source amplifier circuit 1 provides a positive voltage drive to the second channel load 32 through the zero-adjustment resistor 4, the third switch PS3, and the fourth switch PS4.

[0049] Each Source amplifier circuit 1 includes at least a PMOS output transistor current sampling and current limiting circuit 15 and an NMOS output transistor current sampling and current limiting circuit 16, used to sample the current of the two output power transistors of the Source amplifier circuit 1. The output transistor current sampling and current limiting circuits are used to increase the output voltage slew rate during the acceleration drive phase and suppress abnormal power consumption of the Source amplifier circuit 1. Each output transistor current sampling and current limiting circuit includes at least a sampling transistor, a current limiting transistor, and an enable transistor. The gate of the PMOS output transistor current sampling transistor is connected to the gate of the output PMOS power transistor of the Source amplifier circuit 1. The drain of the PMOS current limiting transistor is connected to the source of the sampling transistor. The drain of the sampling transistor is connected to the source of the enable transistor. The drain of the enable transistor is connected to node B inside the OP (e.g., ...). Figure 2This system suppresses premature power-on discharge of the NMOS output power transistor in Source amplifier circuit 1, increasing the duration of the positive overshoot voltage. The gate of the NMOS output current sampling transistor is connected to the gate of the output NMOS power transistor in Source amplifier circuit 1. The drain of the NMOS current limiting transistor is connected to the source of the sampling transistor. The drain of the sampling transistor is connected to the source of the enable transistor. The drain of the enable transistor is connected to node A inside the OP, thus suppressing premature power-on discharge of the PMOS output power transistor in Source amplifier circuit 1 and increasing the duration of the negative overshoot voltage.

[0050] The Source amplifier circuit 1 does not have an internal Miller compensation capacitor in the OP, and a zero-adjustment resistor is connected in series at the output of the OP to obtain a large output slew rate during the acceleration drive phase and a large bandwidth and sufficient phase margin during the stable drive phase.

[0051] refer to Figures 5 to 8 This diagram illustrates the timing of a control method for a dynamic acceleration drive control circuit applied to a high-resolution, high-refresh-rate TFT-LCD display from different perspectives. Specifically, step a is executed first. The polarity switching circuit 2 controls the selection of the correct voltage polarity drive path for the channel loads 31 and 32. After the Source amplifier circuit 1 is enabled, the acceleration drive enable signal controls the positive Source amplifier circuit 11 to form a positive Source acceleration drive buffer and the negative Source amplifier circuit 12 to form a negative Source acceleration drive buffer, entering the acceleration drive stage. Under the large slew rate and sustained overcharge voltage of the acceleration drive buffer, the first channel load 31 and the second channel load 32 are rapidly driven to near the stable voltage.

[0052] Then, step b is executed. By adjusting the duration of the acceleration drive, when the capacitor voltage on channel loads 31 and 32 approaches or slightly exceeds the stable voltage, the acceleration drive circuit is turned off, the positive source amplifier circuit 11 is controlled to form a stable drive buffer for the positive source, and the negative source amplifier circuit 12 is controlled to form a stable drive buffer for the negative source, thus entering the stable drive stage. Taking advantage of the large small signal bandwidth of the stable drive buffer, the first channel load 31 and the second channel load 32 are quickly driven to the stable voltage.

[0053] The duration of the acceleration drive phase depends on the pulse width of the high-level TURBO control signal. When driving different screens with the Source, the pulse width of the TURBO control signal needs to be adjusted according to the channel load to achieve the optimal drive speed. See the following for details. Figures 5 to 7 The illustrated embodiment.

[0054] Further, refer to Figure 7 The illustrated embodiment further describes the process of a control method applied to a dynamic acceleration drive control circuit for a high-resolution, high-refresh-rate TFT-LCD display. Taking the positive polarity voltage displayed by the first channel load 31 as an example:

[0055] A. In the row porch area, the polarity is reversed in the Source. At this time, the Source amplifier circuit 1 does not work. The polarity reversal circuit selects to open the path between OUT_P and the first channel load 31, and close the path between OUT_P and the second channel load 32. The first selector MUX1 selects OUT_P to send to the inverting terminal VIN of the Source amplifier circuit 1 as the feedback voltage.

[0056] B. Source amplifier circuit 1 is enabled and begins operation. At this time, Source amplifier circuit 1 acts as a normal buffer. After approximately one clock cycle (e.g., 10ns), once the internal current of the amplifier (OP) has stabilized slightly, TURBO becomes 1. The first selector MUX1 and the second selector MUX2 select VOP_EX1 through the acceleration control signal TURBO to provide VIN at the inverting input of Source amplifier circuit 1 as feedback voltage. Simultaneously, the output transistor current sampling and current limiting circuit inside the amplifier (OP) is enabled, and the sampled current is injected into points A and B of the load stage. Figure 2 , 3 This causes the output transistor to open faster, and the buffer output will experience a large voltage overshoot, accelerating the charging and discharging of the channel load.

[0057] C. After a set time, the TURBO signal changes from 1 to 0. At this time, the voltage on the channel load has been accelerated to near the stable voltage. The acceleration circuit is turned off, that is, the first selector MUX1 and the second selector MUX2 select OUT_P to send to the inverting terminal VIN of the Source amplifier circuit 1 as the feedback voltage. At the same time, the current sampling and current limiting circuit of the output tube inside the OP is turned off, and the buffer enters the stable working state. Since this OP compensation method has a very high small signal bandwidth, it can drive the channel load to quickly reach the stable voltage.

[0058] Furthermore, refer to Figure 8 The illustrated embodiment further demonstrates the process of a control method for a dynamic acceleration drive control circuit applied to a high-resolution, high-refresh-rate TFT-LCD display. The diagram shows waveforms of the buffer output and voltage changes on the channel load when the dynamic acceleration function is enabled and disabled. The comparison results show that, compared to ordinary buffer driving, the dynamic acceleration drive technology can shorten the driving time by approximately 30%.

[0059] Furthermore, refer to Figures 1 to 8 The illustrated embodiment discloses a circuit diagram and working principle of a control method for a dynamic acceleration drive control circuit of a high-resolution, high-refresh-rate TFT-LCD display. Specifically, through... Figure 9 Explanation:

[0060] 1. Limitation of slew rate (SR): such as Figure 2 , Figure 9 As shown, a zero-adjustment resistor (SD_RES) is connected in series at the output of the amplifier (OP) to set the dominant pole of the loop at the output of the OP. At the same time, a zero is introduced by the zero-adjustment resistor to compensate for the loop phase. In this way, the slew rate is independent of the internal circuit of the amplifier (OP) and depends only on the charging and discharging speed of the power transistor of the amplifier (OP) output stage to the load and the RC value of the load. However, since the zero-adjustment resistor 4 is connected in series at the output, it will have an adverse effect on SR. This adverse effect will be explained in point 2 below, and a specific solution is also given in point 2 below.

[0061] 2. Dynamic Acceleration Drive: By changing the feedback point of the amplifier (OP), the stability of the buffer is altered. Utilizing the high speed and large overshoot characteristics of the OP in its understability state, the OP output voltage is made significantly higher than the input voltage. Simultaneously, the sampling current of the output transistor suppresses the activation of the other output transistor, allowing the overshoot voltage to be maintained for a sufficiently long time, thus achieving accelerated drive of the channel load. During the acceleration drive phase, the OP feedback voltage is the center node voltage VO_EX1 of the polarity-switching circuit. Under the action of negative feedback regulation, the OP dynamically adjusts the output voltage to be higher or lower, effectively canceling out the adverse effects of the zero-adjustment resistor (SD_RES) and the first-stage polarity-switching transistor on the SR. Therefore, the zero-adjustment resistor has no effect on the SR in acceleration mode. Furthermore, the magnitude and direction of the overshoot voltage generated during acceleration drive are closely related to the magnitude and sign of the differential input voltage of the amplifier (OP). This means that not only can a large slew rate SR be achieved, but also the function of adaptive acceleration charging based on the magnitude of the differential input voltage is realized. That is, in the initial process of Source driving the channel load, the amplifier (OP) will dynamically adjust the output voltage of the amplifier (OP) to generate different degrees of overshoot voltage based on the difference between the remaining voltage on the previous channel load and the grayscale voltage to be displayed on the next line, so as to realize independent, fine and dynamic charging and discharging acceleration drive for each channel load.

[0062] 3. Adjustable Acceleration Drive Time: Since the Source ultimately needs to drive the voltage on the channel load to a stable grayscale voltage, the buffer cannot operate in an unstable state continuously. When the channel load is accelerated to near the stable voltage, the feedback point of the amplifier (OP) is switched to the output terminal (OUT_P) of the OP, allowing the amplifier (OP) to enter a stable operating state. Because the amplifier (OP) uses an internal zero-capacitance + zero-adjustment resistor compensation method, compared to the traditional OP using internal RC Miller compensation, it has a much larger small-signal bandwidth. After the acceleration drive phase ends, the Source amplifier circuit 1 can quickly enter a stable state and drive the channel load to a stable voltage. Since different screen load sizes vary greatly, the required acceleration charging time also differs. In practice, the optimal acceleration time can be determined by digital adjustment for different screen specifications.

[0063] 4. Overshoot Voltage Power Loss Issue: During acceleration drive, Source amplifier circuit 1 is in an unstable state, and the amplifier (OP) output voltage will significantly exceed the input voltage. Under the action of negative feedback, the excess voltage can be easily discharged quickly through reverse regulation, which will cause abnormal power loss and affect the acceleration drive effect. Figure 3 As shown, by sampling the current of the OP output transistors NM_0 and PM_0, the sampled current is introduced into the load stage (nodes A and B) of the other output transistor. Figure 2 As shown, during negative acceleration drive, the suppression power transistor PM0 is turned on, and during positive acceleration drive, the suppression output transistor NM1 is turned on early. This effectively suppresses abnormal current leakage in Source amplifier circuit 1, and the overshoot voltage can be maintained for a longer period of time. In addition, to prevent the power consumption of Source amplifier circuit 1 from increasing due to excessive sampling current during acceleration drive, the maximum sampling current needs to be limited. The maximum current limit should not exceed the tail current of the amplifier (OP).

[0064] Furthermore, combined Figure 1 , Figure 2 , Figure 3 as well as Figure 9 As can be seen from the illustrated embodiment, in the process of source driving channel load, whether the voltage on the channel load reaches a stable voltage depends on the probe5 point on the channel load model at the gate sampling time. Figure 3Whether the voltage (shown) reaches 99% of the stable voltage value. Preferably, the specific technical solution is illustrated by taking the two-channel load drive as an example. The two positive and negative source amplifier circuits are composed of OP, which output positive gray level voltage and negative gray level voltage respectively. After the polarity switching circuit selects the correct polarity, it drives the two channel loads, channel load 1 and channel load 2. Figure 9 The source buffer driver circuit is shown as a single-channel load.

[0065] Part 1: Source amplifier circuit 1, the structure is a floating Class AB rail-to-rail op amp, the special feature is that the internal RC compensation of the OP is cancelled, and the current sampling and maximum sampling current limiting function of the output power tube is added. The sampling current is fed into the load stage corresponding to another output tube. Finally, the output terminal is connected to the inverting input terminal to form a buffer.

[0066] Part Two: Polarity Switching Circuit 2 and Zero-Adjustment Resistor 4. A zero-adjustment resistor is connected in series at the OP output terminal to compensate for the stability of the buffer. The resistance value of the zero-adjustment resistor is related to the channel load size. If the buffer phase margin is sufficient, this resistor can be removed. The polarity switching circuit is used to select the polarity of the channel load. The buffer with the correct polarity is connected to the first channel load 31 and the second channel load 32 to drive different channel loads.

[0067] Part Three: Selectors MUX1 and MUX2 are used to select and switch the OP negative feedback voltage signal during the acceleration drive phase. The duration of the acceleration drive needs to be adjusted digitally according to the load of different screens.

[0068] Furthermore, those skilled in the art will understand that the technical solution claimed in this invention is disclosed in the following aspects:

[0069] First, the current sampling and current limiting circuit inside the amplifier (OP) serves three purposes: first, to ensure the amplifier (OP) has a large slew rate during the acceleration drive phase; second, to extend the duration of the overcharge voltage in the unstable buffer during the acceleration drive phase; and third, to prevent the source OP from consuming excessive power during the acceleration drive phase, thus avoiding abnormal power consumption.

[0070] Second, the unstable state buffer during the acceleration drive phase: mainly the voltage of the polarity switching circuit node of the MUX is fed back to the inverting input of the amplifier (OP) to use the overcharge voltage to accelerate the load and drive the load voltage to near the stable voltage.

[0071] Third, the stabilization buffer in the stable drive stage: mainly the voltage at the output of the amplifier (OP) selected by the selector MUX is fed to the inverting input of the amplifier (OP) for feedback. By utilizing the large small-signal bandwidth of the buffer, the load voltage is quickly driven to the stable voltage.

[0072] Fourth, the internal Miller capacitance compensation is cancelled, and a zero-adjustment compensation resistor is connected in series at the output of the amplifier (OP): This is to allow the buffer in the stable drive stage to obtain a larger bandwidth and sufficient phase margin, so that the buffer in the accelerated drive stage is in an unstable state and generates a large overcharge voltage.

[0073] Furthermore, those skilled in the art will understand that the dynamic acceleration drive control method claimed in this invention mainly achieves acceleration drive through the following steps:

[0074] - After the source amplifier circuit 1 is enabled, once the internal current of the OP stabilizes slightly, for example, in a preferred embodiment, this is processed over approximately 10 ns. Based on the polarity judgment signal, MUX1 and MUX2 select the correct positive polarity switching node voltage for the positive source amplifier, and MUX3 and MUX4 select the correct negative polarity switching node voltage for the inverting input of the negative source amplifier, thus forming an unstable positive buffer and an unstable negative buffer. At the same time, the enable transistors of the current sampling and current limiting circuits of the positive and negative source amplifiers are turned on, and the source enters the acceleration drive phase. Under the influence of the large slew rate and overcharge voltage of the unstable buffer, the output load is quickly driven to near the stable voltage.

[0075] - Based on the screen load, the duration of the acceleration drive phase is digitally adjusted. When the voltage on the output load approaches the stable voltage value, the acceleration drive circuit is turned off. MUX1 selects the output voltage of the positive source amplifier and applies it to the inverting input of the positive source amplifier. MUX3 selects the output voltage of the negative source amplifier and applies it to the inverting input of the negative OP, thus forming a stable positive buffer and a stable negative buffer. The source enters the stable drive phase. Since the buffer has a large small signal bandwidth, the channel load is quickly driven to the stable voltage.

[0076] Furthermore, during the acceleration drive phase, the enable transistor of the current sampling and current limiting circuit is turned on. When the amplifier (OP) is driven in the positive direction, the sampling current of the output PMOS transistor is relatively large, while the sampling current of the NMOS transistor is very small. The current sampling and current limiting circuit injects very little current into node A and a relatively large current into node B, causing the output NMOS transistor to turn off and the output PMOS transistor to turn on quickly. In this way, the amplifier (OP) enters the positive acceleration drive state. When the amplifier (OP) is driven in the negative direction, the sampling current of the output PMOS transistor is very small, while the sampling current of the NMOS transistor is relatively large. The current sampling and current limiting circuit injects a relatively large current into node A and a relatively small current into node B, causing the output NMOS transistor to turn on rapidly and the output PMOS transistor to turn off. In this way, the amplifier (OP) enters the negative acceleration drive state.

[0077] The purpose of injecting the sampling current into points A and B of the load stage is twofold: first, to ensure the amplifier (OP) has a large unidirectional slew rate during the acceleration drive phase; and second, to ensure that the overcharge voltage generated by the unstable buffer during the acceleration drive phase is sustained for a sufficiently long time.

[0078] Furthermore, those skilled in the art will understand that the above Figures 1-9 The technical solution provided by the present invention is illustrated by taking a set of channel loads as an example. In practical applications, multiple sets of channel loads can be driven simultaneously, as described in the contents of the invention and the corresponding contents of specific embodiments.

[0079] The specific embodiments of the present invention have been described above. It should be understood that the present invention is not limited to the specific embodiments described above, and those skilled in the art can make various modifications or variations within the scope of the claims, which do not affect the essence of the present invention.

Claims

1. A dynamic acceleration drive control circuit for a high-resolution, high-refresh-rate TFT-LCD display screen, used for driving a high-resolution, high-refresh-rate TFT-LCD display screen, characterized in that, At least one pair of adjacent first channel loads (31) and second channel loads (32) are used as a group of driving units. The first channel loads (31) and second channel loads (32) are controlled by a polarity switching circuit (2) to alternately display positive and negative polarity voltages. The input terminal of the polarity switching circuit (2) is connected to the source amplifier circuit (1). The source amplifier circuit (1) includes at least a positive source amplifier (11) and a negative source amplifier (12). The output terminal of the polarity switching circuit (2) is connected to the input terminals of the first channel loads (31) and the second channel loads (32) respectively. The polarity switching circuit (2) includes at least a second selector (MUX2) for selecting the voltages of the positive polarity path intermediate nodes EX_P1 and EX_P2 to be sent to the positive source amplifier (11) as feedback voltages, and a fourth selector (MUX4) for selecting the voltages of the negative polarity path intermediate nodes EX_N1 and EX_N2 to be sent to the negative source amplifier (12) as feedback voltages. The Source amplifier employs a floating transconducting linear loop controlled Class AB rail-to-rail operational amplifier to improve the bandwidth and driving capability of the operational amplifier. The inverting terminal of the positive source amplifier (11) is connected to the first selector (MUX1), and the input terminal of the first selector (MUX1) is connected to the output terminal of the positive source amplifier (11) and the output terminal of the second selector (MUX2); the inverting terminal of the negative source amplifier (12) is connected to the third selector (MUX3), and the input terminal of the third selector (MUX3) is connected to the output terminal of the negative source amplifier (12) and the output terminal of the fourth selector (MUX4); Specifically, the voltage of the positive polarity path intermediate node EX_P1 is selected by the first selector (MUX1) and the second selector (MUX2) and sent to the positive source amplifier (11) as a feedback voltage to form an acceleration drive buffer for the positive source amplifier (11). The voltage of the negative polarity path intermediate node EX_N1 is selected by the third selector (MUX3) and the fourth selector (MUX4) and sent to the negative source amplifier (12) as a feedback voltage to form an acceleration drive buffer for the negative source amplifier (12). Subsequently, the first selector (MUX1) selects the output voltage OUT_P of the positive source amplifier (11) as a feedback voltage to form a stable drive buffer for the positive source amplifier (11). The third selector (MUX3) selects the output voltage OUT_N of the negative source amplifier (12) as a feedback voltage to form a stable drive buffer for the negative source amplifier (12).

2. The dynamic acceleration drive control circuit according to claim 1, characterized in that, The polarity switching circuit (2) selects driving paths of opposite polarities for the first channel load (31) and the second channel load (32) through a polarity control signal. When the first channel load (31) is selected as the positive polarity driving path, the second channel load (32) is selected as the negative polarity driving path, and vice versa.

3. The dynamic acceleration drive control circuit according to claim 2, characterized in that, The polarities of the first channel load (31) and the second channel load (32) are periodically switched.

4. The dynamic acceleration drive control circuit according to any one of claims 1 to 3, characterized in that, The two input terminals of the second selector (MUX2) are respectively connected to the two control circuits of the polarity switching circuit (2), and the output terminal of the second selector (MUX2) is used to connect to the positive source amplifier (11); the two input terminals of the fourth selector (MUX4) are respectively connected to the two control circuits of the polarity switching circuit (2), and the output terminal of the fourth selector (MUX4) is used to connect to the negative source amplifier (12).

5. The dynamic acceleration drive control circuit according to claim 4, characterized in that, It also includes at least a zero-adjustment resistor (4), the input terminal of the polarity switching circuit (2) is connected to one end of the zero-adjustment resistor (4), and the other end of the zero-adjustment resistor (4) is connected to the output terminal of the positive source amplifier (11) and / or the negative source amplifier (12) circuit.

6. The dynamic acceleration drive control circuit according to claim 5, characterized in that, It also includes at least a first discharge switch (CS1) and a second discharge switch (CS2). The first discharge switch (CS1) is connected to the intermediate nodes EX_P1 and EX_P2 of the positive polarity path, and the second discharge switch (CS2) is connected to the intermediate nodes EX_N1 and EX_N2 of the negative polarity path. The other end of the first discharge switch (CS1) and the second discharge switch (CS2) is grounded to GND for the first channel load (31) and the second channel load (32) to discharge to ground.

7. The dynamic acceleration drive control circuit according to claim 5 or 6, characterized in that, Each Source amplifier circuit (1) includes at least a PMOS output transistor current sampling and current limiting circuit (15) and an NMOS output transistor current sampling and current limiting circuit (16), which are used to increase the overshoot voltage sustaining time of the Source during the acceleration drive phase and suppress the reverse discharge of the power transistor current. Each output transistor current sampling and current limiting circuit includes at least a sampling transistor, a current limiting transistor, and an enable transistor. The gate of the PMOS output transistor current sampling transistor is connected to the gate of the output PMOS power transistor of the Source amplifier circuit (1). The drain of the PMOS current limiting transistor is connected to the source of the sampling transistor. The drain of the sampling transistor is connected to the source of the enable transistor. The drain of the enable transistor is connected to the internal node B of the OP, which is used to suppress the premature reverse discharge of the NMOS output power transistor of the Source amplifier circuit (1). The gate of the NMOS output current sampling transistor is connected to the gate of the output NMOS power transistor of the Source amplifier circuit (1). The drain of the NMOS current limiting transistor is connected to the source of the sampling transistor. The drain of the sampling transistor is connected to the source of the enable transistor. The drain of the enable transistor is connected to node A inside the OP, which suppresses the premature reverse discharge of the PMOS output power transistor of the Source amplifier circuit (1).

8. The dynamic acceleration drive control circuit according to claim 7, characterized in that, The Source amplifier circuit (1) does not have an internal Miller compensation capacitor, and a zero-adjustment resistor (4) is connected in series at the output of the Source amplifier circuit (1) to improve the small signal bandwidth of the operational amplifier.

9. A dynamic acceleration driving method for a high-resolution, high-refresh-rate TFT-LCD display screen, used in the dynamic acceleration driving control circuit according to any one of claims 1 to 8, characterized in that, Includes the following steps: a. The polarity switching circuit (2) controls the selection of the corresponding voltage polarity drive path for the first channel load (31) and the second channel load (32); b. After the Source amplifier circuit (1) is enabled, the positive Source amplifier (11) is made into a positive Source acceleration drive buffer and the negative Source amplifier (12) is made into a negative Source acceleration drive buffer by controlling the acceleration drive enable signal, so that the first channel load (31) and the second channel load (32) are quickly driven to near the stable voltage. c. When the capacitor voltages on the first channel load (31) and the second channel load (32) are close to or slightly exceed the stable voltage, the positive source amplifier (11) is controlled to form a stable drive buffer for the positive source amplifier (11), and the negative source amplifier (12) is controlled to form a stable drive buffer for the negative source amplifier (12). The first channel load (31) and the second channel load (32) are quickly driven to the stable voltage using the stable drive buffer.

10. The dynamic acceleration driving method according to claim 9, characterized in that, In step b, the acceleration drive phase begins, and at least under the action of the large slew rate and persistent overcharge voltage of the acceleration drive buffer, the first channel load (31) and the second channel load (32) are rapidly driven to near the stable voltage.

11. The dynamic acceleration driving method according to claim 9, characterized in that, In step c, the system enters the stable drive stage. With the help of the stable drive buffer which has a large small signal bandwidth, the first channel load (31) and the second channel load (32) are quickly driven to a stable voltage.

12. The dynamic acceleration driving method according to claim 11, characterized in that, During the acceleration drive phase, the voltage of the positive polarity path intermediate node EX_P1 is selected by the first selector (MUX1) and the second selector (MUX2) and sent to the positive source amplifier (11) as feedback voltage to form the acceleration drive buffer of the positive source amplifier (11). The voltage of the negative polarity path intermediate node EX_N1 is selected by the third selector (MUX3) and the fourth selector (MUX4) and sent to the negative source amplifier (12) as feedback voltage to form the acceleration drive buffer of the negative source amplifier (12). During the stable drive phase, the output voltage OUT_P of the positive source amplifier (11) is selected by the first selector (MUX1) as feedback voltage to form the stable drive buffer of the positive source amplifier (11). The output voltage OUT_N of the negative source amplifier (12) is selected by the third selector (MUX3) as feedback voltage to form the stable drive buffer of the negative source amplifier (12).

13. The dynamic acceleration driving method according to claim 12, characterized in that, During the acceleration drive process, the enable transistors in the output transistor current sampling and current limiting circuit (15) and the output transistor current sampling and current limiting circuit (16) are turned on, and during the stable drive phase, the enable transistors in the output transistor current sampling and current limiting circuit (15) and the output transistor current sampling and current limiting circuit (16) are turned off.

14. The dynamic acceleration driving method according to claim 12 or 13, characterized in that, In the polarity switching circuit (2), the third switch (PS3) and the fourth switch (PS4) are open, and the first switch (PS1) and the second switch (PS2) are closed, so as to select the negative polarity driving channel for the first channel load (31). In the polarity switching circuit (2), the seventh switch (NS3) and the eighth switch (NS4) are open, and the fifth switch (NS1) and the sixth switch (NS2) are closed, so as to select the positive polarity driving channel for the second channel load (32). The EN enable signal of the Source amplifier circuit (1) changes from high level to low level, turning off the positive Source amplifier (11) and the negative Source amplifier (12), and the output terminals OUT_P and OUT_N of the Source amplifier circuit (1) are both in a high impedance state.

15. The dynamic acceleration driving method according to claim 14, characterized in that, The first discharge switch (CS1) and the second discharge switch (CS2) of the polarity switching circuit (2) are turned on, and the negative charge on the capacitor in the first channel load (31) is discharged to GND through the eighth switch (NS4) and the second discharge switch (CS2), and the positive charge on the capacitor in the second channel load (32) is discharged to GND through the fourth switch (PS4) and the first discharge switch (CS1). After the first channel load (31) and the second channel load (32) are discharged to GND, the first discharge switch (CS1) and the second discharge switch (CS2) to ground are turned off, and the first channel load (31) and the second channel load (32) to ground are completed.

16. The dynamic acceleration driving method according to claim 15, characterized in that, In the polarity switching circuit (2), the first switch (PS1) and the second switch (PS2) are open, and the output of the positive source amplifier (11) is connected to the first channel load (31) through the first switch (PS1) and the second switch (PS2). The third switch (PS3) and the fourth switch (PS4) are closed, selecting a positive polarity drive channel for the first channel load (31). In the polarity switching circuit, the fifth switch (NS1) and the sixth switch (NS2) are open, and the output of the negative source amplifier (12) is connected to the first channel load (31) through the fifth switch (NS1) and the sixth switch (NS2). 2) Connect to the second channel load (32), and close the seventh switch (NS3) and the eighth switch (NS4) to select the negative polarity drive channel for the second channel load (32); at the same time, control the first selector (MUX1) to connect the OUT_P signal to the inverting input terminal of the positive source amplifier (11) to form the positive drive buffer of the first channel load (31); control the third selector (MUX3) to connect the OUT_N signal to the inverting input terminal of the negative source amplifier (12) to form the negative drive buffer of the second channel load (32).

17. The dynamic acceleration driving method according to claim 16, characterized in that, When the Source enable signal EN_OP changes from low to high, the positive Source amplifier (11) and the negative Source amplifier (12) start working. At this time, the positive drive buffer and the negative drive buffer start to initially drive the first channel load (31) and the second channel load (32). After the Source enable signal EN_OP changes from low to high for a clock delay, the current direction of the power transistors in the output stage of the positive Source amplifier (11) and the negative Source amplifier (12) is basically determined. The acceleration control signal TURBO changes from low to high, controlling the Source to enter the acceleration drive stage.

18. The dynamic acceleration driving method according to claim 17, characterized in that, The acceleration control signal TURBO changes from low level to high level, controlling the first selector (MUX1) and the second selector (MUX2) to select the positive polarity channel node EX_P1 and connect it to the inverting input terminal of the positive source amplifier (11) to form a positive polarity acceleration drive buffer. By controlling the third selector (MUX3) and the fourth selector (MUX4) to select the negative polarity channel node EX_N1 and connect it to the inverting input terminal of the negative source amplifier (12) to form a negative polarity acceleration drive buffer. Both the positive polarity acceleration drive buffer and the negative polarity acceleration drive buffer are in a phase understability state.

19. The dynamic acceleration driving method according to claim 18, characterized in that, During the acceleration drive phase, when the acceleration control signal TURBO changes from low to high, the power transistor current sampling and current limiting enable EN is turned on inside the positive Source amplifier (11) and negative Source amplifier (12) circuits. The sampling transistor current is injected into node A and node B respectively. The overshoot voltage generated by the Source acceleration drive buffer will be maintained for a significantly longer time, greatly enhancing the acceleration drive speed of the first channel load (31) and the second channel load (32). By adjusting the pulse width of the acceleration control signal TURBO, when the channel load capacitor voltage approaches or slightly exceeds the stable voltage, the acceleration signal TURBO immediately changes from high to low, turning off the current sampling and current limiting circuit enable. The acceleration drive phase of the Source for the first channel load (31) and the second channel load (32) is completed.

20. The dynamic acceleration driving method according to claim 19, characterized in that, After the Source acceleration drive phase is completed, TURBO becomes low level, and the first selector (MUX1) connects the OUT_P signal to the inverting input of the positive Source amplifier (11) to form a positive polarity stable drive buffer; the third selector (MUX3) connects the OUT_N signal to the inverting input of the negative Source amplifier (12) to form a negative polarity stable drive buffer. At this time, the Source enters the stable drive phase for the first channel load (31) and the second channel load (32). Both the positive polarity drive buffer and the negative polarity drive buffer are in a phase stable state. Since the zero capacitance compensation has a large small signal bandwidth, the stable drive buffer quickly drives the first channel load (31) and the second channel load (32) to a stable voltage, completing the stable drive phase of the Source for the first channel load (31) and the second channel load (32).

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