Sampling rate conversion device and method and audio playing system

Abstract

The invention discloses a sampling rate conversion device and method and an audio playing system, and the device comprises a phase compensation module and a signal processing module. The phase compensation module determines a phase compensation value according to the first asynchronous clock signal, the second asynchronous clock signal, the first preset number, the second preset number and the initial extraction factor; and the signal processing module compensates the current extraction factor according to the phase compensation value to obtain a target extraction factor, samples the input signal under the control of the target extraction factor to obtain a target input sampling point for generating an output sampling point, and takes the target extraction factor as the current extraction factor for next sampling. Through the above mode, the phase compensation value used for compensating the current extraction factor is determined, and the compensation of the phase difference between the input sampling rate and the output sampling rate is realized by changing the current extraction factor, so that the problem of sound lagging or sound fast forward caused by the existence of the phase difference is solved.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic circuits, and in particular to a sampling rate conversion device, method and audio playback system. Background Art

[0002] In the smart speaker system, the input sampling rate is determined by the crystal oscillator of the audio input device, and the output sampling rate is determined by the crystal oscillator of the audio output device. However, in actual applications, since the crystal oscillator of the audio input device and the crystal oscillator of the audio output device are two independent crystal oscillators, and the operating frequency of each crystal oscillator may differ due to its manufacturing process, there is a phase difference between the input sampling rate and the output sampling rate in the smart speaker system. The existence of the phase difference causes the smart speaker system to experience sound stuttering or fast-forwarding when playing audio, reducing the user experience. Summary of the invention

[0003] The present invention provides a sampling rate conversion device, method and audio playback system, which are used to compensate for the phase difference between the input sampling rate and the output sampling rate in the audio playback system, thereby solving the problem of sound freeze or sound fast forward during playback of the audio playback system due to the phase difference.

[0004] In a first aspect, an embodiment of the present invention provides a sampling rate conversion device, including a phase compensation module and a signal processing module, wherein:

[0005] The phase compensation module is used to determine a phase compensation value for each preset counting cycle according to a first asynchronous clock signal, a second asynchronous clock signal, a first preset number, a second preset number and an initial decimation factor, wherein the first asynchronous clock signal is provided by an audio input device, the second asynchronous clock signal is provided by an audio output device, the first preset number is used to represent the number of the preset counting cycles, the second preset number is used to represent the number of input sample points within the preset counting cycle, and the initial decimation factor is determined by an input sampling rate and an output sampling rate;

[0006] The signal processing module is used to compensate the current decimation factor according to the phase compensation value to obtain a target decimation factor; under the control of the target decimation factor, sample the input signal to obtain a target input sample point, determine the output sample point for generating the output signal according to the target input sample point, and use the target decimation factor as the current decimation factor for the next sampling.

[0007] The sampling rate conversion device provided by the embodiment of the present invention includes a phase compensation module and a signal processing module. For each preset counting cycle, the phase compensation module tracks the phase difference between the input sampling rate and the output sampling rate according to the first asynchronous clock signal, the second asynchronous clock signal, the first preset number, the second preset number and the initial decimation factor, and determines the phase compensation value according to the phase difference; the signal processing module compensates the current decimation factor according to the phase compensation value to obtain the target decimation factor, and changes the current decimation factor to achieve phase adjustment; and under the control of the target decimation factor, samples the input signal to obtain the target input sample point, and determines the output sample point for generating the output signal according to the target input sample point, and uses the target decimation factor as the current decimation factor for the next sampling. In the above manner, the phase compensation value for compensating the current decimation factor is determined, and the compensation of the phase difference between the input sampling rate and the output sampling rate is achieved by changing the current decimation factor, thereby solving the problem of sound freeze or sound fast forward caused by the existence of the phase difference, and improving the user experience.

[0008] In an optional embodiment, the phase compensation module includes a counting unit, a comparison unit and a compensation unit, wherein:

[0009] The counting unit is used to count the first bit clock signal in the first asynchronous clock signal and the second bit clock signal in the second asynchronous clock signal for each preset counting cycle to obtain a first count value and a second count value;

[0010] The comparison unit is used to calculate the first count value, the second count value, the first bit clock signal, the second bit clock signal, the first frame clock signal in the first asynchronous clock signal, the second frame clock signal in the second asynchronous clock signal, and the initial extraction factor to obtain a clock phase difference value;

[0011] The compensation unit is used to determine the phase compensation value according to the clock phase difference value, the first preset number and the second preset number.

[0012] In the above embodiment, the phase compensation module includes a counting unit, a comparison unit and a compensation unit. First, the counting unit determines the first count value used to characterize the number of first-bit clock signals and the second count value used to characterize the number of second-bit clock signals in each preset counting cycle. Then, the comparison unit calculates the first count value, the second count value, the first-bit clock signal, the second-bit clock signal, the first frame clock signal, the second frame clock signal and the initial extraction factor to obtain the clock phase difference value; finally, the compensation unit determines the phase compensation value according to the clock phase difference value, the first preset number and the second preset number. In the above manner, the phase difference between the input sampling rate and the output sampling rate is tracked, and the phase compensation value is determined according to the tracked phase difference to achieve compensation for the current sampling factor.

[0013] In an optional embodiment, the counting unit includes a first counter, a second counter and a third counter, wherein:

[0014] The first counter is used to count the first clock signal for each preset counting cycle, and generate the first counting value and the control signal when the preset counting cycle is reached;

[0015] The second counter is used to count the second clock signal for each preset counting cycle, and output a third counting value corresponding to the preset counting cycle under the control of the control signal;

[0016] The third counter is used to use the difference between the third count value and the count value stored in the third counter as the second count value, and store the third count value, wherein the count value stored in the third counter is the third count value output by the second counter when the last preset count cycle arrives.

[0017] In the above embodiment, the counting unit includes a first counter, a second counter and a third counter. For each preset counting cycle, the first counter counts the first clock signal, and when the preset counting cycle is reached, generates a first counting value and a control signal, and clears its own counting value; the second counter counts the second clock signal, and under the control of the control signal, outputs a third counting value corresponding to the preset counting cycle; the third counter uses the difference between the third counting value and the counting value stored in the third counter as the second counting value, and stores the third counting value. Since the second counter counts the second clock signal continuously and does not need to perform a clearing operation, the counting error of the second clock signal will not accumulate over time, so that there will be no cumulative error in the counting of the second clock, thereby improving the accuracy of the determined phase compensation value.

[0018] In an optional embodiment, the comparison unit includes a comparator;

[0019] The comparator is used to calculate the product of the second count value, the initial decimation factor and the frequency multiplication quotient, and use the difference between the first count value and the product as the clock phase difference;

[0020] The frequency multiplier is the ratio of the first clock frequency multiplier to the second clock frequency multiplier, the first clock frequency multiplier is the ratio of the first bit clock signal to the first frame clock signal, and the second clock frequency multiplier is the ratio of the second bit clock signal to the second frame clock signal.

[0021] In the above embodiment, first, the first clock multiplier is determined according to the ratio of the first bit clock signal to the first frame clock signal, and the second clock multiplier is determined according to the ratio of the second bit clock signal to the second frame clock signal, and the multiplier quotient is determined according to the ratio of the first clock multiplier to the second clock multiplier, then, the product of the second count value, the initial extraction factor and the multiplier quotient is calculated, and finally, the difference between the first count value and the product is used as the clock phase difference, thereby realizing the tracking of the phase difference between the input sampling rate and the output sampling rate.

[0022] In an optional embodiment, the compensation unit includes a divider;

[0023] The divider is used to use the ratio of the clock phase difference value to the first preset number as an intermediate compensation value, and use the ratio of the intermediate compensation value to the second preset number as the phase compensation value.

[0024] In the above embodiment, the divider calculates the ratio of the clock phase difference value to the first preset number to obtain an intermediate compensation value, and calculates the ratio of the intermediate compensation value to the second preset number to obtain a phase compensation value. By dynamically adjusting the first preset number, the compensation speed of the compensation unit can be adjusted. For example, by reducing the first preset number, the compensation speed can be slowed down, and by increasing the first preset number, the compensation speed can be increased. In addition, by dynamically adjusting the second preset number, the distortion tolerance during compensation can be adjusted. For example, the smaller the second preset number, the smaller the distortion tolerance during compensation. When the second preset number is 1, the distortion tolerance is the smallest.

[0025] In an optional embodiment, the compensation unit includes a register;

[0026] The register is used to right-shift the clock phase difference value according to a third preset amount to obtain an intermediate compensation value, and right-shift the intermediate compensation value according to a fourth preset amount to obtain the phase compensation value;

[0027] The first preset number is the product of the third preset number and the preset value; and the second preset number is the product of the fourth preset number and the preset value.

[0028] In the above embodiment, the register performs right shift processing on the clock phase difference value according to the third preset number stored in the register to obtain the intermediate compensation value, and performs right shift processing on the intermediate compensation value according to the fourth preset number stored in the register to obtain the phase compensation value; wherein the first preset number is the product of the third preset number and the preset value; and the second preset number is the product of the fourth preset number and the preset value. By setting the third preset number and the fourth preset number in the register and performing right shift processing on the clock phase difference value to obtain the phase compensation value, the use of a divider is avoided, the chip area can be reduced, and the chip integration is beneficial.

[0029] In an optional embodiment, the signal processing module is specifically used for:

[0030] The sum of the current decimation factor and the phase compensation value is used as the target decimation factor.

[0031] In the above embodiment, the sum of the current decimation factor and the phase compensation value is used as the target decimation factor to achieve compensation for the current decimation factor, thereby adjusting the phase difference between the input sampling rate and the output sampling rate, solving the problem of sound stuttering or sound fast-forwarding caused by the phase difference, and improving the user experience.

[0032] In an optional embodiment, the sampling rate conversion device further includes a fade-in and fade-out module;

[0033] The fade-in and fade-out module is used to adjust the amplitude value of the output signal composed of the output sample points by adopting a preset amplitude variation rule.

[0034] In the above embodiment, the amplitude value of the output signal is adjusted through the fade-in and fade-out module, thereby avoiding the generation of excessively loud sound due to excessive changes in the amplitude value of the output signal, which affects the user's auditory experience, thereby improving the user experience.

[0035] In a second aspect, an embodiment of the present invention provides an audio playback system, comprising an audio input device, an audio output device, and a sampling rate conversion device as described in any embodiment of the first aspect above, wherein:

[0036] The audio input device is used to send an input signal to the sampling rate conversion device and provide a first asynchronous clock signal;

[0037] The audio output device is used to receive the output signal sent by the sampling rate conversion device and provide a second asynchronous clock signal.

[0038] In a third aspect, an embodiment of the present invention provides a sampling rate conversion method, which is applied to the sampling rate conversion device as described in any embodiment of the first aspect above, and the method includes:

[0039] For each preset counting cycle, determining a phase compensation value according to a first asynchronous clock signal, a second asynchronous clock signal, a first preset number, a second preset number, and an initial decimation factor, wherein the first asynchronous clock signal is provided by an audio input device, the second asynchronous clock signal is provided by an audio output device, the first preset number is used to characterize the number of the preset counting cycles, the second preset number is used to characterize the number of input sample points within the preset counting cycle, and the initial decimation factor is determined by an input sampling rate and an output sampling rate;

[0040] According to the phase compensation value, the current decimation factor is compensated to obtain a target decimation factor; under the control of the target decimation factor, the input signal is sampled to obtain a target input sample point, and the output sample point for generating the output signal is determined according to the target input sample point, and the target decimation factor is used as the current decimation factor for the next sampling.

[0041] In an optional embodiment, determining the phase compensation value for each preset counting cycle according to the first asynchronous clock signal, the second asynchronous clock signal, the first preset number, the second preset number and the initial extraction factor includes:

[0042] For each preset counting cycle, a first clock signal in the first asynchronous clock signal and a second clock signal in the second asynchronous clock signal are counted to obtain a first count value and a second count value;

[0043] Calculate the first count value, the second count value, the first bit clock signal, the second bit clock signal, the first frame clock signal in the first asynchronous clock signal, the second frame clock signal in the second asynchronous clock signal, and the initial extraction factor to obtain a clock phase difference value;

[0044] The phase compensation value is determined according to the clock phase difference value, the first preset number, and the second preset number.

[0045] In an optional embodiment, for each preset counting cycle, performing a counting operation on a first clock signal in the first asynchronous clock signal and a second clock signal in the second asynchronous clock signal to obtain a first count value and a second count value includes:

[0046] For each preset counting cycle, the first clock signal is counted, and when the preset counting cycle is reached, the first counting value and the control signal are generated;

[0047] For each preset counting cycle, counting the second clock signal, and generating a third counting value corresponding to the preset counting cycle under the control of the control signal;

[0048] The difference between the third count value and the count value stored in the sampling rate conversion device is used as the second count value, and the third count value is stored, wherein the count value stored in the third counter is the third count value output by the second counter when the last preset count cycle arrives.

[0049] In an optional embodiment, the first count value, the second count value, the first bit clock signal, the second bit clock signal, the first frame clock signal in the first asynchronous clock signal, the second frame clock signal in the second asynchronous clock signal, and the initial extraction factor are calculated to obtain a clock phase difference value, including:

[0050] Calculate the product of the second count value, the initial decimation factor and the frequency multiplication quotient, and use the difference between the first count value and the product as the clock phase difference;

[0051] The frequency multiplier is the ratio of the first clock frequency multiplier to the second clock frequency multiplier, the first clock frequency multiplier is the ratio of the first bit clock signal to the first frame clock signal, and the second clock frequency multiplier is the ratio of the second bit clock signal to the second frame clock signal.

[0052] In an optional embodiment, determining the phase compensation value according to the clock phase difference value, the first preset number, and the second preset number includes:

[0053] The ratio of the clock phase difference value to the first preset number is used as an intermediate compensation value, and the ratio of the intermediate compensation value to the second preset number is used as the phase compensation value.

[0054] In an optional embodiment, determining the phase compensation value according to the clock phase difference value, the first preset number, and the second preset number includes:

[0055] The clock phase difference value is right-shifted according to a third preset amount to obtain an intermediate compensation value, and the intermediate compensation value is right-shifted according to a fourth preset amount to obtain the phase compensation value;

[0056] The first preset number is the product of the third preset number and the preset value; and the second preset number is the product of the fourth preset number and the preset value.

[0057] In an optional embodiment, compensating the current decimation factor to obtain the target decimation factor includes:

[0058] The sum of the current decimation factor and the phase compensation value is used as the target decimation factor.

[0059] In an optional embodiment, after determining the output sample points for generating the output signal according to the target input sample points, the method further includes:

[0060] The amplitude value of the output signal composed of the output sample points is adjusted using a preset amplitude variation rule.

[0061] For the technical effects that may be achieved by the audio playback system disclosed in the second aspect and the sampling rate conversion method disclosed in the fourth aspect, please refer to the technical effects that can be achieved by the first aspect or various possible solutions in the first aspect, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0062] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0063] Figure 1 A schematic diagram of an application scenario of a sampling rate conversion device provided by an embodiment of the present invention;

[0064] Figure 2 A schematic diagram of an application scenario of another sampling rate conversion device provided by an embodiment of the present invention;

[0065] Figure 3 A schematic diagram of the structure of a sampling rate conversion device provided by an embodiment of the present invention;

[0066] Figure 4 A schematic diagram of the structure of another sampling rate conversion device provided by an embodiment of the present invention;

[0067] Figure 5 A schematic diagram of the structure of another sampling rate conversion device provided by an embodiment of the present invention;

[0068] Figure 6 A schematic diagram of the structure of another sampling rate conversion device provided by an embodiment of the present invention;

[0069] Figure 7a A schematic diagram of a structure for obtaining a target filter coefficient corresponding to a target input sample point in a polyphase filter basic coefficient table provided by an embodiment of the present invention;

[0070] Figure 7b A schematic diagram of another target filter coefficient corresponding to a target input sample point obtained in a polyphase filter basic coefficient table provided by an embodiment of the present invention;

[0071] Figure 8 A schematic diagram of a corresponding relationship between input sample points and filter coefficients provided by an embodiment of the present invention;

[0072] Fig. 9 A schematic diagram of the structure of an audio playback system provided by an embodiment of the present invention;

[0073] Fig.10 A schematic flow chart of a sampling rate conversion method based on a sampling rate conversion device provided in an embodiment of the present invention;

[0074] Fig.11 A complete flow chart of a sampling rate conversion method based on a sampling rate conversion device provided by an embodiment of the present invention;

[0075] Fig.12 A schematic diagram of a program product of a sampling rate conversion method based on a sampling rate conversion device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0076] In order to make the purpose, technical scheme and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0077] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present invention. Instead, they are merely examples of devices and methods consistent with some aspects of the present invention as detailed in the appended claims.

[0078] The embodiments of the present invention provide a sampling rate conversion device, method and audio playback system to compensate for the phase difference between the input sampling rate and the output sampling rate in the audio playback system, thereby solving the problem of sound freeze or sound fast forward during playback of the audio playback system due to the phase difference.

[0079] The technical solution in the embodiment of the present invention will be described below in conjunction with the accompanying drawings:

[0080] Figure 1 An application scenario of the sampling rate conversion device provided in an embodiment of the present invention is shown. Figure 1 As shown, the audio playback system includes an audio acquisition device 11, a first integrated circuit (IC) 12, a second integrated circuit 13 and an audio playback device 14, wherein the second integrated circuit 13 receives an audio signal from the first integrated circuit 12 through an audio bus. Exemplarily, the audio bus can be an integrated circuit built-in audio bus (Inter-IC Sound, I2S), or a digital audio interface (Sony / Philips Digital Interface Format, SPDIF), or other buses for transmitting audio signals, and the embodiment of the present invention does not impose any restrictions on this; the first integrated circuit 12 includes an analog to digital converter (ADC) 121, and the second integrated circuit 13 includes a sampling rate conversion device 131, a sound effect processor 132 and a digital to analog converter (DAC) 133 that are electrically connected in sequence.

[0081] In a specific implementation, the audio acquisition device 11 acquires sound signals and sends the acquired sound signals to the first integrated circuit 12 for processing, wherein the analog-to-digital converter 121 determines the input sampling rate for converting the sound signals into digital signals based on its own clock signal, and transmits the digital signals with the input sampling rate to the second integrated circuit 13 for processing. In the process of the second integrated circuit 13 processing the above-mentioned digital signal, since the crystal oscillator of the analog-to-digital converter 121 and the crystal oscillator of the digital-to-analog converter 133 are two independent crystal oscillators, the manufacturing process of the crystal oscillator will cause a phase difference between the clock signal of the analog-to-digital converter 121 and the clock signal of the digital-to-analog converter 133. Therefore, after the second integrated circuit 13 receives the digital signal, first, the sampling rate conversion device 131 is used to adjust the phase difference between the clock signal of the analog-to-digital converter 121 and the clock signal of the digital-to-analog converter 133, that is, the digital signal with an input sampling rate is converted into a digital signal with an output sampling rate; then, the digital signal with the output sampling rate is sent to the sound effect processor 132 for sound effect processing; finally, the digital signal after the sound effect processing is sent to the digital-to-analog converter 133, so that the digital-to-analog converter 133 converts the digital signal after the sound effect processing into a sound signal, and sends it to the audio playback device 14 for playback.

[0082] Figure 2 Another application scenario of the sampling rate conversion device provided in an embodiment of the present invention is shown. Figure 2 As shown, the audio playback system includes an audio acquisition device 11, an integrated circuit 21 and an audio playback device 14, wherein the integrated circuit 21 includes an analog-to-digital converter 211, a sampling rate conversion device 212, a sound effect processor 213 and a digital-to-analog converter 214 electrically connected in sequence.

[0083] In a specific implementation, the audio acquisition device 11 acquires sound signals and sends the acquired sound signals to the integrated circuit 21 for processing. In the process of the integrated circuit 21 processing the acquired sound signals: first, the analog-to-digital converter 211 converts the sound signal into a digital signal with an input sampling rate, and transmits the digital signal with the input sampling rate to the sampling rate conversion device 212; then, the sampling rate conversion device 212 performs sampling rate conversion on the digital signal with the input sampling rate to obtain a digital signal with an output sampling rate, and transmits the digital signal with the output sampling rate to the sound effect processor 213 for sound effect processing; finally, the digital signal processed with sound effects is sent to the digital-to-analog converter 214, so that the digital-to-analog converter 214 converts the digital signal processed with sound effects into a sound signal, and sends the sound signal to the audio playback device 14 for playback.

[0084] It should be noted that the audio acquisition device 11 in the embodiment of the present invention can be a microphone, a voice recorder, or other devices for collecting sound, and the embodiment of the present invention does not impose any restrictions on this; in addition, the audio playback device 14 in the embodiment of the present invention can be a speaker, a mobile phone, or other devices for playing sound, and the embodiment of the present invention does not impose any restrictions on this.

[0085] In addition, in the embodiment of the present invention, other essential components of the audio playback system are well understood by those skilled in the art and are not described in detail herein and should not be construed as limiting the present invention.

[0086] It should be noted that the sampling rate conversion device provided in the embodiment of the present invention can be applied in Figure 1 or Figure 2 The audio playback system shown can also be applied to other systems that require sampling rate conversion, and the embodiment of the present invention does not impose any limitation on this.

[0087] The following is a description of a sampling rate conversion device provided by the present invention through a specific embodiment. Figure 3 As shown, the sampling rate conversion device includes a phase compensation module 31 and a signal processing module 32, wherein:

[0088] The phase compensation module 31 is used to determine the phase compensation value pdelta for each preset counting cycle according to the first asynchronous clock signal (IN_SCLK, IN_LRCLK), the second asynchronous clock signal (OUT_SCLK, OUT_LRCLK), the first preset number frames, the second preset number samps and the initial decimation factor deci_ratio, wherein the first asynchronous clock signal (IN_SCLK, IN_LRCLK) is provided by the audio input device, the second asynchronous clock signal (OUT_SCLK, OUT_LRCLK) is provided by the audio output device, the first preset number frames is used to represent the number of preset counting cycles, the second preset number samps is used to represent the number of input sample points in the preset counting cycle, and the initial decimation factor deci_ratio is determined by the input sampling rate and the output sampling rate;

[0089] It should be noted that the audio input device in the embodiment of the present invention may be an analog-to-digital converter, or an audio bus, such as an I2S bus, an SPDIF bus, etc., or other devices connected to the front stage of the sampling rate conversion device, and the embodiment of the present invention does not impose any restrictions on this; in addition, the audio output device in the embodiment of the present invention may be a digital-to-analog converter, or an audio bus, such as an I2S bus, an SPDIF bus, etc., or other devices connected to the back stage of the sampling rate conversion device, and the embodiment of the present invention does not impose any restrictions on this.

[0090] Optionally, in the embodiment of the present invention, the initial decimation factor deci_ratio is the ratio of the input sampling rate in_ratio to the output sampling rate out_ratio, that is,

[0091] In an optional embodiment, if Figure 3 As shown, the phase compensation module 31 includes a counting unit 311, a comparing unit 312 and a compensating unit 313, wherein:

[0092] The counting unit 311 is used to count the first bit clock signal IN_SCLK and the second asynchronous clock signal (OUT_SCLK, OUT_LRCLK) in the first asynchronous clock signal (IN_SCLK, IN_LRCLK) for each preset counting cycle to obtain a first counting value in_cycle and a second counting value out_cycle;

[0093] The comparison unit 312 is used to calculate the first count value in_cycle, the second count value out_cycle, the first bit clock signal IN_SCLK, the second bit clock signal OUT_SCLK, the first frame clock signal IN_LRCLK in the first asynchronous clock signal (IN_SCLK, IN_LRCLK), the second frame clock signal OUT_LRCLK in the second asynchronous clock signal (OUT_SCLK, OUT_LRCLK), and the initial extraction factor deci_ratio to obtain the clock phase difference value pdiff;

[0094] The compensation unit 313 is configured to determine a phase compensation value pdelta according to the clock phase difference value pdiff, a first preset number frames, and a second preset number samps.

[0095] In an embodiment of the present invention, the input sampling rate in_ratio is determined by the clock frequency of the first frame clock signal IN_LRCLK, and the output sampling rate out_ratio is determined by the clock frequency of the second frame clock signal OUT_LRCLK; the first bit clock signal IN_SCLK is determined by the clock frequency of the input first frame clock signal IN_LRCLK, the sampling width of the audio input device, and the number of input sampling channels of the audio input device, and the second bit clock signal OUT_SCLK is determined by the clock frequency of the second frame clock signal OUT_LRCLK, the sampling width of the audio output device, and the number of output sampling channels of the audio output device.

[0096] It should be noted that the preset counting period in the embodiment of the present invention is an empirical value and can be set through a register. For example, the preset counting period can be set to 10, or the preset counting period can be set to 15, or the preset counting period can be set to other values ​​that match actual business needs, and the embodiment of the present invention does not impose any restrictions on this.

[0097] In a specific implementation, after receiving the first clock signal IN_SCLK provided by the audio input device and the second clock signal OUT_SCLK provided by the audio output device, the counting unit 311 counts the first clock signal IN_SCLK according to a preset counting cycle to obtain a first counting value in_cycle, and counts the second clock signal OUT_SCLK according to a preset counting cycle to obtain a second counting value out_cycle, and sends the obtained first counting value in_cycle and the second counting value out_cycle to the comparing unit 312; after receiving the first counting value in_cycle and the second counting value out_cycle, the comparing unit 312 counts the first counting value in_cycle according to the first counting value in_cycle. cycle, the second counting value out_cycle, the first bit clock signal IN_SCLK, the second bit clock signal OUT_SCLK, the first frame clock signal IN_LRCLK, the second frame clock signal OUT_LRCLK and the initial extraction factor deci_ratio are used to calculate the clock phase difference pdiff, and the obtained clock phase difference pdiff is sent to the compensation unit 313; after receiving the clock phase difference pdiff, the compensation unit 313 calculates the phase compensation value pdelta according to the clock phase difference pdiff, the first preset number frames and the second preset number samps, and sends the phase compensation value pdelta to the signal processing module 32.

[0098] Through the above-mentioned method, the phase difference between the input sampling rate and the output sampling rate is tracked, and the phase compensation value pdelta is determined according to the tracked phase difference to achieve compensation for the current sampling factor.

[0099] In an optional embodiment, if Figure 4 As shown, the counting unit 311 includes a first counter In_cnt, a second counter Out_cnt and a third counter Out_start, wherein:

[0100] A first counter In_cnt, used for counting the first bit clock signal IN_SCLK for each preset counting cycle peroid, and generating a first counting value in_cycle and a control signal when the preset counting cycle is reached;

[0101] The second counter Out_cnt is used to count the second clock signal OUT_SCLK for each preset counting cycle peroid, and output a third counting value mid_cycle corresponding to the preset counting cycle peroid under the control of the control signal;

[0102] The third counter Out_start is used to take the difference between the third count value mid_cycle and the count value stored in the third counter Out_start as the second count value out_cycle, and store the third count value mid_cycle, wherein the count value stored in the third counter Out_start is the third count value mid_cycle output by the second counter Out_cnt when the previous preset count cycle arrives.

[0103] It should be noted that, in the embodiment of the present invention, the second counter Out_cnt and the third counter Out_start may be integrated into one counter module, or may be two separately provided counters, and the embodiment of the present invention does not impose any limitation on this.

[0104] Optionally, the first counter In_cnt and the second counter Out_cnt in the embodiment of the present invention are both 24-bit counters.

[0105] In a specific implementation, a preset counting cycle peroid is set for the first counter In_cnt, and the first clock signal IN_SCLK is counted by the first counter In_cnt, that is, the first counter In_cnt performs a counting operation when the preset clock edge of the first clock signal IN_SCLK appears. When the first counting value in_cycle of the first counter In_cnt is equal to the preset counting cycle peroid, the first counting value in_cycle is output to the comparison unit 312, a control signal is sent to the second counter Out_cnt, and a reset operation is performed under the control of the reset signal reset, and the counting operation of the first clock signal IN_SCLK is restarted. At this time, it indicates that the first counter In_cnt has reached the current preset counting cycle peroid; The second counter Out_cnt counts the second clock signal OUT_SCLK, that is, the second counter Out_cnt performs a counting operation when the preset clock edge of the second clock signal OUT_SCLK appears. When the second counter Out_cnt receives the control signal, it outputs the third count value mid_cycle to the third counter Out_start; the third counter Out_start uses the difference between the third count value mid_cycle and the count value stored in itself as the second count value out_cycle, sends the second count value out_cycle to the comparison unit 312, and stores the third count value mid_cycle. The stored third count value mid_cycle is used for calculating the difference between the count values ​​next time, that is, the second count value out_cycle.

[0106] It should be noted that the preset clock edge in the embodiment of the present invention may be a rising edge of the clock signal or a falling edge of the clock signal, and the embodiment of the present invention does not impose any limitation on this.

[0107] The following embodiments are described by taking the preset clock edge as the rising edge of the clock signal as an example:

[0108] In a specific implementation, the first counter In_cnt can count the first bit clock signal IN_SCLK in the following two ways:

[0109] Method 1: The initial count value of the first counter In_cnt is set to the preset count cycle peroid. When the rising edge of the first clock signal IN_SCLK arrives, the first counter In_cnt counts the first clock signal IN_SCLK once, so that the count value of the first counter In_cnt is reduced by 1 until the count value of the first counter In_cnt becomes 0. At this time, it means that the preset count cycle peroid has arrived. The first counter In_cnt uses the preset count cycle peroid as the first count value in_cycle, that is, in_cycle=peroid, and outputs it to the comparison unit 312. At the same time, a control signal is sent to the second counter Out_cnt, and the reset signal reset is enabled. The initial count value of the first counter In_cnt is reset under the control of the reset signal reset, so that the first counter In_cnt starts counting the first clock signal IN_SCLK again.

[0110] Exemplarily, the preset counting cycle peroid is set to 5, that is, the initial counting value of the first counter In_cnt is 5, and the first counter In_cnt counts the rising edge of the first clock signal IN_SCLK. Within the preset counting cycle peroid, when the first counter In_cnt recognizes the rising edge of the first clock signal IN_SCLK for the first time, the first counter In_cnt subtracts 1 from its initial counting value, and the counting value of the first counter In_cnt is 4. Then, when the first counter In_cnt recognizes the rising edge of the first clock signal IN_SCLK for the second time, the first counter In_cnt subtracts 1 from its initial counting value. cnt performs a subtraction operation on the current count value, at which time the count value of the first counter In_cnt becomes 3, and so on, until the count value of the first counter In_cnt becomes 0, indicating that the preset count cycle peroid has been reached, the first counter In_cnt outputs the first count value in_cycle=peroid=5 to the comparison unit 312, and at the same time sends a control signal to the second counter Out_cnt, and enables the reset signal reset, and under the control of the reset signal reset, the count value of the first counter In_cnt is reset to the initial count value 5, and the next round of counting of the first bit clock signal IN_SCLK is restarted.

[0111] Method 2: Set the initial count value of the first counter In_cnt to 0, and set the preset count cycle peroid in the first counter In_cnt. When the rising edge of the first clock signal IN_SCLK arrives, the first counter In_cnt counts the first clock signal IN_SCLK once, so that the count value of the first counter In_cnt is increased by 1, until the count value of the first counter In_cnt is equal to the preset count cycle peroid. At this time, it means that the preset count cycle peroid has arrived. The first counter In_cnt uses the count value at this time as the first count value in_cycle, that is, in_cycle=peroid, and outputs it to the comparison unit 312, and sends a control signal to the second counter Out_cnt at the same time, and enables the reset signal reset, and resets the initial count value of the first counter In_cnt under the control of the reset signal reset, so that the first counter In_cnt starts counting the first clock signal IN_SCLK again.

[0112] Exemplarily, the initial count value of the first counter In_cnt is set to 0, and the preset count period peroid in the first counter In_cnt is set to 5. The first counter In_cnt counts the rising edge of the first clock signal IN_SCLK. Within the preset count period peroid, when the first counter In_cnt recognizes the rising edge of the first clock signal IN_SCLK for the first time, the first counter In_cnt adds 1 to its initial count value. At this time, the count value of the first counter In_cnt is 1. Then, when the first counter In_cnt recognizes the rising edge of the first clock signal IN_SCLK for the second time, the first counter In_cnt adds 1 to its initial count value. _cnt adds 1 to the current count value, and the count value of the first counter In_cnt becomes 2, and so on, until the count value of the first counter In_cnt is equal to the preset count cycle peroid=5, indicating that the preset count cycle peroid has been reached, the first counter In_cnt outputs the first count value in_cycle=peroid=5 to the comparison unit 312, and at the same time sends a control signal to the second counter Out_cnt, and enables the reset signal reset, and resets the count value of the first counter In_cnt to the initial count value 0 under the control of the reset signal reset, and restarts the next round of counting of the first bit clock signal IN_SCLK.

[0113] In a specific implementation, the initial count value of the second counter Out_cnt is set to 0, and the second counter Out_cnt counts the rising edge of the second clock signal OUT_SCLK, that is, whenever the second counter Out_cnt detects the rising edge of the second clock signal OUT_SCLK, the count value of the second counter Out_cnt is increased by 1; and under the control of a control signal used to characterize the arrival of a preset count period peroid, the current count value is used as the third count value mid_cycle and output to the third counter Out_start.

[0114] Optionally, the maximum allowable count value of the second counter Out_cnt in the embodiment of the present invention is 2 24 -1, only when the count value of the second counter Out_cnt reaches 2 24 -1, the second counter Out_cnt will perform a reset operation, that is, the second counter Out_cnt starts counting again from 0.

[0115] Exemplarily, the preset counting cycle peroid is set to 5. Assume that within the first preset counting cycle peroid, the number of times the second counter Out_cnt recognizes the rising edge of the second clock signal OUT_SCLK is 6, that is, the count value of the second counter Out_cnt is 6. Then, when the first preset counting cycle peroid is reached, the third count value mid_cycle output by the second counter Out_cnt is 6; within the second preset counting cycle peroid, the number of times the second counter Out_cnt recognizes the rising edge of the second clock signal OUT_SCLK is 5, that is, the count value of the second counter Out_cnt is 5. Then, when the second preset counting cycle peroid is reached, the third count value mid_cycle output by the second counter Out_cnt is 6+5=11; and so on.

[0116] In the above embodiment, since the second clock signal OUT_SCLK is counted continuously by the second counter Out_cnt and no reset operation is required, the counting error of the second clock signal OUT_SCLK will not accumulate over time, so that there will be no cumulative error in the counting of the second clock OUT_SCLK, thereby improving the accuracy of the determined phase compensation value.

[0117] In an optional implementation, when the preset counting period peroid arrives, the third counting value mid_cycle of the second counter Out_cnt may be read by a state machine in the sampling rate conversion device, and the read third counting value mid_cycle may be transmitted to the third counter Out_start.

[0118] In a specific implementation, the initial count value of the third counter Out_start is 0. The third counter Out_start is used to store the historical count value of the output of the second counter Out_cnt each time the preset count cycle peroid is reached, and to use the difference between the third count value mid_cycle and the count value stored itself as the second count value out_cycle, that is, out_cycle=mid_cycle-out_start, and after each calculation of the second count value out_cycle is completed, the count value stored itself is updated, that is, out_start=mid_cycle.

[0119] Exemplarily, the count value stored in the third counter Out_start is set to out_start=17, and when the current preset count cycle peroid is reached, the third count value mid_cycle output by the second counter Out_cnt is set to 24, then the second count value output by the third counter Out_start is: out_cycle=mid_cycle-out_start=24-17=7, and the count value stored in the third counter Out_start is updated to the third count value mid_cycle output by the second counter Out_cnt, that is, out_start=mid_cycle=24.

[0120] In an optional embodiment, if Figure 4 As shown, the comparison unit 312 includes a comparator COMP1;

[0121] The comparator COMP1 is used to calculate the product of the second count value out_cycle, the initial extraction factor deci_ratio and the frequency multiplication quotient, and use the difference between the first count value in_cycle and the product as the clock phase difference pdiff;

[0122] The frequency multiplier is the ratio of the first clock frequency multiplier fs_in_ratio to the second clock frequency multiplier fs_out_raito. The first clock frequency multiplier fs_in_ratio is the ratio of the first bit clock signal IN_SCLK to the first frame clock signal IN_LRCLK. The second clock frequency multiplier fs_out_raito is the ratio of the second bit clock signal OUT_SCLK to the second frame clock signal OUT_LRCLK.

[0123] In a specific implementation, first, the ratio of the first bit clock signal IN_SCLK to the first frame clock signal IN_LRCLK is used as the first clock frequency multiplication fs_in_ratio, that is, And the ratio of the second bit clock signal OUT_SCLK to the second frame clock signal OUT_LRCLK is used as the second clock frequency multiplication fs_out_raito, that is, Then, when the current preset counting cycle peroid arrives, the comparator COMP1 receives two counting values, namely the first counting value in_cycle and the second counting value out_cycle, and takes the ratio of the first clock frequency multiplication fs_in_ratio to the second clock frequency multiplication fs_out_raito as the frequency multiplication quotient, namely, the frequency multiplication quotient is And calculate the product of the second count value out_cycle, the initial extraction factor deci_ratio and the frequency multiplication quotient, that is, the product is The difference between the second count value out_cycle and the product is calculated, and the calculated difference is used as the clock phase difference pdiff, that is, the clock phase difference is:

[0124]

[0125] For example, assuming that the first count value in_cycle=5, the second count value out_cycle=7, the initial decimation factor deci_ratio=0.7, and the frequency multiplication factor The clock phase difference is:

[0126]

[0127] In the above embodiment, first, the first clock frequency multiplier fs_in_ratio is determined according to the ratio of the first bit clock signal IN_SCLK and the first frame clock signal IN_LRCLK, and the second clock frequency multiplier fs_out_raito is determined according to the ratio of the second bit clock signal OUT_SCLK and the second frame clock signal OUT_LRCLK, and the frequency multiplier quotient is determined according to the ratio of the first clock frequency multiplier fs_in_ratio to the second clock frequency multiplier fs_out_raito, then, the product of the second count value out_cycle, the initial extraction factor deci_ratio and the frequency multiplier quotient is calculated, and finally, the difference between the first count value in_cycle and the product is used as the clock phase difference pdiff, so as to achieve the tracking of the phase difference between the input sampling rate and the output sampling rate.

[0128] In an optional embodiment, if Figure 4 As shown, the compensation unit 313 includes a divider D1;

[0129] The divider D1 is used for taking the ratio of the clock phase difference value pdiff to the first preset number frames as the intermediate compensation value delta, and taking the ratio of the intermediate compensation value delta to the second preset number samps as the phase compensation value pdelta.

[0130] In a specific implementation, after receiving the clock phase difference value pdiff, the divider D1 calculates the ratio of the clock phase difference value pdiff to the first preset number of frames to obtain the intermediate compensation value delta, that is, the intermediate compensation value is: Then, the ratio of the intermediate compensation value delta to the second preset number samps is calculated to obtain the phase compensation value pdelta, that is, the phase compensation value is:

[0131] Exemplarily, assuming that the first preset number frames is 2, the second preset number samps is 5, and the clock phase difference value pdiff is 0.59, the determined phase compensation value is:

[0132] In the above embodiment, the compensation speed of the compensation unit 313 can be adjusted by dynamically adjusting the first preset number of frames. For example, the compensation speed can be slowed down by reducing the first preset number of frames, and the compensation speed can be increased by increasing the first preset number of frames. In addition, the distortion tolerance during compensation can be adjusted by dynamically adjusting the second preset number samps. For example, the smaller the second preset number samps is, the smaller the distortion tolerance during compensation is. When the second preset number samps is 1, the distortion tolerance is the smallest.

[0133] Since the division calculation will increase the chip area, which is not conducive to chip integration, the embodiment of the present invention also provides another structure of the compensation unit 313, as described below:

[0134] In an optional embodiment, if Figure 5 As shown, the compensation unit 313 includes a register RG1;

[0135] Register RG1, used to right-shift the clock phase difference value pdiff according to a third preset number frames_shift_bits to obtain an intermediate compensation value delta, and right-shift the intermediate compensation value delta according to a fourth preset number samps_shift_bits to obtain a phase compensation value pdelta;

[0136] The first preset number frames is the product of the third preset number frames_shift_bits and the preset values; and the second preset number samps is the product of the fourth preset number samps_shift_bits and the preset values.

[0137] It should be noted that in the embodiment of the present invention, the first preset number of frames can only be 2 n The design is carried out in the form of, and the second preset number of samps can only be 2 n Designed in the form of.

[0138] Optionally, the preset value is 2, then the first preset number is: frames = 2 frames_shift_bits ; The second preset number is: samps = 2 samps_shift_bits .

[0139] In a specific implementation, a third preset number frames_shift_bits and a fourth preset number samps_shift_bits are set in register RG1. After register RG1 receives the clock phase difference value pdiff, the clock phase difference value pdiff is right-shifted according to the third preset number frames_shift_bits to obtain an intermediate compensation value delta, that is, the intermediate compensation value is: delta=pdiff>>frames_shift_bits; then, the intermediate compensation value delta is right-shifted according to the fourth preset number samps_shift_bits to obtain a phase compensation value pdelta, that is, the phase compensation value is: pdelta=delta>>samps_shift_bits, wherein, ">>" represents an arithmetic logic right shift.

[0140] In an optional embodiment, the compensation unit 313 includes a first register RG11 and a second register RG12, wherein:

[0141] The first register RG11 is used to perform a right shift processing on the clock phase difference value pdiff according to a third preset number frames_shift_bits to obtain an intermediate compensation value delta;

[0142] The second register RG12 is used to right-shift the intermediate compensation value delta according to a fourth preset number samps_shift_bits to obtain a phase compensation value pdelta;

[0143] The first preset number frames is the product of the third preset number frames_shift_bits and the preset values; and the second preset number samps is the product of the fourth preset number samps_shift_bits and the preset values.

[0144] In a specific implementation, a third preset number frames_shift_bits is set in the first register RG11, and a fourth preset number samps_shift_bits is set in the second register RG12. After the first register RG11 receives the clock phase difference value pdiff, the clock phase difference value pdiff is right-shifted according to the third preset number frames_shift_bits stored in itself to obtain an intermediate compensation value delta, that is, the intermediate compensation value is: delta=pdiff>>frames_shift_bits; and the obtained intermediate compensation value delta is sent to the second register RG12. The second register RG12 performs a right-shift operation on the intermediate compensation value delta according to the fourth preset number samps_shift_bits to obtain a phase compensation value pdelta, that is, the phase compensation value is: pdelta=delta>>samps_shift_bits, wherein, ">>" represents an arithmetic logical right shift.

[0145] In the above embodiment, by setting the third preset number and the fourth preset number in the register and right-shifting the clock phase difference value to obtain the phase compensation value, the use of a divider is avoided, the chip area can be reduced, and chip integration is facilitated.

[0146] The calculation of the phase compensation value pdelta can be realized through the above embodiment. Since the sampling rate specification supported by the above sampling rate conversion device is 8KHz to 192KHz, and the range of the first clock frequency multiplication fs_in_ratio and the second clock frequency multiplication fs_out_ratio designed by the audio playback system are both 16 to 256, the accuracy error measured by the sampling rate conversion device is:

[0147] Minimum accuracy error:

[0148] Maximum accuracy error:

[0149] Therefore, the sampling rate conversion device has a good compensation effect on the signal whose phase difference between the input sampling rate and the output sampling rate is within 100 ppm.

[0150] The signal processing module 32 is used to compensate the current decimation factor according to the phase compensation value pdelta to obtain the target decimation factor deci_ratio_new; under the control of the target decimation factor deci_ratio_new, sample the input signal to obtain the target input sample point, determine the output sample point for generating the output signal according to the target input sample point, and use the target decimation factor deci_ratio_new as the current decimation factor for the next sampling.

[0151] The sampling rate conversion device provided by the embodiment of the present invention includes a phase compensation module 31 and a signal processing module 32. For each preset counting cycle, the phase compensation module 31 tracks the phase difference between the input sampling rate and the output sampling rate according to the first asynchronous clock signal (IN_SCLK, IN_LRCLK), the second asynchronous clock signal (OUT_SCLK, OUT_LRCLK), the first preset number of frames, the second preset number of samps and the initial extraction factor deci_ratio, and determines the phase compensation value pdelta according to the phase difference; the signal processing module 32 compensates the current extraction factor according to the phase compensation value pdelta to obtain the target extraction factor deci_ratio_new, and adjusts the phase by changing the current extraction factor; and under the control of the target extraction factor deci_ratio_new, samples the input signal to obtain the target input sample point, determines the output sample point for generating the output signal according to the target input sample point, and uses the target extraction factor deci_ratio_new as the current extraction factor for the next sampling. Through the above method, the phase compensation value used to compensate the current decimation factor is determined, and the phase difference between the input sampling rate and the output sampling rate is compensated by changing the current decimation factor, thereby solving the problem of sound stuttering or sound fast-forwarding caused by the existence of the phase difference and improving the user experience.

[0152] In an optional embodiment, if Figure 6 As shown, the signal processing module 32 includes a control unit 321, a signal sampling unit 322 and a signal processing unit 323, wherein:

[0153] The control unit 321 is used to compensate the current decimation factor according to the phase compensation value pdelta to obtain a target decimation factor deci_ratio_new, and use the target decimation factor deci_ratio_new as the current decimation factor for the next sampling;

[0154] The signal sampling unit 322 is used to sample the input signal under the control of the target extraction factor deci_ratio_new to obtain the target input sample point;

[0155] The signal processing unit 323 is used to determine output sample points for generating an output signal according to the target input sample points.

[0156] In a specific implementation, first, the control unit 321 receives the phase compensation value pdelta sent by the phase compensation module 31, and compensates the current decimation factor according to the received phase compensation value pdelta to obtain the target decimation factor deci_ratio_new, and sends the target decimation factor deci_ratio_new to the signal sampling unit 322; after the signal sampling unit 322 receives the target decimation factor deci_ratio_new, under the control of the target decimation factor deci_ratio_new, samples the input signal to obtain the target input sample point, and transmits the target input sample point to the signal processing unit 323; after the signal processing unit 323 receives the target input sample point, it determines the output sample point according to the target input sample point, and then generates an output signal.

[0157] In an optional embodiment, the control unit 321 is specifically configured to: use the sum of the current decimation factor and the phase compensation value pdelta as the target decimation factor deci_ratio_new.

[0158] In a specific implementation, the phase compensation value pdelta determined in the previous preset counting cycle is used to compensate the decimation factor in the current preset counting cycle to obtain the corresponding target decimation factor deci_ratio_new. Specifically, for the current preset counting cycle, the compensation cumulative value pall of the phase compensation value pdelta is calculated, that is, the compensation cumulative value is: pall+=pdelta, where the initial value of the compensation cumulative value pall is 0; then, the sum of the compensation cumulative value pall and the current decimation factor is used as the target decimation factor deci_ratio_new, that is, the target decimation factor is: deci_ratio_new=deci_ratio_x+pall.

[0159] Optionally, if the phase compensation value pdelta is a phase compensation value determined according to the first preset counting cycle in the current playback task, the current decimation factor is the initial decimation factor deci_ratio.

[0160] Exemplarily, it is assumed that the audio playback system is about to perform a certain playback task, for example, playing a song, and assuming that the number of input samples within the preset counting cycle, that is, the second preset number samps=3, the initial decimation factor deci_ratio=0.5, after the current playback task starts, the phase compensation value pdelta=0.059 determined within the first preset counting cycle, then within the second preset counting cycle: the compensation cumulative value pall calculated according to the phase compensation value pdelta is: pall+=pdelta=0+0.059=0.059, and the initial decimation factor deci_ratio=0.5 is compensated according to the compensation cumulative value pall , the target decimation factor deci_ratio_new obtained is: deci_ratio_new=deci_ratio+pall=0.5+0.059=0.559; then, the input signal is sampled using the target decimation factor deci_ratio_new=0.559, the first target input sample is obtained within the second preset counting cycle, and the target decimation factor deci_ratio_new=0.559 is used as the current decimation factor deci_ratio_x, that is, deci_ratio_x=deci_ratio_new=0.559, for use in the next sampling process. After obtaining the first target input sample point within the second preset counting cycle to determine the output sample point, the compensation cumulative value pall is calculated again according to the above phase compensation value pdelta, and the compensation cumulative value pall is: pall+=pdelta=0.059+0.059=0.118, and the current decimation factor deci_ratio_x=0.559 is compensated according to the compensation cumulative value pall, and the target decimation factor deci_ratio_new is: deci_ratio_new=deci_ratio_new atio_x+pall=0.559+0.118=0.667;Then, the input signal is sampled using the target decimation factor deci_ratio_new=0.667, and the second target input sample point is obtained within the second preset counting cycle, and the target decimation factor deci_ratio_new=0.667 is used as the current decimation factor deci_ratio_x, that is, deci_ratio_x=deci_ratio_new=0.667, to be used in the next sampling process. Repeat the above operation until the second preset counting cycle is reached, and the compensation accumulated value pall is cleared.

[0161] In the above embodiment, the sum of the current decimation factor and the phase compensation value is used as the target decimation factor to achieve compensation for the current decimation factor, thereby adjusting the phase difference between the input sampling rate and the output sampling rate, solving the problem of sound stuttering or sound fast-forwarding caused by the phase difference, and improving the user experience.

[0162] In an optional embodiment, if Figure 6 As shown, the signal sampling unit 322 includes a first first-in first-out queue 3221 and an address generating subunit 3222, wherein:

[0163] A first FIFO queue 3221 is used to store input signals sent by an audio input device;

[0164] The address generating subunit 3222 is used to determine the sample point address information according to the target decimation factor deci_ratio_new sent by the control unit 321, and read the target input sample point from the input signal stored in the first FIFO queue 3221 according to the determined sample point address information.

[0165] In a specific implementation, for a certain playback task, the initial value of the sample point address information pos is 0. After the address generation subunit 3222 receives the target decimation factor deci_ratio_new sent by the control unit 321, the sample point address information pos is updated according to the target decimation factor deci_ratio_new, and the input sample point at the corresponding position of the first first-in-first-out queue 3221 is read according to the updated sample point address information. The read input sample point is the target input sample point.

[0166] Optionally, in an embodiment of the present invention, the first FIFO queue 3221 may adopt a 32-level 32-bit wide FIFO queue, and the first FIFO queue 3221 reads / writes data according to the first frame clock signal IN_LRCLK.

[0167] Exemplarily, assuming that the input sampling rate is 24KHz and the output sampling rate is 48000KHz, the initial decimation factor deci_ratio = 24KHz / 48KHz = 0.5, and assuming that at the initial moment, the input sample points stored in the first first-in-first-out queue 3221 are represented as: in1, in2, in3...in(m), and the output sample points calculated based on the input sample points are set to: out1, out2, out3, out4...out(n), and the second preset number samps is set to 2.

[0168] For the above example, the specific process of sampling the input sample points is as follows: first, the first output sample point out1 is calculated: at this time, the sample point address information pos determined by the address generation subunit 3222 is the initial value, that is, the sample point address information pos=0, then the 0th input sample point in1 is read from the input sample points stored in the first first-in first-out queue 3221, and the read input sample point in1 is cached, the address generation subunit 3222 obtains the cached input sample point in1, and uses the input sample point in1 as the target input sample point for determining the output sample point out1. After the output sample point out1 is calculated, the address generation subunit 3222 generates a sample point according to the initial sampling. The sampling point address information pos is updated by the factor deci_ratio=0.5, and the updated sampling point address information pos is: pos=pos+deci_ratio=0+0.5=0.5, and it is identified whether the value of the integer part of the updated sampling point address information pos jumps. For example, if the sampling point address information is updated from pos=0 to pos=0.5, since the value of the integer part of the sampling point address information pos is 0, no jump occurs; if the sampling point address information is updated from pos=0.5 to pos=1.059, since the value of the integer part of the sampling point address information pos jumps from 0 to 1, a jump occurs;

[0169] Then, the second output sample point out2 is calculated: at this time, the input sample point in1 is cached in the cache area of ​​the sampling rate conversion device, and the input sample points stored in the first first-in first-out queue 3221 are represented as: in2, in3...in(m), and the sample point address information pos is the updated sample point address information, that is, the sample point address information pos=0.5, and the value of the integer part of the sample point address information pos=0.5 does not jump, then the address generation subunit 3222 obtains the input sample point in1 cached in the cache area, and uses the input sample point in1 as the target input sample point for determining the output sample point out2. Since the second preset number samps is 2, after the output sample point out2 is calculated, the control unit 321 receives the phase compensation value pdel according to the received phase compensation value pdel. ta, compensate the current decimation factor (i.e., the initial decimation factor deci_ratio) to obtain the target decimation factor deci_ratio_new, and send the target decimation factor deci_ratio_new to the address generation subunit 3222. If the target decimation factor deci_ratio_new=0.559, the address generation subunit 3222 updates the sample point address information pos according to the target decimation factor deci_ratio_new=0.559, and the updated sample point address information pos is: pos=pos+deci_ratio_new=0.5+0.559=1.059, and identifies whether the integer part of the updated sample point address information pos has a jump;

[0170] Next, the third output sample out3 is calculated: at this time, the input sample points stored in the first FIFO queue 3221 are represented as: in2, in3 . . . in(m), the sample point address information pos is the updated sample point address information, that is, the sample point address information pos=1.059, and the value of the integer part of the sample point address information pos=1.059 jumps from 0 to 1, then the first input sample point in2 is read from the input sample points stored in the first FIFO queue 3221, and the read input sample point in2 is cached in the buffer area, the address generation subunit 3222 obtains the input sample point in2 cached in the buffer area, and uses the input sample point in2 as the target input sample point for determining the output sample point out3, and after the output sample point out3 is calculated, the control unit 321 receives the received phase compensation signal. The compensation value pdelta is used to compensate the current decimation factor (i.e., deci_ratio_new=0.559) to obtain a target decimation factor deci_ratio_new, and the target decimation factor deci_ratio_new is sent to the address generation subunit 3222. If the target decimation factor deci_ratio_new=0.667, the address generation subunit 3222 updates the sample point address information pos according to the target decimation factor deci_ratio_new=0.667, and the updated sample point address information pos is: pos=pos+deci_ratio_new=1.059+0.667=1.726, and it is identified whether the value of the integer part of the updated sample point address information pos jumps;

[0171] Next, the fourth output sample out4 is calculated: At this time, the input sample in2 is cached in the cache area of ​​the sampling rate conversion device, the input samples stored in the first first-in first-out queue 3221 are represented as: in3, in4...in(m), the sample address information pos is the updated sample address information, that is, the sample address information pos=1.726, and the value of the integer part of the sample address information pos=1.726 does not jump, then the address generation subunit 3222 obtains the input sample in2 cached in the cache area, and uses the input sample in2 as the target input sample for determining the output sample out4. The second preset number samps is 2. Therefore, after the output sample point out4 is calculated, the control unit 321 compensates the current decimation factor (i.e., deci_ratio_new=0.667) according to the received phase compensation value pdelta, obtains the target decimation factor deci_ratio_new, and sends the target decimation factor deci_ratio_new to the address generation subunit 3222. The address generation subunit 3222 updates the sample point address information pos according to the target decimation factor deci_ratio_new, and so on, until the current playback task is completed.

[0172] It should be noted that the initial decimation factor deci_ratio and the target decimation factor deci_ratio_new in the embodiment of the present invention are both floating point numbers. Therefore, the sampling rate conversion device performs fixed-point processing on the decimation factor. Specifically, the decimal part of the decimation factor is fixed-pointed to 48 bits. In this way, the sampling rate conversion device can be accurate to 48 bits when calculating according to the decimation factor. sample points, improving the accuracy of sampling rate conversion equipment.

[0173] In an optional embodiment, if Figure 6 As shown, the signal processing unit 323 includes a filter coefficient generation subunit 3231, a historical sample point storage subunit 3232, a polyphase filter convolution subunit 3233 and a second first-in first-out queue 3234, wherein:

[0174] The filter coefficient generating subunit 3231 is used to determine the target filter coefficient corresponding to the target input sample point according to the target input sample point and based on the polyphase filter basic coefficient table, and determine the historical filter coefficient corresponding to the historical sample point stored in the historical sample point storing subunit 3232, wherein the polyphase filter basic coefficient table is used to characterize the corresponding relationship between the interpolation sample point and the polynomial coefficient, and the interpolation sample point is determined after upsampling the input signal by N times;

[0175] The polyphase filter convolution subunit 3233 is used to perform a convolution operation on the target input sample point, the target filter coefficient, the historical sample points stored in the historical sample point storage subunit 3232, and the historical filter coefficients corresponding to the historical sample points to obtain an output sample point corresponding to the target input sample point;

[0176] The historical sample point storage subunit 3232 is used to store the target input sample points sampled by the signal sampling unit 322, and use the target input sample points as historical sample points;

[0177] The second FIFO queue 3234 is used to store the generated output samples in sequence.

[0178] In a specific implementation, after the control unit 321 obtains the target decimation factor deci_ratio_new, it transmits the target decimation factor deci_ratio_new to the signal sampling unit 322; the signal sampling unit 322 samples the input signal according to the target decimation factor deci_ratio_new, and after obtaining the target input sample points, the target input sample points are transmitted to the filter coefficient generation subunit 3231, the historical sample point storage subunit 3232 and the multi-phase filter convolution subunit 3233 in the signal processing unit 323 via the control unit 321.

[0179] In the embodiment of the present invention, the size of the historical sample point storage subunit 3232 may be 2*N*32 bits, where the maximum value of N is 64.

[0180] The updating principle of the sample points stored in the historical sample point storage subunit 3232 is first-in-first-out, that is, when the current sample point enters the historical sample point storage subunit 3232, the earliest sample point will be removed from the historical sample point storage subunit 3232.

[0181] The data in the historical sample point storage subunit 3232 is arranged so that the earliest sample point is written at the head of the data area and the latest sample point is written at the tail of the data area. This data arrangement facilitates convolution calculation of the polyphase filter.

[0182] In a specific implementation, after receiving the target input sample point, the filter coefficient generation subunit 3231 generates the target filter coefficient corresponding to the target input sample point based on the data in the multi-phase filter basic coefficient table, and generates the historical filter coefficient corresponding to the historical sample point, and sends the target filter coefficient and the historical filter coefficient to the multi-phase filter convolution subunit 3233 via the control unit 321; the multi-phase filter convolution subunit 3233 obtains the historical sample points stored in the historical sample point storage subunit 3232, and performs convolution calculation based on the received target input sample point, target filter coefficient, historical sample point and historical filter coefficient to obtain the output sample point, and stores the output sample point in the second first-in-first-out queue 3234.

[0183] It should be noted that the basic coefficient table of the multi-phase filter in the embodiment of the present invention can be stored in the memory of the audio playback system, for example, on an SD card or NAND storage medium. The filter coefficient generation subunit 3231 in the sampling rate conversion device can read the data in the basic coefficient table of the multi-phase filter. It can also be stored in the sampling rate conversion device. The filter coefficient generation subunit 3231 can directly obtain the data in the basic coefficient table of the multi-phase filter. The embodiment of the present invention does not impose any restrictions on this.

[0184] Optionally, the polyphase filter basic coefficient table is a pre-designed table, which is designed according to the order of the polyphase filter in the polyphase filter convolution subunit 3233 in the sampling rate conversion device. For example, it can be designed that the higher the order of the polyphase filter, the more data in the polyphase filter basic coefficient table. In a specific implementation, the data in the polyphase filter basic coefficient table can be made bilaterally symmetrical. Therefore, when storing the polyphase filter basic coefficient table, only 1 / 2 of the data in the polyphase filter basic coefficient table needs to be stored, wherein one coefficient component in the data of the polyphase filter basic coefficient table can be represented by 128 bits, thereby reducing the storage space used to store the polyphase filter basic coefficient table.

[0185] Exemplarily, the design process of the basic coefficient table of the multi-phase filter can be: perform N-fold upsampling and interpolation operations on the input signal to obtain a series of interpolation signals, each of which has its own corresponding filter coefficient, and integrate the above-mentioned interpolation signals and the filter coefficients corresponding to each interpolation signal together to form a data table, which is the basic coefficient table of the multi-phase filter. Among them, it is assumed that there are 2N+1 groups of data in the basic coefficient table of the polyphase filter, that is, the data in the basic coefficient table of the polyphase filter are arranged in sequence as follows: 0, 1, 2, N-2, N-1, N, N+1, N+2, ... 2N. Since the basic coefficient table of the polyphase filter is designed to be left-right symmetrical (even symmetrical), the data in the basic coefficient table of the polyphase filter is centered on N, and the data on both sides are even symmetrical and equal, that is, the data content at the N-1 position is the same as the data content at the N+1 position, the data content at the N-2 position is the same as the data content at the N+2 position, ..., the data content at the 0 position is the same as the data content at the 2N position. Therefore, only data with sequence numbers 0 to N need to be stored, and the data content in the basic coefficient table of the polyphase filter is the polynomial coefficient of a 4th-order polynomial approximate calculation function, occupying 128 bits of storage space.

[0186] For example, a 4th-order polynomial is used as an example. For a 4th-order polynomial, each interpolation sample point corresponds to 5 polynomial coefficients, and the 5 groups of coefficients are polynomial coefficient a, polynomial coefficient b, polynomial coefficient c, polynomial coefficient d, and polynomial coefficient e, from high to low polynomial order.

[0187] Assume that the polynomial coefficient a has 17 coefficients, namely coefficients 0 to 16. The design will be centered on coefficient 8, and the coefficient values ​​on the left and right sides of coefficient 8 will be designed to be symmetrical and equal (the value of coefficient 7 = the value of coefficient 9, the value of coefficient 6 = the value of coefficient 10...). When storing the table coefficients, only coefficients 0 to 8 need to be stored, and coefficients 9 to 16 do not need to be stored (they are equal to the corresponding coefficients 7 to 0).

[0188] The other polynomial coefficient tables b, c, d, and e are similar to the polynomial coefficient table a. The coefficients in the coefficient tables are designed to be 2N+1, and N is the center point, and the coefficient values ​​on both sides of the center point are symmetrical and equal.

[0189] Table 1 is a basic coefficient table of a polyphase filter provided in an embodiment of the present application:

[0190] Interpolation Samples 4th order coefficient Coefficient of third order term Second-order coefficient First-order coefficient Constant term coefficient Interpolation sample 1 a1 b1 c1 d1 e1 Interpolation sample 2 a2 b2 c2 d2 e2 Interpolation sample 3 a3 b3 c3 d3 e3 Interpolation sample 4 a4 b4 c4 d4 e4 …… …… …… …… …… …… Interpolation sample point n an bn cn dn en

[0191] Table 1

[0192] It should be noted that the polynomial coefficient table in the embodiment of the present invention is designed so that the coefficients of the 1st degree polynomial and the 3rd degree polynomial are odd functions, and the coefficients of the 2nd degree polynomial and the 4th degree polynomial are even functions. According to the even-odd property, only half of the polynomial coefficients need to be stored in the system memory, saving half of the storage space.

[0193] In a specific implementation, the target input sample point is set to S1. After the filter coefficient generating subunit 3231 receives the target input sample point S1, the target filter coefficient is determined according to the sample point address information pos of the target input sample point S1 and based on the polyphase filter basic coefficient table. Specifically, the target interpolation sample point is determined according to the sample point address information pos of the target input sample point S1 and the position information of the interpolation sample point in the polyphase filter basic coefficient table, and then the polynomial coefficient corresponding to the target interpolation point in the polyphase filter basic coefficient table is used as the initial filter coefficient.

[0194] In one embodiment, when determining the target interpolation sample point, first determine the interpolation sample point position information corresponding to the target input sample point based on the sample point address information of the target input sample point and a preset target interpolation magnification, and then select the target interpolation sample point from the polyphase filter basic coefficient table based on the interpolation sample point position information corresponding to the target input sample point and the principle of the closest distance.

[0195] Exemplarily, the target input sample point is the target input sample point S1, and the sample point address information pos of the target input sample point S1 is 1.35, then the interpolation sample point position information corresponding to the target input sample point S1 is 0.35 multiplied by the target interpolation factor N. If the target interpolation factor N is 8, then the interpolation sample point position information corresponding to the target input sample point S1 is N×[M-1]+0.35×8=8×[5-1]+0.35×8=34.8, where M is the order of the polyphase filter.

[0196] Determine the position of the target input sample point S1 between the interpolation sample points in the polyphase filter basic coefficient table. For example, as shown in Table 1, the interpolation sample points in the polyphase filter basic coefficient table include interpolation sample point 1, interpolation sample point 2, interpolation sample point 3, interpolation sample point 4 ... interpolation sample point n, wherein interpolation sample point 1, interpolation sample point 2, interpolation sample point 3, interpolation sample point 4 ... interpolation sample point n can be determined by the address information of the input signal received by the sampling rate conversion device after N-fold upsampling. In the process of generating the filter coefficient corresponding to the target input sample point S1, there are the following two situations:

[0197] Scenario 1:

[0198] Set the sample point address information pos of the target input sample point S1 to 1.35, and the interpolation sample point position information corresponding to the target input sample point S1 is 34.8, then Figure 7a and Figure 7b As shown, according to the interpolation sample point position information corresponding to the target input sample point S1, it is determined that the target input sample point S1 is located between the interpolation sample point 35 and the interpolation sample point 36, that is, the position of the target input sample point S1 mapped to the N-fold interpolation queue is located between the interpolation sample point 35 and the interpolation sample point 36. It should be noted that the N-fold interpolation queue is the queue of interpolation sample points in Table 1, interpolation sample point 1, interpolation sample point 2, interpolation sample point 3, interpolation sample point 4... interpolation sample point n. It should also be noted that the interpolation sample point position information corresponding to the interpolation sample point 1 is 0, the interpolation sample point position information corresponding to the interpolation sample point 2 is 1, the interpolation sample point position information corresponding to the interpolation sample point 3 is 2..., then the generation process of the target filter coefficient corresponding to the target input sample point S1 is:

[0199] Step 1, according to the address information pos of the target input sample point S1, calculate the interpolation sample point position information corresponding to the target input sample point S1, and then calculate the first distance L1 between the target input sample point S1 and the interpolation sample point 35, and the second distance L2 between the target input sample point S1 and the interpolation sample point 36 respectively according to the interpolation sample point position information corresponding to the target input sample point S1;

[0200] Exemplarily, since the sample point address information pos of the target input sample point S1 is 1.35 and N=8, the interpolation sample point position information corresponding to the target input sample point S1 is 8×[5-1]+0.35×8=34.8. Since the position information of the interpolation sample point 35 is 34 and the position information of the interpolation sample point 36 is 35, the distance between the target input sample point S1 and the interpolation sample point 35 is 0.8, that is, the first distance L1=0.8; the distance between the target input sample point S1 and the interpolation sample point 36 is 0.2, that is, the second distance L2=0.2.

[0201] Step 2, according to the relationship between the first distance L1 and the second distance L2, determine the target interpolation sample point according to the principle of the shortest distance;

[0202] Specifically, if the first distance L1<the second distance L2, the interpolation sample point 35 is used as the target interpolation sample point; if the second distance L2<the first distance L1, the interpolation sample point 36 is used as the target interpolation sample point; if the first distance L1=the second distance L2, the interpolation sample point 35 is used as the target interpolation sample point, or the interpolation sample point 36 is used as the target interpolation sample point.

[0203] For example, Figure 7a As shown, the first distance L1=0.8, the second distance L2=0.2, the first distance L1>the second distance L2, and the interpolation sample point 36 is used as the target interpolation sample point.

[0204] For example, Figure 7b As shown, the first distance L1=0.5, the second distance L2=0.5, and the first distance L1=the second distance L2, then the interpolation sample point 35 is used as the target interpolation sample point, or the interpolation sample point 36 is used as the target interpolation sample point.

[0205] It should be noted that when the distances between the target input sample point S1 and the two interpolation sample points are equal, it can be set which interpolation sample point is selected as the target interpolation sample point.

[0206] Step 3: According to the target interpolation sample point, the polynomial coefficient corresponding to the target interpolation sample point is taken out from the polyphase filter basic coefficient table, and the polynomial coefficient is used as the initial filter coefficient; then, according to the decimal part of the interpolation sample point position information corresponding to the target input sample point, the initial filter coefficient is calculated four times by polynomial calculation to obtain the target filter coefficient coef corresponding to the target input sample point S1. That is, the linear approximation method is used to obtain the target filter coefficient corresponding to the target input sample point S1.

[0207] For example, as shown in Table 1, the polynomial coefficients corresponding to the interpolation sample point 3 are a3, b3, c3, d3, e3. When the interpolation sample point 3 is the target interpolation sample point, the initial filter coefficients are a3, b3, c3, d3, e3, the interpolation sample point position information corresponding to the target input sample point is 2.8, and the decimal part of the interpolation sample point position information corresponding to the target input sample point is 0.8. Then, the initial filter coefficients (a3, b3, c3, d3, e3) are calculated four times by polynomial calculation based on 0.8 to obtain the target filter coefficient coef corresponding to the target input sample point S1.

[0208] Scenario 2:

[0209] The target input sample point S1 just falls on a certain interpolation sample point in the basic coefficient table of the polyphase filter, then the generation process of the target filter coefficient corresponding to the target input sample point S1 is:

[0210] Step 1, according to the address information pos of the target input sample point S1, calculate the interpolation sample point position information corresponding to the target input sample point S1, and determine the target interpolation sample point according to the interpolation sample point position information corresponding to the target input sample point S1;

[0211] For example, the sample point address information of the target input interpolation sample point S1 is pos=1.5, N=8, then the interpolation sample point position information corresponding to the target input sample point S1 is N×[M-1]+0.5×8=8×[5-1]+4=36. Since the position information corresponding to the interpolation sample point 37 is 36, the target interpolation sample point is the interpolation sample point 37.

[0212] Step 2, selecting a polynomial coefficient corresponding to the interpolation sample point 37 from the polyphase filter basic coefficient table, and using the selected polynomial coefficient as the initial filter coefficient;

[0213] Step 3, according to the decimal information (0) that the interpolation sample point position information corresponding to the target input sample point S1 is 8×[5-1]+4=36, a 4th-order polynomial calculation is performed on the initial filter coefficient to obtain the target filter coefficient corresponding to the target input sample point S1.

[0214] For example, as shown in Table 1, the polynomial coefficients corresponding to the interpolation sample point 37 are a37, b37, c37, d37, e37. When the interpolation sample point 37 is the target interpolation sample point, the initial filter coefficients are a37, b37, c37, d37, e37. Then, based on 0, the initial filter coefficients (a37, b37, c37, d37, e37) are calculated four times by polynomial calculation to obtain the target filter coefficient coef corresponding to the target input sample point S1.

[0215] The above is an explanation of how to generate target filter coefficients. The following is an explanation of how to generate historical filter coefficients.

[0216] In one embodiment, first, the interpolation sample point position information corresponding to the target input sample point is determined according to the sample point address information pos of the target input sample point, and then the interpolation sample point position information corresponding to the historical sample point is determined according to the interpolation sample point position information corresponding to the target input sample point, the position of the historical sample point in the sample point historical data storage unit, and the target interpolation magnification, and finally the historical filter coefficient corresponding to the historical sample point is determined according to the interpolation sample point position information corresponding to the historical sample point and the polyphase filter basic coefficient table.

[0217] Specifically, first, the product of the target interpolation factor and the difference between the polyphase filter order and 1 is calculated as the first product, the product of the decimal part in the sample point address information pos of the target input sample point and the target interpolation factor is used as the second product, and the sum of the first product and the second product is used as the interpolation sample point position information corresponding to the target input sample point, and then the difference between the interpolation sample point position information corresponding to the target input sample point and the product of the position of the historical sample point and the target interpolation factor is used as the interpolation sample point position information corresponding to the historical sample point. After the interpolation sample point position information corresponding to the historical sample point is determined, the interpolation sample point in the polyphase filter basic coefficient table that is closest to the interpolation sample point position information corresponding to the historical sample point is determined as the target interpolation sample point, the polynomial coefficient corresponding to the target interpolation sample point is used as the initial filter coefficient, and the initial filter coefficient is polynomially calculated based on the decimal part in the interpolation sample point position information corresponding to the historical sample point to obtain the historical filter coefficient.

[0218] The method for calculating the historical filter coefficients can refer to the method for calculating the target filter coefficients, and the repeated parts will not be repeated here.

[0219] For example, Figure 8 As shown, the historical sample point storage subunit 3232 stores n-1 historical sample points, namely historical sample point Samp1, historical sample point Samp2, historical sample point Samp3...historical sample point Sampn-1. The current target input sample point is Sampn, the position of the historical sample point corresponding to the historical sample point Sampn-1 is 1, the position of the historical sample point corresponding to the historical sample point Samp1 is n-1, the position of the historical sample point corresponding to the historical sample point Samp2 is n-2, and so on.

[0220] If the target input sample point is Sampn, the sample point address information pos=1.35, N=8, then the interpolation sample point position information corresponding to the target input sample point Sampn is 8×[5-1]+0.35×8=34.8, then the interpolation sample point position information of the historical sample point Sampn-1 is 34.8-8=26.8, and the interpolation sample point position information of the historical sample point Sampn-2 is 34.8-2×8=18.8, and so on, the interpolation sample point position information corresponding to each historical sample point can be obtained.

[0221] After obtaining the interpolation sample point position information corresponding to each historical sample point, for each historical sample point, according to the interpolation sample point position information corresponding to the historical sample point, the minimum distance principle is adopted to find the interpolation sample point closest to the historical sample point from the polyphase filter basic coefficient table, and the interpolation sample point found is used as the target interpolation sample point. For example, the interpolation sample point position information of the historical sample point Sampn-1 is 34.8-8=26.8, then the interpolation sample point closest to the historical sample point Sampn-1 is the interpolation sample point 28, and the polynomial coefficients corresponding to the interpolation sample point 28 are determined from the polyphase filter basic coefficient table as a28, b28, c28, d28, e28, and then the initial filter coefficients (a28, b28, c28, d28, e28) are calculated four times by polynomial according to the decimal part 0.6 to obtain the historical filter coefficient coefn-1 corresponding to the historical sample point Sampn-1.

[0222] The method of calculating the historical filter coefficients corresponding to other historical sample points is the same as the above, and the repeated parts will not be repeated.

[0223] In the embodiment of the present application, 2N filter coefficients may be generated.

[0224] In a specific implementation, after the filter coefficient generation subunit 3231 generates the target filter coefficient and the historical filter coefficient, the filter coefficient is sent to the multi-phase filter convolution subunit 3233 via the control unit 321. At the start of any playback task, the multi-phase filter convolution subunit 3233 performs convolution calculation on the received target input sample points, target filter coefficients, historical sample points and historical filter coefficients. The number of convolution calculations is equal to the number of taps of the multi-phase filter in the multi-phase filter convolution subunit 3233. The sum of the results of multiple convolution calculations is used as the output sample point, which is output to the second first-in-first-out queue 3234 as an output signal for transmission to the audio output device until the playback task is completed, thereby achieving the purpose of filtering.

[0225] In the embodiment of the present invention, the number of convolutions of the polyphase filter is 2N, that is, an even number.

[0226] Complete the filter convolution calculation, that is, convolve the current target input sample point, the target filter coefficient corresponding to the target input sample point, the historical sample point, and the historical filter coefficient corresponding to the historical sample point. The convolution calculation can be implemented using a 32bit*28bit multiplier, and the calculation result is saved in a 64bit storage space. Considering the multiplier area and preventing data overflow, the generated polyphase filter coefficient can be represented by 28bit.

[0227] Optionally, in an embodiment of the present invention, the second FIFO queue 3234 may adopt a 32-level 32-bit wide FIFO queue, and the second FIFO queue 3234 reads / writes data according to the second frame clock signal OUT_LRCLK.

[0228] It should be noted that the historical sample point storage subunit 3232 in the embodiment of the present invention can perform a data clearing operation under the control of the reset control signal reset to prevent the historical data of the previous playback task from affecting the current playback task and causing noise during playback. The reset control signal reset can be triggered at the end of the previous playback task or at the start of the current playback task, and the embodiment of the present invention does not impose any restrictions on this.

[0229] To facilitate understanding, the embodiments of the present application are described below with examples.

[0230] For example, Figure 8 As shown, the sample point history data storage unit 34 stores n-1 history sample points, the target input sample point is Sampn, and it is assumed that the interpolation sample point address information corresponding to the target input sample point Sampn in the interpolation queue is 2.25. From Table 1, it can be seen that the target input sample point Sampn is located between the interpolation sample point 3 and the interpolation sample point 4, the distance between the target input sample point Sampn and the interpolation sample point 3 is 0.25, and the distance between the target input sample point Sampn and the interpolation sample point 4 is 0.75. According to the principle of the shortest distance, the interpolation sample point 3 is taken as For the target interpolation sample point, the polynomial coefficients a3, b3, c3, d3 and e3 corresponding to the interpolation sample point 3 are obtained from the polyphase filter basic coefficient table shown in Table 1, a3, b3, c3, d3 and e3 are used as the initial filter coefficients, 0.25 (the decimal part of the interpolation sample point address information 2.25 corresponding to the target input sample point Sampn in the interpolation queue) is used with the initial filter coefficients a3, b3, c3, d3 and e3 to perform four polynomial calculations to obtain the filter coefficient Coefn corresponding to the target input sample point Sampn.

[0231] At the same time, according to the interpolation sample point address information corresponding to the target input sample point Sampn, the interpolation sample point address information corresponding to each historical sample point is calculated, and then the historical filter coefficient corresponding to each historical sample point is calculated in the same way as the target filter coefficient is calculated, and then for each historical sample point stored in the sample point historical data storage unit 34, a convolution operation is performed on the historical sample point and the corresponding historical filter coefficient, and a convolution operation is performed on the target input sample point and the corresponding target filter coefficient, and finally the sum of the convolution operations is used as the output sample point corresponding to the target input sample point, as expressed by the following formula:

[0232] S=Samp1*Coef1+Samp2*Coef2+Samp3*Coef3+……+Sampn-1*Coefn-1+Sa mpn*Coefn

[0233] It should be noted that the historical filter coefficients corresponding to the historical sample points are calculated in real time.

[0234] In an optional embodiment, if Figure 6 As shown, the sampling rate conversion device further includes a fade-in and fade-out module 61;

[0235] The fade-in and fade-out module 61 is used to adjust the amplitude value of the output signal composed of the output samples by adopting a preset amplitude variation rule, so as to produce the effect of gradually weakening or gradually increasing the sound.

[0236] In a specific implementation, the fade module 61 is controlled by a switch signal. When the switch signal controls the fade function, the fade module 61 works; when the switch signal controls the fade function, the fade module 61 is bypassed.

[0237] In the above embodiment, the amplitude of the output signal is adjusted by the fade-in and fade-out module 61 to produce a sound weakening or gradually increasing effect, and can also be used for mute effect (the output sample amplitude is 0).

[0238] The sampling rate conversion device in the embodiment of the present invention may be an asynchronous sampling rate converter (ASRC). The sampling rate conversion device provided by the embodiment of the present invention may be placed in an audio input device or in an audio output device.

[0239] Based on the same concept, an embodiment of the present invention further provides an audio playback system. Since the principle of solving the problem by the audio playback system is similar to that of the aforementioned sampling rate conversion device, the implementation of the audio playback system can refer to the implementation of the aforementioned sampling rate conversion device, and the repeated parts will not be repeated.

[0240] Fig. 9A schematic diagram of the structure of an audio playback system provided in an embodiment of the present application is shown. Fig. 9 As shown, the audio playback system includes an audio input device 91, an audio output device 92 and a sampling rate conversion device 93 as provided in any of the above embodiments, wherein:

[0241] An audio input device 91, for sending an input signal to a sampling rate conversion device and providing a first asynchronous clock signal;

[0242] The audio output device 92 is used to receive the output signal sent by the sampling rate conversion device and provide a second asynchronous clock signal.

[0243] In specific implementation, in the embodiment of the present invention, the audio playback system can be a product or component such as a smart speaker, a wired headset, a Bluetooth headset, etc. Other essential components of the audio playback system are well understood by those skilled in the art, and are not described in detail here, nor should they be used as limitations of the present invention.

[0244] Based on the same concept, an embodiment of the present invention further provides a sampling rate conversion method, which is applied to a sampling rate conversion device provided in any of the above embodiments. Fig.10 As shown, the method comprises the following steps:

[0245] Step S1001, for each preset counting cycle, determining a phase compensation value according to a first asynchronous clock signal, a second asynchronous clock signal, a first preset number, a second preset number, and an initial decimation factor, wherein the first asynchronous clock signal is provided by an audio input device, the second asynchronous clock signal is provided by an audio output device, the first preset number is used to represent the number of preset counting cycles, the second preset number is used to represent the number of input sample points within the preset counting cycle, and the initial decimation factor is determined by an input sampling rate and an output sampling rate;

[0246] Step S1002, according to the phase compensation value, the current decimation factor is compensated to obtain the target decimation factor; under the control of the target decimation factor, the input signal is sampled to obtain the target input sample point, and the output sample point for generating the output signal is determined according to the target input sample point, and the target decimation factor is used as the current decimation factor for the next sampling.

[0247] In an optional embodiment, for each preset counting cycle, determining a phase compensation value according to the first asynchronous clock signal, the second asynchronous clock signal, the first preset number, the second preset number, and the initial extraction factor includes:

[0248] For each preset counting cycle, a first clock signal in the first asynchronous clock signal and a second clock signal in the second asynchronous clock signal are counted to obtain a first count value and a second count value;

[0249] Calculate the first count value, the second count value, the first bit clock signal, the second bit clock signal, the first frame clock signal in the first asynchronous clock signal, the second frame clock signal in the second asynchronous clock signal, and the initial extraction factor to obtain a clock phase difference value;

[0250] A phase compensation value is determined according to the clock phase difference value, the first preset number and the second preset number.

[0251] In an optional embodiment, for each preset counting cycle, a first bit clock signal in the first asynchronous clock signal and a second bit clock signal in the second asynchronous clock signal are counted to obtain a first count value and a second count value, including:

[0252] For each preset counting cycle, the first bit clock signal is counted, and when the preset counting cycle is reached, a first counting value and a control signal are generated;

[0253] For each preset counting cycle, counting the second clock signal, and generating a third counting value corresponding to the preset counting cycle under the control of the control signal;

[0254] The difference between the third count value and the count value stored in the sampling rate conversion device is used as the second count value, and the third count value is stored, wherein the count value stored in the third counter is the third count value output by the second counter when the last preset count cycle arrives.

[0255] In an optional embodiment, the first count value, the second count value, the first bit clock signal, the second bit clock signal, the first frame clock signal in the first asynchronous clock signal, the second frame clock signal in the second asynchronous clock signal, and the initial extraction factor are calculated to obtain the clock phase difference value, including:

[0256] Calculate the product of the second count value, the initial decimation factor and the frequency multiplication quotient, and use the difference between the first count value and the product as the clock phase difference;

[0257] The frequency multiplier is the ratio of the first clock frequency multiplier to the second clock frequency multiplier, the first clock frequency multiplier is the ratio of the first bit clock signal to the first frame clock signal, and the second clock frequency multiplier is the ratio of the second bit clock signal to the second frame clock signal.

[0258] In an optional embodiment, determining the phase compensation value according to the clock phase difference value, the first preset number, and the second preset number includes:

[0259] The ratio of the clock phase difference value to the first preset number is used as the intermediate compensation value, and the ratio of the intermediate compensation value to the second preset number is used as the phase compensation value.

[0260] In an optional embodiment, determining the phase compensation value according to the clock phase difference value, the first preset number, and the second preset number includes:

[0261] The clock phase difference value is right-shifted according to a third preset amount to obtain an intermediate compensation value, and the intermediate compensation value is right-shifted according to a fourth preset amount to obtain a phase compensation value;

[0262] The first preset number is the product of the third preset number and the preset values; and the second preset number is the product of the fourth preset number and the preset values.

[0263] In an optional embodiment, compensating the current decimation factor to obtain a target decimation factor includes:

[0264] The sum of the current decimation factor and the phase compensation value is taken as the target decimation factor.

[0265] In an optional embodiment, after determining the output sample points for generating the output signal according to the target input sample points, the method further includes:

[0266] The amplitude value of the output signal composed of the output sample points is adjusted using a preset amplitude variation rule.

[0267] Fig.11 A complete flow chart of a sampling rate conversion method based on a sampling rate conversion device is shown, such as Fig.11 As shown, the method comprises the following steps:

[0268] Step S1101, configuring relevant parameters for the sampling rate conversion device: a preset counting period peroid, a first preset number frames, and a second preset number samps;

[0269] Step S1102, the state machine is initialized to set: the compensation accumulation value pall = 0, the phase compensation value pdelta = 0, the target decimation factor deci_ratio_new = the initial decimation factor deci_ratio;

[0270] Step S1103, the first FIFO queue reads and stores input samples, and reads target input samples in the first FIFO queue according to the target decimation factor deci_ratio_new;

[0271] Step S1104, determining a target filter coefficient according to the target input sample point and determining a historical filter coefficient corresponding to the historical sample point, and performing a polyphase filtering convolution calculation on the target input sample point, the target filter coefficient, the historical sample point and the historical filter coefficient;

[0272] Step S1105, determining whether the polyphase filter convolution calculation of the target input sample point is completed, if so, executing step S1111, otherwise, executing step S1104;

[0273] Step S1106, tracking and recording the first clock signal IN_SCLK in the first asynchronous clock signal and the second clock signal OUT_SCLK in the second asynchronous clock signal within a preset counting period peroid;

[0274] Step S1107, determining whether the count number of the first clock signal IN_SCLK is equal to the preset count period peroid, if so, executing step S1108, otherwise, executing step S1106;

[0275] Step S1108, outputting the first count value in_cycle, the second count value out_cycle, and updating the third count value mid_cycle;

[0276] Step S1109, calculating the clock phase difference value pdiff according to the first count value in_cycle, the second count value out_cycle, the initial decimation factor deci_ratio and the frequency multiplication quotient;

[0277] Step S1110, calculating a phase compensation value pdelta according to the clock phase difference value pdiff, a first preset number frames and a second preset number samps;

[0278] Step S1111, according to the obtained phase compensation value pdelta, the compensation cumulative value is updated to pall+=pdelta, and the target decimation factor is updated to deci_ratio_new=deci_ratio_new+pall, and the updated target decimation factor deci_ratio_new is fed back to step S1103;

[0279] Step S1112, determining whether the sampling rate conversion device has a fade-in / fade-out function enabled, if so, executing step S1113, otherwise, executing step S1114;

[0280] Step S1113, performing fade-in and fade-out processing on the result of the polyphase filter convolution calculation;

[0281] Step S1114, writing the output samples obtained by the polyphase filter convolution calculation into the second first-in-first-out queue.

[0282] In some possible implementations, various aspects of the present invention may also be implemented in the form of a program product, which includes a program code. When the program product is run on a terminal device, the program code is used to enable the terminal device to execute the steps of each module in the sampling rate conversion device according to various exemplary implementations of the present disclosure described in the above "Exemplary Method" section of this specification, for example, for each preset counting cycle, according to the first asynchronous clock signal, the second asynchronous clock signal, the first preset number, the second preset number and the initial decimation factor, determine a phase compensation value, wherein the first asynchronous clock signal is provided by the audio input device, the second asynchronous clock signal is provided by the audio output device, the first preset number is used to characterize the number of preset counting cycles, the second preset number is used to characterize the number of input sample points within the preset counting cycle, and the initial decimation factor is determined by the input sampling rate and the output sampling rate; according to the phase compensation value, compensate the current decimation factor to obtain a target decimation factor; under the control of the target decimation factor, sample the input signal to obtain a target input sample point, determine the output sample point for generating the output signal according to the target input sample point, and use the target decimation factor as the current decimation factor for the next sampling.

[0283] The program product may employ any combination of one or more readable media. The readable medium may be a readable signal medium or a readable storage medium. The readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or device, or any combination thereof. More specific examples of readable storage media (a non-exhaustive list) include: an electrical connection with one or more wires, a portable disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination thereof.

[0284] like Fig.12 As shown, a program product 120 for sampling rate conversion according to an embodiment of the present invention is described, which can adopt a portable compact disk read-only memory (CD-ROM) and include program code, and can be run on a terminal device, such as a personal computer. However, the program product of the present invention is not limited thereto, and in this document, a readable storage medium can be any tangible medium containing or storing a program, which can be used by or in combination with an instruction execution system, an apparatus or a device.

[0285] A readable signal medium may include a data signal propagated in baseband or as part of a carrier wave, wherein readable program code is carried. Such propagated data signals may take a variety of forms, including, but not limited to, electromagnetic signals, optical signals, or any suitable combination of the foregoing. A readable signal medium may also be any readable medium other than a readable storage medium, which may transmit, propagate, or transfer a program for use by or in conjunction with an instruction execution system, apparatus, or device.

[0286] The program code embodied on the readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing.

[0287] Program code for performing the operations of the present invention may be written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Java, C++, etc., and conventional procedural programming languages ​​such as "C" or similar programming languages. The program code may be executed entirely on the user computing device, partially on the user device, as a separate software package, partially on the user computing device and partially on a remote computing device, or entirely on a remote computing device or server. In the case of a remote computing device, the remote computing device may be connected to the user computing device through any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computing device (e.g., through the Internet using an Internet service provider).

[0288] It should be noted that although several modules or submodules of the system are mentioned in the above detailed description, this division is merely exemplary and not mandatory. In fact, according to an embodiment of the present invention, the features and functions of two or more modules described above can be embodied in one module. Conversely, the features and functions of one module described above can be further divided into multiple modules to be embodied.

[0289] In addition, although the operations of the modules of the system of the present invention are described in a specific order in the drawings, this does not require or imply that the operations must be performed in this specific order, or that all the operations shown must be performed to achieve the desired results. Additionally or alternatively, some operations may be omitted, multiple operations may be combined into one operation, and / or one operation may be decomposed into multiple operations.

[0290] The present application is described above with reference to the block diagrams and / or flow charts showing the methods, devices (systems) and / or computer program products according to the embodiments of the present application. It should be understood that a block of the block diagram and / or flow chart diagram and a combination of blocks of the block diagram and / or flow chart diagram can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer and / or other programmable data processing device to produce a machine, so that the instructions executed by the computer processor and / or other programmable data processing device create a method for implementing the functions / actions specified in the block diagram and / or flow chart block.

[0291] Accordingly, the present application may also be implemented with hardware and / or software (including firmware, resident software, microcode, etc.). Furthermore, the present application may take the form of a computer program product on a computer-usable or computer-readable storage medium, which has a computer-usable or computer-readable program code implemented in the medium, for use by an instruction execution system or in conjunction with an instruction execution system. In the context of the present application, a computer-usable or computer-readable medium may be any medium that may contain, store, communicate, transmit, or convey a program for use by an instruction execution system, device, or apparatus, or in conjunction with an instruction execution system, device, or apparatus.

[0292] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims

1. A sampling rate conversion device, characterized in that: It includes a phase compensation module and a signal processing module, wherein: The phase compensation module is used to determine a phase compensation value for each preset counting cycle according to a first asynchronous clock signal, a second asynchronous clock signal, a first preset number, a second preset number and an initial decimation factor, wherein the first asynchronous clock signal is provided by an audio input device, the second asynchronous clock signal is provided by an audio output device, the first preset number is used to represent the number of the preset counting cycles, the second preset number is used to represent the number of input sample points within the preset counting cycle, and the initial decimation factor is determined by an input sampling rate and an output sampling rate; The signal processing module is used to compensate the current decimation factor according to the phase compensation value to obtain a target decimation factor; under the control of the target decimation factor, sample the input signal to obtain a target input sample point, determine the output sample point for generating the output signal according to the target input sample point, and use the target decimation factor as the current decimation factor for the next sampling.

2. The device according to claim 1, characterized in that The phase compensation module includes a counting unit, a comparing unit and a compensating unit, wherein: The counting unit is used to count the first bit clock signal in the first asynchronous clock signal and the second bit clock signal in the second asynchronous clock signal for each preset counting cycle to obtain a first count value and a second count value; The comparison unit is used to calculate the first count value, the second count value, the first bit clock signal, the second bit clock signal, the first frame clock signal in the first asynchronous clock signal, the second frame clock signal in the second asynchronous clock signal, and the initial extraction factor to obtain a clock phase difference value; The compensation unit is used to determine the phase compensation value according to the clock phase difference value, the first preset number and the second preset number.

3. The device according to claim 2, characterized in that The counting unit comprises a first counter, a second counter and a third counter, wherein: The first counter is used to count the first clock signal for each preset counting cycle, and generate the first counting value and the control signal when the preset counting cycle is reached; The second counter is used to count the second clock signal for each preset counting cycle, and output a third counting value corresponding to the preset counting cycle under the control of the control signal; The third counter is used to use the difference between the third count value and the count value stored in the third counter as the second count value, and store the third count value, wherein the count value stored in the third counter is the third count value output by the second counter when the last preset count cycle arrives.

4. The device according to claim 2, characterized in that The comparison unit includes a comparator; The comparator is used to calculate the product of the second count value, the initial decimation factor and the frequency multiplication quotient, and use the difference between the first count value and the product as the clock phase difference; The frequency multiplier is the ratio of the first clock frequency multiplier to the second clock frequency multiplier, the first clock frequency multiplier is the ratio of the first bit clock signal to the first frame clock signal, and the second clock frequency multiplier is the ratio of the second bit clock signal to the second frame clock signal.

5. The device according to claim 2, characterized in that The compensation unit includes a divider; The divider is used to use the ratio of the clock phase difference value to the first preset number as an intermediate compensation value, and use the ratio of the intermediate compensation value to the second preset number as the phase compensation value.

6. The device according to claim 2, characterized in that The compensation unit includes a register; The register is used to right-shift the clock phase difference value according to a third preset amount to obtain an intermediate compensation value, and right-shift the intermediate compensation value according to a fourth preset amount to obtain the phase compensation value; The first preset number is the product of the third preset number and the preset value; and the second preset number is the product of the fourth preset number and the preset value.

7. The device according to claim 1, characterized in that The signal processing module is specifically used for: The sum of the current decimation factor and the phase compensation value is used as the target decimation factor.

8. The device according to any one of claims 1 to 7, characterized in that: Also includes a fade module; The fade-in and fade-out module is used to adjust the amplitude value of the output signal composed of the output sample points by adopting a preset amplitude variation rule.

9. An audio playback system, characterized in that: The method comprises an audio input device, an audio output device and a sampling rate conversion device as claimed in any one of claims 1 to 8, wherein: The audio input device is used to send an input signal to the sampling rate conversion device and provide a first asynchronous clock signal; The audio output device is used to receive the output signal sent by the sampling rate conversion device and provide a second asynchronous clock signal.

10. A sampling rate conversion method, characterized in that: Applied to the sampling rate conversion device according to any one of claims 1 to 8, the method comprises: For each preset counting cycle, determining a phase compensation value according to a first asynchronous clock signal, a second asynchronous clock signal, a first preset number, a second preset number, and an initial decimation factor, wherein the first asynchronous clock signal is provided by an audio input device, the second asynchronous clock signal is provided by an audio output device, the first preset number is used to characterize the number of the preset counting cycles, the second preset number is used to characterize the number of input sample points within the preset counting cycle, and the initial decimation factor is determined by an input sampling rate and an output sampling rate; According to the phase compensation value, the current decimation factor is compensated to obtain a target decimation factor; under the control of the target decimation factor, the input signal is sampled to obtain a target input sample point, and the output sample point for generating the output signal is determined according to the target input sample point, and the target decimation factor is used as the current decimation factor for the next sampling.

11. The method according to claim 10, characterized in that The method of determining the phase compensation value for each preset counting cycle according to the first asynchronous clock signal, the second asynchronous clock signal, the first preset number, the second preset number and the initial extraction factor comprises: For each preset counting cycle, a first clock signal in the first asynchronous clock signal and a second clock signal in the second asynchronous clock signal are counted to obtain a first count value and a second count value; Calculate the first count value, the second count value, the first bit clock signal, the second bit clock signal, the first frame clock signal in the first asynchronous clock signal, the second frame clock signal in the second asynchronous clock signal, and the initial extraction factor to obtain a clock phase difference value; The phase compensation value is determined according to the clock phase difference value, the first preset number, and the second preset number.

12. The method according to claim 11, characterized in that The method of performing a counting operation on the first bit clock signal in the first asynchronous clock signal and the second bit clock signal in the second asynchronous clock signal for each preset counting cycle to obtain a first count value and a second count value includes: For each preset counting cycle, the first clock signal is counted, and when the preset counting cycle is reached, the first counting value and the control signal are generated; For each preset counting cycle, counting the second clock signal, and generating a third counting value corresponding to the preset counting cycle under the control of the control signal; The difference between the third count value and the count value stored in the sampling rate conversion device is used as the second count value, and the third count value is stored, wherein the count value stored in the third counter is the third count value output by the second counter when the last preset count cycle arrives.

13. The method according to claim 11, characterized in that The step of calculating the first count value, the second count value, the first bit clock signal, the second bit clock signal, the first frame clock signal in the first asynchronous clock signal, the second frame clock signal in the second asynchronous clock signal, and the initial extraction factor to obtain a clock phase difference value includes: Calculate the product of the second count value, the initial decimation factor and the frequency multiplication quotient, and use the difference between the first count value and the product as the clock phase difference; The frequency multiplier is the ratio of the first clock frequency multiplier to the second clock frequency multiplier, the first clock frequency multiplier is the ratio of the first bit clock signal to the first frame clock signal, and the second clock frequency multiplier is the ratio of the second bit clock signal to the second frame clock signal.

14. The method according to claim 11, characterized in that The determining the phase compensation value according to the clock phase difference value, the first preset number and the second preset number includes: The ratio of the clock phase difference value to the first preset number is used as an intermediate compensation value, and the ratio of the intermediate compensation value to the second preset number is used as the phase compensation value.

15. The method according to claim 11, characterized in that The determining the phase compensation value according to the clock phase difference value, the first preset number and the second preset number includes: The clock phase difference value is right-shifted according to a third preset amount to obtain an intermediate compensation value, and the intermediate compensation value is right-shifted according to a fourth preset amount to obtain the phase compensation value; The first preset number is the product of the third preset number and the preset value; and the second preset number is the product of the fourth preset number and the preset value.

16. The method according to claim 10, characterized in that The compensating the current decimation factor to obtain the target decimation factor includes: The sum of the current decimation factor and the phase compensation value is used as the target decimation factor.

17. The method according to any one of claims 10 to 16, characterized in that: After determining the output sample points for generating the output signal according to the target input sample points, the method further includes: The amplitude value of the output signal composed of the output sample points is adjusted using a preset amplitude variation rule.

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