An operating method, a memory controller, and a memory system

Abstract

Embodiments of the present application disclose an operation method, a memory controller and a memory system. The operation method comprises: determining that a memory device of the memory system is in a first usage state in response to a read error occurring in the memory device; determining a first voltage offset corresponding to the first usage state according to a preset mapping relationship; wherein the preset mapping relationship comprises a correspondence between usage states of the memory device and voltage offsets; the voltage offset is an offset value relative to a preset reference read voltage; and obtaining a first read voltage used for performing a read operation on the memory device in the first usage state according to the preset reference read voltage and the first voltage offset.

Description

Technical Field

[0001] This application relates to the field of memory technology, and in particular to an operating method, a memory controller, and a memory system. Background Technology

[0002] With the development of storage technology, 3D NAND flash memory has evolved from single-level cells (SLC) capable of storing 1 bit of information, to double-level cells (DLC) capable of storing 2 bits of information, to triple-level cells (TLC) capable of storing 3 bits of information, and even quadruple-level cells (QLC) capable of storing 4 bits of information. Faced with memory devices with increasingly more layers and storage bits, the performance of these devices needs to be optimized. Summary of the Invention

[0003] In view of this, embodiments of this application provide an operating method, a memory controller, and a memory system.

[0004] In a first aspect, embodiments of this application provide an operation method for a memory system, including:

[0005] When a read error occurs in the memory device of the memory system, it is determined that the memory device is currently in a first usage state;

[0006] A first voltage offset corresponding to the first usage state is determined according to a preset mapping relationship; wherein, the preset mapping relationship includes the correspondence between the usage state of the memory device and the voltage offset; the voltage offset is an offset value relative to a preset reference read voltage;

[0007] The first read voltage used to perform a read operation on the memory device in the first usage state is obtained based on the preset reference read voltage and the first voltage offset.

[0008] In the above scheme, the first voltage offset includes one or more; and the first read voltage includes one or more; the method further includes:

[0009] At least one first read voltage is selected as the soft read reference voltage for soft decision error correction;

[0010] Based on each of the soft read reference voltages and the preset offset rule, a set of soft read voltages containing the soft read reference voltages is obtained.

[0011] The soft decision error correction is performed on the memory device based on at least one set of soft read voltages.

[0012] In the above scheme, the preset mapping relationship includes a mapping table; the method further includes:

[0013] This allows the memory device to be in different usage states;

[0014] In each usage state, a read retry table (RRT) is obtained from the memory device; the RRT is traversed, and a read operation is performed on the memory device one by one to obtain at least one voltage offset in the RRT when a read error meets a preset condition; a correspondence between each usage state and the corresponding at least one voltage offset is established.

[0015] The mapping table is generated based on each correspondence.

[0016] In the above scheme, the status parameters include at least one of the following: the number of erases, the number of programs, the number of reads, the read temperature, the program temperature, and the time interval between programming and reading of the memory device;

[0017] The process of placing the memory device in different usage states includes:

[0018] Assign values ​​to the number of erases, the number of programs, the number of reads, the read temperature, the program temperature, and the time interval from programming to reading to form several sets of status parameters;

[0019] The memory device is processed according to the aforementioned sets of state parameters to put the memory device into different usage states;

[0020] Each set of state parameters corresponds to a usage state of the memory device.

[0021] In the above scheme, determining the first voltage offset corresponding to the first usage state according to a preset mapping relationship includes:

[0022] Compare the first usage state with each second usage state recorded in the mapping table;

[0023] The first voltage offset is obtained from the mapping table based on the comparison results.

[0024] In the above scheme, the state parameters include multiple parameters; the comparison of the first usage state with the second usage state recorded in the mapping table includes:

[0025] Each parameter in the state parameters of the first usage state is compared with each parameter in the state parameters of the second usage state respectively;

[0026] The step of obtaining the first voltage offset from the mapping table based on the comparison result includes:

[0027] If the comparison result includes a ratio of identical parameters between the first usage state and a certain second usage state, exceeding a first set threshold, then the second voltage offset corresponding to the second usage state is determined from the mapping table as the first voltage offset.

[0028] Alternatively, if the absolute value of the difference between the parameters corresponding to the state parameters of the first usage state and a certain second usage state in the comparison result does not exceed the second set threshold, the second voltage offset corresponding to the second usage state is determined from the mapping table as the first voltage offset.

[0029] Alternatively, if the comparison result includes a ratio of the number of identical parameters in the first usage state and a certain second usage state exceeding the first set threshold, and the absolute value of the difference between the parameters corresponding to each parameter in the first usage state and the second usage state does not exceed the second set threshold, then the second voltage offset corresponding to the second usage state is determined from the mapping table as the first voltage offset.

[0030] In the above scheme, the method further includes:

[0031] The erase count, programming count, read count, read temperature, programming temperature, and time interval between programming and reading are updated periodically.

[0032] The step of determining that the memory device is currently in a first usage state includes:

[0033] The latest updated erase count, programming count, read count, read temperature, programming temperature, and time interval from programming to reading are used as the first usage state.

[0034] In the above scheme, the method further includes:

[0035] Before determining that the memory device is currently in a first usage state, a set of hard read voltages is determined based on the preset reference read voltage and the read retry table RRT, wherein the set of hard read voltages includes: a default read voltage and multiple reread voltages; the multiple reread voltages have a certain offset from the preset reference read voltage;

[0036] Hard decision error correction is performed on the memory device based on the set of hard read voltages.

[0037] In the above scheme, performing the soft decision error correction on the memory device based on at least one set of soft read voltages includes:

[0038] The soft decision error correction is performed on the memory device gradually based on one of the multiple soft read voltages; the soft decision error correction is terminated when a successful soft decision error correction occurs and / or the number of soft decision error corrections is performed reaches a preset threshold.

[0039] In the above scheme, soft-decision error correction is performed on the memory device based on a certain set of soft read voltages, including:

[0040] Obtain a set of voltage offsets corresponding to a certain set of soft read voltages;

[0041] The set of voltage offsets is configured to the memory device so that the memory device obtains a certain set of soft read voltages based on the set of voltage offsets and the preset reference read voltage, and obtains a set of soft read data based on the set of soft read voltages;

[0042] Perform soft-decision error correction on the set of soft-read data.

[0043] Secondly, embodiments of this application also provide a memory controller coupled to one or more memory devices; the memory controller includes: a processor; wherein,

[0044] The processor is configured to: in response to a read error occurring in the memory device, determine that the memory device is currently in a first usage state; determine a first voltage offset corresponding to the first usage state according to a preset mapping relationship; and obtain a first read voltage used to perform a read operation on the memory device in the first usage state according to the preset reference read voltage and the first voltage offset; wherein the preset mapping relationship includes a correspondence between the usage state of the memory device and the voltage offset; and the voltage offset is an offset value relative to the preset reference read voltage.

[0045] In the above scheme, the memory controller further includes: memory;

[0046] The processor is further configured to: send a first read command to the memory device; receive the preset mapping relationship fed back by the memory device in response to the first read command; and cache the preset mapping relationship in the memory.

[0047] In the above scheme, the first voltage offset includes one or more; and the first read voltage includes one or more; the processor is further configured to: select at least one first read voltage as a soft read reference voltage for soft decision error correction; obtain a set of soft read voltages including the soft read reference voltage according to each soft read reference voltage and a preset offset rule; and perform the soft decision error correction on the memory device according to at least one set of soft read voltages.

[0048] In the above scheme, the preset mapping relationship includes a mapping table; the memory controller further includes: memory;

[0049] The processor is further configured to: send a second read command to the memory device; receive a read retry table (RRT) from the memory device in response to the second read command; cache the RRT in the memory; put the memory device into different usage states; in each usage state, traverse the RRTs in the memory, perform read operations on the memory device one by one, and obtain at least one voltage offset in the RRT corresponding to a read error meeting a preset condition; establish a correspondence between each usage state and the corresponding at least one voltage offset; and generate the mapping table based on each correspondence.

[0050] In the above scheme, the status parameters include at least one of the following: the number of erase cycles, the number of programming cycles, the number of read cycles, the read temperature, the programming temperature, and the time interval between programming and reading of the memory device; the processor is further configured to: assign values ​​to the number of erase cycles, the number of programming cycles, the number of read cycles, the read temperature, the programming temperature, and the time interval between programming and reading to form several sets of status parameters; and process the memory device according to the several sets of status parameters to put the memory device into different usage states; wherein each set of status parameters corresponds to one usage state of the memory device.

[0051] In the above scheme, the processor is further configured to: compare the first usage state with each second usage state recorded in the mapping table; and obtain the first voltage offset from the mapping table based on the comparison result.

[0052] In the above scheme, the processor is further configured to: perform a corresponding comparison between each parameter of the state parameters in the first usage state and each parameter of the state parameters in each second usage state;

[0053] Wherein, if the comparison result includes a ratio of identical parameters in the state parameters of the first usage state and a certain second usage state exceeding a first preset threshold, the second voltage offset corresponding to the second usage state is determined from the mapping table as the first voltage offset; or, if the comparison result includes an absolute value of the difference between the corresponding parameters in the state parameters of the first usage state and a certain second usage state not exceeding a second preset threshold, the second voltage offset corresponding to the second usage state is determined from the mapping table as the first voltage offset; or, if the comparison result includes a ratio of identical parameters in the state parameters of the first usage state and a certain second usage state exceeding the first preset threshold and an absolute value of the difference between the corresponding parameters in the state parameters of the first usage state and the second usage state not exceeding the second preset threshold, the second voltage offset corresponding to the second usage state is determined from the mapping table as the first voltage offset.

[0054] In the above scheme, the processor is further configured to: periodically update the number of erases, the number of programs, the number of reads, the read temperature, the program temperature, and the time interval between programming and reading in the memory; and retrieve the latest updated number of erases, the number of programs, the number of reads, the read temperature, the program temperature, and the time interval between programming and reading from the memory as the first usage state.

[0055] Thirdly, embodiments of this application also provide a memory system, including:

[0056] One or more memory devices; and

[0057] A memory controller, coupled to and configured to control the one or more memory devices; wherein...

[0058] The memory controller includes a processor configured to: in response to a read error occurring in the memory device, determine that the memory device is currently in a first usage state; determine a first voltage offset corresponding to the first usage state according to a preset mapping relationship; and obtain a first read voltage used to perform a read operation on the memory device in the first usage state according to the preset reference read voltage and the first voltage offset.

[0059] The preset mapping relationship includes the correspondence between the usage state of the memory device and the voltage offset; the voltage offset is relative to the preset reference read voltage.

[0060] In the above scheme, the memory device includes: a memory array and peripheral circuitry coupled to the memory array; wherein,

[0061] The peripheral circuitry includes control logic and registers; wherein,

[0062] The processor is further configured to: obtain a set of voltage offsets corresponding to one of a plurality of soft read voltages; and configure each of the voltage offsets in the set of voltage offsets into the register;

[0063] The control logic is configured to: access the register to obtain the set of voltage offsets; obtain a certain set of soft read voltages based on a preset reference read voltage and the set of voltage offsets; and gradually provide each soft read voltage in the certain set of soft read voltages to the selected word line corresponding to the selected memory cell in the memory array to obtain a corresponding set of soft read data.

[0064] The processor is also configured to perform soft-decision error correction on the set of soft-read data.

[0065] This application provides an operation method, a memory controller, and a memory system. The operation method includes: in response to a read error occurring in a memory device of the memory system, determining that the memory device is currently in a first usage state; determining a first voltage offset corresponding to the first usage state according to a preset mapping relationship; wherein the preset mapping relationship includes a correspondence between the usage state of the memory device and the voltage offset; the voltage offset is an offset value relative to a preset reference read voltage; and obtaining a first read voltage used to perform a read operation on the memory device in the first usage state based on the preset reference read voltage and the first voltage offset. The operation method provided in this application determines the first voltage offset corresponding to the first usage state of the memory device using a preset mapping relationship, and then obtains the first read voltage required to read the memory device based on these first voltage offsets and the preset reference read voltage. This method of obtaining a suitable read voltage is applicable to various types of memory systems, such as memory systems containing memory controllers without complex computing capabilities, and memory systems where the memory device does not have the function of finding a suitable read voltage, etc. Even memory systems with complex computing capabilities, such as memory controllers and / or memory devices, that have the function of finding a suitable read voltage can use the operation method provided in the embodiments of this application to determine the required read voltage. Because the operation is simple (for example, the voltage offset can be obtained by using a simple matching search operation), the read voltage that matches the actual application scenario can be obtained quickly. Attached Figure Description

[0066] In accompanying drawings that are not necessarily drawn to scale, the same reference numerals can describe similar components in different views. The same numbers with different letter suffixes can represent different instances of similar components. The accompanying drawings generally illustrate the various embodiments discussed in this document by way of example, not limitation.

[0067] Figure 1 A schematic diagram of an exemplary system with a memory system provided in an embodiment of this application;

[0068] Figure 2a A schematic diagram of an exemplary memory card with a memory system provided in an embodiment of this application;

[0069] Figure 2b A schematic diagram of an exemplary solid-state drive with a memory system provided in an embodiment of this application;

[0070] Figure 3 This is a schematic diagram of the structure of a memory controller provided in an embodiment of this application;

[0071] Figure 4 This is a schematic diagram of the structure of a memory device provided in an embodiment of this application;

[0072] Figure 5 A schematic diagram of an exemplary memory device including a memory array and peripheral circuitry, provided for an embodiment of this application;

[0073] Figure 6 An exemplary schematic diagram of soft decision error correction provided in an embodiment of this application;

[0074] Figure 7 A flowchart illustrating an operation method of a memory system provided in an embodiment of this application. Figure 1 ;

[0075] Figure 8 A schematic flowchart of an operation method for a memory system provided in an embodiment of this application is shown below;

[0076] Figure 9 A flowchart illustrating an operation method of a memory system provided in an embodiment of this application. Figure 3 ;

[0077] Figure 10 A flowchart illustrating an operation method of a memory system provided in an embodiment of this application. Figure 4 ;

[0078] Figure 11 An exemplary schematic diagram of a set of soft readout voltages provided in an embodiment of this application;

[0079] Figure 12A flowchart illustrating an operation method of a memory system provided in an embodiment of this application. Figure 5 ;

[0080] Figure 13 This is a schematic diagram of a memory controller provided in an embodiment of this application. Detailed Implementation

[0081] Exemplary embodiments of the present application will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present application are shown in the drawings, it should be understood that the present application may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided to provide a more thorough understanding of the present application and to fully convey the scope of the disclosure of the present application to those skilled in the art.

[0082] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this application. However, it will be apparent to those skilled in the art that this application can be practiced without one or more of these details. In other instances, to avoid confusion with this application, some technical features well-known in the art have not been described: that is, not all features of the actual embodiments described herein, nor well-known functions and structures are described in detail.

[0083] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0084] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," "coupled to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intermediate elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intermediate elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this application, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. When discussing a second element, component, region, layer, or portion, it does not imply that the application necessarily contains a first element, component, region, layer, or portion.

[0085] Spatial relation terms such as “below,” “under,” “below,” “below,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0086] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0087] In order to gain a more detailed understanding of the features and technical content of the embodiments of this application, the implementation of the embodiments of this application will be described in detail below with reference to the accompanying drawings. The accompanying drawings are for reference and illustration only and are not intended to limit the embodiments of this application.

[0088] Memory devices are storage devices used to store information in modern information technology. As a typical non-volatile memory device, 3D NAND (Not-And) memory devices have become the mainstream product in the storage market due to their high storage density, controllable production costs, suitable programming and erasing speeds, and retention characteristics. With the increase in the number of bits per memory cell and the number of stacking layers, the types of errors that occur during read operations on memory devices become increasingly complex.

[0089] Based on one or more of the above-mentioned problems, embodiments of this application provide an operation method for a memory system. By pre-storing a preset mapping relationship between the usage state of the memory device and the bias voltage in the memory controller, at least one offset voltage is determined. Then, at least one read voltage is obtained based on these voltage offsets. This eliminates the need for modules such as the memory controller to perform calculations to obtain a suitable read voltage, and also eliminates the need for the memory device to have the function of finding a suitable read voltage. It can quickly and accurately obtain a read voltage that matches the actual application scenario. If a suitable read voltage is used, data with high accuracy can be obtained. In this way, the decoding time of the read data by the decoder will be shortened, thereby improving the read speed.

[0090] The embodiments of this disclosure will be further described in detail below with reference to the accompanying drawings and specific examples.

[0091] Figure 1 This is a schematic diagram of an exemplary system with a memory system provided according to an embodiment of the present disclosure. Figure 1 In this context, system 100 can be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having a memory system therein. For example... Figure 1As shown, system 100 may include host 108 and memory system 102. Host 108 may include a processor, such as a central processing unit (CPU) or a system-on-chip (SoC), where the SoC may be, for example, an application processor (AP). Host 108 also includes at least one operating system (OS) that can typically manage and control the functions and operations performed in host 108. The OS enables interoperability between host 108 coupled to memory system 102 and users who need and use memory system 102. The OS may support functions and operations corresponding to user requests. For example, and not limited to, depending on whether host 108 is a removable host, OS may be classified as a general-purpose operating system and a mobile operating system. The general-purpose operating system may include personal operating systems and enterprise operating systems. The personal operating system may be an operating system, including Windows and Chrome, used for general purposes to support services; the enterprise operating system may be an operating system, including Windows Server, Linux, Unix, etc., dedicated to ensuring and supporting higher performance. The mobile operating system can refer to an operating system for services or functions related to mobility (such as power saving functions). Generally, a mobile operating system can be an operating system such as Android, iOS, or Windows Mobile. In some embodiments, the host 108 may include multiple OSes; correspondingly, the host 108 may run multiple operating systems associated with the memory system 102. In other embodiments, the host 108 translates a user's request into one or more commands and transmits the one or more commands to the memory system 102 so that the memory system 102 performs operations related to the one or more commands.

[0092] The memory system 102 is capable of responding to requests from the host 108, performing specific functions, or executing various internal operations. In some embodiments, the memory system 102 can store data accessed by the host 108. The memory system 102 can serve as the main memory system or auxiliary memory system of the host 108. The memory system 102 and the host 108 can be electrically connected and communicate with each other according to appropriate protocols. The memory system 102 can be implemented and packaged into different types of terminal electronic products, such as, and not limited to, solid-state drives (SSDs), multimedia cards (MMCs), embedded MMCs (eMMCs), miniature MMCs (RSMMCs), micro MMCs, secure digital cards (SDs), mini SDs, micro SDs, universal serial bus (USB) storage devices, universal flash memory (UFS) devices, compact flash memory (CF) cards, smart media (SM) cards, and memory sticks, etc.

[0093] In some embodiments, the memory system 102 may also be configured as part of, for example, a computer, an ultra-mobile PC (UMPC), a workstation, a netbook, a personal digital assistant (PDA), a portable computer, a network tablet, a tablet computer, a wireless telephone, a mobile phone, a smartphone, an e-book reader, a portable multimedia player (PMP), a portable game console, a navigation system, a black box, a digital camera, a digital multimedia broadcasting (DMB) player, a three-dimensional (3D) television, a smart television, a digital audio recorder, a digital audio player, a digital picture recorder, a digital picture player, a digital video recorder, a digital video player, a storage device configured for a data center, a device capable of transmitting and receiving information in a wireless environment, one of various electronic devices configured for a home network, one of various electronic devices configured for a computer network, one of various electronic devices configured for a telematics network, a radio frequency identification (RFID) device, or one of various components configured for a computing system.

[0094] Return as Figure 1 As shown, the memory system 102 may include one or more memory devices 104 and a memory controller 106. The memory controller 106 can respond to requests from the host 108 and control the memory devices 104. For example, the memory controller 106 can read data from the memory devices 104 and transfer the read data to the host 108; it can also receive data to be stored from the host 108 and store the data to be stored in the memory devices 104. In other words, the memory controller 106 can control the write (or programming) operations, read operations, erase operations, and background operations of the memory devices 104, etc. Furthermore, the memory system 102 can be implemented and packaged into different types of terminal electronic products. Figure 2aIn one example shown, the memory controller 106 and a single memory device 104 can be integrated into a memory card 202. The memory card 202 can include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 202 can also include a connection between the memory card 202 and a host computer (e.g., Figure 1 The host 108) is coupled to the memory card connector 204. In such a... Figure 2b In another example shown, the memory controller 106 and multiple memory devices 104 may be integrated into the SSD 206. The SSD 206 may also include a connection between the SSD 206 and a host (e.g., Figure 1 The SSD connector 208 is coupled to the host 108. In some embodiments, the storage capacity and / or operating speed of the SSD 206 is greater than the storage capacity and / or operating speed of the memory card 202.

[0095] Among them, such as Figure 3 As shown, the memory controller 106 may include a host I / F (or front-end interface) 301, a memory I / F (or back-end interface) 302, a processor 303, and memory 304. The aforementioned components 301, 302, 303, and 304 within the memory controller 106 can share internal transmission signals via an internal bus. In some embodiments, the host I / F 301 may interface with the memory system 102 in response to a protocol of the host 108, and the host I / F 301 may exchange transmission commands and data operations between the host 108 and the memory system 102. The host I / F 301 can process commands and data sent by the host 108 and may include at least one of the following: Universal Serial Bus (USB), Multimedia Card (MMC), High-Speed ​​Peripheral Component Interconnect (PCI). (e or PCIe), Small Computer System Interface (SCSI), Serial SCSI (SAS), Serial Advanced Technology Attachment (SATA), Parallel Advanced Technology Attachment (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), and Electronic Integrated Drive (IDE). In some embodiments, the host I / F301 is a component of the memory system 102 used to exchange data with the host 108, and can be implemented through firmware referred to as the host interface layer (HIL).

[0096] Memory I / F 302 can serve as an interface for transmitting commands and data between memory controller 106 and memory device 104, allowing memory controller 106 to control memory device 104 in response to requests transmitted from host 108. Memory I / F 302 can generate control signals for controlling memory device 104. In some embodiments, if memory device 104 is NAND flash memory, memory I / F 302 can write data to or read data from memory device 104 under the control of processor 303. Memory I / F 302 can process commands and data between memory controller 106 and memory device 104, such as operations of the NAND flash interface, particularly operations between memory controller 106 and memory device 104. According to embodiments, memory I / F 302 can be implemented as a component for exchanging data with memory device 104 via firmware referred to as the Flash Interface Layer (FIL).

[0097] Processor 303 may be implemented as a microprocessor or a central processing unit (CPU). Memory system 102 may include one or more processors 303. Processor 303 may control all operations of memory system 102. By way of example and not limitation, processor 303 may control programming or reading operations of memory device 104 in response to write or read requests from host 108. According to embodiments, processor 303 may use or run firmware to control all operations of memory system 102. In this disclosure, firmware may be referred to as a flash translation layer (FTL). FTL may act as an interface between host 108 and memory device 104. Host 108 may transmit requests related to write and read operations to memory device 104 via FTL. For example, memory controller 106 uses processor 303 when performing an operation requested from host 108 in memory device 104. Processor 303 coupled to memory device 104 may process instructions or commands related to commands from host 108. The memory controller 106 can perform foreground operations such as command operations corresponding to commands input from the host 108, such as programming operations corresponding to write commands, reading operations corresponding to read commands, erasing / discarding operations corresponding to erase / discard commands, and parameter setting operations corresponding to setting parameter commands or setting feature commands with setting commands.

[0098] In another example, memory controller 106 may perform background operations on memory device 104 via processor 303. By way of example and not limitation, these background operations may include garbage collection (GC) operations, wear leveling (WL) operations, map sweeping operations, and bad block management operations that check or search for bad blocks. Garbage collection operations may include copying and processing data stored in one memory block of memory device 104 to another memory block. Wear leveling operations may include exchanging and processing stored data between memory blocks of memory device 104. Map sweeping operations may include storing mapped data stored in memory controller 106 in memory blocks of memory device 104. Bad block management operations may include checking and processing bad blocks in memory blocks of memory device 104. Memory controller 106 may respond to operations that access memory blocks of memory device 104, wherein accessing memory blocks of memory device 104 may include foreground or background operations performed on memory blocks of memory device 104.

[0099] Memory 304 may be the working memory of memory controller 106, configured to store data used to drive memory controller 106. More specifically, memory 304 may store firmware driven by processor 303 and data (e.g., metadata) required to drive the firmware when memory controller 106 controls memory device 104 in response to a request from host 108. Memory 304 may also be a buffer memory of memory controller 106, configured to temporarily store write data transferred from host 108 to memory device 104 and read data transferred from memory device 104 to host 108. Memory 304 may include program memory, data memory, write buffer / cache, read buffer / cache, data buffer / cache, and mapped buffer / cache for storing write and read data. Memory 304 may be implemented using volatile memory. Memory 304 may be implemented using static random access memory (SRAM), dynamic random access memory (DRAM), or both.

[0100] Although Figure 3 The diagram shows that memory 304 is included in memory controller 106, but this disclosure is not limited thereto. In embodiments, memory 304 may be included outside of memory controller 106, and memory controller 106 may input and output data to memory 304 via a separate memory interface (not shown).

[0101] The error correction (ECC) module 305 includes an encoding unit 3051 and a decoding unit 3052. The encoding unit 3051 performs an encoding operation, such as LDPC, on the data to be programmed into the semiconductor memory device 104 and outputs data including additional parity bits. The parity bits can be stored in the semiconductor memory device 104. The decoding unit 3052 performs error correction decoding on data read from the semiconductor memory device 104; it can also determine whether the error correction decoding was successful and output a command signal based on the determination result; it can also use the parity bits generated by the LDPC encoding operation to correct erroneous bits in the data.

[0102] Here, although Figure 3 The error correction module 305 is shown to be included in the memory controller 106, but this disclosure is not limited thereto. In an embodiment, the error correction module 305 may be included outside the memory controller 106, and the memory controller 106 may communicate with the error correction module 305 via a separate interface (not shown).

[0103] See back Figure 1 The memory device 104 may include non-volatile memory, which retains stored data even when no power is supplied. The memory device 104 may also include volatile memory. The device 104 can store data provided from the host 108 via write operations; the memory device 104 can also provide the stored data to the host 108 via read operations. In embodiments of this disclosure, the memory device 104 may include any disclosed memory, such as volatile memory devices of dynamic random access memory (DRAM) and static RAM (SRAM), or non-volatile memory devices such as read-only memory (ROM), mask ROM (MROM), programmable ROM (PROM), erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), ferroelectric RAM (FRAM), phase-change RAM (PRAM), magnetoresistive RAM (MRAM), resistive RAM (RRAM or ReRAM), and flash memory (e.g., three-dimensional NAND flash memory).

[0104] To illustrate memory devices using 3D NAND flash memory as an example, see [link to documentation]. Figure 4 The diagram illustrates a schematic circuit diagram of an exemplary memory device 400 including peripheral circuitry according to some aspects of this disclosure. The memory device 400 may be... Figure 1An example of memory device 104 is provided. Memory device 400 may include memory array 401 and peripheral circuitry 402 coupled to memory array 401. Taking memory array 401 as an example of a three-dimensional NAND-type memory array, memory cells 406 are provided in the form of an array of NAND memory strings 408, each NAND memory string 408 extending vertically above a substrate (not shown). In some embodiments, each NAND memory string 408 includes a plurality of memory cells 406 coupled in series and stacked vertically. Each memory cell 406 may hold a continuous analog value, such as voltage or charge, depending on the number of electrons trapped in the region of memory cell 406. Each memory cell 406 may be a floating-gate type memory cell including a floating-gate transistor, or a charge-trapping type memory cell including a charge-trapping transistor.

[0105] In some implementations, each memory cell 406 is a single-level cell (SLC) having two possible memory states and thus capable of storing one bit of data. For example, a first memory state "0" may correspond to a first voltage range, and a second memory state "1" may correspond to a second voltage range. In some implementations, each memory cell 406 is a multi-level cell (MLC) capable of storing more than one bit of data in more than four memory states. For example, an MLC may store two bits per cell, three bits per cell (also known as a three-bit cell (TLC), a four-bit cell (QLC), or five bits per cell (also known as a five-bit cell (PLC)). Each MLC may be programmed to take a range of possible nominal stored values. In one example, if each MLC stores two bits of data, the MLC can be programmed to take one of three possible programming levels from the erase state by writing one of three possible nominal storage values ​​to the cell, with a fourth nominal storage value that can be used for the erase state.

[0106] like Figure 4As shown, each NAND memory string 408 may include a lower select gate (BSG) 410 at its source end and an upper select gate (TSG) 412 at its drain end. BSG 410 and TSG 412 can be configured to activate the selected NAND memory string 408 during read and program operations. In some embodiments, the sources of NAND memory strings 408 within the same memory block 404 are coupled via a common source line (SL) 414 (e.g., a common SL). In other words, according to some embodiments, all NAND memory strings 408 within the same memory block 404 have an array common source (ACS). According to some embodiments, the TSG 412 of each NAND memory string 408 is coupled to a corresponding bit line (BL) 416, from which data can be read or written via an output bus (not shown). In some implementations, each NAND memory string 408 is configured to be selected or deselected by applying a selection voltage (e.g., higher than the threshold voltage of the transistor having TSG 412) or a deselection voltage (e.g., 0V) to the corresponding TSG 412 via one or more TSG lines 413 and / or by applying a selection voltage (e.g., higher than the threshold voltage of the transistor having BSG 410) or a deselection voltage (e.g., 0V) to the corresponding BSG 410 via one or more BSG lines 415.

[0107] like Figure 4 As shown, NAND memory strings 408 can be organized into multiple memory blocks 404, each of which may have a common source line 414 (e.g., coupled to ground). In some implementations, each memory block 404 is the basic data unit for an erase operation, i.e., all memory cells 406 on the same memory block 404 are erased simultaneously. To erase memory cells 406 in a selected memory block 404, an erase voltage (Vers) (e.g., a high positive voltage (e.g., 20V or higher)) can be used to bias and couple the source line 414 of the selected memory block 404 and the unselected memory blocks 404 on the same plane as the selected memory block 404. It should be understood that in some examples, erase operations can be performed at the half-block level, at the quarter-block level, or at a level with any suitable number of memory blocks or any suitable fraction of memory blocks. Memory cells 406 of adjacent NAND memory strings 408 can be coupled via word lines 418, which select which row of memory cells 406 is affected by read and program operations.

[0108] Return to reference Figure 4Peripheral circuitry 402 can be coupled to memory array 401 via bit line 416, word line 418, source line 414, BSG line 415, and TSG line 413. Peripheral circuitry 402 can include any suitable analog, digital, and mixed-signal circuitry to facilitate operation of memory array 401 by applying voltage and / or current signals to each target memory cell 406 via bit line 416, word line 418, source line 414, BSG line 415, and TSG line 413, and by sensing voltage and / or current signals from each target memory cell 406. Peripheral circuitry 402 can include various types of circuitry formed using metal-oxide-semiconductor (MOS) technology. For example, Figure 5 Some exemplary peripheral circuitry is shown. Peripheral circuitry 402 includes a page buffer / sensor amplifier 504, a column decoder / bit line driver 506, a row decoder / word line driver 508, a voltage generator 510, control logic 512, a register 514, an interface 516, and a data bus 518. It should be understood that in some examples, additional peripheral circuitry may be included. Figure 6 Additional peripheral circuitry not shown.

[0109] Page buffer / sensor amplifier 504 can be configured to read data from memory array 401 and program (write) data to memory array 401 according to control signals from control logic 512. In one example, page buffer / sensor amplifier 504 can store programming data to be programmed into memory array 401 (write data). In another example, page buffer / sensor amplifier 504 can perform a programming verification operation to ensure that data has been correctly programmed into memory cell 406 coupled to selected word line 418. In yet another example, page buffer / sensor amplifier 504 can also sense a low-power signal from bit line 416 representing a data bit stored in memory cell 406 and amplify a small voltage swing to a recognizable logic level during read operations. Column decoder / bit line driver 506 can be configured to be controlled by control logic 512 and select one or more NAND memory strings 408 by applying a bit line voltage generated from voltage generator 510.

[0110] The row decoder / word line driver 508 can be configured to be controlled by control logic 512 and to select / deselect memory blocks 404 of memory array 401 and select / deselect word lines 418 of memory blocks 404. The row decoder / word line driver 508 can also be configured to drive word lines 418 using word line voltages generated from voltage generator 510. In some embodiments, the row decoder / word line driver 508 can also select / deselect and drive BSG line 415 and TSG line 413. The row decoder / word line driver 508 can be configured to perform programming operations on memory cells 406 coupled to one or more selected word lines 418. The voltage generator 510 can be configured to be controlled by control logic 512 and to generate word line voltages (e.g., read voltage, programming voltage, pass voltage, channel boost voltage, verification voltage, etc.), bit line voltages, and source line voltages to be supplied to memory array 401.

[0111] Control logic 512 can be coupled to various circuits in the peripheral circuitry described above, such as voltage generator 510, row decoder / word line driver 508, etc., and is configured to control the operation of each circuit. Register 514 can be coupled to control logic 512 and includes a status register, a command register, and an address register for storing status information, command opcodes (OP codes), and command addresses for controlling the operation of each peripheral circuit. Interface 516 can be coupled to control logic 512 and acts as a control buffer to buffer control commands received from the host (not shown) and relay them to control logic 512, as well as to buffer status information received from control logic 512 and relay it to the host. Interface 516 can also be coupled to column decoder / bit line driver 506 via data bus 518 and acts as a data I / O interface and data buffer to buffer data and relay it to or from memory array 401.

[0112] The memory devices in the embodiments of this application include, but are not limited to, three-dimensional NAND type memory. For ease of understanding, a three-dimensional (3D) NAND type memory will be used as an example for explanation.

[0113] In 3D NAND flash memory devices, as the number of bits per memory cell and the number of stacked layers increase, the types of errors become increasingly complex. The error correction process can include: first, hard-decision error correction; then, if that fails, soft-decision error correction; and finally, if that fails again, independent NAND redundancy array error correction. Among these, the soft read reference voltage is particularly important for maximizing the effectiveness of soft-decision error correction. The information input to the next stage decoder for soft-decision error correction can be the log-likelihood ratio (LLR), also known as soft data. This soft data is probabilistic information used to determine the reliability of a particular read data, measuring the reliability of the decision. Here, the particular read data is the reference read data, and the read voltage used to obtain this reference read data is the soft read reference voltage.

[0114] like Figure 6 As shown, assume the first read data read using the first read voltage is 100; the second read data read using the second read voltage is 110; correspondingly, the soft data is 010. In this case, if data is read based on the first read data, then a bit in the soft data that is "0" indicates that the reliability of that bit in the first read data is relatively high; in other words, that bit is judged to be relatively close to the truth. For example, in... Figure 6 In the first read data, the leftmost bit is "1", while the corresponding bit in the soft data is "0". Therefore, this bit has high reliability, i.e., a strong "1". Similarly, if the middle bit in the first read data corresponds to a "1" in the soft data, then the middle bit has weak reliability, i.e., a weak "1" or "0". The rightmost bit in the first read data is a strong "0". The analysis is similar when reading data based on the second read data, and will not be elaborated further.

[0115] However, many memory controllers used in memory systems lack a Digital Signal Processing (DSP) engine, making it impossible for them to perform complex calculations in their hardware to obtain the optimal soft read reference voltage. For data reading, they rely more on firmware (FW) algorithms to recover data from the memory device, maintaining the storage medium in a relatively good state, hoping to correctly read the data through hard error correction before soft error correction; or relying on subsequent RAID error correction to rebuild the data. The industry cannot resolve UECC issues in some harsh application scenarios before rebuilding. This leads to the rebuild process being initiated in harsh scenarios, causing a sharp drop in read performance.

[0116] To address the issue of finding the optimal soft read reference voltage, in some embodiments, a DSP engine is added to the memory controller of the memory system, and the optimal soft read reference voltage is calculated using an algorithm. In other embodiments, the memory device of the memory system can employ a memory chip with an optimal read voltage finding function, meaning the memory device itself finds the optimal soft read reference voltage. Furthermore, given one or more fixed read voltages as the soft read reference voltage for soft decision error correction, the read voltage in more severe scenarios not covered by the FW algorithm can be selected as the soft read reference voltage.

[0117] To address the issue of finding the optimal soft read reference voltage, embodiments of this application provide an operation method for a memory system. By establishing a pre-defined mapping relationship, at least one first read voltage is obtained as a soft read reference voltage for subsequent soft decision error correction (soft decoding).

[0118] Specifically, see Figure 7 , Figure 7 This is a flowchart illustrating the operation method of the memory system provided in an embodiment of this application.

[0119] Specifically, the operation method may include:

[0120] Step 701: In response to a read error occurring in the memory device of the memory system, determine that the memory device is currently in a first usage state;

[0121] Step 702: Determine the first voltage offset corresponding to the first usage state according to a preset mapping relationship; wherein, the preset mapping relationship includes the correspondence between the usage state of the memory device and the voltage offset; the voltage offset is an offset value relative to a preset reference read voltage;

[0122] Step 703: Obtain the first read voltage used to perform a read operation on the memory device in the first usage state based on the preset reference read voltage and the first voltage offset.

[0123] It should be noted that, in practice, the error correction process is only initiated when a read operation is performed on the memory device and an error occurs in the read data. Therefore, the operation method of this application embodiment should also be triggered only when an error occurs in the read data of the memory device. That is, in response to a read error in the memory device, it is determined that the memory device is currently in a first usage state. Then, a first voltage offset is obtained according to a preset mapping relationship and the first usage state, and subsequently, a first read voltage is obtained. The first voltage offset may include one or more; correspondingly, the first read voltage may also include one or more. In other words, one first voltage offset corresponds to one first read voltage. Then, at least one first read voltage is selected as the subsequent soft read reference voltage for subsequent soft decision error correction.

[0124] The operation method provided in this application provides for obtaining a first read voltage and then a soft read reference voltage. Its advantages include: it eliminates the need for the memory controller in the memory system to have a DSP engine, reducing the additional costs associated with using a special memory controller; it is compatible with a wider range of memory controllers; and it provides a shorter time to obtain the soft read reference voltage. Furthermore, it eliminates the need for the storage medium (such as NAND) in the memory device to have an automatic function to find the optimal read voltage, allowing for compatibility with more storage media and a shorter time to obtain the soft read reference voltage. Additionally, the embodiments in this application establish a preset mapping relationship based on the corresponding usage state of the memory device, which better matches actual application scenarios.

[0125] The following details the implementation of the operation method provided in the embodiments of this application.

[0126] See back Figure 1 In the process described above, a read error in the memory device can refer to an error occurring in the data being read during the process of reading data from the memory device. When a read error occurs in the memory device, the memory controller in the memory system can perform error correction decoding (such as using the aforementioned...). Figure 3 The error correction (ECC) module 305 in the memory performs error correction decoding to correct errors that occur in the read data. The application scenarios of the operation method provided in this application embodiment include, but are not limited to, selecting a soft read reference voltage when performing soft-decision error correction after a read error occurs in the memory device. For example, the application scenarios of this application embodiment may also include selecting the read voltage during normal read operations, and selecting the read voltage during hard-decision error correction, etc.

[0127] Here, the usage state of the memory device may refer to the usage state of its contained storage medium (e.g., NAND medium), or more specifically, the usage state of the storage medium contained in the memory device when it is in the current codeword to be decoded (CW, CodeWord) in the soft decision error correction process (which can be the soft read data in the soft decision error correction process, or the codeword to be decoded after being flipped in a certain iteration).

[0128] The usage status mentioned can be measured by parameters such as the number of erase cycles (EC) of the storage medium in the memory device, the time between programming and the first read (Program to Read Time), the number of read cycles (ReadCount), and the programming / read temperature. These will be explained in detail later.

[0129] Here, the preset mapping relationship can refer to the correspondence between the usage state of the memory device and the voltage offset established through a large number of experiments or empirical records. The voltage offset can refer to the offset value relative to a preset reference read voltage, which can be the reference voltage of a read retry table (RRT). The preset mapping relationship provided in this application embodiment includes, but is not limited to, a mapping table.

[0130] It should be noted that the RRT is a table containing multiple voltage offsets, each of which is relative to a preset reference read voltage. These voltage offsets are implemented through hardware circuitry in the memory device; for example, registers within the memory device can store one or more of these voltage offsets. The memory controller can change the values ​​of the voltage offsets by configuring these registers in the memory device.

[0131] In other words, the read voltage application process in a certain read operation may include: the memory device responding to the read command determines the required voltage offset; then, the required voltage offset is obtained from the register of the memory device; then, the voltage offset is transmitted to the voltage generator, which superimposes the voltage offset with a preset reference read voltage (including the superposition of signs, that is: if the voltage offset is negative, the final read voltage is less than the preset reference read voltage) to obtain the required read voltage, and then applies it to the corresponding word line.

[0132] In other words, the voltage generator stores the corresponding preset reference read voltage, and the voltage offset is transmitted between the memory controller and the memory device. Finally, the voltage offset is superimposed on the preset reference read voltage value in the voltage generator to apply the required read voltage to the corresponding word line.

[0133] For example, as shown in Table 1, the RRT is the RRT corresponding to a TLC type storage cell provided in the embodiments of this application.

[0134] Each column in Table 1 represents a set of voltage offsets, Rd1 to Rd7, that distinguishes adjacent programming states relative to the corresponding preset reference read voltage.

[0135] It should be noted that since TLC type memory cells have 8 data states, they can be distinguished using 7 read voltages, which is why Table 1 has 7 columns.

[0136] The set of voltage offsets described above may include a positive offset that increases in the direction of a voltage greater than the preset reference voltage, and a negative offset that decreases in the direction of a voltage less than the preset reference voltage.

[0137] For example, for Rd7, +V1, +V2, +V3, and +V4 are positive offsets, where the values ​​of V1, V2, V3, and V4 increase sequentially; while -V5 to -V11 are negative offsets, where the values ​​of V5 to V11 decrease sequentially.

[0138] Table 1 RRT

[0139]

[0140] Based on the aforementioned definitions of RRT and preset mapping relationships, for obtaining the preset mapping relationship, please refer to [link to documentation]. Figure 8 As shown, the preset mapping relationship includes a mapping table; the method may further include:

[0141] Step 801: Put the memory device into different usage states;

[0142] Step 802: In each usage state, obtain the Read Retry Table (RRT) from the memory device; traverse the RRT, perform read operations on the memory device one by one, and obtain at least one voltage offset in the RRT corresponding to the read error meeting the preset conditions; establish the correspondence between each usage state and the corresponding at least one voltage offset;

[0143] Step 803: Generate the mapping table according to each correspondence.

[0144] It should be noted that the term "putting the memory device in different usage states" can refer to processing the memory device (such as reading, erasing, and writing) during experiments to establish a preset mapping relationship. Depending on the different state parameters of the memory device during reading, erasing, and writing, the memory device will be put in different usage states.

[0145] In some embodiments, the status parameters include at least one of the following: erase count, programming count, read count, read temperature, programming temperature, and time interval between programming and reading; for step 801, it may include:

[0146] Assign values ​​to the number of erases, the number of programs, the number of reads, the read temperature, the program temperature, and the time interval from programming to reading to form several sets of status parameters;

[0147] The memory device is processed according to the aforementioned sets of state parameters to put the memory device into different usage states;

[0148] Each set of state parameters corresponds to a usage state of the memory device.

[0149] It should be noted that, as described above, the usage state of a memory device can be represented by the erase count, programming count, read count, read temperature, programming temperature, and the time interval between programming and reading. Different combinations of these state parameters represent different usage states of the memory device. Therefore, we can first assign values ​​to the erase count, programming count, read count, read temperature, programming temperature, and the time interval between programming and reading to form several sets of state parameters, which represent the corresponding usage states of the memory device under these parameters. It should be understood that putting the memory device into different usage states is not simply a matter of configuring the state parameters into the memory device; rather, it requires processing the memory device (e.g., reading, writing, erasing, etc.) to make the memory device's state parameters reach the assigned values.

[0150] In other words, first, values ​​are assigned to the status parameters (at least one of the erase count, programming count, read count, read temperature, programming temperature, and the time interval between programming and reading), forming several sets of status parameters. Each set of status parameters corresponds to a usage state of the memory device. Then, the memory device is processed, such as the aforementioned read, write, and erase processes, so that the memory device reaches one of the sets of status parameters, thus indicating that the memory device has reached the usage state corresponding to that set of status parameters. Afterward, the memory device is processed sequentially, sequentially bringing the memory device to each of the several sets of status parameters, thereby ensuring that the memory device reaches each usage state.

[0151] In practical applications, the larger the values ​​of each parameter in the status parameters, the more severe the application scenario corresponding to that usage state. In more severe application scenarios, the memory device will encounter more read errors when performing read operations. Furthermore, it should be understood that the usage state of the memory device gradually deteriorates; therefore, processing the memory device to place it in different usage states follows this principle sequentially.

[0152] When the memory device is in each usage state, the Reference Time Limit (RRT) is obtained from the memory device. Then, the RRT is traversed, and read operations are performed on the memory device one by one to obtain at least one voltage offset in the corresponding RRT when a read error meets a preset condition. Afterward, a correspondence is established between each usage state and the corresponding at least one voltage offset; each correspondence constitutes the mapping table. That is, the mapping table contains each of the aforementioned correspondences. This mapping table can be stored in the memory controller or the memory device, depending on the size of the mapping table.

[0153] Here, the RRT can be stored in the storage medium of the memory device. When using the RRT, the memory controller needs to read the RRT from the memory device. The so-called traversal of the RRT and performing read operations on the memory device one by one means that each voltage offset in the RRT table is superimposed with a preset reference read voltage to form a read voltage, and then the memory device is read.

[0154] It should be understood that, as shown in Table 1, there are 7 sets of voltage offsets, Rd1 to Rd7, corresponding to the TLC type memory cells; in each set, at least one voltage offset is obtained when a read error meets a preset condition. After obtaining at least one voltage offset in each set, a correspondence is established with the corresponding usage state, and this correspondence is one entry in the mapping table.

[0155] Here, "meeting the preset condition for read errors" can mean that the number of read errors is no greater than a certain threshold, or that the number of read errors is minimal. For example, under a certain voltage bias, if the number of read errors occurring in the memory device is no greater than a certain threshold or the number of read errors is minimal, then that voltage bias is considered to meet the preset condition for read errors. In practical applications, the number of error bits contained in the read data can be measured using a syndrome weight value, and the larger the syndrome weight value, the more error bits the read data contains. Therefore, in this embodiment, "meeting the preset condition for read errors" can also be determined by whether the voltage bias is the voltage bias that meets the preset condition for read errors when reading the memory device at a certain voltage bias, where the syndrome weight value corresponding to the read data is the smallest or the syndrome weight value is less than a certain threshold.

[0156] It should be noted that even with minimal read errors, the voltage offset that satisfies the preset conditions may include multiple values. This is because there may be a value in the RRT that results in the minimum voltage offset for the memory device to have read errors. The thresholds described earlier can be set by the designer, for example, thresholds of 1, 2, 3, etc.

[0157] For example, as shown in Table 2, a mapping table.

[0158] In the mapping table in Table 2, RRT is the voltage offset table corresponding to TLC type memory cells as shown in Table 1. The NAND state is also a specific example of the storage medium of the memory device described above. The usage state of NAND is characterized by the number of programming cycles, the number of read cycles, the programming temperature / read temperature, and the time from programming to reading; RR-1, RR-2, RR-3, ..., RR-n are at least one voltage offset corresponding to the usage state described above.

[0159] It should be noted that the one usage state described in Table 2 corresponding to one voltage offset is only an example. In actual use, as described above, one usage state can correspond to at least one voltage offset.

[0160] Table 2 Mapping Table

[0161]

[0162] After obtaining the aforementioned mapping table, in some embodiments, the method may further include:

[0163] The erase count, programming count, read count, read temperature, programming temperature, and time interval between programming and reading are updated periodically.

[0164] The step of determining that the memory device is currently in a first usage state includes:

[0165] The latest updated erase count, programming count, read count, read temperature, programming temperature, and time interval from programming to reading are used as the first usage state.

[0166] This describes the steps for obtaining the first usage state of a memory device. The memory device updates the values ​​in the recorded state parameters at regular time intervals, thus recording the new usage state of the memory device. Then, the latest recorded state parameter is retrieved to determine the first usage state of the memory device.

[0167] After obtaining the mapping table and the first usage state, in some embodiments, for step 703, such as Figure 9 As shown, it may include:

[0168] Step 901: Compare the first usage state with each second usage state recorded in the mapping table;

[0169] Step 902: Obtain the first voltage offset from the mapping table based on the comparison results.

[0170] In some embodiments, the state parameters include multiple parameters; for step 901, it may include:

[0171] Each parameter in the state parameters of the first usage state is compared with each parameter in the state parameters of the second usage state respectively;

[0172] For step 902, it may include:

[0173] If the comparison result includes a ratio of identical parameters between the first usage state and a certain second usage state, exceeding a first set threshold, then the second voltage offset corresponding to the second usage state is determined from the mapping table as the first voltage offset.

[0174] Alternatively, if the absolute value of the difference between the parameters corresponding to the state parameters of the first usage state and a certain second usage state in the comparison result does not exceed the second set threshold, the second voltage offset corresponding to the second usage state is determined from the mapping table as the first voltage offset.

[0175] Alternatively, if the comparison result includes a ratio of the number of identical parameters in the first usage state and a certain second usage state exceeding the first set threshold, and the absolute value of the difference between the parameters corresponding to each parameter in the first usage state and the second usage state does not exceed the second set threshold, then the second voltage offset corresponding to the second usage state is determined from the mapping table as the first voltage offset.

[0176] It should be noted that the aforementioned status parameters may include at least one of the following: the number of erases, the number of programs, the number of reads, the read temperature, the program temperature, and the time interval between programming and reading for the memory device described above. When multiple status parameters are included, each parameter in the status parameters corresponding to the first usage state is compared with each parameter in the status parameters of each second usage state recorded in the mapping table. Specifically, the number of erases in the first usage state is compared with the number of erases in each second usage state; the number of programs in the first usage state is compared with the number of programs in each second usage state; and so on. Here, the usage state of the memory device recorded in the mapping table is recorded as the second usage state to distinguish it from the current first usage state of the memory device. It should be understood that "first" and "second" here are not a limitation on the number, but rather different descriptions used to distinguish different scenarios.

[0177] Subsequently, based on the comparison results, the first voltage offset is obtained from the mapping table. Specifically, if the comparison results include: the ratio of identical parameters in the state parameters of the first usage state and a certain second usage state exceeds a first set threshold, the second voltage offset corresponding to the second usage state is determined as the first voltage offset; or, if the comparison results include: the absolute value of the difference between the parameters in the state parameters of the first usage state and a certain second usage state and the corresponding parameters in the state parameters of the second usage state does not exceed a second set threshold, the second voltage offset corresponding to the second usage state is determined as the first voltage offset; or, if the comparison results include: the ratio of identical parameters in the state parameters of the first usage state and a certain second usage state exceeds the first set threshold and the absolute value of the difference between the parameters corresponding to the state parameters of the first usage state and the second usage state does not exceed the second set threshold, the second voltage offset corresponding to the second usage state is determined from the mapping table as the first voltage offset.

[0178] Here, the statement that the ratio of the number of parameters with the same values ​​in the state parameters of the first usage state and a certain second usage state exceeds the first set threshold can mean that the ratio of the number of parameters in the state parameters of the first usage state that have the same values ​​as the parameters in the state parameters of the second usage state to the number of parameters in the state parameters exceeds the first set threshold.

[0179] For example, suppose the status parameters include a total of 6 parameters: the number of erases, the number of programs, the number of reads, the read temperature, the program temperature, and the time interval between programming and reading. And suppose the first set threshold is 2 / 3, that is, when the values ​​of 4 or more parameters in the status parameters of the first usage state are the same as the values ​​of the status parameters in the second usage state, then the second voltage offset corresponding to the second usage state is determined as the first offset voltage corresponding to the first usage state.

[0180] In another case, the statement that the absolute value of the difference between the state parameters of the first usage state and the corresponding parameters of a certain second usage state does not exceed the second set threshold may mean that the absolute value of the difference between the value of each parameter in the first usage state and the value of the corresponding parameter in a certain second usage state does not exceed the second set threshold.

[0181] For example, suppose the status parameters include: the number of erases, the number of programs, the number of reads, the read temperature, the program temperature, and the time interval between programming and reading of the memory device, a total of 6 parameters. And suppose the first set threshold is 1, that is, the absolute value of the difference between the number of erases in the first use state and the number of erases in a certain second use state cannot exceed 1, the number of programs cannot exceed 1, the number of reads cannot exceed 1, the read temperature cannot exceed 1 degree, the program temperature cannot exceed 1 degree, and the time interval between programming and reading cannot exceed 1 (a suitable time unit such as a second, microsecond, or nanosecond).

[0182] Another scenario, where the ratio of identical parameters in the first usage state and a certain second usage state exceeds the first set threshold and the absolute value of the difference between the parameters corresponding to each parameter in the first usage state and the second usage state does not exceed the second set threshold, can mean that when the ratio of identical parameters in the state parameters of a certain second usage state included in the mapping table exceeds the first set threshold and the absolute value of the difference between the parameters corresponding to each parameter does not exceed the second set threshold, the second voltage offset corresponding to the second usage state is determined as the first voltage offset.

[0183] It should be noted that, in either case, the second voltage offset may include one or more voltage offsets.

[0184] After obtaining the first voltage offset, step 703 may include: calculating the preset reference reading voltage with each first voltage offset to obtain at least one first reading voltage in the first use state.

[0185] It should be noted that, as shown in Table 1 above, the calculations here are also signed. In other words, the obtained first reading voltage can be greater than, less than, or even equal to the preset reference reading voltage. This depends entirely on whether the first voltage offset is positive or negative. In fact, when the first voltage offset is 0, the first reading voltage is equal to the preset reference reading voltage.

[0186] After obtaining one or more first read voltages, in some embodiments, such as Figure 10 As shown, the method may further include:

[0187] Step 1001: Select at least one first read voltage as the soft read reference voltage for soft decision error correction;

[0188] Step 1002: Based on each of the soft read reference voltages and the preset offset rule, obtain a set of soft read voltages that include the soft read reference voltages;

[0189] Step 1003: Perform the soft decision error correction on the memory device based on at least one set of soft read voltages.

[0190] It should be noted that after obtaining one or more first read voltages according to the preceding method, during soft decision error correction, at least one first read voltage can be selected as the soft read reference voltage for soft decision error correction (i.e., step 1001), and soft decision error correction can be performed once or multiple times. After obtaining one or more soft read reference voltages, a set of soft read voltages containing the reference read voltages is obtained according to each soft read reference voltage and a preset offset rule (i.e., step 1002); then, soft decision error correction is performed on the memory device according to at least one set of soft read voltages (step 1003) to obtain the correct read data.

[0191] Here, the preset offset rule in step 1002 can refer to offsetting at predetermined intervals around the soft read reference voltage to obtain multiple soft read voltages. For example, Figure 11 As shown, the reading voltage at the center is the soft read reference voltage; the reading voltages on its left and right are the reading voltages set according to a preset offset rule. A set of soft read voltages can refer to both the soft read reference voltage and the reading voltages on either side of it. It should be noted that here, a set of soft read voltages is formed by offsetting a certain amount to the left and right of the soft read reference voltage as the center. In practical applications, a set of soft read voltages can include more voltages; the specific settings depend on the specific circumstances and will not be detailed here.

[0192] In some embodiments, step 1003 may include:

[0193] The soft decision error correction is performed on the memory device gradually based on one of the multiple soft read voltages; the soft decision error correction is terminated when a successful soft decision error correction occurs and / or the number of soft decision error corrections is performed reaches a preset threshold.

[0194] It should be noted that in practical applications, all the obtained soft read voltages can be used to perform soft decision error correction on the memory device, or only one or a few soft read voltages can be used to obtain correct read data. That is, when performing soft decision error correction on the memory device based on multiple soft read voltages, soft decision error correction is performed progressively based on a specific soft read voltage from the multiple sets until a successful soft decision error occurs and / or the number of soft decision error correction executions reaches a preset threshold, at which point the soft decision error correction process ends. The preset threshold can be set manually, and its value can be the same as the number of soft read data sets. In other words, when performing soft decision error correction on the memory device, if a successful soft decision error occurs and / or the number of soft decision error correction executions reaches the preset threshold, soft decision error correction stops, either outputting correct read data or proceeding to the next stage of error correction. Alternatively, if a successful soft decision error occurs and the number of soft decision error correction executions reaches the preset threshold, correct read data will also be output, and the entire error correction process will stop.

[0195] The process of each soft-decision error correction is similar, differing only in the soft read reference voltage and reference read data used. The following description focuses on a single soft-decision error correction instance to illustrate the soft-decision decoding process. That is, performing soft-decision error correction on the memory device based on a set of soft read voltages may include:

[0196] Obtain a set of voltage offsets corresponding to a certain set of soft read voltages;

[0197] The set of voltage offsets is configured to the memory device so that the memory device obtains a certain set of soft read voltages based on the set of voltage offsets and the preset reference read voltage, and obtains a set of soft read data based on the set of soft read voltages;

[0198] Perform soft-decision error correction on the set of soft-read data.

[0199] It should be noted that, according to the previous description of the RRT table, when performing a read operation on the memory device, the memory device, in response to the read command, determines the required voltage offset; then, it obtains the required voltage offset from the memory device's registers; subsequently, it transmits the voltage offset to the voltage generator, which superimposes the voltage offset with a preset reference read voltage (including the sign of the superposition, i.e., if the voltage offset is negative, the final read voltage will be less than the preset reference read voltage) to obtain the required read voltage, which is then applied to the corresponding word line. That is, in this embodiment, the memory controller obtains a corresponding set of voltage offsets based on a previously determined set of soft read voltages, and then configures this set of voltage offsets to the memory device, which means writing this set of voltage offsets into the corresponding registers in the memory device; then, the memory controller sends a read command to the memory device, and the memory device, in response to the read command, applies the corresponding read voltage to the corresponding word line according to the above-described word line read voltage application process to obtain a set of soft read data. Then, soft decision error correction is performed based on this set of soft read data. The specific soft-decision error correction process will not be described in detail here.

[0200] In some embodiments, the method may further include:

[0201] Before determining that the memory device is currently in a first usage state, a set of hard read voltages is determined based on the preset reference read voltage and the read retry table RRT, wherein the set of hard read voltages includes: a default read voltage and multiple reread voltages; the multiple reread voltages have a certain offset from the preset reference read voltage;

[0202] Hard decision error correction is performed on the memory device based on the set of hard read voltages.

[0203] It should be noted that this describes hard-decision error correction in the stage preceding soft-decision error correction. Specifically, a set of hard read voltages is determined based on a preset reference read voltage and a read retry table (RRT). This set of hard read voltages may include a default read voltage and multiple retry voltages with a certain offset from the preset reference read voltage. The default voltage value may refer to the first voltage value used for the read operation during hard-decision error correction, and this default read voltage may be preset in the memory system based on experience. This default read voltage may be the same as or different from the preset reference read voltage in the retry read table (RRT). The multiple retry voltages are a set of read voltages formed by the RRT and the default read voltage according to a certain offset setting, which can be set by an expert. Then, at least one hard-decision error correction is performed based on this set of hard read voltages. Error correction ends when one of the following occurs: the hard-decision decoding is successful and / or the number of hard read retries reaches the maximum preset number.

[0204] Based on the preceding description, see Figure 12 As shown in the figure, this application embodiment provides an error correction process for a memory system. This error correction process may include:

[0205] Step 1201: First-stage ECC error correction. Also known as hard decision error correction.

[0206] The first phase of ECC error correction includes: initial read; hard-decision decoding of the initial read data; if the initial read fails, a first reread and hard-decision decoding are performed; thereafter, this process is repeated, proceeding to the next decoding step if decoding fails. The first phase of ECC error correction ends when the number of rereads reaches a threshold and at least one of the hard-decision decodings succeeds.

[0207] Step 1202: Second-stage ECC error correction. Also known as soft decision error correction.

[0208] The second stage of ECC error correction includes at least one soft-decision decoding. The soft read reference voltage used for each soft-decision decoding is determined according to the method described above.

[0209] Step 1203: The third stage of RAIN error correction. That is, error correction of the Redundant Array of Independent NAND (RAIN).

[0210] Specifically, after the RAIN error correction fails in the third stage, an indication message indicating the error correction failure is output; when the RAIN error correction succeeds in the third stage, the read data that has been successfully corrected is output.

[0211] The memory system operation method provided in this application embodiment, by establishing a mapping table between the usage state of the memory device and the voltage offset required for reading, can simply, quickly, and accurately obtain the soft read reference voltage in soft decision error correction, thereby reducing the error correction time of soft decision error correction and increasing the success probability of soft decision error correction. Moreover, the operation method provided in this application embodiment does not require the memory controller to have modules such as DSP to perform complex calculations to obtain the corresponding soft read reference voltage, nor does it require the storage medium of the memory device to have the function of finding the optimal read voltage; instead, by clearly recording the usage state of the memory device when it is in the current CW and fully characterizing the storage medium of the memory device, it can more accurately map one or several voltage offsets in the pre-stored RRT corresponding to the current CW to obtain the reference read voltage for subsequent soft decision error correction (soft decode), improve the probability of soft decision error correction success (soft decode pass), avoid entering the subsequent rebuild process, and avoid affecting the read performance of the memory device. This operation method can be adapted to more controllers while improving read performance (memory controller operations take time); it can also be adapted to more storage media (such as NAND media) while improving read performance (NAND itself needs time to find its function); it can also reduce the probability of UECC in harsh application scenarios, increase the probability of soft decode pass, reduce the probability of entering the subsequent rebuild process, and improve read performance in extreme scenarios.

[0212] Based on the same inventive concept, embodiments of this application also provide a memory controller, such as... Figure 13 As shown, the memory controller 1300 is coupled to one or more memory devices; the memory controller includes: a processor 1301; wherein,

[0213] The processor 1301 is configured to: in response to a read error occurring in the memory device, determine that the memory device is currently in a first usage state; determine a first voltage offset corresponding to the first usage state according to a preset mapping relationship; and obtain a first read voltage used to perform a read operation on the memory device in the first usage state according to the preset reference read voltage and the first voltage offset; wherein the preset mapping relationship includes a correspondence between the usage state of the memory device and the voltage offset; and the voltage offset is an offset value relative to the preset reference read voltage.

[0214] It should be noted that the structure of the memory controller here is the same as that described above. Figure 3 The memory controllers shown are mostly identical in structure. The functions implemented by the components of the memory controller provided in this application embodiment, in addition to those described above, are also... Figure 3In addition to the functions shown and described, the operating method provided in the embodiments of this application is also implemented. This operating method is mainly implemented in the processor 1301 in the memory controller.

[0215] In some embodiments, the preset mapping relationship is stored in the memory device; the memory controller further includes: memory 1302;

[0216] The processor is further configured to: send a first read command to the memory device; receive the preset mapping relationship fed back by the memory device in response to the first read command; and cache the preset mapping relationship in the memory.

[0217] In some embodiments, the first voltage offset includes one or more; and the first read voltage includes one or more; the processor is further configured to: select at least one first read voltage as a soft read reference voltage for soft decision correction; obtain a set of soft read voltages including the soft read reference voltages according to each soft read reference voltage and a preset offset rule; and perform the soft decision correction on the memory device according to at least one set of soft read voltages.

[0218] In some embodiments, the preset mapping relationship includes a mapping table; the memory controller further includes: memory 1302;

[0219] The processor is further configured to: send a second read command to the memory device; receive a read retry table (RRT) from the memory device in response to the second read command; cache the RRT in the memory; put the memory device into different usage states; in each usage state, traverse the RRTs in the memory, perform read operations on the memory device one by one, and obtain at least one voltage offset in the RRT corresponding to a read error meeting a preset condition; establish a correspondence between each usage state and the corresponding at least one voltage offset; and generate the mapping table based on each correspondence.

[0220] In some embodiments, the status parameters include at least one of the following: the number of erase cycles, the number of programming cycles, the number of read cycles, the read temperature, the programming temperature, and the time interval between programming and reading of the memory device; the processor is further configured to: assign values ​​to the number of erase cycles, the number of programming cycles, the number of read cycles, the read temperature, the programming temperature, and the time interval between programming and reading to form several sets of status parameters; and process the memory device according to the several sets of status parameters to put the memory device into different usage states; wherein each set of status parameters corresponds to one usage state of the memory device.

[0221] In some embodiments, the processor is further configured to: compare the first usage state with each second usage state recorded in the mapping table; and obtain the first voltage offset from the mapping table based on the comparison result.

[0222] In some embodiments, the processor is further configured to: perform a corresponding comparison between each of the state parameters in the first usage state and each of the state parameters in each second usage state;

[0223] Wherein, if the comparison result includes a ratio of identical parameters in the state parameters of the first usage state and a certain second usage state exceeding a first preset threshold, the second voltage offset corresponding to the second usage state is determined from the mapping table as the first voltage offset; or, if the comparison result includes an absolute value of the difference between the corresponding parameters in the state parameters of the first usage state and a certain second usage state not exceeding a second preset threshold, the second voltage offset corresponding to the second usage state is determined from the mapping table as the first voltage offset; or, if the comparison result includes a ratio of identical parameters in the state parameters of the first usage state and a certain second usage state exceeding the first preset threshold and an absolute value of the difference between the corresponding parameters in the state parameters of the first usage state and the second usage state not exceeding the second preset threshold, the second voltage offset corresponding to the second usage state is determined from the mapping table as the first voltage offset.

[0224] In some embodiments, the processor is further configured to: periodically update the erase count, programming count, read count, read temperature, programming temperature, and programming-to-read time interval in the memory; and retrieve the latest updated erase count, programming count, read count, read temperature, programming temperature, and programming-to-read time interval from the memory as the first usage state.

[0225] It should be noted that the memory controller provided in this application embodiment is configured to implement the operation method provided in this application embodiment. The specific implementation of the operation method has been described in detail above and will not be repeated here.

[0226] Based on the same inventive concept, embodiments of this application also provide a memory system, which may include:

[0227] One or more memory devices; and

[0228] A memory controller, coupled to and configured to control the one or more memory devices; wherein...

[0229] The memory controller includes a processor configured to: in response to a read error occurring in the memory device, determine that the memory device is currently in a first usage state; determine a first voltage offset corresponding to the first usage state according to a preset mapping relationship; and obtain a first read voltage used to perform a read operation on the memory device in the first usage state according to the preset reference read voltage and the first voltage offset.

[0230] The preset mapping relationship includes the correspondence between the usage state of the memory device and the voltage offset; the voltage offset is relative to the preset reference read voltage.

[0231] In some embodiments, the memory device includes: a memory array and peripheral circuitry coupled to the memory array; wherein,

[0232] The peripheral circuitry includes control logic and registers; wherein,

[0233] The processor is further configured to: obtain a set of voltage offsets corresponding to one of a plurality of soft read voltages; and configure each of the voltage offsets in the set of voltage offsets into the register;

[0234] The control logic is configured to: access the register to obtain the set of voltage offsets; obtain a certain set of soft read voltages based on a preset reference read voltage and the set of voltage offsets; and gradually provide each soft read voltage in the certain set of soft read voltages to the selected word line corresponding to the selected memory cell in the memory array to obtain a corresponding set of soft read data.

[0235] The processor is also configured to perform soft-decision error correction on the set of soft-read data.

[0236] It should be noted that the structure of the memory system provided here, as well as the structure of its included memory controller and memory devices, are similar to those described above. Figures 1 to 6 The structures are mostly the same. The memory system provided in this application embodiment is also configured to implement the operation method provided in this application embodiment.

[0237] Specifically, in the processor included in the memory controller of the memory system, following the previously described operation flow, a soft read reference voltage for soft decision error correction is obtained. Then, a set of soft read voltages is obtained based on the soft read reference voltage and a preset offset rule, and soft decision error correction is performed. During soft decision error correction, the processor included in the memory controller obtains a set of voltage offsets corresponding to one of the multiple sets of soft read voltages; each voltage offset in the set is configured into a corresponding register; then, the control logic included in the peripheral circuitry accesses the registers to obtain the set of voltage offsets; and obtains the set of soft read voltages based on the preset reference read voltage and the set of voltage offsets; and progressively provides each soft read voltage in the set of soft read voltages to the selected word line corresponding to the selected memory cell in the memory array to obtain a corresponding set of soft read data; and feeds back the set of soft read data to the processor; the processor performs soft decision error correction on the set of soft read data. The specific execution method of soft decision correction is not described in detail here.

[0238] The above description is intended to be illustrative and not restrictive. For example, the above examples (or one or more aspects thereof) may be used in combination with each other. Other embodiments may be used, such as those that may be used by one of ordinary skill in the art upon reading the above description. It should be understood that it is not intended to interpret or limit the scope or meaning of the claims. Furthermore, in the above detailed description, various features may be combined together to simplify the application. This should not be construed as meaning that any unclaimed disclosed feature is essential to any claim. Rather, the subject matter of the disclosure may lie in fewer than all features of a particular disclosed embodiment. Therefore, the appended claims are thus incorporated into the detailed description, wherein each claim is an independent, separate embodiment, and these embodiments are contemplated to be combined with each other in various combinations or substitutions. The scope of this application should be determined by reference to the appended claims and the full scope of their equivalents.

Claims

1. A method for operating a memory system, characterized in that, include: When a read error occurs in the memory device of the memory system, it is determined that the memory device is currently in a first usage state; A first voltage offset corresponding to the first usage state is determined according to a preset mapping relationship; wherein, the preset mapping relationship includes the correspondence between the usage state of the memory device and the voltage offset; the voltage offset is an offset value relative to a preset reference read voltage; The first read voltage used to perform a read operation on the memory device in the first usage state is obtained based on the preset reference read voltage and the first voltage offset. The acquisition of the preset mapping relationship includes: when the memory device is in each usage state, traversing and reading the retry table RRT, performing a read operation on the memory device one by one, obtaining at least one voltage offset in the RRT when the read error meets the preset condition, and establishing a correspondence between each usage state and the corresponding at least one voltage offset.

2. The operating method according to claim 1, characterized in that, The first voltage offset includes one or more; and the first read voltage includes one or more; the method further includes: At least one first read voltage is selected as the soft read reference voltage for soft decision error correction; Based on each of the soft read reference voltages and the preset offset rule, a set of soft read voltages containing the soft read reference voltages is obtained. The soft decision error correction is performed on the memory device based on at least one set of soft read voltages.

3. The operating method according to claim 1, characterized in that, Each set of state parameters corresponds to a usage state of the memory device; The preset mapping relationship includes a mapping table; the method further includes: The mapping table is generated based on each of the aforementioned correspondences.

4. The operating method according to claim 3, characterized in that, The status parameters include at least one of the following: the number of erases, the number of programs, the number of reads, the read temperature, the program temperature, and the time interval between programming and reading of the memory device; The process of placing the memory device in different usage states includes: Assign values ​​to the number of erases, the number of programs, the number of reads, the read temperature, the program temperature, and the time interval from programming to reading to form several sets of status parameters; The memory device is processed according to the aforementioned sets of state parameters to put the memory device into different usage states.

5. The operating method according to claim 3, characterized in that, The step of determining the first voltage offset corresponding to the first usage state according to a preset mapping relationship includes: Compare the first usage state with each second usage state recorded in the mapping table; The first voltage offset is obtained from the mapping table based on the comparison results.

6. The operating method according to claim 5, characterized in that, The status parameters include multiple parameters; the comparison of the first usage status with the second usage status recorded in the mapping table includes: Each parameter in the state parameters of the first usage state is compared with each parameter in the state parameters of the second usage state respectively; The step of obtaining the first voltage offset from the mapping table based on the comparison result includes: If the comparison result includes a ratio of identical parameters between the first usage state and a certain second usage state, exceeding a first set threshold, then the second voltage offset corresponding to the second usage state is determined from the mapping table as the first voltage offset. Alternatively, if the absolute value of the difference between the parameters corresponding to the state parameters of the first usage state and a certain second usage state in the comparison result does not exceed the second set threshold, the second voltage offset corresponding to the second usage state is determined from the mapping table as the first voltage offset. Alternatively, if the comparison result includes a ratio of the number of identical parameters in the first usage state and a certain second usage state exceeding the first set threshold, and the absolute value of the difference between the parameters corresponding to each parameter in the first usage state and the second usage state does not exceed the second set threshold, then the second voltage offset corresponding to the second usage state is determined from the mapping table as the first voltage offset.

7. The operating method according to claim 4, characterized in that, The method further includes: The erase count, programming count, read count, read temperature, programming temperature, and time interval between programming and reading are updated periodically. The step of determining that the memory device is currently in a first usage state includes: The latest updated erase count, programming count, read count, read temperature, programming temperature, and time interval from programming to reading are used as the first usage state.

8. The operating method according to claim 2, characterized in that, The method further includes: Before determining that the memory device is currently in a first usage state, a set of hard read voltages is determined based on the preset reference read voltage and the read retry table RRT, wherein the set of hard read voltages includes: a default read voltage and multiple reread voltages; the multiple reread voltages have a certain offset from the preset reference read voltage; Hard decision error correction is performed on the memory device based on the set of hard read voltages.

9. The operating method according to claim 2, characterized in that, The step of performing the soft-decision error correction on the memory device based on at least one set of soft read voltages includes: The soft decision error correction is performed on the memory device gradually based on one of the multiple soft read voltages; the soft decision error correction is terminated when a successful soft decision error correction occurs and / or the number of soft decision error corrections is performed reaches a preset threshold.

10. The operating method according to claim 9, characterized in that, Perform soft-decision error correction on the memory device based on a set of soft read voltages, including: Obtain a set of voltage offsets corresponding to a certain set of soft read voltages; The set of voltage offsets is configured to the memory device so that the memory device obtains a certain set of soft read voltages based on the set of voltage offsets and the preset reference read voltage, and obtains a set of soft read data based on the set of soft read voltages; Perform soft-decision error correction on the set of soft-read data.

11. A memory controller, characterized in that, Coupled to one or more memory devices; the memory controller includes: a processor; wherein, The processor is configured to: in response to a read error occurring in the memory device, determine that the memory device is currently in a first usage state; determine a first voltage offset corresponding to the first usage state according to a preset mapping relationship; and obtain a first read voltage used to perform a read operation on the memory device in the first usage state according to a preset reference read voltage and the first voltage offset; wherein the preset mapping relationship includes a correspondence between the usage state of the memory device and the voltage offset; and the voltage offset is an offset value relative to the preset reference read voltage. The processor is further configured to: put the memory device in different usage states; in each usage state, traverse and read the retry table RRT, perform read operations on the memory device one by one, obtain at least one voltage offset in the RRT when the read error meets a preset condition; and establish a correspondence between each usage state and the corresponding at least one voltage offset.

12. The memory controller according to claim 11, characterized in that, The preset mapping relationship is stored in the memory device; The memory controller further includes: memory; The processor is further configured to: send a first read command to the memory device; receive the preset mapping relationship fed back by the memory device in response to the first read command; and cache the preset mapping relationship in the memory.

13. The memory controller according to claim 11, characterized in that, The first voltage offset includes one or more; and the first read voltage includes one or more; the processor is further configured to: select at least one first read voltage as a soft read reference voltage for soft decision error correction; and obtain a set of soft read voltages containing the soft read reference voltages according to each soft read reference voltage and a preset offset rule; And perform the soft decision error correction on the memory device based on at least one set of soft read voltages.

14. The memory controller according to claim 11, characterized in that, Each set of state parameters corresponds to a usage state of the memory device; The preset mapping relationship includes a mapping table; the memory controller further includes: memory; The processor is further configured to: send a second read command to the memory device; receive the RRT (Responding Voltage Regulator) from the memory device in response to the second read command; cache the RRT in the memory; put the memory device into different usage states; in each usage state, traverse the RRTs in the memory, perform read operations on the memory device one by one, and obtain at least one voltage offset in the RRT corresponding to a read error satisfying a preset condition; establish a correspondence between each usage state and the corresponding at least one voltage offset; and generate the mapping table based on each correspondence.

15. The memory controller according to claim 14, characterized in that, The status parameters include at least one of the following: the number of erases, the number of programs, the number of reads, the read temperature, the program temperature, and the time interval between programming and reading of the memory device; the processor is further configured to: assign values ​​to the number of erases, the number of programs, the number of reads, the read temperature, the program temperature, and the time interval between programming and reading to form several sets of status parameters; and process the memory device according to the several sets of status parameters to put the memory device into different usage states.

16. The memory controller according to claim 14, characterized in that, The processor is further configured to: compare the first usage state with each second usage state recorded in the mapping table; and obtain the first voltage offset from the mapping table based on the comparison result.

17. The memory controller according to claim 16, characterized in that, The processor is further configured to: perform a corresponding comparison between each of the state parameters in the first usage state and each of the state parameters in each second usage state; Wherein, if the comparison result includes a ratio of identical parameters in the state parameters of the first usage state and a certain second usage state exceeding a first preset threshold, the second voltage offset corresponding to the second usage state is determined from the mapping table as the first voltage offset; or, if the comparison result includes an absolute value of the difference between the corresponding parameters in the state parameters of the first usage state and a certain second usage state not exceeding a second preset threshold, the second voltage offset corresponding to the second usage state is determined from the mapping table as the first voltage offset; or, if the comparison result includes a ratio of identical parameters in the state parameters of the first usage state and a certain second usage state exceeding the first preset threshold and an absolute value of the difference between the corresponding parameters in the state parameters of the first usage state and the second usage state not exceeding the second preset threshold, the second voltage offset corresponding to the second usage state is determined from the mapping table as the first voltage offset.

18. The memory controller according to claim 15, characterized in that, The processor is also configured to periodically update the erase count, programming count, read count, read temperature, programming temperature, and programming-to-read time interval in the memory; The first usage state is defined as the number of erases, the number of programs, the number of reads, the read temperature, the program temperature, and the time interval from programming to reading, which are the latest times updated in the memory.

19. A memory system, characterized in that, include: One or more memory devices; and A memory controller, coupled to and configured to control the one or more memory devices; wherein... The memory controller includes a processor configured to: in response to a read error occurring in the memory device, determine that the memory device is currently in a first usage state; determine a first voltage offset corresponding to the first usage state according to a preset mapping relationship; and obtain a first read voltage used to perform a read operation on the memory device in the first usage state according to a preset reference read voltage and the first voltage offset. The preset mapping relationship includes the correspondence between the usage state of the memory device and the voltage offset; the voltage offset is an offset value relative to the preset reference read voltage. The processor is further configured to: put the memory device in different usage states; in each usage state, traverse and read the retry table RRT, perform read operations on the memory device one by one, obtain at least one voltage offset in the RRT when the read error meets a preset condition; and establish a correspondence between each usage state and the corresponding at least one voltage offset.

20. The memory system according to claim 19, characterized in that, The memory device includes: a memory array and peripheral circuitry coupled to the memory array; wherein, The peripheral circuitry includes control logic and registers; wherein, The processor is further configured to: obtain a set of voltage offsets corresponding to one of a plurality of soft read voltages; and configure each of the voltage offsets in the set of voltage offsets into the register; The control logic is configured to: access the register to obtain the set of voltage offsets; obtain a certain set of soft read voltages based on a preset reference read voltage and the set of voltage offsets; and gradually provide each soft read voltage in the certain set of soft read voltages to the selected word line corresponding to the selected memory cell in the memory array to obtain a corresponding set of soft read data. The processor is also configured to perform soft-decision error correction on the set of soft-read data.

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