Semiconductor package and method of forming the same

Abstract

Embodiments of the present disclosure provide a semiconductor package and a method of forming a semiconductor package, the semiconductor package comprising: a semiconductor structure having a first surface, the first surface being provided with a first connection region and a second connection region; the rewiring layer is provided with a connecting surface opposite to the first surface, and the connecting surface is provided with a third connecting area and a fourth connecting area; the first interconnection structure is arranged between the first connection area and the third connection area and used for connecting the first connection area and the third connection area, the second interconnection structure is arranged between the second connection area and the fourth connection area, and the second interconnection structure is connected with the second connection area and used for connecting the second connection area and the fourth connection area. The interconnection density of the second interconnection structure is greater than that of the first interconnection structure; and a sealing layer disposed between the semiconductor structure and the redistribution layer, the sealing layer sealing the first interconnection structure and the second interconnection structure.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of semiconductor technology, and more particularly, to a semiconductor package and a method for forming the semiconductor package. Background Art

[0002] The booming development of computing power has driven the growing demand for signal bandwidth, high-speed signal driving capabilities, etc. In the current 2.5D packaging, chips with multiple different functions are highly integrated and packaged together to meet the demand for signal bandwidth.

[0003] However, as the number of chips or layers increases, the yield rate drops sharply and the manufacturing cost increases sharply. For example, when the number of rewiring layers or the thickness of the plastic package is large, it will produce greater warping, increasing the difficulty of tape-out. Summary of the invention

[0004] Embodiments of the present disclosure provide a semiconductor package with higher integration and a method of forming the semiconductor package.

[0005] Problems to be solved by the technical spirit of the present disclosure are not limited to the above-mentioned problems, and other problems not mentioned will be clearly understood by those skilled in the art from the following description.

[0006] Some embodiments of the present disclosure provide a semiconductor package, including: a semiconductor structure, the semiconductor structure having a first surface, the first surface being provided with a first connection area and a second connection area; a redistribution layer, the redistribution layer having a connection surface arranged opposite to the first surface, the connection surface being provided with a third connection area and a fourth connection area; a first interconnection structure and a second interconnection structure, the first interconnection structure being arranged between the first connection area and the third connection area and used to connect the first connection area and the third connection area, the second interconnection structure being arranged between the second connection area and the fourth connection area, the second interconnection structure connecting the second connection area, and the interconnection density of the second interconnection structure being greater than the interconnection density of the first interconnection structure; a sealing layer, the sealing layer being arranged between the semiconductor structure and the redistribution layer, the sealing layer sealing the first interconnection structure and the second interconnection structure.

[0007] Some embodiments of the present disclosure provide a semiconductor package, wherein the semiconductor structure includes: a substrate; a first semiconductor structure and a second semiconductor structure arranged in the substrate, the first semiconductor structure and the second semiconductor structure having surfaces exposed to the first surface, a first connection region and a second connection region arranged on the surface of the first semiconductor structure exposed relative to the substrate, the first connection region and the second connection region are also simultaneously arranged on the surface of the second semiconductor structure exposed relative to the substrate, the second connection region of the first semiconductor structure is arranged adjacent to the second connection region of the second semiconductor structure, the first connection region of the first semiconductor structure is arranged adjacent to the second connection region of the first semiconductor structure, and the second connection region of the second semiconductor structure adjacent to the first connection region is arranged adjacent to the second connection region of the second semiconductor structure; a first interconnection structure simultaneously connects the first connection region of the first semiconductor structure and the first connection region of the second semiconductor structure, and the second interconnection structure connects the second connection region of the first semiconductor structure and the second connection region of the second semiconductor structure.

[0008] Some embodiments of the present disclosure provide a semiconductor package, wherein the first semiconductor structure includes a first substrate, the second semiconductor structure includes a second substrate, the first substrate and the second substrate are arranged in a substrate, the first substrate and the second substrate are fixedly connected to the substrate, and the first substrate, the second substrate and the substrate are substrates of the same type.

[0009] Some embodiments of the present disclosure provide a semiconductor package, wherein a first interconnect structure is arranged perpendicular to a first surface, and a second interconnect structure includes a primary interconnect structure arranged perpendicular to the first surface, the primary interconnect structure being arranged corresponding to a second connection region of the first semiconductor structure and a second connection region of the second semiconductor structure at the same time; the second interconnect structure also includes a secondary interconnect structure, the secondary interconnect structure being arranged relative to a fourth connection region, the secondary interconnect structure connecting the primary interconnect structure corresponding to the first semiconductor structure and the primary interconnect structure corresponding to the second semiconductor structure.

[0010] Some embodiments of the present disclosure provide a semiconductor package, wherein the secondary interconnect structure is electrically connected to the fourth connection region.

[0011] Some embodiments of the present disclosure provide a semiconductor package, wherein a secondary interconnect structure includes a third substrate and a wiring layer, the third substrate and the substrate are of the same type, the wiring layer is connected to the primary interconnect structure, and the interconnection density of the wiring layer is greater than the interconnection density of the primary interconnect structure in the sealing layer.

[0012] Some embodiments of the present disclosure provide a semiconductor package, wherein the sealing layer is further disposed between the first semiconductor structure and the substrate and between the second semiconductor structure and the substrate.

[0013] Some embodiments of the present disclosure provide a semiconductor package, wherein the first semiconductor structure or the second semiconductor structure includes a plurality of semiconductor chips, and a sealing layer is further disposed between the semiconductor chips.

[0014] Some embodiments of the present disclosure also provide a method for forming a semiconductor package, including: providing a semiconductor structure, the semiconductor structure having a first surface, the first surface being provided with a first connection area and a second connection area; forming a first interconnect structure on the first connection area, and forming a second interconnect structure on the second connection area, respectively, the interconnection density of the second interconnect structure being greater than the interconnection density of the first interconnect structure; forming a sealing layer, the sealing layer covering the first surface and sealing the first interconnect structure and the second interconnect structure, the surfaces of the first interconnect structure and the second interconnect structure being exposed to the sealing layer; forming a redistribution layer on the sealing layer, the redistribution layer having a connection surface arranged opposite to the first surface, the connection surface being provided with a third connection area and a fourth connection area, the third connection area being connected to the exposed surface of the first interconnect structure, and the fourth connection area being arranged corresponding to the second interconnect structure.

[0015] The method for forming a semiconductor package provided by an embodiment of the present disclosure, wherein a semiconductor structure is provided, including: providing a substrate; arranging a first semiconductor structure and a second semiconductor structure in the substrate, wherein surfaces of the first semiconductor structure and the second semiconductor structure are exposed to the first surface, and a first connection region and a second connection region are respectively arranged on the exposed surfaces of the first semiconductor structure and the second semiconductor structure, wherein the second connection region of the first semiconductor structure is arranged adjacent to the second connection region of the second semiconductor structure, the first connection region of the first semiconductor structure is arranged adjacent to the second connection region of the first semiconductor structure, and the first connection region of the second semiconductor structure is arranged adjacent to the second connection region of the second semiconductor structure.

[0016] The method for forming a semiconductor package provided by an embodiment of the present disclosure, wherein a first interconnect structure is formed on a first connection area, and a second interconnect structure is formed on a second connection area, respectively, comprising: forming a first interconnect structure in a direction perpendicular to a first surface, the first interconnect structure being connected to a first connection area of ​​a first semiconductor structure and a first connection area of ​​a second semiconductor structure; forming a primary interconnect structure connected to a second connection area of ​​the first semiconductor structure and a second connection area of ​​the second semiconductor structure in a direction perpendicular to the first surface; forming a secondary interconnect structure connected to the primary interconnect structure, the primary interconnect structure and the secondary interconnect structure forming a second interconnect structure.

[0017] The method for forming a semiconductor package provided by an embodiment of the present disclosure, wherein forming a sealing layer comprises: filling a sealing material between a first interconnect structure and a second interconnect structure, wherein the sealing material is simultaneously formed on a first surface and between the first semiconductor structure and a substrate and between the second semiconductor structure and the substrate; grinding the sealing material to expose at least the surface of the first interconnect structure, wherein the retained sealing material forms a sealing layer.

[0018] The sealing layer of the semiconductor package provided by the embodiment of the present disclosure is arranged between the semiconductor structure and the redistribution layer, and the first interconnection structure and the second interconnection structure connecting the semiconductor structure and the redistribution layer are arranged in the sealing layer, thereby reducing the contact area between the sealing layer and the semiconductor structure and the redistribution layer, so that the material adaptability of each part in the entire package is better and the packaging stability is good. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The accompanying drawings herein are incorporated in and constitute a part of the specification, illustrate embodiments consistent with the embodiments of the present disclosure, and together with the description, serve to explain the principles of the embodiments of the present disclosure.

[0020] Figure 1-Figure 8 A schematic cross-sectional view of a semiconductor package provided according to an embodiment of the present disclosure.

[0021] Fig. 9 A schematic diagram of a process for forming a semiconductor package provided by an embodiment of the present disclosure.

[0022] Figures 10A-10G A schematic cross-sectional view of a semiconductor package corresponding to corresponding steps in a method for forming a semiconductor package provided in an embodiment of the present disclosure.

[0023] The above drawings show clear embodiments of the present disclosure, which will be described in more detail below. These drawings and text descriptions are not intended to limit the scope of the present disclosure in any way, but to illustrate the concepts of the present disclosure for those skilled in the art by referring to specific embodiments. DETAILED DESCRIPTION

[0024] The following will be combined with the drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. It is understood that the specific embodiments described herein are only used to explain the relevant disclosure, rather than to limit the disclosure. It should also be noted that, for ease of description, only relevant parts are shown in the drawings. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those generally understood by technicians in the technical field of the present disclosure. The terms used herein are only for the purpose of describing the embodiments of the present disclosure and are not intended to limit the present disclosure. In the following description, "some embodiments" are involved, which describe a subset of all possible embodiments, but it is understood that "some embodiments" can be the same subset or different subsets of all possible embodiments, and can be combined with each other without conflict. It should be noted that the terms "first\second\third" involved in the embodiments of the present disclosure are only used to distinguish similar objects, and do not represent a specific order for objects. It is understandable that "first\second\third" can be interchanged with a specific order or sequence where permitted, so that the embodiments of the present disclosure described here can be implemented in an order other than that shown or described.

[0025] Figure 1 A cross-sectional schematic diagram of a semiconductor package provided according to some embodiments of the present disclosure is shown. The semiconductor package 100 includes a semiconductor structure 110, which may be one or more semiconductor chips or semiconductor functional structures or a combination thereof. The semiconductor structure 110 has a first surface 1101, on which a first connection region 1102 and a second connection region 1103 are disposed.

[0026] In some embodiments, the first connection region 1102 and the second connection region 1103 are input / output regions provided with signals or power sources connected to the functional structures inside the semiconductor structure 110, and are electrically connected to the functional structures inside the semiconductor structure 110 through at least one conductive wiring layer. In some embodiments, the first connection region 1102 and the second connection region 1103 are regions for transmitting different types of signals, for example, the first connection region 1102 may be a region for transmitting power signals for the semiconductor structure 110, and the second connection region 1103 may be a region for transmitting I / O signals. In some embodiments, the first connection region 1102 and the second connection region 1103 may both be data transmission regions, for example, I / O signal transmission regions. The first connection region 1102 and the second connection region 1103 correspond to different data transmission regions, for example, the second connection region 1103 may be a region for transmitting higher speed signals than the first connection region 1102.

[0027] In some embodiments, the number of the first connection regions 1102 may be multiple, and the number of the second connection regions 1103 may be one or more. In some embodiments, the second connection region 1103 is disposed between at least two adjacent first connection regions 1102 .

[0028] In some embodiments, see Figure 1 and Figure 2 , Figure 2 A cross-sectional schematic diagram of a semiconductor package provided for the disclosed embodiment. As shown, the first connection area 1102 and the second connection area 1103 are both provided with connection pads 1104 exposed to the first surface 1101, correspondingly connected to the corresponding functional area or transmission area in the semiconductor structure 100. In some embodiments, the top surface of each connection pad 1104 can be flush with the first surface 1101 of the semiconductor structure 110, and each connection pad 1104 can be isolated by an insulating dielectric layer. In other embodiments, each connection pad 1104 is arranged on the first surface 1101, that is, each connection pad 1104 is arranged to protrude relative to the first surface 1101.

[0029] Continue to see Figure 1 , the semiconductor package 100 further includes a redistribution layer 120, the redistribution layer 120 having a connection surface 1201 disposed opposite to the first surface 1101 of the semiconductor structure 110, the connection surface 1201 including a third connection region 1202 and a fourth connection region 1203. In some embodiments, the redistribution layer 120 is formed by alternating multiple metal layers and insulating layers, the metal layers are used for wiring, and the insulating layers are used for isolating and protecting the metal layers. The third connection region 1202 and the fourth connection region 1203 correspond to different regions of the redistribution layer 120. In some embodiments, as Figure 2 As shown, the third connection region 1202 and the fourth connection region 1203 are both provided with a connection pad 12021 and a connection pad 12031 exposed to the connection surface 1201, and each connection pad is correspondingly connected to a transmission channel in the redistribution layer 120. In some embodiments, the connection pad 12031 corresponding to the fourth connection region 1203 is not exposed to the connection surface 1201, and it can be covered by the insulating layer in the redistribution layer 120. At this time, the fourth connection region 1203 and the third connection region 1202 are interconnected in the redistribution layer 120. In some embodiments, the insulating layer of the redistribution layer 120 can be made of materials such as silicon, resin or glass.

[0030] Continue to see Figure 1In some embodiments, the semiconductor package 100 further includes a first interconnect structure 130 and a second interconnect structure 131. The first interconnect structure 130 is disposed corresponding to the first connection region 1102 and the third connection region 1202, and is disposed between the first connection region 1102 and the third connection region 1202. The second interconnect structure 131 is disposed corresponding to the second connection region 1103 and the fourth connection region 1203, and is disposed between the second connection region 1103 and the fourth connection region 1203.

[0031] In some embodiments, Figure 1 As shown, the first interconnect structure 130 connects the first connection region 1102 and the third connection region 1202, and the second interconnect structure 131 connects the second connection region 1103, but does not directly contact the fourth connection region 1203. In this case, the parts that need to be interconnected inside the semiconductor structure 110 are interconnected through the second interconnect structure 131 disposed outside the semiconductor structure 110, and then the signals of the semiconductor structure 110 are input or output as a whole to the redistribution layer 120 through the first interconnect structure 130.

[0032] In some embodiments, Figure 2 As shown, the second interconnection structure 131 is electrically connected to the fourth connection area 1203, so that the interconnection between the second connection area 1103 and the fourth connection area 1203 is achieved through the second interconnection structure 131. This interconnection method can effectively shorten the signal transmission distance between the second connection area 1103 and the fourth connection area 1203 and speed up the interaction between signals.

[0033] In some embodiments, Figure 3 As shown, Figure 3 1 is a cross-sectional schematic diagram of another semiconductor package of an embodiment of the present disclosure. The first interconnect structure 130 connects the first connection region 1102 and the third connection region 1202, the second interconnect structure 131 connects the second connection region 1103, and the portion of the second interconnect structure 131 adjacent to the fourth connection region 1203 is in direct contact with the fourth connection region 1203 but is not electrically connected to the fourth connection region 1203. In this case, the portion that needs to be interconnected inside the semiconductor structure 110 is still interconnected through the second interconnect structure 131 disposed outside the semiconductor structure 110. In these embodiments, through such an arrangement, a good heat transfer channel can be formed between the second interconnect structure 131 and the redistribution layer 120, thereby improving the overall thermal performance of the package.

[0034] In some embodiments, the interconnection density of the first interconnection structure 130 is less than the interconnection density of the second interconnection structure 131. Such a configuration can achieve higher speed and more complex signal interaction of some functional structures in the semiconductor structure 110. The interconnection density mentioned here refers to the number of interconnection lines or the average spacing of the interconnection lines in the first interconnection structure 130 and the second interconnection structure 131 per unit area. The second interconnection structure 131 with a higher interconnection density can achieve a more complex circuit design, a higher signal transmission speed, and a smaller size.

[0035] In some embodiments, Figure 2 The first interconnect structure 130 includes a plurality of interconnect lines 1301 arranged perpendicular to the first surface 1101 and the connection surface 1201, so as to achieve the shortest distance connection between the first connection area 1102 and the third connection area 1202, thereby shortening the signal transmission time.

[0036] In some embodiments, the second interconnect structure 131 may also include a plurality of primary interconnect structures 1311 arranged perpendicular to the first surface 1101 and the connection surface 1201 . In this case, unlike the first interconnect structure 130 , the density of interconnect lines in the second interconnect structure 131 is higher and the average spacing is smaller.

[0037] In some embodiments, Figure 2 As shown, the second interconnect structure 131 includes a primary interconnect structure 1311 and a secondary interconnect structure 1312. The primary interconnect structure 1311 may be a plurality of vertically arranged conductive lines, and the secondary interconnect structure 1312 may be an integrated interconnect with high-density metal wiring, such as a silicon bridge.

[0038] In some embodiments, Figure 2 As shown, the second interconnection structure 131 also includes a primary interconnection structure 1313. The primary interconnection structure 1311 and the primary interconnection structure 1313 are respectively arranged at opposite ends of the secondary interconnection structure 1312 to form a signal input and output channel of the primary interconnection structure. The primary interconnection structure 1311 is connected to the second connection area 1103, and the primary interconnection structure 1313 is connected to the fourth connection area 1203.

[0039] Continue to see Figure 1In some embodiments, the semiconductor package 100 further includes a sealing layer 140, which is disposed between the semiconductor structure 110 and the redistribution layer 120 and is used to seal the space between the semiconductor structure 110 and the redistribution layer 120. At the same time, the first interconnection structure 130 and the second interconnection structure 131 are also sealed. The sealing layer 140 may be an adhesive material or a sealing material containing organic compounds and / or inorganic compounds. For example, it may be an insulating material such as a plastic encapsulation material, a non-conductive film (NCF), silicon dioxide, silicon carbonitride, etc.

[0040] In some embodiments, Figure 2 As shown, a connection pad 12021 is disposed on the third connection region 1202 of the redistribution layer 120 , and a connection pad 12031 is disposed on the fourth connection region 1203 , and each connection pad is used to connect to the first interconnect structure 130 and the second interconnect structure 131 , respectively.

[0041] In some embodiments, Figure 2 As shown, each interconnection line 1301 in the first interconnection structure 130 has a top surface exposed to the sealing layer 140. The top surface of the primary interconnection structure 1311 disposed adjacent to the semiconductor structure 110 in the second interconnection structure 131 is exposed to the surface of the sealing layer 140, and the top surface of the primary interconnection structure 1313 disposed adjacent to the redistribution layer 120 is exposed to the surface of the sealing layer 140. In some embodiments, the exposed surface of each interconnection line 1301 is connected to each connection pad 1104 on the first connection region 1102 of the semiconductor structure 110, for example, by direct bonding interconnection or by welding. In some embodiments, the exposed surface of the primary interconnection structure 1311 is connected to each connection pad 1104 on the second connection region 1103 of the semiconductor structure 110, for example, by direct bonding interconnection or by welding. In some embodiments, the other exposed surface of each interconnection line 1301 is connected to the connection pad 12021 on the surface of the third connection region 1202 of the redistribution layer 120, for example, by direct bonding interconnection or by welding. In some embodiments, the exposed surface of the primary interconnect structure 1313 is connected to the connection pad 12031 on the surface of the fourth connection region 1203 of the redistribution layer 120 , and may be connected by direct bonding or by welding.

[0042] In these embodiments, the interconnection between the connection areas through direct bonding can effectively shorten the signal transmission distance between the areas and improve the signal transmission rate.

[0043] In some embodiments, when each connection pad on the first surface 1101 is arranged to protrude from the first surface 1101 , the sealing layer 140 is further formed between the connection pads to achieve sealing and insulation of the connection pads.

[0044] The sealing layer of the semiconductor package provided by the embodiment of the present disclosure is arranged between the semiconductor structure and the redistribution layer, and the first interconnection structure and the second interconnection structure connecting the semiconductor structure and the redistribution layer are arranged in the sealing layer, thereby reducing the contact area between the sealing layer and the semiconductor structure and the redistribution layer, so that the material adaptability of each part in the entire package is better and the packaging stability is good.

[0045] Continue to see Figure 4 , Figure 4 A schematic cross-sectional view of a semiconductor package provided for an embodiment of the present disclosure. In some embodiments, the semiconductor structure 110 includes a substrate 111 and a first semiconductor structure 112 and a second semiconductor structure 113 disposed in the substrate 111, and the first semiconductor structure 112 and the second semiconductor structure 113 are disposed at intervals in the substrate 111. The surface of the first semiconductor structure 112 is exposed to the surface of the substrate 111 (i.e., the first surface 1101), and the surface of the second semiconductor structure 113 is exposed to the surface of the substrate 111. The surface of the first semiconductor structure 112 includes a first connection region 1102 and a second connection region 1103, and the surface of the second semiconductor structure 113 also includes a first connection region 1102 and a second connection region 1103. In some embodiments, the second connection region 1103 of the first semiconductor structure 112 and the second connection region 1103 of the second semiconductor structure 113 are disposed adjacent to each other, and the first connection region 1102 of the first semiconductor structure 112 and the first connection region 1102 of the second semiconductor structure 113 are disposed adjacent to their corresponding second connection regions 1103, respectively.

[0046] In some embodiments, the first interconnect structure 130 simultaneously connects the first connection region 1102 of the first semiconductor structure 112 and the first connection region 1102 of the second semiconductor structure 113 , and the second interconnect structure 131 simultaneously connects the second connection region 1103 of the first semiconductor structure 112 and the second connection region 1103 of the second semiconductor structure 113 .

[0047] In some embodiments, each connection region surface of the first semiconductor structure 112 and the second semiconductor structure 113 is provided with a connection pad exposed to the first surface 1101, and each semiconductor structure is connected to the first interconnection structure 130 and the second interconnection structure 131 through each connection pad. In some embodiments, each connection pad is interconnected with the first interconnection structure 130 and the second interconnection structure 131 through direct bonding without adhesive. In some embodiments, each connection pad includes a solder ball, and is interconnected with the first interconnection structure 130 and the second interconnection structure 131 through the solder ball.

[0048] In some embodiments, the number of the first semiconductor structures 112 in the package 100 may be less than the number of the second semiconductor structures 113. In some embodiments, the number of the first semiconductor structure 112 may be one, and the number of the second semiconductor structures 113 may be equal to or greater than 2. In one embodiment, when the number of the second semiconductor structures 113 is greater than the number of the first semiconductor structures 112, the first semiconductor structure 112 may be disposed between two adjacent second semiconductor structures 113.

[0049] In some embodiments, the substrate 111 is a silicon substrate, a resin substrate, a glass substrate or other substrates suitable for being a semiconductor structure carrier.

[0050] In some embodiments, the insulating layer in the redistribution layer 120 can be made of silicon, resin, glass or other materials, which can be the same material as the substrate 111 to further improve the adaptability of the overall material of the package, such as the adaptability of the thermal expansion coefficient.

[0051] In some embodiments, the first semiconductor structure 112 includes functional devices disposed therein and wiring layers connecting these functional devices; the second semiconductor structure 113 includes functional devices disposed therein and wiring layers connecting these functional devices, and the functional devices in the first semiconductor structure 112 and the functional devices in the second semiconductor structure 113 may be the same or different, for example, they may both be devices with information storage functions or devices with logic control functions. In some embodiments, the functional devices in the first semiconductor structure 112 include devices with logic control, for example, ASIC circuit devices, and the functional devices in the second semiconductor structure 113 include capacitor storage devices and devices for performing read and write operations on the capacitor storage devices, for example, DRAM storage devices. The first semiconductor structure 112 and the second semiconductor structure 113 may realize corresponding functions independently or in combination with each other.

[0052] Continue to see Figure 5 , Figure 5A cross-sectional schematic diagram of a semiconductor structure provided for an embodiment of the present disclosure. In some embodiments, the first semiconductor structure 112 and the second semiconductor structure 113 are fixedly connected to the substrate 111 via an adhesive 150. At this time, the first semiconductor structure 112 includes a first substrate 1121, the second semiconductor structure 113 includes a second substrate 1131, and the adhesive 150 is respectively disposed between the bottom surface of the first substrate 1121 and the bottom surface of the second substrate 1131 and the substrate 11, thereby achieving a fixed connection between the first semiconductor structure 112 and the second semiconductor structure 113 and the substrate 111.

[0053] In some embodiments, the adhesive 150 may be a die attach film (DAF) or other materials suitable for bonding substrates.

[0054] In some embodiments, the first substrate 1121 and the second substrate 1131 are the same type of substrates as the substrate 111 , for example, both are silicon substrates, resin substrates, or glass substrates.

[0055] In some embodiments, Figure 6 As shown, Figure 6 A schematic cross-sectional view of a semiconductor package provided for an embodiment of the present disclosure. The second interconnect structure 131 includes a primary interconnect structure 1311 and a secondary interconnect structure 1312 connected to the primary interconnect structure 1311. The primary interconnect structure 1311 is connected and arranged adjacent to the second connection region 1103 of the semiconductor structure 110, and the secondary interconnect structure 1312 is arranged adjacent to the fourth connection region 1203 of the redistribution layer 120. In some embodiments, the secondary interconnect structure 1312 is not directly connected to the fourth connection region 1203. In some embodiments, the secondary interconnect structure 1312 is directly connected to the fourth connection region 1203. The direct connection between the secondary interconnect structure 1312 and the fourth connection region 1203 includes two situations: an electrical direct connection and a non-electrical direct connection, such as Figure 2 and Figure 3 When the secondary interconnect structure 1312 is electrically and directly connected to the fourth connection region 1203, a connection pad is provided on the surface of the secondary interconnect structure 1312 adjacent to the fourth connection region 1203, and is electrically connected to the connection pad on the surface of the fourth connection region 1203. When the secondary interconnect structure 1312 is not electrically and directly connected to the fourth connection region 1203, no connection pad is provided on the surface of the secondary interconnect structure 1312 adjacent to the fourth connection region 1203, that is, at this time, the surface of the secondary interconnect structure 1312 adjacent to the fourth connection region 1203 and the fourth connection region 1203 are only physically connected, not functionally connected.

[0056] Continue to see Figure 5 and Figure 6In some embodiments, a sealing layer 140 is further provided between the first semiconductor structure 112 and the second semiconductor structure 113, that is, the side walls of the first semiconductor structure 112 and the second semiconductor structure 113 are not in direct contact with the substrate 111, and the sealing layer 140 is formed between the side walls of the first semiconductor structure 112 and the second semiconductor structure 113 and the substrate 111, further realizing the sealing and fixation between the first semiconductor structure 112 and the second semiconductor structure 113 and the substrate 111.

[0057] In some embodiments, Figure 7 As shown, the secondary interconnect structure 1312 includes a third substrate 13121 and a wiring layer 13122 . The third substrate 13121 and the substrate 111 are of the same type. The wiring layer 13122 connects the primary interconnect structure 1311 . The interconnection density of the wiring layer is greater than the interconnection density of the secondary interconnect structure 1311 in the sealing layer 140 .

[0058] In some embodiments, the third substrate 13121 and the substrate 111 are the same type of substrates. For example, the third substrate 13121 is a silicon substrate, a resin substrate, a glass substrate, or other types of substrates.

[0059] In some embodiments, the wiring layer 13122 is further disposed in the third substrate 13121 and has exposed connection pads on the bottom surface of the third substrate 13121, ultimately forming a Figure 2 Secondary interconnect structure 1312 is shown.

[0060] In some embodiments, functional devices are also provided in the third substrate 13121 , and these devices can be connected to the wiring layer 13122 to achieve specific functions.

[0061] The semiconductor package provided by the embodiment of the present disclosure uses a substrate to seal the first semiconductor structure and the second semiconductor structure. Compared with the method of using a sealing layer to seal the first semiconductor structure and the second semiconductor structure, the material compatibility between the first semiconductor structure and the second semiconductor structure and the substrate can be improved, thereby improving the overall stability of the package.

[0062] In some embodiments, Figure 8 As shown, Figure 8 A cross-sectional schematic diagram of a semiconductor package provided in an embodiment of the present disclosure. In some embodiments, the second semiconductor structure 113 includes a plurality of stacked semiconductor chips 114, and a connection portion 115 is provided between each stacked and connected semiconductor chip 114 to achieve interconnection between each chip. In some embodiments, a sealing layer 140 fills the space between the connection portions 115 of each chip to achieve isolation between each connection portion 115 and fixation between each chip.

[0063] In some embodiments, the stacked semiconductor chips 114 are directly interconnected without using adhesives.

[0064] In some embodiments, the types of the semiconductor chips 114 may be the same or different.

[0065] In some embodiments, the first semiconductor structure 112 may also be a structure formed by stacking a plurality of semiconductor chips, and the sealing layer 140 may also be formed between the chips of the first semiconductor structure 112 .

[0066] In some embodiments, the first semiconductor structure 112 and the second semiconductor structure 113 have different extension depths in the substrate 111 , and the extension depth of the first semiconductor structure 112 may be greater than or less than the extension depth of the second semiconductor structure 113 .

[0067] Continue to see Figure 8 In some embodiments, a connection portion 1205 is provided on a surface 1204 of the redistribution layer 120 away from the connection surface 1201. The semiconductor package 100 is connected to the circuit board 160. Specifically, the semiconductor package 100 is connected to the circuit board 160 through the connection portion 1205 of the redistribution layer 120. In some embodiments, the connection portion 1205 may be a solder ball. In these embodiments, since the amount of the sealing layer 140 used in the package is less, the semiconductor package 100 has a smoother connection surface before being connected to the circuit board 160, so the effect of mounting on the circuit board 160 is better, and the connection failure between the connection portion 1205 and the circuit board 160 is avoided.

[0068] The embodiment of the present disclosure also provides a method for forming a semiconductor package. The method for forming the package is described in detail below in conjunction with the corresponding drawings.

[0069] like Fig. 9 As shown, Fig. 9 A flowchart of a method for forming a semiconductor package provided by an embodiment of the present disclosure. The method for forming a semiconductor package disclosed herein comprises the following steps:

[0070] S1, providing a semiconductor structure, wherein the semiconductor structure has a first surface, and a first connection region and a second connection region are disposed on the first surface.

[0071] In some embodiments, a process of providing a semiconductor structure includes the following steps:

[0072] S11, providing a substrate.

[0073] S12, a first semiconductor structure and a second semiconductor structure are arranged in a substrate, surfaces of the first semiconductor structure and the second semiconductor structure are exposed to the first surface, a first connection region and a second connection region are respectively arranged on the exposed surfaces of the first semiconductor structure and the second semiconductor structure, wherein the second connection region of the first semiconductor structure is arranged adjacent to the second connection region of the second semiconductor structure, and the first connection region of the first semiconductor structure and the first connection region of the second semiconductor structure are respectively arranged adjacent to their corresponding second connection regions.

[0074] Now combined FIG. 10A to FIG. 10B Describe the above process in detail. Fig. 10A and Fig. 10B The schematic cross-sectional views of the semiconductor packages corresponding to the above steps are shown in FIG. Fig. 10A The process of providing the semiconductor structure 110 includes: providing a substrate 111, wherein the substrate 111 is provided with gaps 201 and gaps 202, wherein the number of gaps 201 and gaps 202 may be multiple, and the number of gaps 202 may be greater than the number of gaps 201. In some embodiments, at least two gaps 202 are arranged around the gap 201. In some embodiments, the depth of the gap 202 in the substrate 111 may be greater than the depth of the gap 201 in the substrate. In some embodiments, the substrate 111 may be a silicon substrate, a resin substrate, a glass substrate or other substrates. The substrate 111 may be an 8-inch, 12-inch, 16-inch or larger substrate.

[0075] In some embodiments, the volume of the gaps 201 and 202 is no greater than 70% of the volume of the substrate 111 . Such a configuration can ensure the strength of the substrate 111 .

[0076] Continue to see Fig. 10B After forming the void 201 and the void 202, the first semiconductor structure 112 and the second semiconductor structure 113 are added to the void 201 and the void 202 respectively, and the top surfaces of the first semiconductor structure 112 and the second semiconductor structure 113 are exposed to the first surface 1101 of the substrate 111. The top surface of the first semiconductor structure 112 has a first connection region 1102 and a second connection region 1103, and the top surface of the second semiconductor structure 113 has a first connection region 1102 and a second connection region 1103. The first connection regions and the second connection regions are distributed corresponding to different functional regions or different signal transmission regions in the first semiconductor structure and the second semiconductor structure.

[0077] In some embodiments, Fig. 10BAs shown, the bottom surfaces of the first semiconductor structure 112 and the second semiconductor structure 113 are fixedly connected to the substrate 111 through an adhesive 150. In some embodiments, there is a gap 203 between the sidewalls of the first semiconductor structure 112 and the second semiconductor structure 113 and the substrate 111. In some embodiments, the first semiconductor structure 112 and the second semiconductor structure 113 are directly formed in the substrate 111. There is no gap between the sidewalls of the first semiconductor structure 112 and the second semiconductor structure 113 and the substrate 111.

[0078] The second connection regions 1103 on the top surfaces of the first semiconductor structure 112 and the second semiconductor structure 113 are disposed adjacent to each other, and the first connection region 1102 of each semiconductor structure is disposed adjacent to its corresponding second connection region 1103 .

[0079] Continue to see Fig. 9 , the method of forming the package further includes:

[0080] S2, forming a first interconnection structure on the first connection region and a second interconnection structure on the second connection region, wherein the interconnection density of the second interconnection structure is greater than the interconnection density of the first interconnection structure.

[0081] In some embodiments, the process of forming the first interconnect structure on the first connection region and the second interconnect structure on the second connection region comprises the following steps:

[0082] S21: forming a first interconnect structure in a direction perpendicular to the first surface, the first interconnect structure being connected to a first connection region of the first semiconductor structure and a first connection region of the second semiconductor structure.

[0083] S22: Forming a primary interconnect structure connected to the second connection region of the first semiconductor structure and the second connection region of the second semiconductor structure in a direction perpendicular to the first surface.

[0084] S23: forming a secondary interconnect structure connected to the primary interconnect structure, the primary interconnect structure and the secondary interconnect structure forming a second interconnect structure.

[0085] Combine the following FIG. 10C to FIG. 10D Describe the above process in detail. Fig. 10C and Fig. 10D The schematic cross-sectional views of the semiconductor packages corresponding to the above steps are shown in FIG. Fig. 10C, a first interconnect structure 130 is formed on the first connection region 1102 of the first semiconductor structure 112 and the second semiconductor structure 113, a primary interconnect structure 1311 is formed on the second connection region 1103 of the first semiconductor structure 112 and the second semiconductor structure 113, and the second connection region 1103 of the first semiconductor structure 112 and the second semiconductor structure 113 are interconnected through the primary interconnect structure 1311. In some embodiments, Fig. 10C As shown, the first interconnect structure 130 and the primary interconnect structure 1311 are directly connected to each connection pad on the top surface of the first semiconductor structure 112 and the second semiconductor structure 113. The first interconnect structure 130 and the primary interconnect structure 1311 can be perpendicular to the metal conductive wires arranged in each connection area, such as copper wires or gold wires. In some embodiments, the first interconnect structure 130 and the primary interconnect structure 1311 can be obtained by a vertical wire bonding process. In some embodiments, the first interconnect structure 130 is formed before the primary interconnect structure 1311, and the length of the primary interconnect structure is less than the length of the first interconnect structure 130.

[0086] Continue to see Fig. 10D After forming the first interconnect structure 130 and the primary interconnect structure 1311, a secondary interconnect structure 1312 connected to the primary interconnect structure is formed on the primary interconnect structure 1311. The secondary interconnect structure 1312 is connected across the primary interconnect structures 1311 of the first semiconductor structure 112 and the second semiconductor structure 113. The secondary interconnect structure 1312 may be an interconnect with a higher integration density, such as a silicon bridge. In some embodiments, the surface of the secondary interconnect structure 1312 may be lower than the surface of the first interconnect structure 130. In some embodiments, the surface of the secondary interconnect structure 1312 may be flush with the surface of the first interconnect structure 130. Fig. 10D The surface of the secondary interconnect structure 1312 may be lower than the surface of the first interconnect structure 130 for illustration only, but this does not constitute a limitation on the secondary interconnect structure 1312 in the present disclosure.

[0087] In some embodiments, when the surface of the secondary interconnect structure 1312 is lower than the surface of the first interconnect structure 130, after forming the secondary interconnect structure 1312, a second layer may be formed on the surface of the secondary interconnect structure 1312. Figure 2 The connection pads 1313 shown are formed so as to form a connection structure on the surface of the secondary interconnect structure 1312 that is flush with the surface of the first interconnect structure.

[0088] Continue to see Fig. 9 , the method of forming the package further includes:

[0089] S3, forming a sealing layer, wherein the sealing layer covers the first surface and seals the first interconnect structure and the second interconnect structure, and at least the surface of the first interconnect structure is exposed to the surface of the sealing layer.

[0090] In some embodiments, the process of forming the sealing layer includes the following steps:

[0091] S31: Filling a sealing material between the first interconnect structure and the second interconnect structure, wherein the sealing material is simultaneously formed on the first surface and between the first semiconductor structure and the substrate and between the second semiconductor structure and the substrate.

[0092] S32: grinding the sealing material to expose at least the surface of the first interconnect structure, and the remaining sealing material forms a sealing layer.

[0093] Combine the following FIG. 10E to FIG. 10F Describe the above process in detail. Fig.10E and Fig.10F The schematic cross-sectional views of the semiconductor packages corresponding to the above steps are shown in FIG. Fig.10E , a sealing material 1401 is filled on the surface of the substrate 111 , the sealing material 1401 seals the first interconnect structure 130 and the primary interconnect structure and the secondary interconnect structure 1312 , and the sealing material 1401 is further filled in the gap between the first semiconductor structure 112 and the second semiconductor structure 113 and the substrate 111 .

[0094] Continue to see Fig.10F , grinding the excess sealing material so that the surface of the first interconnect structure 130 is exposed, which is convenient for further interconnection of the first interconnect structure 130. The retained sealing material forms the sealing layer 140. In some embodiments, the top surface of the secondary interconnect structure 1312 is lower than the surface of the first interconnect structure 130, so that during the process of grinding to expose the first interconnect structure 130, the surface of the secondary interconnect structure 1312 is not exposed. In some embodiments, after the grinding of the grinding material is completed, a primary interconnect structure connected to the secondary interconnect structure 1312 can be formed in the sealing layer 140 on the surface of the secondary interconnect structure 1312, such as Figure 2 In some embodiments, the top surface of the secondary interconnect structure 1312 is flush with the surface of the first interconnect structure 130, and during the grinding of the abrasive material, the surfaces of the first interconnect structure 130 and the secondary interconnect structure 1312 are simultaneously exposed, facilitating subsequent further interconnection.

[0095] In some embodiments, grinding the abrasive material may be accomplished using a chemical mechanical polishing process.

[0096] S4, forming a redistribution layer on the sealing layer, the redistribution layer having a connection surface arranged opposite to the first surface, the connection surface being provided with a third connection area and a fourth connection area, the third connection area being connected to the exposed surface of the first interconnection structure, and the fourth connection area being arranged corresponding to the second interconnection structure.

[0097] like Figure 10G As shown, Figure 10G 1 is a schematic cross-sectional view of a semiconductor package corresponding to the above steps. After forming a sealing layer thickness, a redistribution layer 120 is formed on the sealing layer. The redistribution layer 120 is an interconnection structure having multiple layers of metal wiring. The redistribution layer 120 is provided with a third connection region 1202 and a fourth connection region 1203 on a connection surface opposite to the first surface 1101 of the substrate 111, respectively corresponding to the first connection region 1102 and the second connection region 1103. The third connection region 1202 is connected to the first interconnection structure 130, and the fourth connection region 1203 is provided corresponding to the second connection region 1103. In some embodiments, the secondary interconnection structure 1312 is in contact with the fourth connection region 1203, as shown in FIG. Figure 2 and Figure 3 shown.

[0098] In some embodiments, after forming the redistribution layer 120, the substrate 111 is further cut to separate the semiconductor structures and their combinations in the substrate 111. In some embodiments, the minimum unit of cutting is a combination of at least one first semiconductor structure and at least one second semiconductor structure. The cutting method can be blade cutting, laser cutting, etc. Finally, the package 111 is formed.

[0099] The method for forming a semiconductor package provided in the embodiment of the present disclosure uses a substrate 111 to provide a holding space for the first semiconductor structure and the second semiconductor structure. Since the material of the substrate 111 can be the same as the material of the base material of the first semiconductor structure and the second semiconductor structure, the thermal expansion coefficients (CTE) of these materials are close, which can not only achieve a good sealing effect, but also further reduce the amount of the sealing layer. Since the thermal expansion coefficient of the sealing layer is quite different from the thermal expansion coefficients of the first semiconductor structure and the second semiconductor structure, problems such as delamination are likely to occur between the two, and due to the mismatch of stress, the warping of the package will also increase, which will affect the stability of the package when mounted on the circuit board. In the present disclosure, the amount of the sealing layer is further reduced, and the packaging yield is improved.

[0100] In some embodiments, after forming the package, the step of connecting the package to the circuit board is further included, and finally obtaining Figure 8 The structure shown facilitates the use of the semiconductor structure in combination with modules such as servers and controllers.

[0101] Those skilled in the art can understand that the above-mentioned embodiments are specific examples for implementing the present disclosure, and in practical applications, various changes can be made to them in form and detail without departing from the spirit and scope of the embodiments of the present disclosure. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the embodiments of the present disclosure, so the protection scope of the embodiments of the present disclosure shall be based on the scope defined in the claims.

Claims

1. A semiconductor package, comprising: A semiconductor structure having a first surface, wherein the first surface is provided with a first connection region and a second connection region; a redistribution layer, the redistribution layer having a connection surface arranged opposite to the first surface, the connection surface being provided with a third connection region and a fourth connection region; a first interconnection structure and a second interconnection structure, wherein the first interconnection structure is disposed between the first connection region and the third connection region and is used to connect the first connection region and the third connection region, and the second interconnection structure is disposed between the second connection region and the fourth connection region, and the second interconnection structure connects the second connection region, and an interconnection density of the second interconnection structure is greater than an interconnection density of the first interconnection structure; A sealing layer is provided between the semiconductor structure and the redistribution layer, and the sealing layer seals the first interconnect structure and the second interconnect structure.

2. The package according to claim 1, characterized in that The semiconductor structure comprises: substrate; a first semiconductor structure and a second semiconductor structure disposed in the substrate, the first semiconductor structure and the second semiconductor structure having surfaces exposed to the first surface, the first connection region and the second connection region disposed on the surface of the first semiconductor structure exposed relative to the substrate, the first connection region and the second connection region also disposed on the surface of the second semiconductor structure exposed relative to the substrate, the second connection region of the first semiconductor structure being disposed adjacent to the second connection region of the second semiconductor structure, the first connection region of the first semiconductor structure being disposed adjacent to the second connection region of the first semiconductor structure, and the second connection region of the second semiconductor structure being adjacent to the first connection region being disposed adjacent to the second connection region of the second semiconductor structure; The first interconnect structure simultaneously connects the first connection region of the first semiconductor structure and the first connection region of the second semiconductor structure, and the second interconnect structure connects the second connection region of the first semiconductor structure and the second connection region of the second semiconductor structure.

3. The semiconductor package according to claim 2, wherein: The first semiconductor structure includes a first substrate, the second semiconductor structure includes a second substrate, the first substrate and the second substrate are arranged in the substrate, the first substrate and the second substrate are fixedly connected to the substrate, and the first substrate, the second substrate and the substrate are substrates of the same type.

4. The semiconductor package according to claim 2, wherein: The first interconnect structure is arranged perpendicular to the first surface, and the second interconnect structure includes a primary interconnect structure arranged perpendicular to the first surface, and the primary interconnect structure is arranged corresponding to the second connection area of ​​the first semiconductor structure and the second connection area of ​​the second semiconductor structure at the same time; the second interconnect structure also includes a secondary interconnect structure, and the secondary interconnect structure is arranged relative to the fourth connection area, and the secondary interconnect structure connects the primary interconnect structure corresponding to the first semiconductor structure and the primary interconnect structure corresponding to the second semiconductor structure.

5. The semiconductor package according to claim 4, wherein: The secondary interconnect structure is electrically connected to the fourth connection region.

6. The semiconductor package according to claim 4, wherein: The secondary interconnect structure includes a third substrate and a wiring layer. The third substrate is the same type as the substrate. The wiring layer connects the primary interconnect structure. The interconnection density of the wiring layer is greater than the interconnection density of the primary interconnect structure in the sealing layer.

7. The semiconductor package according to claim 2, wherein: The sealing layer is also disposed between the first semiconductor structure and the substrate and between the second semiconductor structure and the substrate.

8. The semiconductor package according to claim 2, wherein: The first semiconductor structure or the second semiconductor structure includes a plurality of semiconductor chips, and the sealing layer is further disposed between the semiconductor chips.

9. A method of forming a semiconductor package, comprising: A semiconductor structure is provided, wherein the semiconductor structure has a first surface, wherein the first surface is provided with a first connection region and a second connection region; forming a first interconnection structure on the first connection region and a second interconnection structure on the second connection region, respectively, wherein the interconnection density of the second interconnection structure is greater than the interconnection density of the first interconnection structure; forming a sealing layer, the sealing layer covering the first surface and sealing the first interconnect structure and the second interconnect structure, wherein surfaces of the first interconnect structure and the second interconnect structure are exposed to the sealing layer; A redistribution layer is formed on the sealing layer, the redistribution layer having a connection surface arranged opposite to the first surface, the connection surface being provided with a third connection region and a fourth connection region, the third connection region being connected to the exposed surface of the first interconnect structure, and the fourth connection region being arranged corresponding to the second interconnect structure.

10. The method according to claim 9, characterized in that Provide semiconductor structures, including: providing a substrate; A first semiconductor structure and a second semiconductor structure are arranged in the substrate, surfaces of the first semiconductor structure and the second semiconductor structure are exposed to the first surface, and the first connection region and the second connection region are arranged on the exposed surfaces of the first semiconductor structure and the second semiconductor structure, respectively, wherein the second connection region of the first semiconductor structure is arranged adjacent to the second connection region of the second semiconductor structure, the first connection region of the first semiconductor structure is arranged adjacent to the second connection region of the first semiconductor structure, and the first connection region of the second semiconductor structure is arranged adjacent to the second connection region of the second semiconductor structure.

11. The method according to claim 10, characterized in that Forming a first interconnect structure on the first connection region and forming a second interconnect structure on the second connection region respectively, comprising: forming a first interconnect structure in a direction perpendicular to the first surface, the first interconnect structure being connected to the first connection region of the first semiconductor structure and the first connection region of the second semiconductor structure; forming a primary interconnect structure connected to the second connection region of the first semiconductor structure and the second connection region of the second semiconductor structure in a direction perpendicular to the first surface; A secondary interconnect structure is formed to connect with the primary interconnect structure, the primary interconnect structure and the secondary interconnect structure forming the second interconnect structure.

12. The method according to claim 11, characterized in that Forming a sealing layer, comprising: Filling a sealing material between the first interconnect structure and the second interconnect structure, wherein the sealing material is simultaneously formed on the first surface and between the first semiconductor structure and the substrate and between the second semiconductor structure and the substrate; The sealing material is ground to expose at least the surface of the first interconnect structure, and the remaining sealing material forms the sealing layer.

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