A Method and System for Mitigating Voltage Imbalance in Distribution Substations Based on Phase Switches and SVG

Abstract

This invention discloses a method and system for managing voltage imbalance in distribution substations based on commutation switches and SVG (Static Var Generator). First, a multi-objective function for optimizing voltage imbalance across all nodes in the distribution network and an optimization model for the phase sequence of commutation switches and the SVG compensation command current are established. The three-phase voltage at each node is calculated using a three-phase unbalanced power flow calculation. A fast non-dominated sorting genetic algorithm is used to optimize the obtained phase sequence of commutation switches and the SVG compensation command current, yielding Pareto front solutions for the optimized phase sequence of commutation switches and the negative-sequence compensation current of the SVG. The Pareto front solutions are then screened, and the result that meets national standards while reducing the number of commutation switches and the negative-sequence compensation current of the SVG is selected as the optimal command. Based on the optimal command, commutation commands and compensation current commands are issued to the commutation switches and SVGs in the distribution network, respectively, achieving comprehensive management of voltage imbalance across all nodes in the distribution network.

Description

Technical Field

[0001] This invention belongs to the field of power quality management technology for distribution networks, specifically relating to a method and system for managing voltage imbalance in distribution substations based on phase-switching switches and SVG. Background Technology

[0002] In low-voltage distribution networks, most power users are single-phase loads. Due to the large-scale integration of distributed power sources and the diversification of household appliances, there is significant uncertainty in the source-load relationship within the distribution network, leading to three-phase imbalance in distribution substations. Three-phase imbalance increases distribution network losses and reduces the operating efficiency of power equipment. Current methods for mitigating imbalance in low-voltage distribution networks include phase sequence optimization and active compensation. Phase sequence optimization adjusts the phase sequence of single-phase loads connected to the three-phase lines to bring the three-phase loads closer together, thus mitigating the imbalance. Phase sequence optimization can be further divided into manual phase adjustment and intelligent phase adjustment. Manual phase adjustment is time-consuming and labor-intensive, and cannot be adjusted online based on real-time load conditions in the distribution area. Intelligent phase adjustment uses optimization algorithms to calculate commutation commands and sends the commutation information to commutation switches composed of power electronic devices, achieving online real-time mitigation of three-phase imbalance. Active compensation uses power quality management equipment such as Static Var Generators (SVG) to compensate for unbalanced currents.

[0003] Current mainstream intelligent phase sequence optimization methods only consider the three-phase current imbalance at the low-voltage distribution transformer outlet side, failing to account for the three-phase voltage imbalance at each node within the distribution area. Therefore, the effectiveness of voltage imbalance mitigation at these nodes cannot be guaranteed. Furthermore, the phase sequence optimization results are related to the current single-phase load within the distribution area, potentially leading to situations where optimization fails to address the imbalance, thus affecting the overall effectiveness. In addition, adjusting the load current of users during single-phase load phase sequence switching is not a simple phase-to-phase transfer; it requires consideration of power flow redistribution after the network architecture is implemented, a point not addressed by current mainstream intelligent phase sequence optimization methods. While traditional point-to-point local compensation strategies in active compensation schemes can effectively mitigate imbalances, they significantly increase the cost. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a method and system for managing voltage imbalance in distribution substations based on phase-switching switches and SVG, which addresses the shortcomings of the prior art. This method solves the technical problems that traditional phase-switching switch control strategies cannot achieve full-node voltage imbalance management in the distribution system and that phase-switching switches and SVG resources cannot be efficiently coordinated and controlled, so as to achieve comprehensive management of multi-node voltage imbalance within the substation.

[0005] The present invention adopts the following technical solution:

[0006] The method for mitigating voltage imbalance in distribution substations based on commutation switches and SVG includes the following steps:

[0007] S1. Obtain the topology, line impedance data, data of each node, and data of the commutator and SVG of the distribution network;

[0008] S2. Based on the distribution network topology, line impedance data, data of each node, data of commutator and SVG obtained in step S1, establish a multi-objective function for optimizing the voltage imbalance of all nodes in the distribution network and an optimization model for the phase sequence of commutator and the compensation command current of SVG.

[0009] S3. The three-phase voltage of the node is calculated using a three-phase unbalanced power flow calculation. The fast non-dominated sorting genetic algorithm is used to optimize the phase sequence of the commutation switch and the SVG compensation command current optimization model obtained in step S2, and the Pareto front solution set of the phase sequence optimization of the commutation switch and the negative sequence compensation current of the SVG is obtained.

[0010] S4. Screen the Pareto front solution set obtained in step S3, and select the result that meets the national standard and reduces the number of commutation switches and the negative sequence compensation current of SVG as the optimal instruction.

[0011] S5. Based on the optimal instruction obtained in step S4, issue commutation instructions and compensation current instructions to the commutation switches and SVG in the distribution network respectively, so as to realize the comprehensive management of voltage imbalance at all nodes of the distribution network.

[0012] Preferably, in step S1, the distribution network topology includes a three-phase network topology; the three-phase line impedance data includes the three-phase line impedance of adjacent nodes; the data for each node includes the load power, voltage amplitude, and phase angle data of each node; the commutation switch data includes the current phase sequence of the commutation switch; the SVG data includes the rated capacity of each SVG and the current output negative sequence current; forming Positive, negative, and zero order nodal admittance matrices , , .

[0013] Preferably, step S2 specifically includes:

[0014] S201. The comprehensive management target for the three-phase imbalance of the distribution network is set as negative sequence voltage imbalance at each node <2%;

[0015] S202. Construct a multi-objective function for optimizing voltage imbalance across all nodes in the distribution network, as well as an optimization model for the phase sequence of commutation switches and the SVG compensation command current. The optimization objectives are to minimize the sum of negative sequence voltage imbalance across all nodes, minimize the number of commutations, and minimize the sum of the amplitudes of the negative sequence compensation current output by the SVG. Constraints include maintaining the three-phase voltage of the distribution network nodes within the range specified by national standards, ensuring that the number of consecutive operations of a single commutation switch does not exceed the specified upper limit, and ensuring that the negative sequence current output by the SVG does not exceed the rated capacity. The control variables are the phase sequence of the commutation switches and the negative sequence compensation current output by the SVG.

[0016] Preferably, the multi-objective function for optimizing voltage imbalance across all nodes in the distribution network includes:

[0017] Total negative sequence voltage imbalance objective function:

[0018]

[0019] in, Number the nodes. For the number of network nodes, For nodes Negative sequence voltage imbalance For nodes m negative sequence voltage, For nodes m The positive sequence voltage;

[0020] Objective function for total output capacity of SVG:

[0021]

[0022] in, k For SVG numbering, K This represents the total number of SVGs. This represents the negative sequence output current of the k-th SVG.

[0023] Objective function for commutation number:

[0024]

[0025] in, This represents the total number of commutations of the commutator relative to the current phase sequence.

[0026] Preferably, the node voltage constraint conditions are as follows:

[0027]

[0028] in, This represents the minimum node voltage. This represents the maximum node voltage.

[0029] Each commutator switch is set with a maximum number of consecutive commutations. If the number of consecutive operations of a certain commutator switch exceeds the specified value, its current phase sequence will remain unchanged during the next commutation. The operation constraints are as follows:

[0030]

[0031] in, For the first p The number of consecutive commutations of the commutator switch. For the first p The maximum number of consecutive phase commutations of the commutator.

[0032] Preferably, in step S3, the three-phase unbalanced power flow and the fast non-dominated sorting genetic algorithm NSGA-II are applied to solve the multi-objective optimization model, and the multi-node voltage imbalance optimization model and the three objective functions of the model are solved. Through multiple iterations of optimization by the NSGA-II genetic algorithm, a set of Pareto optimal solutions is obtained. The objective function of the Pareto optimal solution set is equivalent to the Pareto optimal frontier of the total negative sequence voltage imbalance degree, the number of commutations, and the total output capacity of the SVG.

[0033] Preferably, the NSGA-II algorithm is used to solve the multi-objective optimization problem established in step S2, as follows:

[0034] S3021. Generate the initial population for the genetic algorithm. The population size is POP. Each individual includes the phase sequence of the commutation switch and the negative sequence current of the SVG output.

[0035] S3022. Calculate the three objective functions for an individual. The objective function for total voltage imbalance needs to be obtained from the results of unbalanced power flow calculation.

[0036] S3023, Non-dominated ranking and crowding analysis: Non-dominated ranking and crowding calculation are performed on all individuals in the population. The priority and ranking of individuals are determined using three fitness functions. Next, crowding is calculated, and individuals at the same level are ranked to prevent the algorithm from getting trapped in local optima. Retaining individuals with high crowding is beneficial to population diversity.

[0037] S3024. Select suitable parent offspring for reproduction based on the tournament selection method and put them into the mating pool. The number of individuals in the mating pool is half of the initial population.

[0038] S3025. Randomly select parent individuals from the mating pool, perform crossover and genetic operations, and generate offspring individuals;

[0039] S3026. Merge the parent and offspring populations to obtain a merged population. Based on the elite selection strategy, perform non-dominant ranking and crowding calculation on the merged population. The top-ranked POP individuals generate a new population.

[0040] S3027. Based on the objective function and number of iterations of each individual in the new population, determine whether to stop the iteration. If the iteration is not stopped, perform selection, crossover, and mutation operations on the population to generate the next generation population and proceed to step S302. If the convergence conditions are met, output the Pareto optimal solution set.

[0041] Preferably, in step S3021, the objective function for total voltage imbalance is obtained through the unbalanced power flow calculation results, as follows:

[0042] S30221, Set the initial values ​​of the positive sequence, negative sequence, and zero sequence voltages of the nodes. , , The positive sequence voltage amplitude is 1.0 pu, and the negative sequence and zero sequence voltage amplitudes are 0. Calculate the initial values ​​of the three-phase voltages at the nodes. , , ;

[0043] S30222, Based on node injection power , , The three-phase current injected into the nodes is updated, and the positive-sequence, negative-sequence, and zero-sequence currents injected into the nodes in the update network are calculated based on the symmetrical component method. , , ;

[0044] S30223, the positive sequence network is an active network, and the forward-backward substitution method is used to solve for the nodal positive sequence voltages. Negative-sequence and zero-sequence networks are passive networks, and their values ​​are obtained using nodal voltage equations. , , t This represents the number of iterations.

[0045] S30224, Generating node three-phase voltage , , ;

[0046] S30225. Determine if convergence has occurred or the maximum number of iterations has been reached. If convergence has not occurred or the maximum number of iterations has not been reached, update... t=t+ 1. The next iteration begins from step S30222.

[0047] Preferably, in step S4, feasible solutions that meet the standard are first screened from the Pareto optimal solution set obtained in step S3. After adopting the phase sequence optimization command of the commutation switch represented by the feasible solution and the negative sequence current command of SVG output, the voltage imbalance of all nodes in the local distribution network meets the national standard requirements.

[0048] Then, a non-dominated sorting is performed again among the remaining feasible solutions. The optimal compromise solution with low commutation count and small total SVG output capacity is selected as the commutation switch phase sequence optimization command and the SVG output negative sequence current command.

[0049] Secondly, embodiments of the present invention provide a distribution area voltage imbalance mitigation system based on a commutation switch and an SVG, comprising:

[0050] The data module acquires the topology, line impedance data, data of each node, and data of the phase-changing switch and SVG of the distribution network.

[0051] The module is constructed based on the obtained distribution network topology, line impedance data, data of each node, data of commutation switches and SVG, to establish a multi-objective function for optimizing the voltage imbalance of all nodes in the distribution network and an optimization model for the phase sequence of commutation switches and the compensation command current of SVG.

[0052] The optimization module uses the three-phase voltage of the node to calculate the three-phase unbalanced power flow, and uses the fast non-dominated sorting genetic algorithm to optimize the obtained commutation switch phase sequence and SVG compensation command current optimization model, and obtains the Pareto front solution set of the commutation switch phase sequence optimization and SVG negative sequence compensation current.

[0053] The filtering module filters the obtained Pareto front solution set and selects the result that meets national standards and reduces the number of commutation switches and SVG negative sequence compensation current as the optimal instruction.

[0054] The output module, based on the obtained optimal instructions, sends commutation instructions and compensation current instructions to the commutation switches and SVG in the distribution network, respectively, to achieve comprehensive management of voltage imbalance across all nodes of the distribution network.

[0055] Thirdly, a computer device includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor, when executing the computer program, implements the steps of the above-described method for managing voltage imbalance in distribution substations based on commutation switches and SVG.

[0056] Fourthly, embodiments of the present invention provide a computer-readable storage medium including a computer program, which, when executed by a processor, implements the steps of the above-described method for managing voltage imbalance in distribution substations based on commutation switches and SVG.

[0057] Fifthly, a chip includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor, when executing the computer program, implements the steps of the above-described method for managing voltage imbalance in distribution substations based on commutation switches and SVG.

[0058] In a sixth aspect, embodiments of the present invention provide an electronic device, including a computer program, which, when executed by the electronic device, implements the steps of the above-described method for managing voltage imbalance in distribution substations based on commutation switches and SVG.

[0059] Compared with the prior art, the present invention has at least the following beneficial effects:

[0060] A method for managing voltage imbalance in distribution substations based on phase-switching switches and SVG (Static Var Generator) is proposed. This method uses phase-switching switches and SVG as management devices, comprehensively considering the three-phase voltage imbalance across all nodes of the local distribution network as the management target. Compared with traditional phase-switching switch management schemes, it can achieve efficient management of voltage imbalance across all nodes, not just limited to suppressing the current imbalance on the low-voltage side of the transformer. This method is based on the voltage imbalance calculated from the three-phase unbalanced power flow, and considers the impact of phase-switching switch operation on network power flow reconstruction, thus better reflecting the actual operating state of the distribution network. This invention employs a fast non-dominated sorting genetic algorithm to solve the model, enabling efficient optimization of phase sequence commands for phase-switching switches and optimal compensation commands for SVG.

[0061] Furthermore, step S1 obtains local distribution network topology, line impedance data, and node data to support unbalanced power flow calculation, and obtains data on commutation switches and SVG to support the fast non-dominated genetic algorithm to optimize the optimal commands for commutation switches and SVG. The above data is the data foundation for the implementation of this method.

[0062] Furthermore, step S2 aims to minimize the sum of negative-sequence voltage imbalance across all nodes, the number of commutations, and the sum of the negative-sequence compensation current amplitudes of the SVG output. It also considers the constraint characteristics of the commutation switch and the SVG, using the phase sequence switching of the commutation switch and the output compensation current of the SVG as control variables. A multi-objective function optimization mathematical model is constructed as the basis for solving subsequent steps.

[0063] Furthermore, three objective functions are constructed: total negative sequence voltage imbalance, total SVG output capacity, and number of commutations, as optimization objectives for the NSGA-II algorithm. Considering the governance effect, the optimization of governance equipment capacity, and the limitation of the number of actions, the governance effect is ensured to be achieved with a smaller governance cost.

[0064] Furthermore, by setting node voltage constraints, the voltage of the optimized power distribution system is ensured to operate within a reasonable range. By setting a limit on the number of consecutive operations of a single phase-switching switch, the system is prevented from operating frequently, thus extending its service life.

[0065] Furthermore, in step S3, given that the multi-objective function optimization model constructed by this method has the characteristics of a mixed integer programming problem, a fast non-dominated sorting genetic algorithm is adopted to achieve efficient solution of the optimization problem; for the objective function of the sum of negative sequence voltage imbalance of all nodes, node voltage data is obtained through unbalanced power flow calculation to realize the calculation of the objective function.

[0066] Furthermore, this invention employs the NSGA-II algorithm, which updates the offspring population through an elite selection strategy based on non-dominated sorting and crowding analysis to prevent the population from converging to local optima, thereby achieving a fast solution to the optimization problem and improving optimization efficiency. By using tournament selection and crossover and mutation operations, it helps to explore a wider solution space and improve the algorithm's convergence speed, thus achieving a fast solution to the optimization problem.

[0067] Furthermore, unbalanced power flow can enable accurate calculation of the three-phase voltage distribution of the local distribution network, accurately reflecting the operating status of the distribution network after the operation of the phase switching switch and the update of the SVG injection current, thereby achieving an accurate solution to the objective function of the total voltage imbalance, ensuring the effectiveness and accuracy of this method.

[0068] Furthermore, step S4 selects the optimal solution from the Pareto solution set, and then selects a compromise solution with the minimum number of commutations and a small SVG output capacity. This avoids the problem of insignificant improvement in the treatment effect due to excessive operation of the commutation switch. At the same time, considering the SVG capacity, it achieves effective treatment of system voltage imbalance with a small treatment cost.

[0069] It is understood that the beneficial effects of the second to sixth aspects mentioned above can be found in the relevant descriptions in the first aspect mentioned above, and will not be repeated here.

[0070] In summary, this invention optimizes the phase sequence of the phase-switching switches and the negative sequence output current of the SVG in the distribution network, thereby addressing the imbalance from the load side. At the same time, it combines the advantages of active compensation for fine compensation, achieving comprehensive and efficient management of voltage imbalance across all nodes in the distribution network.

[0071] The technical solution of the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0072] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the embodiments of this application will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0073] Figure 1This is a flowchart of the treatment method of the present invention;

[0074] Figure 2 This is a flowchart of the fast non-dominated sorting genetic algorithm of the present invention;

[0075] Figure 3 This is a flowchart of the three-phase unbalanced power flow algorithm used in this invention;

[0076] Figure 4 This is a diagram of the low-voltage distribution network topology.

[0077] Figure 5 A bar chart showing the negative sequence voltage imbalance at each node in the distribution network before the application of this method;

[0078] Figure 6 A schematic diagram of the Pareto optimal solution set;

[0079] Figure 7 The bar chart shows the negative sequence voltage imbalance at each node in the distribution network after the method was applied.

[0080] Figure 8 A schematic diagram of a computer device provided in an embodiment of the present invention;

[0081] Figure 9 This is a block diagram of an electronic device according to an embodiment of the present invention. Detailed Implementation

[0082] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0083] In the description of this invention, it should be understood that the terms "comprising" and "including" indicate the presence of the described features, integrals, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or collections thereof.

[0084] It should also be understood that the terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used in this specification and the appended claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise.

[0085] It should also be further understood that the term "and / or" as used in this specification and the appended claims refers to any combination and all possible combinations of one or more of the associated listed items, and includes such combinations. For example, A and / or B can represent three cases: A alone, A and B simultaneously, and B alone. Additionally, the character " / " in this invention generally indicates that the preceding and following objects have an "or" relationship.

[0086] It should be understood that although terms such as first, second, third, etc., may be used in the embodiments of the present invention to describe the preset range, these preset ranges should not be limited to these terms. These terms are only used to distinguish the preset ranges from one another. For example, without departing from the scope of the embodiments of the present invention, the first preset range may also be referred to as the second preset range, and similarly, the second preset range may also be referred to as the first preset range.

[0087] Depending on the context, the word "if" as used here can be interpreted as "when," "when," "in response to determination," or "in response to detection." Similarly, depending on the context, the phrase "if determination" or "if detection (of the stated condition or event)" can be interpreted as "when determination," "in response to determination," "when detection (of the stated condition or event)," or "in response to detection (of the stated condition or event)."

[0088] The accompanying drawings illustrate various structural schematic diagrams according to embodiments disclosed in this invention. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.

[0089] This invention provides a method for managing voltage imbalance in distribution substations based on phase-switching switches and SVG (Static Var Generator). Aiming at comprehensive management of voltage imbalance in distribution networks with a large number of single-phase loads, the method optimizes the phase sequence of the installed phase-switching switches and the output negative-sequence compensation current command of the SVG. This approach can minimize the number of phase switching cycles and the total output capacity of the SVG while maintaining the effectiveness of voltage imbalance management. This solution has good practical value and economic benefits.

[0090] Example 1

[0091] Please see Figure 1 This invention discloses a method for mitigating voltage imbalance in distribution substations based on commutation switches and SVG, comprising the following steps:

[0092] S1. Obtain the topology, line impedance data, data of each node, and data of the commutator and SVG of the distribution network;

[0093] The distribution network topology is obtained, including the three-phase network topology, the three-phase line impedance data including the three-phase line impedance of adjacent nodes, and the data of each node including the load power, voltage amplitude and phase angle of each node; the commutation switch data and SVG data are obtained, the commutation switch data including the current phase sequence of the commutation switch, and the SVG data including the rated capacity of each SVG and the current output negative sequence current.

[0094] Based on the obtained data, form Positive, negative, and zero order nodal admittance matrices , , .

[0095] S2. Based on the establishment of a multi-objective function for optimizing voltage imbalance at all nodes of the distribution network and an optimization model for the phase sequence of the switching switch and the SVG compensation command current;

[0096] S201. Determine the governance objectives for comprehensive management of three-phase imbalance in the distribution network;

[0097] The governance objective is formulated based on the national standard GB / T 15543-2008 "Power Quality - Three-Phase Voltage Imbalance" regarding the requirements for voltage imbalance during normal grid operation. The governance objective in this invention is no less than the standard in the aforementioned national standard. Specifically, the governance objective is that the negative sequence voltage imbalance at each node is <2%, as detailed below:

[0098]

[0099] in, m Represents the network node number. This represents the negative sequence voltage imbalance at nodes. Representative node m Negative sequence voltage, Representative node m Positive sequence voltage.

[0100] S202. Construct a multi-objective function for optimizing voltage imbalance across all nodes in the distribution network, as well as an optimization model for the phase sequence of commutation switches and the SVG compensation command current. The optimization objectives are to minimize the sum of negative sequence voltage imbalance across all nodes, minimize the number of commutations, and minimize the sum of the amplitudes of the negative sequence compensation current output by the SVG. Constraints include maintaining the three-phase voltage of the distribution network nodes within the range specified by national standards, ensuring that the number of consecutive operations of a single commutation switch does not exceed the specified upper limit, and ensuring that the negative sequence current output by the SVG does not exceed the rated capacity. The control variables are the phase sequence of the commutation switches and the negative sequence compensation current output by the SVG.

[0101] The objective function for total negative sequence voltage imbalance is as follows:

[0102]

[0103] in, Number the nodes. For the number of network nodes, For nodes The negative sequence voltage unbalance is calculated using the following formula: , For nodes m negative sequence voltage, For nodes m The positive sequence voltage.

[0104] The objective function for the total output capacity of SVG is as follows:

[0105]

[0106] in, k For SVG numbering, K This represents the total number of SVGs. This represents the negative sequence output current of the k-th SVG.

[0107] The objective function for the number of commutations is as follows:

[0108]

[0109] Where N is the total number of commutation cycles of the commutation switch relative to the current phase sequence.

[0110] During commutation operations, adjusting the voltage of nodes with large loads may result in significant changes that exceed the constraints. Therefore, node voltage constraints are established as follows:

[0111]

[0112] in, This represents the minimum node voltage. This represents the maximum node voltage.

[0113] To prevent the service life of the commutator switches from decreasing due to repeated consecutive operations, a maximum number of consecutive commutations is set for each commutator switch. If the number of consecutive operations of a commutator switch exceeds the specified value, its current phase sequence will remain unchanged during the next commutation. The operation constraints are as follows:

[0114]

[0115] in, For the first p The number of consecutive commutations of the commutator switch. For the first pThe maximum number of consecutive phase commutations of the commutator.

[0116] S3. The three-phase voltage of the nodes is calculated using the three-phase unbalanced power flow calculation. The non-dominated sorting genetic algorithm (NSGA-II) is used for optimization to obtain the Pareto front solution set of the commutation switch phase sequence optimization and SVG negative sequence compensation current.

[0117] S301. The three-phase unbalanced power flow and the fast non-dominated sorting genetic algorithm NSGA-II are applied to solve the multi-objective optimization model, and the multi-node voltage imbalance optimization model and the three objective functions of the model are solved.

[0118] S302. Through multiple iterations of optimization using the NSGA-Ⅱ genetic algorithm, a set of Pareto optimal solutions is obtained. The objective function of the Pareto optimal solution set is equivalent to the Pareto optimal frontier of the total negative sequence voltage imbalance, the number of commutations, and the total output capacity of the SVG.

[0119] Please see Figure 2 The NSGA-II algorithm is used to solve the multi-objective optimization problem established in step S2, as follows:

[0120] S3021. Generate the initial population for the genetic algorithm. The population size is POP. Each individual includes the phase sequence of the commutation switch and the negative sequence current of the SVG output.

[0121] S3022. Calculate the three objective functions for an individual system. The objective function for total voltage imbalance needs to be obtained from the unbalanced power flow calculation results.

[0122] Please see Figure 3 The specific steps are as follows:

[0123] S30221, Set the initial values ​​of the positive sequence, negative sequence, and zero sequence voltages of the nodes. , , The positive sequence voltage amplitude is 1.0 pu, and the negative sequence and zero sequence voltage amplitudes are 0. Calculate the initial values ​​of the three-phase voltages at the nodes. , , ;

[0124] S30222, Based on node injection power , , The three-phase current injected into the nodes is updated, and the positive-sequence, negative-sequence, and zero-sequence currents injected into the nodes in the update network are calculated based on the symmetrical component method. , , ;

[0125]

[0126] in, , , The vector represents the three-phase current injected into the node.

[0127] S30223. Calculate the node voltages in the network: The positive-sequence network is an active network, and the forward-backward substitution method is used to solve for the node positive-sequence voltages. Negative-sequence and zero-sequence networks are passive networks, and their values ​​are obtained using nodal voltage equations. , , t This represents the number of iterations.

[0128] S30224, Generating node three-phase voltage , , ;

[0129] S30225. Determine if convergence has occurred or the maximum number of iterations has been reached. If convergence has not occurred or the maximum number of iterations has not been reached, update... t=t+ 1. The next iteration begins from step S30222.

[0130] S3023, Non-dominated ranking and crowding analysis: Non-dominated ranking and crowding calculation are performed on all individuals in the population. The priority and ranking of individuals are determined using three fitness functions. Next, crowding is calculated, and individuals at the same level are ranked to prevent the algorithm from getting trapped in local optima. Retaining individuals with high crowding is beneficial to population diversity.

[0131] S3024. Select suitable parent offspring for reproduction based on the tournament selection method and put them into the mating pool. The number of individuals in the mating pool is half of the initial population.

[0132] S3025. Randomly select parent individuals from the mating pool, perform crossover and genetic operations, and generate offspring individuals;

[0133] S3026. Merge the parent and offspring populations to obtain a merged population. Based on the elite selection strategy, perform non-dominant ranking and crowding calculation on the merged population. The top-ranked POP individuals generate a new population.

[0134] S3027. Based on the objective function and number of iterations of each individual in the new population, determine whether to stop the iteration. If the iteration is not stopped, perform selection, crossover, and mutation operations on the population to generate the next generation population and proceed to step S302. If the convergence conditions are met, output the Pareto optimal solution set.

[0135] Through multiple iterations of optimization using the NSGA-II genetic algorithm, a set of Pareto optimal solutions is obtained. The objective function of the Pareto optimal solution set is equivalent to the Pareto optimal frontier of the total negative sequence voltage imbalance, commutation times, and total SVG output capacity.

[0136] S4. Screen the obtained Pareto front solution set and select the result that meets the national standard and reduces the number of commutation switches and SVG negative sequence compensation current as the optimal instruction.

[0137] Step S4 describes how to filter the obtained Pareto solution set and select the result that meets national standards and reduces the number of commutation switches and SVG negative sequence compensation current as the optimal instruction.

[0138] Specifically, firstly, feasible solutions that meet the standard are selected from the Pareto optimal solution set obtained in step S3. After adopting the phase sequence optimization command of the switching switch and the negative sequence current command of the SVG output represented by the feasible solution, the voltage imbalance of all nodes in the local distribution network meets the national standard requirements.

[0139] Then, a non-dominated sorting is performed again among the remaining feasible solutions, and the optimal compromise solution with low commutation count and small total SVG output capacity is selected as the commutation switch phase sequence optimization command and the SVG output negative sequence current command.

[0140] After the optimization instructions represented by the feasible solution set have completed the treatment of the regional distribution network system, the voltage imbalance of all nodes in the system must meet the national standard requirements, as follows:

[0141]

[0142] S5. Based on the obtained optimal instructions, issue commutation instructions and compensation current instructions to the commutation switches and SVG in the distribution network respectively to achieve comprehensive management of voltage imbalance at all nodes of the distribution network.

[0143] Based on the obtained optimal instructions, commutation instructions and compensation current instructions are issued to the commutation switches and SVG in the distribution network, respectively, to realize multi-node comprehensive compensation for voltage imbalance problems in the system.

[0144] Those skilled in the art will understand that various aspects of the present invention can be implemented as systems, methods, or program products. Therefore, various aspects of the present invention can be specifically implemented in the following forms: a completely hardware implementation, a completely software implementation (including firmware, microcode, etc.), or a combination of hardware and software aspects, collectively referred to herein as a "circuit," "module," or "platform."

[0145] Example 2

[0146] This invention provides a distribution area voltage imbalance mitigation system based on commutation switches and SVG. This system can be used to implement the above-mentioned distribution area voltage imbalance mitigation method based on commutation switches and SVG. Specifically, the distribution area voltage imbalance mitigation system based on commutation switches and SVG includes a data module, a construction module, an optimization module, a filtering module, and an output module.

[0147] The data module acquires the topology, line impedance data, data of each node, and data of the phase-changing switch and SVG of the distribution network.

[0148] The module is constructed based on the obtained distribution network topology, line impedance data, data of each node, data of commutation switches and SVG, to establish a multi-objective function for optimizing the voltage imbalance of all nodes in the distribution network and an optimization model for the phase sequence of commutation switches and the compensation command current of SVG.

[0149] The optimization module uses the three-phase voltage of the node to calculate the three-phase unbalanced power flow, and uses the fast non-dominated sorting genetic algorithm to optimize the obtained commutation switch phase sequence and SVG compensation command current optimization model, and obtains the Pareto front solution set of the commutation switch phase sequence optimization and SVG negative sequence compensation current.

[0150] The filtering module filters the obtained Pareto front solution set and selects the result that meets national standards and reduces the number of commutation switches and SVG negative sequence compensation current as the optimal instruction.

[0151] The output module, based on the obtained optimal instructions, sends commutation instructions and compensation current instructions to the commutation switches and SVG in the distribution network, respectively, to achieve comprehensive management of voltage imbalance across all nodes of the distribution network.

[0152] Example 3

[0153] This invention provides a terminal device comprising a processor and a memory. The memory stores a computer program, which includes program instructions. The processor executes the program instructions stored in the computer storage medium. The processor may be a Central Processing Unit (CPU), or other general-purpose processors, graphics processing units (GPUs), tensor processing units (TPUs), digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. It is the computing and control core of the terminal, suitable for implementing one or more instructions, specifically suitable for loading and executing one or more instructions to achieve a corresponding method flow or function. The processor described in this embodiment can be used in the operation of a distribution station voltage imbalance mitigation method based on commutation switches and SVG, including:

[0154] Data on the topology, line impedance, individual nodes, commutator switches, and SVG of the distribution network are acquired. Based on this data, a multi-objective function for optimizing voltage imbalance across all nodes in the distribution network, as well as optimization models for commutator switch phase sequence and SVG compensation command current, are established. Three-phase voltage at nodes is calculated using three-phase unbalanced power flow. A fast non-dominated sorting genetic algorithm is used to optimize the commutator switch phase sequence and SVG compensation command current models, yielding Pareto front solutions for commutator switch phase sequence optimization and SVG negative-sequence compensation current. The Pareto front solutions are then selected to meet national standards while reducing the number of commutator switches and SVG negative-sequence compensation current as the optimal command. Based on the optimal command, commutator commands and compensation current commands are issued to the commutator switches and SVGs within the distribution network, achieving comprehensive management of voltage imbalance across all nodes in the distribution network.

[0155] Please see Figure 8The terminal device is a computer device. In this embodiment, the computer device 60 includes a processor 61, a memory 62, and a computer program 63 stored in the memory 62 and executable on the processor 61. When executed by the processor 61, the computer program 63 implements the distribution area voltage imbalance mitigation method based on commutation switches and SVG in this embodiment. To avoid repetition, these details are not elaborated here. Alternatively, when executed by the processor 61, the computer program 63 implements the functions of each model / unit in the distribution area voltage imbalance mitigation system based on commutation switches and SVG in this embodiment. To avoid repetition, these details are not elaborated here.

[0156] Computer device 60 can be a desktop computer, laptop, handheld computer, cloud server, or other computing device. Computer device 60 may include, but is not limited to, a processor 61 and a memory 62. Those skilled in the art will understand that... Figure 8 This is merely an example of computer device 60 and does not constitute a limitation on computer device 60. It may include more or fewer components than shown, or combine certain components, or different components. For example, computer device may also include input / output devices, network access devices, buses, etc.

[0157] The processor 61 may be a Central Processing Unit (CPU), or other general-purpose processors, graphics processing units (GPUs), tensor processing units (TPUs), digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or any conventional processor.

[0158] The memory 62 can be an internal storage unit of the computer device 60, such as a hard disk or RAM of the computer device 60. The memory 62 can also be an external storage device of the computer device 60, such as a plug-in hard disk, smart media card (SMC), secure digital (SD) card, flash card, etc., provided on the computer device 60.

[0159] Furthermore, the memory 62 may include both internal storage units of the computer device 60 and external storage devices. The memory 62 is used to store computer programs and other programs and data required by the computer device. The memory 62 can also be used to temporarily store data that has been output or will be output.

[0160] Please see Figure 9 The terminal device is an electronic device 600, which is manifested in the form of a general-purpose computing device. The components of the electronic device may include, but are not limited to: at least one processing unit 610, at least one storage unit 620, a bus 630 connecting different platform components (including storage unit 620 and processing unit 610), a display unit 640, etc.

[0161] The storage unit stores program code, which can be executed by the processing unit 610 to perform the steps described in the method section of this specification according to various exemplary embodiments of the present invention. For example, the processing unit 610 can perform actions such as... Figure 1 The steps are shown in the figure.

[0162] Storage unit 620 may include a readable medium in the form of a volatile storage unit, such as random access memory (RAM) 6201 and / or cache memory 6202, and may further include a read-only memory (ROM) 6203.

[0163] Storage unit 620 may also include a program / utility 6204 having a set (at least one) program module 6205, such program module 6205 including but not limited to: operating system, one or more application programs, other program modules and program data, each or some combination of these examples may include an implementation of a network environment.

[0164] Bus 630 can represent one or more of several types of bus structures, including a memory cell bus or memory cell controller, a peripheral bus, a graphics acceleration port, a processing unit, or a local bus using any of the multiple bus structures.

[0165] Electronic device 600 can also communicate with one or more external devices 700 (e.g., keyboard, pointing device, Bluetooth device, etc.), and with one or more devices that enable a user to interact with electronic device 600, and / or with any device that enables electronic device 600 to communicate with one or more other computing devices (e.g., router, modem, etc.). This communication can be performed via input / output (I / O) interface 650. Furthermore, electronic device 600 can also communicate with one or more networks (e.g., local area network (LAN), wide area network (WAN), and / or public networks, such as the Internet) via network adapter 660. Network adapter 660 can communicate with other modules of electronic device 600 via bus 630. It should be understood that, although not shown in the figures, other hardware and / or software modules can be used in conjunction with electronic device 600, including but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data backup storage platforms.

[0166] Example 4

[0167] This invention also provides a storage medium, specifically a computer-readable storage medium (Memory), which is a memory device in a terminal device used to store programs and data. It is understood that the computer-readable storage medium here can include both built-in storage media in the terminal device and extended storage media supported by the terminal device; it can be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, apparatus, or device. The computer-readable storage medium provides storage space that stores the terminal's operating system. Furthermore, the storage space also stores one or more instructions suitable for loading and execution by a processor, which can be one or more computer programs (including program code). It should be noted that more specific examples (a non-exhaustive list) of the computer-readable storage medium include: an electrical connection having one or more wires, a portable disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0168] Computer-readable storage media also include data signals propagated in baseband or as part of a carrier wave, carrying readable program code. Such propagated data signals can take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. A readable storage medium can also be any readable medium other than a readable storage medium that can send, propagate, or transmit a program for use by or in connection with an instruction execution system, apparatus, or device. The program code contained on the readable storage medium can be transmitted using any suitable medium, including but not limited to wireless, wired, optical fiber, RF, etc., or any suitable combination thereof.

[0169] Program code for performing the operations of this invention can be written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Java and C++, and conventional procedural programming languages ​​such as C or similar languages. The program code can execute entirely on the user's computing device, partially on the user's device, as a standalone software package, partially on the user's computing device and partially on a remote computing device, or entirely on a remote computing device or server. In cases involving remote computing devices, the remote computing device can be connected to the user's computing device via any type of network, including a local area network (LAN) or a wide area network (WAN), or it can be connected to an external computing device (e.g., via the Internet using an Internet service provider).

[0170] One or more instructions stored in a computer-readable storage medium can be loaded and executed by a processor to implement the corresponding steps of the distribution network voltage imbalance mitigation method based on commutation switches and SVG in the above embodiments; one or more instructions in the computer-readable storage medium are loaded by the processor and executed as follows:

[0171] Data on the topology, line impedance, individual nodes, commutator switches, and SVG of the distribution network are acquired. Based on this data, a multi-objective function for optimizing voltage imbalance across all nodes in the distribution network, as well as optimization models for commutator switch phase sequence and SVG compensation command current, are established. Three-phase voltage at nodes is calculated using three-phase unbalanced power flow. A fast non-dominated sorting genetic algorithm is used to optimize the commutator switch phase sequence and SVG compensation command current models, yielding Pareto front solutions for commutator switch phase sequence optimization and SVG negative-sequence compensation current. The Pareto front solutions are then selected to meet national standards while reducing the number of commutator switches and SVG negative-sequence compensation current as the optimal command. Based on the optimal command, commutator commands and compensation current commands are issued to the commutator switches and SVGs within the distribution network, achieving comprehensive management of voltage imbalance across all nodes in the distribution network.

[0172] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0173] To demonstrate the correctness and effectiveness of the proposed method, the following section, in conjunction with accompanying figures and simulation tests, verifies the overall node imbalance suppression effect of the proposed distribution network voltage imbalance mitigation method.

[0174] Figure 4 The system is a 15-node power distribution network with 8 phase-changing switches installed at nodes 3, 4, 7, 8, 10, 11, 12, and 13, and 2 SVG units installed at nodes 2 and 11. A large number of single-phase loads are connected to the nodes, resulting in significant voltage imbalance within the system.

[0175] The initial phase sequence of the commutation switch is shown in Table 1:

[0176] Table 1

[0177]

[0178] Figure 5The figure shows the negative sequence voltage imbalance at each node in the local distribution network before the treatment. According to national standards, the negative sequence voltage imbalance should be less than 2% during normal operation of the power grid. As shown in the figure, each node in the system has a high negative sequence voltage imbalance, with the highest approaching 10%, which far exceeds the national standard.

[0179] As mentioned earlier, the phase sequence of the commutator switches and the negative-sequence current output of the SVG are optimized based on the NSGA-II algorithm. The objective functions are the sum of the negative-sequence voltage imbalance across all nodes, minimizing the number of commutation switches, and minimizing the SVG output compensation current capacity. The Pareto optimal solution set for the commutator switching phase sequence and the SVG output negative-sequence current is calculated. As shown in the figure, when the number of commutator switches is 0 (i.e., when none of the commutator switches operate), the two installed SVGs can mitigate the voltage imbalance across all nodes to a certain extent, but cannot guarantee that all node voltage imbalances meet national standards. With the increase in the number of commutator switches operating, the voltage imbalance of the system after mitigation decreases, and the total output current capacity of the SVG required for the same mitigation effect decreases, leading to a feasible solution that meets national standards.

[0180] Among the feasible solutions obtained, the optimal compromise solution with a smaller number of commutation switches and a smaller total negative sequence current capacity of the SVG is selected. The solution with 3 commutation switches can be selected. The phase sequence of the commutation switches is shown in Table 2, and the negative sequence current of the SVG output is shown in Table 3.

[0181] Table 2

[0182]

[0183] Table 3

[0184]

[0185] Figure 7 As shown in the figure, the negative sequence voltage imbalance of each node in the system after treatment has been reduced to below the national standard. This result verifies the economy and feasibility of the treatment method proposed in this invention.

[0186] In summary, this invention provides a distribution network voltage imbalance mitigation method and system based on phase-switching switches and SVG. It uses the overall voltage imbalance of the distribution network as the mitigation target, specifically the negative-sequence three-phase voltage imbalance. Compared to traditional phase-switching switch mitigation schemes, this method can suppress voltage imbalance across all nodes, not just the low-voltage side current imbalance of the transformer. The imbalance calculated using three-phase unbalanced power flow considers both voltage amplitude and phase, better reflecting the actual operating state of the distribution network. By optimizing the phase sequence of the phase-switching switches and the negative-sequence output current of the SVG in the distribution network, comprehensive mitigation of voltage imbalance across all nodes can be achieved. This approach addresses imbalance from the load side while incorporating the advantages of active compensation for precise compensation.

[0187] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is merely an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiments can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit. Furthermore, the specific names of the functional units and modules are only for easy differentiation and are not intended to limit the scope of protection of this application. The specific working process of the units and modules in the above system can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0188] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0189] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed in this invention can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.

[0190] In the embodiments provided by this invention, it should be understood that the disclosed devices / terminals and methods can be implemented in other ways. For example, the device / terminal embodiments described above are merely illustrative. For instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.

[0191] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0192] Furthermore, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0193] If the integrated module / unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, all or part of the processes in the methods of the above embodiments can also be implemented by a computer program instructing related hardware. The computer program can be stored in a computer-readable storage medium, and when executed by a processor, it can implement the steps of the various method embodiments described above. The computer program includes computer program code, which can be in the form of source code, object code, executable files, or certain intermediate forms. The computer-readable medium can include: any entity or device capable of carrying the computer program code, recording media, USB flash drives, portable hard drives, magnetic disks, optical disks, computer memory, read-only memory (ROM), random-access memory (RAM), electrical carrier signals, telecommunication signals, and software distribution media, etc. It should be noted that the content included in the computer-readable medium can be appropriately added or removed according to the requirements of legislation and patent practice in the jurisdiction. For example, in some jurisdictions, according to legislation and patent practice, computer-readable media do not include electrical carrier signals and telecommunication signals.

[0194] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus, and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart... Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0195] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0196] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0197] The above content is only for illustrating the technical concept of the present invention and should not be construed as limiting the scope of protection of the present invention. Any modifications made to the technical solution based on the technical concept proposed in this invention shall fall within the scope of protection of the claims of this invention.

Claims

1. A method for mitigating voltage imbalance in distribution substations based on commutation switches and SVG, characterized in that, Includes the following steps: S1. Obtain the distribution network topology, line impedance data, data for each node, and data for commutator switches and SVGs. The distribution network topology includes the three-phase network topology; the three-phase line impedance data includes the three-phase line impedance of adjacent nodes; the data for each node includes the load power, voltage amplitude, and phase angle data of each node; the commutator switch data includes the current phase sequence of the commutator switches; the SVG data includes the rated capacity of each SVG and the current output negative sequence current; form... Positive, negative, and zero order nodal admittance matrices , , ; S2. Based on the distribution network topology, line impedance data, data of each node, and data of commutator switches and SVG obtained in step S1, establish a multi-objective function for optimizing the voltage imbalance of all nodes in the distribution network, as well as an optimization model for the phase sequence of commutator switches and the SVG compensation command current. Specifically: S201. The comprehensive management target for the three-phase imbalance of the distribution network is set as negative sequence voltage imbalance at each node <2%; S202. Construct a multi-objective function for optimizing voltage imbalance at all nodes in the distribution network, as well as an optimization model for the phase sequence of commutation switches and the SVG compensation command current. The optimization objectives are to minimize the sum of negative sequence voltage imbalance at all nodes, minimize the number of commutations, and minimize the sum of the negative sequence compensation current amplitudes of the SVG output. Constraints include maintaining the three-phase voltage at the distribution network nodes within the range specified by national standards, ensuring that the number of consecutive operations of a single commutation switch does not exceed the specified upper limit, and ensuring that the negative sequence current output by the SVG does not exceed the rated capacity. The control variables are the phase sequence switching of the commutation switch and the negative sequence compensation current output by the SVG; S3. Using a three-phase unbalanced power flow to calculate the three-phase voltage at the nodes, the fast non-dominated sorting genetic algorithm is used to optimize the commutation switch phase sequence and SVG compensation command current optimization model obtained in step S2, resulting in the Pareto front solution set for the commutation switch phase sequence optimization and SVG negative sequence compensation current. The three-phase unbalanced power flow and the fast non-dominated sorting genetic algorithm NSGA-II are applied to solve the multi-objective optimization model, solving the multi-node voltage imbalance optimization model and its three objective functions. Through multiple iterations of optimization using the fast non-dominated genetic algorithm, a Pareto optimal solution set is obtained. The objective function of the Pareto optimal solution set is equivalent to the Pareto optimal front of the total negative sequence voltage imbalance degree, the number of commutations, and the total output capacity of the SVG. S4. Screen the Pareto front solution set obtained in step S3, and select the result that meets the national standard and reduces the number of commutation switches and the negative sequence compensation current of SVG as the optimal instruction. S5. Based on the optimal instruction obtained in step S4, issue commutation instructions and compensation current instructions to the commutation switches and SVG in the distribution network respectively to achieve comprehensive management of voltage imbalance at all nodes of the distribution network.

2. The method for managing voltage imbalance in distribution substations based on commutation switches and SVG according to claim 1, characterized in that, The multi-objective function for optimizing voltage imbalance across all nodes in a distribution network includes: Total negative sequence voltage imbalance objective function: in, Number the nodes. For the number of network nodes, For nodes Negative sequence voltage imbalance , For nodes m negative sequence voltage, For nodes m The positive sequence voltage; Objective function for total output capacity of SVG: in, k For SVG numbering, K This represents the total number of SVGs. This represents the negative sequence output current of the k-th SVG. Objective function for commutation number: in, This represents the total number of commutations of the commutator relative to the current phase sequence.

3. The method for managing voltage imbalance in distribution substations based on commutation switches and SVG according to claim 1, characterized in that, The node voltage constraints are as follows: in, This represents the minimum node voltage. This represents the maximum node voltage. Each commutator switch is set with a maximum number of consecutive commutations. If the number of consecutive operations of a certain commutator switch exceeds the specified value, its current phase sequence will remain unchanged during the next commutation. The operation constraints are as follows: in, For the first p The number of consecutive commutations of the commutator switch. For the first p The maximum number of consecutive phase commutations of the commutator.

4. The method for managing voltage imbalance in distribution substations based on commutation switches and SVG according to claim 1, characterized in that, The NSGA-II algorithm is used to solve the multi-objective optimization problem established in step S2, as follows: S3021. Generate the initial population for the genetic algorithm. The population size is POP. Each individual includes the phase sequence of the commutation switch and the negative sequence current of the SVG output. S3022. Calculate the three objective functions for an individual. The objective function for total voltage imbalance needs to be obtained from the results of unbalanced power flow calculation. S3023, Non-dominated ranking and crowding analysis: Non-dominated ranking and crowding calculation are performed on all individuals in the population. The priority and ranking of individuals in the population are determined by the three fitness functions of the individuals. Secondly, the crowding degree is calculated, and individuals at the same level are sorted to prevent the algorithm solution from getting trapped in local optima; retaining individuals with high crowding degree is beneficial to population diversity. S3024. Select suitable parent offspring for reproduction based on the tournament selection method and put them into the mating pool. The number of individuals in the mating pool is half of the initial population. S3025. Randomly select parent individuals from the mating pool, perform crossover and genetic operations, and generate offspring individuals; S3026. Merge the parent and offspring populations to obtain a merged population. Based on the elite selection strategy, perform non-dominant ranking and crowding calculation on the merged population. The top-ranked POP individuals generate a new population. S3027. Based on the objective function and number of iterations of each individual in the new population, determine whether to stop the iteration. If the iteration is not stopped, perform selection, crossover, and mutation operations on the population to generate the next generation population and proceed to step S302. If the convergence conditions are met, output the Pareto optimal solution set.

5. The method for managing voltage imbalance in distribution substations based on commutation switches and SVG according to claim 4, characterized in that, In step S3022, the objective function for total voltage imbalance is obtained through the unbalanced power flow calculation results, as follows: S30221, Set the initial values ​​of the positive sequence, negative sequence, and zero sequence voltages of the nodes. , , The positive sequence voltage amplitude is 1.0 pu, and the negative sequence and zero sequence voltage amplitudes are 0. Calculate the initial values ​​of the three-phase voltages at the nodes. , , ; S30222, Based on node injection power , , The three-phase current injected into the nodes is updated, and the positive-sequence, negative-sequence, and zero-sequence currents injected into the nodes in the update network are calculated based on the symmetrical component method. , , ; S30223, the positive sequence network is an active network, and the forward-backward substitution method is used to solve for the nodal positive sequence voltages. Negative-sequence and zero-sequence networks are passive networks, and their values ​​are obtained using nodal voltage equations. , , t This represents the number of iterations. S30224, Generating node three-phase voltage , , ; S30225. Determine if convergence has occurred or the maximum number of iterations has been reached. If convergence has not occurred or the maximum number of iterations has not been reached, update... t= t+ 1. The next iteration begins from step S30222.

6. The method for managing voltage imbalance in distribution substations based on commutation switches and SVG according to claim 1, characterized in that, In step S4, feasible solutions that meet the standard are first selected from the Pareto optimal solution set obtained in step S3. After adopting the phase sequence optimization command of the switching switch and the negative sequence current command of SVG output represented by the feasible solution, the voltage imbalance of all nodes in the local distribution network meets the national standard requirements. Then, a non-dominated sorting is performed again among the remaining feasible solutions. The optimal compromise solution with low commutation count and small total SVG output capacity is selected as the commutation switch phase sequence optimization command and the SVG output negative sequence current command.

7. A distribution substation voltage imbalance mitigation system based on a commutator switch and an SVG, characterized in that, include: The data module acquires the distribution network topology, line impedance data, data for each node, and data for commutator switches and SVGs. The distribution network topology includes the three-phase network topology; the three-phase line impedance data includes the three-phase line impedance of adjacent nodes; the data for each node includes the load power, voltage amplitude, and phase angle data for each node; the commutator switch data includes the current phase sequence of the commutator switches; and the SVG data includes the rated capacity of each SVG and the current output negative sequence current. This data forms... Positive, negative, and zero order nodal admittance matrices , , ; The construction module, based on the obtained distribution network topology, line impedance data, data of each node, and data of commutator switches and SVG, establishes a multi-objective function for optimizing the voltage imbalance of all nodes in the distribution network, as well as an optimization model for the phase sequence of commutator switches and the compensation command current of SVG. Specifically: The comprehensive management objective for three-phase imbalance in the distribution network is set as negative sequence voltage imbalance at each node <2%. A multi-objective function for optimizing voltage imbalance across all nodes in the distribution network, as well as an optimization model for the phase sequence of commutation switches and the SVG compensation command current, are constructed. The optimization objectives are to minimize the sum of negative sequence voltage imbalances across all nodes, minimize the number of commutations, and minimize the sum of the negative sequence compensation current amplitudes output by the SVG. Constraints include maintaining the three-phase voltage at distribution network nodes within the range specified by national standards, ensuring that the number of consecutive operations of a single commutation switch does not exceed the specified upper limit, and ensuring that the negative sequence current output by the SVG does not exceed its rated capacity. The control variables are the phase sequence switching of the commutation switch and the negative sequence compensation current output by the SVG; The optimization module uses a three-phase unbalanced power flow to calculate the three-phase voltage at the nodes. A fast non-dominated sorting genetic algorithm is used to optimize the obtained commutation switch phase sequence and SVG compensation command current optimization model, yielding the Pareto front solution set for the commutation switch phase sequence optimization and the SVG negative-sequence compensation current. The three-phase unbalanced power flow and the fast non-dominated sorting genetic algorithm NSGA-II are applied to solve the multi-objective optimization model, solving for the multi-node voltage imbalance optimization model and its three objective functions. Through multiple iterative optimizations using the fast non-dominated genetic algorithm, a Pareto optimal solution set is obtained. The objective function of the Pareto optimal solution set is equivalent to the Pareto optimal front of the total negative-sequence voltage imbalance, the number of commutations, and the total output capacity of the SVG. The filtering module filters the obtained Pareto front solution set and selects the result that meets national standards and reduces the number of commutation switches and SVG negative sequence compensation current as the optimal instruction. The output module, based on the obtained optimal instructions, sends commutation instructions and compensation current instructions to the commutation switches and SVG in the distribution network, respectively, to achieve comprehensive management of voltage imbalance across all nodes of the distribution network.

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