Inverter BUS bus capacitor voltage-sharing control method

Abstract

The invention relates to an inverter BUS bus capacitor voltage-sharing control method, which is used for detecting capacitor voltage of positive and negative bus capacitors arranged between BUS buses and determining whether voltage-sharing control needs to be carried out or not, if the voltage-sharing control needs to be carried out, a single-phase inverter circuit of any phase in an inverter circuit is used as a voltage-sharing circuit, and if the voltage-sharing control needs to be carried out, a single-phase inverter circuit of any phase is used as a voltage-sharing circuit; and carrying out discharge voltage sharing on the positive bus capacitor or the negative bus capacitor through an inversion capacitor and an inversion inductor in the single-phase inversion circuit. On the basis of an existing inverter hardware circuit, by combining control of the control method, voltage-sharing processing of the bus capacitor is achieved, control over the capacitor voltage of the bus capacitor is completed on the premise that the hardware cost is not increased, the cost is low, and the inverter can operate safely and stably.

Description

Technical Field

[0001] The present invention relates to the technical field of safety circuits, and in particular to a method for controlling the voltage balancing of a BUS bus capacitor of an inverter. Background Art

[0002] With the rapid development of the global economy, the demand for electric energy is increasing. As a clean energy and a sustainable energy, the application of solar energy is increasing, and the corresponding application of photovoltaic inverters is also becoming more and more extensive.

[0003] The common architecture of photovoltaic inverters is a two-stage topology, with the front stage being a BOOST boost circuit and the back stage being an INVERTER inverter circuit. Figure 1 For example, the front stage can be a multi-channel string boost circuit, the middle stage is a bus capacitor, and the back stage is an inverter circuit. After inversion, it is converted into AC output and connected to the grid. As the voltage and power of the photovoltaic inverter are also increasing, the back stage needs to adopt a three-level inverter circuit. The use of a three-level inverter circuit involves the introduction of positive BUS electrolytic bus capacitors and negative BUS electrolytic bus capacitors. Bus capacitors play an important role in smoothing voltage, reducing inductance parameters, protecting inverters, storing and releasing energy, improving power factor, and providing instantaneous power. However, electrolytic capacitors generally have a withstand voltage limit. If this limit is exceeded, the electrolytic capacitor will burst. Therefore, photovoltaic inverters generally have a strategy for equalizing the voltage of positive and negative bus capacitors.

[0004] When the inverter is in operation, a control algorithm can be used to achieve equal voltages between the positive and negative BUS electrolytic capacitors. When the inverter is in sleep mode, such as when the system is in standby mode, the voltage of the electrolytic capacitor is in a natural equalized voltage state because the inverter circuit is not working. However, due to the inconsistent leakage current of the electrolytic capacitor and the inconsistency of the relevant resistance of the entire circuit, such as the sampling resistor, between the positive and negative poles of the BUS bus, it is very easy to cause uneven capacitor voltages between the positive bus capacitor and the negative bus capacitor. If the imbalance between the positive bus capacitor and the negative bus capacitor is too large, it will cause overvoltage of the electrolytic capacitor, causing damage and explosion of the inverter.

[0005] In summary, it is necessary to introduce a balancing mechanism to balance the capacitor voltages of the positive and negative bus capacitors when the inverter is in sleep mode. Summary of the invention

[0006] A main purpose of the present invention is to overcome at least one of the above-mentioned defects, and to provide an inverter BUS bus capacitor voltage equalization control method, which can realize dynamic voltage equalization of the bus capacitor by adjusting the inverter circuit combined with the control algorithm when the inverter is in sleep mode, while simplifying the circuit structure and reducing cost investment.

[0007] In order to achieve the above object, the technical solution adopted by the present invention is: The present invention provides a method for controlling voltage balancing of a BUS bus capacitor of an inverter, which is used for voltage balancing and processing positive and negative bus capacitors between BUS buses, wherein a positive bus capacitor and a negative bus capacitor are connected in series and then connected between the BUS buses, and the BUS buses are connected to the positive and negative bus capacitors and then to an inverter circuit of an inverter, wherein the capacitor voltages of the positive bus capacitor and the negative bus capacitor are detected and it is determined whether voltage balancing control is required, and if voltage balancing control is required, a single-phase inverter circuit of any one phase in the inverter circuit is used as a voltage balancing circuit, and the positive bus capacitor or the negative bus capacitor is discharged and voltage balanced through an inverter capacitor and an inverter inductor in the single-phase inverter circuit.

[0008] According to one embodiment of the present invention, the single-phase inverter circuit includes a first bridge arm and a second bridge arm, the first bridge arm and the second bridge arm form a T-shaped inverter circuit or an I-shaped inverter circuit, the connection point of the first bridge arm and the second bridge arm is connected in series with the inverter inductor and the inverter capacitor, and the inverter capacitor is further connected to the connection midpoint of the positive and negative bus capacitors. Among them, by controlling the switch tubes in the first bridge arm and the second bridge arm to be intermittently turned on or off, the bus capacitor with a higher capacitance voltage among the positive and negative bus capacitors is controlled to periodically use the inverter capacitor and the inverter inductor to discharge and balance the voltage.

[0009] According to one embodiment of the present invention, in the process of discharging and equalizing the one of the positive and negative bus capacitors with a higher capacitor voltage, firstly, some of the switch tubes in the first bridge arm and the second bridge arm are controlled to be turned on or off, so that the positive bus capacitor or the negative bus capacitor to be discharged and equalized is first connected in series with the inverter capacitor, and the positive bus capacitor or the negative bus capacitor charges the inverter capacitor, and then some of the switch tubes in the first bridge arm and the second bridge arm are controlled to be turned off or on, so that the connection between the positive bus capacitor or the negative bus capacitor to be discharged and equalized is disconnected from the inverter capacitor, and the inverter capacitor is discharged through the inverter inductor; the process of periodically charging the inverter capacitor and then discharging it through the inverter inductor is performed to realize the discharge and equalization of the positive bus capacitor or the negative bus capacitor with a higher capacitor voltage.

[0010] According to one embodiment of the present invention, the first bridge arm and the second bridge arm form a T-shaped inverter circuit, the first bridge arm is two switch tubes connected in series in sequence, the first bridge arm is arranged between the BUS bus bars and connected in parallel with the positive and negative bus capacitors, the second bridge arm is two switch tubes connected in series in reverse order, the first end of the second bridge arm is connected to the connection midpoint of the positive and negative bus capacitors, and the first end of the second bridge arm is connected to the midpoint of the first bridge arm. Among them, when there is a first bus capacitor whose capacitor voltage is higher than a threshold value among the positive and negative bus capacitors, the switch tube connected to the first bus capacitor in the first bridge arm is first controlled to be turned on, so that the first bus capacitor charges the inverter capacitor, and then the switch tube connected to the first bus capacitor in the first bridge arm is controlled to be turned off, and the two switch tubes in the second bridge arm are turned on, and the inverter capacitor is discharged through the inverter inductor connected in series with it; the process of periodically charging the inverter capacitor and then discharging it through the inverter inductor is carried out to achieve discharge and voltage equalization of the first bus capacitor with a higher capacitor voltage.

[0011] According to one embodiment of the present invention, during the process of discharging and balancing the first bus capacitor with a higher capacitor voltage, each switch tube in the first bridge arm and the second bridge arm receives a control signal to cooperate with being turned on or off. Among them, a bus capacitor with a higher voltage among the positive and negative bus capacitors is recorded as a first bus capacitor, and the other bus capacitor is recorded as a second bus capacitor. The switch tube connected to the first bus capacitor in the first bridge arm receives a first PWM signal to be intermittently turned on or off, the switch tube connected to the second bus capacitor in the first bridge arm is constantly turned off, one switch tube in the second bridge arm is constantly turned on, and the other switch tube in the second bridge arm receives a second PWM signal to be intermittently turned off or on, and the level states of the first PWM signal and the second PWM signal are complementary in time.

[0012] According to one embodiment of the present invention, the first bridge arm and the second bridge arm form an I-shaped inverter circuit, the first bridge arm and the second bridge arm are two switch tubes connected in series in sequence, the first bridge arm and the second bridge arm are connected in series and arranged between the BUS busbars, one end of the first bridge arm is connected to the positive busbar capacitor, one end of the second bridge arm is connected to the negative busbar capacitor, the negative side of the two diodes connected in series is connected to the connection midpoint of the first bridge arm, the positive side is connected to the connection midpoint of the second bridge arm, and the connection midpoint of the positive and negative busbar capacitors is connected to the connection midpoint of the two diodes; Among them, when there is a first bus capacitor with a capacitor voltage higher than a threshold value among the positive and negative bus capacitors, the two switch tubes in the bridge arm connected to the first bus capacitor are controlled to be turned on, so that the first bus capacitor charges the inverter capacitor, and then the two adjacent switch tubes in the first bridge arm and the second bridge arm are controlled to be turned on, and the other two switch tubes are turned off, and the inverter capacitor is discharged through the inverter inductor connected in series with it; the process of periodically charging the inverter capacitor and then discharging it through the inverter inductor is carried out to achieve discharge and voltage equalization of the first bus capacitor with a higher capacitor voltage.

[0013] According to one embodiment of the present invention, during the process of discharging and balancing the first bus capacitor with a higher capacitor voltage, each switch tube in the first bridge arm and the second bridge arm receives a control signal to cooperate with being turned on or off. Among them, a bus capacitor with a higher voltage among the positive and negative bus capacitors is recorded as a first bus capacitor, and the other bus capacitor is recorded as a second bus capacitor. The switch tube directly connected to the first bus capacitor in the bridge arm connected to the first bus capacitor is recorded as a first switch tube, and the other switch tube is recorded as a second switch tube. The switch tube directly connected to the second bus capacitor in the bridge arm connected to the second bus capacitor is recorded as a fourth switch tube, and the other switch tube is recorded as a third switch tube, that is, the first switch tube, the second switch tube, the third switch tube, and the fourth switch tube are sequentially connected in series and then connected between the BUS busbars; the first switch tube receives the first PWM signal to be intermittently turned on or off, the second switch tube is constantly turned on, the third switch tube receives the second PWM signal to be intermittently turned off or turned on, and the fourth switch tube is constantly turned off, and the level states of the first PWM signal and the second PWM signal are complementary in time.

[0014] According to one embodiment of the present invention, each switch tube in the first bridge arm and the second bridge arm has a body diode, and the conduction direction of the body diode is opposite to the conduction direction of the switch tube in which it is located.

[0015] According to one embodiment of the present invention, when detecting the capacitor voltages of the positive bus capacitor and the negative bus capacitor and determining whether voltage equalization control is required, the capacitor voltages of the positive bus capacitor and the negative bus capacitor are collected and compared with the half-bus voltage respectively. If the capacitor voltage of one of the bus capacitors is greater than the half-bus voltage and exceeds a preset lower limit threshold, the first bus capacitor with a higher capacitor voltage is discharged for voltage equalization until the capacitor voltage of the first bus capacitor is lower than a preset safety voltage threshold.

[0016] According to one embodiment of the present invention, when the positive bus capacitor or the negative bus capacitor is discharged and voltage-balanced by the inverter capacitor and the inverter inductor in the single-phase inverter circuit, the inverter is in a standby state.

[0017] According to one embodiment of the present invention, the positive bus capacitor or the negative bus capacitor each includes at least one capacitor, and the capacitors in each bus capacitor are connected in series to form a capacitor group. The capacitor group with one side connected to the positive pole of the BUS bus is recorded as the positive bus capacitor, and the capacitor group with one side connected to the negative pole of the BUS bus is recorded as the negative bus capacitor.

[0018] In particular, the present invention also provides a computing device, comprising a memory, a processor, and a computer program stored in the memory and executable by the processor, wherein the processor implements the method as described above when executing the computer program.

[0019] The present invention also provides a computer-readable storage medium, in which a computer program is stored, and when the computer program is executed by a processor, the method described above is implemented. The computer-readable storage medium is preferably a non-volatile readable storage medium.

[0020] Compared with the prior art, the advantages and beneficial effects of the inverter BUS bus capacitor voltage balancing control method of the present invention patent application are: The inverter BUS bus capacitor voltage equalization control method of the present application does not add additional hardware circuits. On the basis of the existing inverter hardware circuit, combined with the control of the control method, it realizes the voltage equalization processing of the bus capacitor, and completes the control of the capacitor voltage of the bus capacitor without increasing the hardware cost, thereby achieving low cost and enabling the inverter to operate safely and stably. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Hereinafter, some specific embodiments of the present invention will be described in detail in an exemplary and non-limiting manner with reference to the accompanying drawings. The same reference numerals in the accompanying drawings indicate the same or similar components or parts. It should be understood by those skilled in the art that these drawings are not necessarily drawn to scale. In the accompanying drawings: Figure 1 It is a schematic diagram of the topological structure of the inverter in the prior art; Figure 2 1 is a schematic diagram of a circuit structure for voltage balancing control in a T-shaped inverter circuit according to an embodiment of the present invention; Figure 3 1 is a schematic diagram of a circuit structure for voltage balancing control in a T-shaped inverter circuit according to an embodiment of the present invention, wherein the current flow direction when the inverter capacitor C3 is charged is shown, and the voltage of the positive bus capacitor C1 is relatively high; Figure 4a and Figure 4b 1 is a schematic diagram of a circuit structure for voltage balancing control in a T-shaped inverter circuit according to an embodiment of the present invention, wherein the current flow direction when discharging through the inverter inductor L1 is shown, and the voltage of the positive bus capacitor C1 is relatively high; Figure 5 1 is a waveform diagram of main components for voltage balancing control in a T-shaped inverter circuit according to an embodiment of the present invention; Figure 61 is a schematic diagram of a circuit structure for voltage balancing control in a T-shaped inverter circuit according to an embodiment of the present invention, wherein the current flow direction when the inverter capacitor C3 is charged is shown, and the voltage of the negative bus capacitor C2 is relatively high; Figure 7a and Figure 7b 1 is a schematic diagram of a circuit structure for voltage balancing control in a T-shaped inverter circuit according to an embodiment of the present invention, wherein the current flow direction when discharging through the inverter inductor L1 is shown, and the voltage of the negative bus capacitor C2 is relatively high; Figure 8 1 is a schematic diagram of a circuit structure for voltage balancing control in an I-shaped inverter circuit according to an embodiment of the present invention; Fig. 9 1 is a schematic diagram of a circuit structure for voltage balancing control in an I-shaped inverter circuit according to an embodiment of the present invention, wherein the current flow direction when the inverter capacitor C3 is charged is shown, and the voltage of the positive bus capacitor C1 is relatively high; Fig.10a and Fig.10b 1 is a schematic diagram of a circuit structure for voltage balancing control in an I-shaped inverter circuit according to an embodiment of the present invention, wherein the current flow direction when discharging through the inverter inductor L1 is shown, and the voltage of the positive bus capacitor C1 is relatively high; Fig.11 is a structural diagram of a computing device according to another embodiment of the present application; Fig.12 It is a structural diagram of a computer-readable storage medium according to another embodiment of the present application. DETAILED DESCRIPTION

[0022] The technical solution of the present invention will be described clearly and completely below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0023] In addition, the technical features involved in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0024] The architecture commonly used by inverters is a two-level topology, such as Figure 1As shown, it can generally include a boost circuit at the front stage and an inverter circuit at the back stage. Each group of PV cells is boosted by the boost circuit and then connected to the power grid through the inverter circuit. A positive bus capacitor and a negative bus capacitor are arranged between the boost circuit and the inverter circuit. The positive bus capacitor and the negative bus capacitor play multiple roles in the operation of the inverter, such as energy storage, voltage smoothing, reducing inductance parameters, preventing voltage overcharge and transient voltage effects, and midpoint potential balance. Especially in a three-phase inverter, the positive and negative bus capacitors can play a role in midpoint potential balance, which can ensure that the midpoint potential at the output end of the inverter remains stable, thereby avoiding the problem of output voltage imbalance caused by midpoint potential offset.

[0025] The positive and negative bus capacitors are generally selected as electrolytic capacitors, but due to the inconsistent leakage current of the electrolytic capacitors and the inconsistent effects of the entire circuit-related resistors such as the sampling resistor between the positive and negative bus, it is very easy to cause the capacitor voltage of the positive bus capacitor and the negative bus capacitor to be uneven. If the capacitor voltage imbalance between the positive bus capacitor and the negative bus capacitor is too large, it will cause capacitor overvoltage and even cause the inverter to be damaged and exploded. Therefore, it is necessary to introduce a balancing mechanism to balance the capacitor voltage of the positive and negative bus capacitors.

[0026] At present, the commonly used voltage equalization circuits for the positive and negative bus capacitors connected in series are as follows: 1. Connect the equalizing resistor in parallel to the capacitor branch of the positive and negative bus capacitors. The resistance of the equalizing resistor is generally small. This method will add extra circuit loss because the equalizing resistor is added between the bus voltages. However, if the resistance of the equalizing resistor is increased, the circuit loss can be reduced, but the equalizing effect will be affected. 2. In view of the weak voltage-equalizing effect of large series resistors, a set of switch circuits can be used to connect smaller resistors in series. When the capacitor voltage imbalance value of the positive and negative bus capacitors exceeds a certain value, the switch circuit is started; and when the voltage is relatively balanced, the switch circuit is closed to avoid large power consumption of the voltage-equalizing resistor. Generally, due to the high half-bus voltage, the voltage withstand value of the switch tube as the main control device of the switch circuit is required to be high, and it is often difficult to select. Therefore, relays are used instead of switch tubes, but this will increase the size and cost of the equipment, and increase the complexity of the control algorithm; 3. Use a balanced bridge circuit. This balanced bridge circuit requires an additional high-power power topology circuit, including high-power semiconductor devices and energy storage elements (such as inductors), and introduces a complex control algorithm, which is disadvantageous in terms of cost and volume.

[0027] In summary, the existing technology for equalizing the voltage of positive and negative bus capacitors is relatively costly and has a complex control algorithm.

[0028] The present application describes a method for controlling voltage balancing of a BUS bus capacitor of an inverter, which is used to balance and process the positive and negative bus capacitors between the BUS buses. The positive bus capacitor and the negative bus capacitor are connected in series and then connected between the BUS buses. The BUS bus is connected to the positive and negative bus capacitors and then to the inverter circuit of the inverter. The capacitor voltages of the positive bus capacitor and the negative bus capacitor are detected and it is determined whether voltage balancing control is required. Generally speaking, a collection resistor or other collection circuit is used to complete the capacitor voltage collection of the positive bus capacitor or the negative bus capacitor. The existing technology can be used for this capacitor voltage collection process, which does not involve the protection points of the present invention application and is not elaborated here.

[0029] The positive bus capacitor or the negative bus capacitor each includes at least one capacitor, and the capacitors in each bus capacitor are connected in series to form a capacitor group. The capacitor group with one side connected to the positive pole of the BUS bus is recorded as the positive bus capacitor, and the capacitor group with one side connected to the negative pole of the BUS bus is recorded as the negative bus capacitor.

[0030] The capacitor voltages of the positive bus capacitor and the negative bus capacitor are detected and it is determined whether equalizing voltage control is required. If it is determined that equalizing voltage control is required, the single-phase inverter circuit of any phase in the inverter circuit is used as the equalizing voltage circuit, and the positive bus capacitor or the negative bus capacitor is discharged and equalized through the inverter capacitor and inverter inductor in the single-phase inverter circuit. Otherwise, the capacitor voltages of the positive bus capacitor and the negative bus capacitor continue to be detected.

[0031] When detecting the capacitor voltages of the positive bus capacitor and the negative bus capacitor and determining whether voltage equalization control is required, the capacitor voltages of the positive bus capacitor and the negative bus capacitor are collected and compared with the half-bus voltage respectively; if the capacitor voltage of one of the bus capacitors is greater than the half-bus voltage and exceeds a preset lower limit threshold, the first bus capacitor with a higher capacitor voltage is discharged for voltage equalization until the capacitor voltage of the first bus capacitor is lower than a preset safety voltage threshold.

[0032] For the inverter of the three-level inverter circuit, the inverter can generally include inverter circuits corresponding to the three phases A, B, and C, that is, three single-phase inverter circuits, each of which is generally composed of two bridge arms, an inverter inductor, and an inverter capacitor.

[0033] Inverters can generally be divided into T-type three-level inverters or I-type three-level inverters according to the circuit structure of the three-level inverter circuit therein.

[0034] The single-phase inverter circuit includes a first bridge arm and a second bridge arm, wherein the first bridge arm and the second bridge arm form a T-shaped inverter circuit (corresponding to a T-shaped three-level inverter) or an I-shaped inverter circuit (corresponding to an I-shaped three-level inverter), and the connection point between the first bridge arm and the second bridge arm is connected in series with the inverter inductor and the inverter capacitor, and the inverter capacitor is further connected to the connection midpoint of the positive and negative bus capacitors, wherein, by controlling each switch tube in the first bridge arm and the second bridge arm to be intermittently turned on or off, the bus capacitor with a higher capacitance voltage among the positive and negative bus capacitors is controlled to periodically discharge and equalize the voltage using the inverter capacitor and the inverter inductor. When the positive bus capacitor or the negative bus capacitor is discharged and equalized by the inverter capacitor and the inverter inductor in the single-phase inverter circuit, the inverter is in a standby state.

[0035] In the process of discharging and equalizing the one with the higher capacitor voltage among the positive and negative bus capacitors, firstly, some of the switch tubes in the first bridge arm and the second bridge arm are controlled to be turned on or off, so that the positive bus capacitor or the negative bus capacitor to be discharged and equalized is first connected in series with the inverter capacitor, and the positive bus capacitor or the negative bus capacitor charges the inverter capacitor, and then some of the switch tubes in the first bridge arm and the second bridge arm are controlled to be turned off or on, so that the connection between the positive bus capacitor or the negative bus capacitor to be discharged and equalized is disconnected from the inverter capacitor, and the inverter capacitor is discharged through the inverter inductor; the process of periodically charging the inverter capacitor and then discharging it through the inverter inductor is carried out to realize the discharge and equalization of the positive bus capacitor or the negative bus capacitor with the higher capacitor voltage.

[0036] The following describes the control process of voltage balancing control according to the type of inverter, whether it is a T-type three-level inverter or an I-type three-level inverter.

[0037] Embodiment 1: In this embodiment, Figure 2 As shown, the first bridge arm and the second bridge arm in the single-phase inverter circuit form a T-shaped inverter circuit, the first bridge arm is two switch tubes connected in series in sequence, the first bridge arm is arranged between the BUS busbars and connected in parallel with the positive and negative bus capacitors, the second bridge arm is two switch tubes connected in series in reverse, the first end of the second bridge arm is connected to the connection midpoint of the positive and negative bus capacitors, and the first end of the second bridge arm is connected to the midpoint of the first bridge arm. Among them, when there is a first bus capacitor whose capacitor voltage is higher than a threshold value among the positive and negative bus capacitors, the switch tube connected to the first bus capacitor in the first bridge arm is first controlled to be turned on, so that the first bus capacitor charges the inverter capacitor, and then the switch tube connected to the first bus capacitor in the first bridge arm is controlled to be turned off, and the two switch tubes in the second bridge arm are turned on, and the inverter capacitor is discharged through the inverter inductor connected in series with it; the process of periodically charging the inverter capacitor and then discharging it through the inverter inductor is carried out to achieve discharge and voltage equalization of the first bus capacitor with a higher capacitor voltage.

[0038] In the process of discharging and voltage equalizing the first bus capacitor with a higher capacitor voltage, each switch tube in the first bridge arm and the second bridge arm receives a control signal to cooperate in turning on or off, wherein the bus capacitor with a higher voltage among the positive and negative bus capacitors is recorded as the first bus capacitor, and the other bus capacitor is recorded as the second bus capacitor. The switch tube in the first bridge arm connected to the first bus capacitor receives a first PWM signal to be intermittently turned on or off, the switch tube in the first bridge arm connected to the second bus capacitor is constantly turned off, one switch tube in the second bridge arm is constantly turned on, and the other switch tube in the second bridge arm receives a second PWM signal to be intermittently turned off or on, and the level states of the first PWM signal and the second PWM signal are complementary in time.

[0039] Below Figure 2 Taking the positive bus capacitor, negative bus capacitor and single-phase T-shaped inverter circuit connection circuit shown as an example, the working process of controlling when the capacitor voltage of the positive bus capacitor is higher or the capacitor voltage of the negative bus capacitor is higher is specifically described.

[0040] like Figure 2As shown, the positive bus capacitor C1 and the negative bus capacitor C2 are connected in series and connected between the BUS busbars, the first end of the positive bus capacitor C1 is connected to the positive line BUS+ of the BUS busbar, the first end of the negative bus capacitor C2 is connected to the negative line BUS- of the BUS busbar, the second end of the positive bus capacitor C1 is connected to the second end of the negative bus capacitor C2, and the connection point where the second end of the positive bus capacitor C1 and the second end of the negative bus capacitor C2 are connected is the connection midpoint BUSN of the positive and negative bus capacitors. The first bridge arm includes a first switch tube Q1 and a second switch tube Q2, the first switch tube Q1 and the second switch tube Q2 are connected in series in sequence, the collector of the first switch tube Q1 is connected to the positive line BUS+, the emitter of the first switch tube Q1 is connected to the collector of the second switch tube Q2, the connection point where the emitter of the first switch tube Q1 and the collector of the second switch tube Q2 are connected is the midpoint of the first bridge arm, and the emitter of the second switch tube Q2 is connected to the negative line BUS-; the second bridge arm includes a third switch tube Q3 and a fourth switch tube Q4, the collector of the third switch tube Q3 is connected to the connection midpoint BUSN of the positive and negative bus capacitors, the emitter of the third switch tube Q3 is connected to the emitter of the fourth switch tube Q4, and the collector of the fourth switch tube Q4 is connected to the midpoint of the first bridge arm. The base of each switch tube receives a control signal to be turned on or off, and each switch tube has a body diode. The first end of the inverter inductor L1 is connected to the midpoint of the first bridge arm, the second end of the inverter inductor L1 is connected to the first end of the inverter capacitor C3, and the second end of the inverter capacitor C3 is connected to the connection midpoint BUSN of the positive and negative bus capacitors. The switch tube selected in this embodiment is an IGBT tube.

[0041] When the first bus capacitor with a higher capacitor voltage is the positive bus capacitor C1, the second switch tube Q2 is controlled to be constantly turned off and the fourth switch tube Q4 is constantly turned on. The first switch tube Q1 receives the first PWM signal to be intermittently turned on or off, and the third switch tube Q3 receives the second PWM signal to be intermittently turned off or on. The level states of the first PWM signal and the second PWM signal are complementary in time. The process of periodically charging the inverter capacitor C3 and then discharging through the inverter inductor L1 finally completes the discharge voltage equalization of the positive bus capacitor C1.

[0042] When discharging and equalizing the positive bus capacitor C1 with a higher capacitor voltage, there are two working modes, wherein the first working mode is to charge the inverter capacitor C3, and the second working mode is to discharge through the inverter inductor L1. Figure 5Schematic diagram of waveforms of major components in the above two working modes, which involve the first PWM signal received by the first switch tube Q1, the second PWM signal received by the third switch tube Q3, the current in the inverter inductor L1, the voltage of the positive bus capacitor C1, and the voltage of the inverter capacitor C3.

[0043] like Figure 3 As shown, the working mode of charging the inverter capacitor C3 is shown. At this time, the first PWM signal is at a high level, and the first switch tube Q1 is in a conducting state after receiving the first PWM signal. The second PWM signal is at a low level, and the third switch tube Q3 is in a shut-off state after receiving the second PWM signal. The positive bus capacitor C1 is connected to the inverter capacitor C3 via Figure 3 The current flow indicated by the arrow in the middle charges the inverter capacitor, and the current loop is C1->Q1->L1->C3->BUSN. In this process, the current in the inverter inductor L1 increases, and the voltage of the inverter capacitor C3 increases.

[0044] like Figure 4a and Figure 4b As shown, the working mode of discharging through the inverter inductor L1 is shown. At this time, the first PWM signal is at a low level, and the first switch tube Q1 is in an off state after receiving the first PWM signal. The second PWM signal is at a high level, and the third switch tube Q3 is in an on state after receiving the second PWM signal. The inverter capacitor C3 is connected via Figure 4a The current flow indicated by the arrow in the middle discharges through the inverter inductor L1, and the corresponding current loop becomes the current loop L1->C3->BUSN->Q3->D4, where D4 is the body diode of the fourth switch tube Q4. In addition, since the inductor voltage of the inverter inductor L1 is negative at this time, its current keeps decreasing. In the early stage when the second PWM signal is at a high level, the inductor current is positive, and in the later stage, the inductor current drops to negative, that is, it will pass through Figure 4b The current flow indicated by the arrow in the middle discharges through the inverter inductor L1, and the corresponding current loop becomes a current loop of L1->Q4->D3->BUSN->C3, where D3 is the body diode of the third switch tube Q3. In this process, the voltage across the inverter inductor C3 rises when the inductor current is positive (the current direction when the positive bus capacitor C1 with a higher capacitance charges the inverter capacitor C3 is positive, and here the direction of L1->C3 is positive). As the inductor current in the inverter inductor L1 decreases, the voltage of the inverter capacitor C3 decreases when the inductor current is negative (the direction of C3->L1 is negative).

[0045] In the above discharge and voltage equalization process of the positive bus capacitor C1, the inductor current in the inverter inductor L1 increases when entering the first working mode, and the inductor current in the inverter inductor L1 decreases when entering the second working mode. In the entire process of discharging and voltage equalization of the positive bus capacitor C1, the capacitor voltage of the positive bus capacitor C1 is continuously decreasing, while the capacitor voltage of the inverter capacitor C3 increases when the loop current is positive and decreases when the loop current is negative. By repeating the above first working mode and second working mode, the capacitor voltage of the positive bus capacitor C1 is reduced. When the capacitor voltage of the positive bus capacitor C1 is reduced to the safety voltage threshold Vth1 (such as 700V), the pulsation stops, and the output of the control signal for each switch tube is stopped. If after a period of time, the capacitor voltage of the positive bus capacitor C1 continues to rise due to circuit leakage current and uneven resistance on the BUS bus, then when the capacitor voltage of the positive bus voltage C1 reaches a set lower threshold value Vth2 (such as 800V, note that a little hysteresis needs to be retained to ensure Vth2>Vth1), the above-mentioned wave-beating action can be performed again until the C1 voltage drops to the safe voltage threshold value Vth1.

[0046] When the first bus capacitor with a higher capacitor voltage is the negative bus capacitor C2, the first switch tube Q1 is controlled to be constantly turned off and the third switch tube Q3 is constantly turned on. The second switch tube Q2 receives the first PWM signal to be intermittently turned on or off, and the fourth switch tube Q4 receives the second PWM signal to be intermittently turned off or on. The level states of the first PWM signal and the second PWM signal are complementary in time. The process of periodically charging the inverter capacitor C3 and then discharging through the inverter inductor L1 finally completes the discharge voltage equalization of the negative bus capacitor C2.

[0047] Accordingly, when discharging and equalizing the negative bus capacitor C2 with a higher capacitor voltage, two working modes are included, wherein the first working mode is to charge the inverter capacitor C3, and the second working mode is to discharge through the inverter inductor L1.

[0048] like Figure 6 As shown, the working mode of charging the inverter capacitor C3 is shown. At this time, the first PWM signal is at a high level, the second switch tube Q2 is in a conducting state after receiving the first PWM signal, the second PWM signal is at a low level, the fourth switch tube Q4 is in a shut-off state after receiving the second PWM signal, and the positive bus capacitor C1 is connected to the inverter capacitor C3 via Figure 6 The current flow indicated by the arrow in the middle charges the inverter capacitor, and the current loop is C2->BUSN->C3->L1->Q2. In this process, the current in the inverter inductor L1 increases, and the voltage of the inverter capacitor C3 increases.

[0049] like Figure 7a and Figure 7b As shown, the working mode of discharging through the inverter inductor L1 is shown. At this time, the first PWM signal is at a low level, and the second switch tube Q2 is in an off state after receiving the first PWM signal. The second PWM signal is at a high level, and the fourth switch tube Q4 is in an on state after receiving the second PWM signal. The inverter capacitor C3 is connected via Figure 7a The current flow indicated by the arrow in the middle discharges through the inverter inductor L1, and the corresponding current loop becomes the current loop L1->Q4->D3->BUSN->C3, where D3 is the body diode of the third switch tube Q3. In addition, since the inductor voltage of the inverter inductor L1 is negative at this time, its current keeps decreasing. In the early stage when the second PWM signal is at a high level, the inductor current is positive, and in the later stage, the inductor current drops to negative, that is, it will pass through Figure 7b The current flow indicated by the arrow in the middle discharges through the inverter inductor L1, and the corresponding current loop becomes a current loop of L1->C3->BUSN->Q3->D4, where D4 is the body diode of the fourth switch tube Q4. In this process, the voltage across the inverter inductor C3 rises when the inductor current is positive (the current direction when the positive bus capacitor C1 with a higher capacitance charges the inverter capacitor C3 is positive, and here the direction of C3->L1 is positive). As the inductor current in the inverter inductor L1 decreases, the voltage of the inverter capacitor C3 decreases when the inductor current is negative (the direction of L1->C3 is negative).

[0050] In the above discharge and voltage equalization process of the negative bus capacitor C2, the inductor current in the inverter inductor L1 increases when entering the first working mode, and the inductor current in the inverter inductor L1 decreases when entering the second working mode. In the entire process of discharging and voltage equalization of the negative bus capacitor C2, the capacitor voltage of the negative bus capacitor C2 is continuously decreasing, while the capacitor voltage of the inverter capacitor C3 increases when the loop current is positive and decreases when the loop current is negative. By repeating the above first working mode and second working mode, the capacitor voltage of the negative bus capacitor C2 is reduced. When the capacitor voltage of the negative bus capacitor C2 is reduced to the safety voltage threshold Vth1 (such as 700V), the pulsation stops, and the output of the control signal for each switch tube is stopped. If after a period of time, the capacitor voltage of the negative bus capacitor C2 continues to rise due to circuit leakage current and uneven resistance on the BUS bus, then when the capacitor voltage of the negative bus capacitor C2 reaches a set lower threshold value Vth2 (such as 800V, note that a little hysteresis needs to be retained to ensure Vth2>Vth1), the above-mentioned wave-beating action can be performed again until the C1 voltage drops to the safe voltage threshold value Vth1.

[0051] Embodiment 2: In this embodiment, Figure 8As shown, the first bridge arm and the second bridge arm in the single-phase inverter circuit constitute an I-shaped inverter circuit, the first bridge arm and the second bridge arm are two switch tubes connected in series in sequence, the first bridge arm and the second bridge arm are connected in series and arranged between the BUS busbars, one end of the first bridge arm is connected to the positive busbar capacitor, one end of the second bridge arm is connected to the negative busbar capacitor, the negative side of the two diodes connected in series is connected to the connection midpoint of the first bridge arm, the positive side is connected to the connection midpoint of the second bridge arm, and the connection midpoint of the positive and negative busbar capacitors is connected to the connection midpoint of the two diodes; Among them, when there is a first bus capacitor with a capacitor voltage higher than a threshold value among the positive and negative bus capacitors, the two switch tubes in the bridge arm connected to the first bus capacitor are controlled to be turned on, so that the first bus capacitor charges the inverter capacitor, and then the two adjacent switch tubes in the first bridge arm and the second bridge arm are controlled to be turned on, and the other two switch tubes are turned off, and the inverter capacitor is discharged through the inverter inductor connected in series with it; the process of periodically charging the inverter capacitor and then discharging it through the inverter inductor is carried out to achieve discharge and voltage equalization of the first bus capacitor with a higher capacitor voltage.

[0052] In the process of discharging and balancing the first bus capacitor with a higher capacitor voltage, the switch tubes in the first bridge arm and the second bridge arm receive the control signal to cooperate with each other to turn on or off. Among them, a bus capacitor with a higher voltage among the positive and negative bus capacitors is recorded as a first bus capacitor, and the other bus capacitor is recorded as a second bus capacitor. The switch tube directly connected to the first bus capacitor in the bridge arm connected to the first bus capacitor is recorded as a first switch tube, and the other switch tube is recorded as a second switch tube. The switch tube directly connected to the second bus capacitor in the bridge arm connected to the second bus capacitor is recorded as a fourth switch tube, and the other switch tube is recorded as a third switch tube, that is, the first switch tube, the second switch tube, the third switch tube, and the fourth switch tube are sequentially connected in series and then connected between the BUS busbars; the first switch tube receives the first PWM signal to be intermittently turned on or off, the second switch tube is constantly turned on, the third switch tube receives the second PWM signal to be intermittently turned off or turned on, and the fourth switch tube is constantly turned off, and the level states of the first PWM signal and the second PWM signal are complementary in time.

[0053] Below Figure 8 Taking the positive bus capacitor, negative bus capacitor and single-phase I-shaped inverter circuit connection circuit shown as an example, the working process of controlling when the capacitor voltage of the positive bus capacitor is higher or the capacitor voltage of the negative bus capacitor is higher is specifically described.

[0054] like Figure 8As shown, the positive bus capacitor C1 and the negative bus capacitor C2 are connected in series and connected between the BUS busbars, the first end of the positive bus capacitor C1 is connected to the positive line BUS+ of the BUS busbar, the first end of the negative bus capacitor C2 is connected to the negative line BUS- of the BUS busbar, the second end of the positive bus capacitor C1 is connected to the second end of the negative bus capacitor C2, and the connection point where the second end of the positive bus capacitor C1 and the second end of the negative bus capacitor C2 are connected is the connection midpoint BUSN of the positive and negative bus capacitors. The first bridge arm includes a first switch tube Q1 and a second switch tube Q2, which are sequentially connected in series, a collector of the first switch tube Q1 is connected to a positive line BUS+, an emitter of the first switch tube Q1 is connected to a collector of the second switch tube Q2, and a connection point where the emitter of the first switch tube Q1 is connected to the collector of the second switch tube Q2 is the connection midpoint of the first bridge arm; the second bridge arm includes a third switch tube Q3 and a fourth switch tube Q4, which are sequentially connected in series, a collector of the third switch tube Q3 is connected to an emitter of the second switch tube Q2, an emitter of the third switch tube Q3 is connected to a collector of the fourth switch tube Q4, an emitter of the fourth switch tube Q4 is connected to a negative line BUS-, and a connection point where the emitter of the third switch tube Q3 is connected to a collector of the fourth switch tube Q4 is the connection midpoint of the second bridge arm. The diode D5 and the diode D6 are connected in series in the forward direction, and the connection point between the diode D5 and the diode D6 is the connection midpoint of the two diodes. The negative side of the diode D5 and the diode D6 after being connected in series is connected to the connection midpoint of the first bridge arm, and the positive side is connected to the connection midpoint of the second bridge arm. The base of each switch tube receives a control signal to be turned on or off. The first end of the inverter inductor L1 is connected to the emitter of the second switch tube Q2 (the connection point between the first bridge arm and the second bridge arm), the second end of the inverter inductor L1 is connected to the first end of the inverter capacitor C3, and the second end of the inverter capacitor C3 is connected to the connection midpoint BUSN of the positive and negative bus capacitors.

[0055] When the first bus capacitor with a higher capacitor voltage is the positive bus capacitor C1, the second switch tube Q2 is controlled to be constantly turned on and the fourth switch tube Q4 is constantly turned off. The first switch tube Q1 receives the first PWM signal to be intermittently turned on or turned off, and the third switch tube Q3 receives the second PWM signal to be intermittently turned off or turned on. The level states of the first PWM signal and the second PWM signal are complementary in time. The process of periodically charging the inverter capacitor C3 and then discharging through the inverter inductor L1 finally completes the discharge voltage equalization of the positive bus capacitor C1.

[0056] When discharging and equalizing the positive bus capacitor C1 with a higher capacitor voltage, there are two working modes, wherein the first working mode is to charge the inverter capacitor C3, and the second working mode is to discharge through the inverter inductor L1.

[0057] like Fig. 9 As shown, the working mode of charging the inverter capacitor C3 is shown. At this time, the first PWM signal is at a high level, and the first switch tube Q1 is in a conducting state after receiving the first PWM signal. The second PWM signal is at a low level, and the third switch tube Q3 is in a shut-off state after receiving the second PWM signal. The positive bus capacitor C1 is connected to the inverter capacitor C3 via Fig. 9 The current flow indicated by the arrow in the middle charges the inverter capacitor, and the current loop is C1->Q1->Q2->L1->C3->BUSN. In this process, the current in the inverter inductor L1 increases, and the voltage of the inverter capacitor C3 increases.

[0058] like Fig.10a and Fig.10b As shown, the working mode of discharging through the inverter inductor L1 is shown. At this time, the first PWM signal is at a low level, and the first switch tube Q1 is in an off state after receiving the first PWM signal. The second PWM signal is at a high level, and the third switch tube Q3 is in an on state after receiving the second PWM signal. The inverter capacitor C3 is connected via Fig.10a The current flow indicated by the arrow in the middle discharges through the inverter inductor L1, and the corresponding current loop becomes the current loop L1->C3->BUSN->D5->Q2. In addition, since the inductor voltage of the inverter inductor L1 is negative at this time, its current keeps decreasing. In the early stage when the second PWM signal is at a high level, the inductor current is positive, and in the later stage, the inductor current drops to negative. In other words, it will pass through Fig.10b The current flow indicated by the arrow in the middle discharges through the inverter inductor L1, and the corresponding current loop becomes a current loop of L1->Q3->D6->BUSN->C3. In this process, the voltage across the inverter inductor C3 rises when the inductor current is positive (the current direction when the positive bus capacitor C1 with higher capacitance charges the inverter capacitor C3 is positive, and here the direction of L1->C3 is positive), and as the inductor current in the inverter inductor L1 decreases, the voltage of the inverter capacitor C3 decreases when the inductor current is negative (the direction of C3->L1 is negative).

[0059] In the above discharge and voltage equalization process of the positive bus capacitor C1, the inductor current in the inverter inductor L1 increases when entering the first working mode, and the inductor current in the inverter inductor L1 decreases when entering the second working mode. In the entire process of discharging and voltage equalization of the positive bus capacitor C1, the capacitor voltage of the positive bus capacitor C1 is continuously decreasing, while the capacitor voltage of the inverter capacitor C3 increases when the loop current is positive and decreases when the loop current is negative. By repeating the above first working mode and second working mode, the capacitor voltage of the positive bus capacitor C1 is reduced. When the capacitor voltage of the positive bus capacitor C1 is reduced to the safety voltage threshold Vth1 (such as 700V), the pulsation stops, and the output of the control signal for each switch tube is stopped. If after a period of time, the capacitor voltage of the positive bus capacitor C1 continues to rise due to circuit leakage current and uneven resistance on the BUS bus, then when the capacitor voltage of the positive bus voltage C1 reaches a set lower threshold value Vth2 (such as 800V, note that a little hysteresis needs to be retained to ensure Vth2>Vth1), the above-mentioned wave-beating action can be performed again until the C1 voltage drops to the safe voltage threshold value Vth1.

[0060] When the first bus capacitor with a higher capacitor voltage is the negative bus capacitor C2, the second switch tube Q2 is controlled to be constantly turned off and the fourth switch tube Q4 is constantly turned on. The third switch tube Q3 receives the first PWM signal to be intermittently turned on or off, and the first switch tube Q1 receives the second PWM signal to be intermittently turned off or on. The level states of the first PWM signal and the second PWM signal are complementary in time. The process of periodically charging the inverter capacitor C3 and then discharging through the inverter inductor L1 finally completes the discharge voltage balancing for the negative bus capacitor C2. As for other specific processes, they are similar to the discharge voltage balancing for the positive bus capacitor C1 described above, except for the difference in controlling the switch tubes, which will not be repeated here.

[0061] In summary, the inverter BUS bus capacitor voltage equalization control method of the present application does not add additional hardware circuits. On the basis of the existing inverter hardware circuit, combined with the control method, it realizes the voltage equalization processing of the bus capacitor, and completes the control of the capacitor voltage of the bus capacitor without increasing the hardware cost, thereby achieving low cost and enabling the inverter to operate safely and stably.

[0062] The present application also provides a computing device, referring to Fig.11 The computing device includes a memory 1120, a processor 1110, and a computer program stored in the memory 1120 and executable by the processor 1110. The computer program is stored in a space 1130 for program code in the memory 1120. When the computer program is executed by the processor 1110, it is implemented to execute any one of the method steps 1131 according to the present invention.

[0063] The present application also provides a computer-readable storage medium. Fig.12 The computer-readable storage medium comprises a storage unit for program code, the storage unit being provided with a program 1131 ′ for executing the method steps according to the present invention, the program being executed by a processor.

[0064] The embodiment of the present application further provides a computer program product including instructions. When the computer program product is run on a computer, the computer is caused to execute the method steps according to the present invention.

[0065] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer loads and executes the computer program instructions, the process or function described in the embodiment of the present application is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from a website site, computer, server or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) mode to another website site, computer, server or data center. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that includes one or more available media integrated. The available medium can be a magnetic medium (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid-state drive Solid State Disk (SSD)), etc.

[0066] The professionals should also be further aware that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented with electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in terms of function in the above description. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0067] A person skilled in the art can understand that all or part of the steps in the above-mentioned embodiment method can be completed by instructing a processor through a program, and the program can be stored in a computer-readable storage medium, and the storage medium is a non-transitory medium, such as a random access memory, a read-only memory, a flash memory, a hard disk, a solid-state drive, a magnetic tape, a floppy disk, an optical disc, and any combination thereof.

[0068] In particular, the present invention also provides a computing device, comprising a memory, a processor, and a computer program stored in the memory and executable by the processor, wherein the processor implements the method as described above when executing the computer program.

[0069] The present invention also provides a computer-readable storage medium, in which a computer program is stored, and when the computer program is executed by a processor, the method described above is implemented. The computer-readable storage medium is preferably a non-volatile readable storage medium.

[0070] The above embodiments are only for illustrating the technical concept and features of the present invention, and their purpose is to enable people familiar with this technology to understand the contents of the present invention and implement them accordingly. They cannot be used to limit the protection scope of the present invention. Any equivalent changes or modifications made according to the spirit of the present invention should be included in the protection scope of the present invention.

Claims

1. A method for controlling voltage balancing of a BUS bus capacitor of an inverter, for balancing and processing the positive and negative bus capacitors between the BUS bus, wherein the positive bus capacitor and the negative bus capacitor are connected in series and then connected between the BUS bus, and the BUS bus is connected to the positive and negative bus capacitors and then connected to the inverter circuit of the inverter, characterized in that: The capacitor voltages of the positive bus capacitor and the negative bus capacitor are detected to determine whether voltage equalization control is required. If voltage equalization control is required, the single-phase inverter circuit of any phase in the inverter circuit is used as the voltage equalization circuit, and the positive bus capacitor or the negative bus capacitor is discharged and voltage equalized through the inverter capacitor and inverter inductor in the single-phase inverter circuit.

2. The inverter BUS bus capacitor voltage balancing control method according to claim 1, characterized in that: The single-phase inverter circuit comprises a first bridge arm and a second bridge arm, wherein the first bridge arm and the second bridge arm form a T-shaped inverter circuit or an I-shaped inverter circuit, wherein the connection point between the first bridge arm and the second bridge arm is connected in series with the inverter inductor and the inverter capacitor, and the inverter capacitor is further connected to the connection midpoint of the positive and negative bus capacitors. Among them, by controlling the switch tubes in the first bridge arm and the second bridge arm to be intermittently turned on or off, the bus capacitor with a higher capacitance voltage among the positive and negative bus capacitors is controlled to periodically use the inverter capacitor and the inverter inductor to discharge and balance the voltage.

3. The inverter BUS bus capacitor voltage balancing control method according to claim 2, characterized in that: In the process of discharging and balancing the capacitor with the higher voltage among the positive and negative bus capacitors, First, some of the switch tubes in the first bridge arm and the second bridge arm are controlled to be turned on or off, so that the positive bus capacitor or the negative bus capacitor to be discharged and equalized is first connected in series with the inverter capacitor, and the positive bus capacitor or the negative bus capacitor charges the inverter capacitor. Then, some of the switch tubes in the first bridge arm and the second bridge arm are controlled to be turned off or on, so that the connection between the positive bus capacitor or the negative bus capacitor to be discharged and the inverter capacitor is disconnected, and the inverter capacitor is discharged through the inverter inductor; the process of periodically charging the inverter capacitor and then discharging it through the inverter inductor is performed to achieve discharge equalization of the positive bus capacitor or the negative bus capacitor with a higher capacitor voltage.

4. The inverter BUS bus capacitor voltage balancing control method according to claim 2 or 3, characterized in that: The first bridge arm and the second bridge arm form a T-shaped inverter circuit, the first bridge arm is two switch tubes connected in series in sequence, the first bridge arm is arranged between the BUS busbars and connected in parallel with the positive and negative bus capacitors, the second bridge arm is two switch tubes connected in series in reverse, the first end of the second bridge arm is connected to the connection midpoint of the positive and negative bus capacitors, and the first end of the second bridge arm is connected to the midpoint of the first bridge arm. Among them, when there is a first bus capacitor whose capacitor voltage is higher than a threshold value among the positive and negative bus capacitors, the switch tube connected to the first bus capacitor in the first bridge arm is first controlled to be turned on, so that the first bus capacitor charges the inverter capacitor, and then the switch tube connected to the first bus capacitor in the first bridge arm is controlled to be turned off, and the two switch tubes in the second bridge arm are turned on, and the inverter capacitor is discharged through the inverter inductor connected in series with it; the process of periodically charging the inverter capacitor and then discharging it through the inverter inductor is carried out to achieve discharge and voltage equalization of the first bus capacitor with a higher capacitor voltage.

5. The inverter BUS bus capacitor voltage balancing control method according to claim 4, characterized in that: In the process of discharging and balancing the first bus capacitor with a higher capacitor voltage, the switch tubes in the first bridge arm and the second bridge arm receive the control signal to cooperate with each other to turn on or off. Among them, a bus capacitor with a higher voltage among the positive and negative bus capacitors is recorded as a first bus capacitor, and the other bus capacitor is recorded as a second bus capacitor. The switch tube connected to the first bus capacitor in the first bridge arm receives a first PWM signal to be intermittently turned on or off, the switch tube connected to the second bus capacitor in the first bridge arm is constantly turned off, one switch tube in the second bridge arm is constantly turned on, and the other switch tube in the second bridge arm receives a second PWM signal to be intermittently turned off or on, and the level states of the first PWM signal and the second PWM signal are complementary in time.

6. The inverter BUS bus capacitor voltage balancing control method according to claim 2 or 3, characterized in that: The first bridge arm and the second bridge arm form an I-shaped inverter circuit, the first bridge arm and the second bridge arm are two switch tubes connected in series in sequence, the first bridge arm and the second bridge arm are connected in series and arranged between the BUS busbars, one end of the first bridge arm is connected to the positive busbar capacitor, one end of the second bridge arm is connected to the negative busbar capacitor, the negative side of the two diodes connected in series is connected to the connection midpoint of the first bridge arm, the positive side is connected to the connection midpoint of the second bridge arm, and the connection midpoint of the positive and negative busbar capacitors is connected to the connection midpoint of the two diodes; Among them, when there is a first bus capacitor with a capacitor voltage higher than a threshold value among the positive and negative bus capacitors, the two switch tubes in the bridge arm connected to the first bus capacitor are controlled to be turned on, so that the first bus capacitor charges the inverter capacitor, and then the two adjacent switch tubes in the first bridge arm and the second bridge arm are controlled to be turned on, and the other two switch tubes are turned off, and the inverter capacitor is discharged through the inverter inductor connected in series with it; the process of periodically charging the inverter capacitor and then discharging it through the inverter inductor is carried out to achieve discharge and voltage equalization of the first bus capacitor with a higher capacitor voltage.

7. The inverter BUS bus capacitor voltage balancing control method according to claim 6, characterized in that: In the process of discharging and balancing the first bus capacitor with a higher capacitor voltage, the switch tubes in the first bridge arm and the second bridge arm receive the control signal to cooperate with each other to turn on or off. Among them, a bus capacitor with a higher voltage among the positive and negative bus capacitors is recorded as a first bus capacitor, and the other bus capacitor is recorded as a second bus capacitor. The switch tube directly connected to the first bus capacitor in the bridge arm connected to the first bus capacitor is recorded as a first switch tube, and the other switch tube is recorded as a second switch tube. The switch tube directly connected to the second bus capacitor in the bridge arm connected to the second bus capacitor is recorded as a fourth switch tube, and the other switch tube is recorded as a third switch tube, that is, the first switch tube, the second switch tube, the third switch tube, and the fourth switch tube are sequentially connected in series and then connected between the BUS busbars; the first switch tube receives the first PWM signal to be intermittently turned on or off, the second switch tube is constantly turned on, the third switch tube receives the second PWM signal to be intermittently turned off or turned on, and the fourth switch tube is constantly turned off, and the level states of the first PWM signal and the second PWM signal are complementary in time.

8. The inverter BUS bus capacitor voltage balancing control method according to claim 2, characterized in that: Each switch tube in the first bridge arm and the second bridge arm has a body diode, and the conduction direction of the body diode is opposite to the conduction direction of the switch tube in which it is located.

9. The inverter BUS bus capacitor voltage balancing control method according to claim 1, characterized in that: When detecting the capacitor voltages of the positive bus capacitor and the negative bus capacitor and determining whether voltage equalization control is required, the capacitor voltages of the positive bus capacitor and the negative bus capacitor are collected and compared with the half-bus voltage respectively; if the capacitor voltage of one of the bus capacitors is greater than the half-bus voltage and exceeds a preset lower limit threshold, the first bus capacitor with a higher capacitor voltage is discharged for voltage equalization until the capacitor voltage of the first bus capacitor is lower than a preset safety voltage threshold.

10. The inverter BUS bus capacitor voltage balancing control method according to claim 1, characterized in that: When the positive bus capacitor or the negative bus capacitor is discharged and voltage-balanced through the inverter capacitor and the inverter inductor in the single-phase inverter circuit, the inverter is in a standby state.

11. A computing device comprising a memory, a processor and a computer program stored in the memory and executable by the processor, characterized in that: When the processor executes the computer program, the method according to any one of claims 1 to 10 is implemented.

12. A computer-readable storage medium having a computer program stored therein, characterized in that: The computer program implements the method according to any one of claims 1 to 10 when executed by a processor.

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