Gate voltage bootstrapped switch circuit for SAR ADC

Abstract

The invention discloses a bootstrapped switching circuit for SAR ADC, which comprises a voltage control unit and a switching tube unit, the voltage control unit comprises a first capacitor and a second capacitor which are connected in parallel, one end of the first capacitor and one end of the second capacitor are both connected with an external power supply, and the other end of the first capacitor and the other end of the second capacitor are both connected with the switching tube unit; the switch tube unit comprises a switch MOS tube, a first MOS tube and a second MOS tube, the grid electrode of the switch MOS tube is connected with the other end of the first capacitor and the other end of the second capacitor, when the capacitors discharge, the voltage of the grid electrode of the switch MOS tube is increased to two times of the voltage of the power supply, the substrate of the switch MOS tube is connected with the drain electrode of the first MOS tube and the source electrode of the second MOS tube, the drain electrode of the second MOS tube is connected with the source electrode of the switch MOS tube, and the grid electrode of the switch MOS tube is connected with the source electrode of the second MOS tube. And the grid electrode is connected with the grid electrode of the switch MOS tube. According to the bootstrapped switching circuit, the electric leakage behavior of the switching MOS tube is prevented, the on resistance of the switching MOS tube is reduced, and the sampling rate of the SAR ADC is increased.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuits, and more particularly to a gate voltage bootstrap switch circuit applied to a SAR ADC. Background Art

[0002] All SAR ADC sampling is divided into upper plate sampling and lower plate sampling. Upper plate sampling can save one clock cycle, but the switch requirement is relatively high; lower plate sampling does not require a switch but will add one more clock cycle. When upper plate sampling is selected, the switch needs to be made into a gate voltage bootstrap switch under the requirements of high-precision ADC (12 bits and above).

[0003] The traditional gate voltage bootstrap switch circuit for SAR ADC is as follows: Figure 1 As shown in Figure 1 In the figure, M21~M210 are MOS tubes, CS is a capacitor, clks is a sampling clock signal, clkb is an inverted signal of the sampling clock signal, Vin is an input signal, Vout is an output signal, AVD is a power supply voltage, and a, b, c, d are different circuit nodes.

[0004] When clks is low, clkb is high. At this time, MOS tubes M21, M23, M24, M27 and M28 are turned on, and the other MOS tubes are turned off. At this time, the voltage of node a is the ground voltage, and the voltage of node c is the power supply voltage AVD; when clks is high, MOS tubes M22, M25, M26, M29 and M210 are turned on, and the other MOS tubes are turned off. At this time, because MOS tube M29 is turned on, the voltage of node a is the voltage Vin of the input signal. Since the voltage difference across the capacitor Cs does not change, the voltage of node c changes to AVD+Vin; and because MOS tube M25 is turned on, the voltage of node d is equal to the voltage of node c, so the gate voltage of MOS tube M210 is AVD+Vin, and the formula of the on-resistance Ron of each MOS tube is as follows:

[0005]

[0006] In the above formula, u and Cox are respectively the carrier mobility and the unit capacitance of the gate oxide layer, W and L are the width and length of each MOS tube, Vgs and Vth are respectively the gate-source voltage and the turn-on voltage of each MOS tube, and except for the gate-source voltage Vgs, the other variables are constants, so the linearity of the on-resistance Ron can be guaranteed by ensuring that the gate-source voltage Vgs remains unchanged. Among them, the MOS tube M210 is the switch MOS tube of the entire switch circuit, and under any input voltage Vin, the gate-source voltage Vgs of the MOS tube M210 is: Vgs=AVD+Vin-Vin=AVD, so the linearity of the on-resistance of the MOS tube M210 can be guaranteed.

[0007] However, the above-mentioned traditional gate voltage bootstrap switch circuit for SAR ADC still has the following disadvantages:

[0008] First, when the power supply voltage AVD is relatively low (below 1V), the on-resistance of each MOS tube will be relatively large, which will affect the sampling speed of the SAR ADC and cause distortion.

[0009] Secondly, the substrate of the switch MOS tube M210 is connected to its source, that is, connected to the input voltage Vin. If the output voltage Vout is lower than the input voltage Vin during the conversion process, leakage behavior will occur.

[0010] Therefore, it is necessary to provide an improved gate voltage bootstrap switch circuit for SAR ADC to overcome the above defects. Summary of the invention

[0011] The object of the present invention is to provide a gate voltage bootstrap switch circuit for SAR ADC. The gate voltage bootstrap switch circuit of the present invention prevents leakage of the switch MOS tube, reduces the on-resistance of the switch MOS tube, and speeds up the sampling rate of the SAR ADC.

[0012] To achieve the above-mentioned object, the present invention provides a gate voltage bootstrap switch circuit for SAR ADC, comprising a voltage control unit and a switch tube unit, wherein the voltage control unit is respectively connected to a power supply voltage and an external clock, the external clock generates a first clock signal and a second clock signal with opposite phases, the voltage control unit applies the power supply voltage to the switch tube unit by receiving different external clock signals to control the voltage of the switch tube unit, an external signal is input to the switch tube unit, and under the voltage control of the voltage control unit, when the switch tube unit is turned on, the external signal is output through the switch tube unit; wherein the voltage control unit comprises a first capacitor and a second capacitor connected in parallel, one end of each of the first capacitor and the second capacitor is connected to an external power supply, and the other end is connected to the switch tube unit. The switch tube unit comprises a switch MOS tube, a first MOS tube and a second MOS tube, the gate of the switch MOS tube is connected to the other end of the first capacitor and the second capacitor, when the first capacitor and the second capacitor are discharged, the gate voltage of the switch MOS tube increases to twice the power supply voltage, the external signal is input to the source of the switch MOS tube, the drain of the switch MOS tube forms an output end to output the signal, the substrate of the switch MOS tube is commonly connected to the drain of the first MOS tube and the source of the second MOS tube, the source of the first MOS tube is grounded, the first clock signal is input to the gate of the first MOS tube, the drain of the second MOS tube is connected to the source of the switch MOS tube, and the gate thereof is connected to the gate of the switch MOS tube.

[0013] Preferably, the switch tube unit further includes a third MOS tube, the source of the third MOS tube is connected to the gate of the switch MOS tube, the drain of the third MOS tube is grounded, and the first clock signal is input into the gate of the third MOS tube.

[0014] Preferably, the voltage control unit includes a fourth MOS tube, a fifth MOS tube, a sixth MOS tube, a seventh MOS tube, an eighth MOS tube, a ninth MOS tube, a tenth MOS tube and a voltage control switch, the external power supply voltage is respectively input into the source of the fourth MOS tube and the fifth MOS tube, the gates of the fourth MOS tube, the fifth MOS tube and the eighth MOS tube are connected together and connected to the gate of the switch MOS tube, the drain of the fourth MOS tube, the drain of the eighth MOS tube and one end of the first capacitor are connected together, the other end of the first capacitor is connected to the drain of the sixth MOS tube, the drain of the fifth MOS tube is connected to one end of the second capacitor, the other end of the second capacitor is connected to the source of the eighth MOS tube, the drain of the seventh MOS tube and the drain of the eighth MOS tube. The drains of the MOS tubes are connected in common, the first clock signal is respectively input into the gates of the sixth MOS tube and the seventh MOS tube, and the sources of the sixth MOS tube and the seventh MOS tube are both grounded; the drain of the ninth MOS tube is connected in common with the drain of the sixth MOS tube and the input end of the voltage-controlled switch, the source of the ninth MOS tube is connected with the source of the switch MOS tube, the gate of the ninth MOS tube is connected in common with a control end of the voltage-controlled switch and the gate of the switch MOS tube, the drain of the tenth MOS tube is connected with the drain of the fifth MOS tube, the source thereof is connected with the gate of the switch MOS tube, and the gate of the tenth MOS tube is connected with the output end of the voltage-controlled switch; the second clock signal is input into the other control end of the voltage control.

[0015] Preferably, the voltage control unit further includes an eleventh MOS tube, the drain of the eleventh MOS tube is connected to the drain of the fifth MOS tube, the source of the eleventh MOS tube is connected to the gate of the tenth MOS tube, and the first clock signal is input to the gate of the eleventh MOS tube.

[0016] Compared with the prior art, the gate voltage bootstrap switch circuit for SAR ADC of the present invention has a first capacitor and a second capacitor connected in parallel in the voltage control unit, and the upper plates of the first capacitor and the second capacitor can be charged to the power supply voltage, and the first capacitor and the second capacitor are both connected to the gate of the switch MOS tube, so that the voltage of the gate of the switch MOS tube can be pulled to twice the power supply voltage, thereby reducing the resistance of the switch MOS tube when it is turned on, and correspondingly improving the sampling rate of the SAR ADC; in addition, the substrate of the switch MOS tube is connected to the drain of the first MOS tube, and the second MOS tube is turned on when the first MOS tube is turned off, so that the substrate voltage of the switch MOS tube is also the voltage of the external input signal, and is equal to the drain-source voltage of the switch MOS tube, thereby preventing the occurrence of leakage of the switch MOS tube.

[0017] The present invention will become more apparent from the following description taken in conjunction with the accompanying drawings, which are used to illustrate embodiments of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 It is a schematic diagram of the structure of an existing gate voltage bootstrap switch circuit for SAR ADC.

[0019] Figure 2 The figure is a schematic structural diagram of a gate voltage bootstrap switch circuit for SAR ADC of the present invention. DETAILED DESCRIPTION

[0020] Embodiments of the present invention are now described with reference to the accompanying drawings, in which like element numbers represent like elements. As described above, the present invention provides a gate voltage bootstrap switch circuit for SAR ADC, which prevents leakage of the switch MOS tube, reduces the on-resistance of the switch MOS tube, and speeds up the sampling rate of the SAR ADC.

[0021] Please refer to Figure 2 , Figure 2The present invention is a schematic diagram of the structure of the gate voltage bootstrap switch circuit for SAR ADC. As shown in the figure, the gate voltage bootstrap switch circuit for SAR ADC of the present invention includes a voltage control unit and a switch tube unit, the voltage control unit is connected to the power supply voltage AVD and the external clock respectively, and the external clock generates a first clock signal clkb and a second clock signal clks with opposite phases, that is, the first clock signal clkb and the second clock signal clks have the same frequency and amplitude, but are only opposite in phase. In practical applications, a pair of clock signals with opposite phases can be easily obtained through an inverter, which will not be described in detail here; the voltage control unit applies the power supply voltage AVD to the switch tube unit by receiving different external clock signals to control the voltage of the switch tube unit, and the external signal Vin is input to the switch tube unit. Under the voltage control of the voltage control unit, when the switch tube unit is turned on, the external signal is output through the switch tube unit to form an output signal Vout, thereby realizing the function of the switch.

[0022] The voltage control unit includes a first capacitor C1 and a second capacitor C2 connected in parallel, one end of the first capacitor C1 and the second capacitor C2 are connected to an external power supply AVD, and the other end is connected to the switch tube unit; the switch tube unit includes a switch MOS tube M0, a first MOS tube M1 and a second MOS tube M2, the gate of the switch MOS tube M0 is connected to the other end of the first capacitor C1 and the second capacitor C2, and when the first capacitor C1 and the second capacitor C2 are discharged, they both apply the power supply voltage AVD to the gate of the switch MOS tube M0. The gate of the switch MOS tube M0 is increased to twice the power supply voltage, that is, 2AVD; the external signal Vin is input to the source of the switch MOS tube M0, so that the gate voltage Vg of the switch MOS tube M0 is: Vg=2AVD+Vin (Vin represents the voltage value of the external signal Vin), that is, the gate-source voltage Vgs of the switch MOS tube M0 is: Vgs=(2AVD+Vin)-Vin=2AVD, thereby reducing the on-resistance of the switch MOS tube M0 and correspondingly improving the SAR. ADC sampling rate; the drain of the switch MOS tube M0 forms an output terminal to output a signal Vout, the substrate of the switch MOS tube M0 is commonly connected to the drain of the first MOS tube and the source of the second MOS tube M2, the source of the first MOS tube M1 is grounded, the first clock signal clkb is input to the gate of the first MOS tube M1, the drain of the second MOS tube M2 is connected to the source of the switch MOS tube M0, and the gate thereof is connected to the gate of the switch MOS tube M0; when the first clock signal clkb is at a low level, the first MOS tube M1 is turned off, and the second MOS tube M2 is turned on, at this time, the substrate voltage of the switch MOS tube M0 is also the voltage Vin of the external input signal, and is equal to the drain-source voltage of the switch MOS tube M0, thereby preventing the occurrence of leakage of the switch MOS tube M0.

[0023] Specifically, the switch tube unit further includes a third MOS tube M3, a source of the third MOS tube M3 is connected to the gate of the switch MOS tube M0, a drain of the third MOS tube M3 is grounded, and a first clock signal clkb is input to the gate of the third MOS tube M3; when the first clock signal clkb is at a high level, the third MOS tube M3 is turned on to pull the voltage of the node e to the ground, so as to ensure that when the first capacitor C1 and the second capacitor C2 discharge the switch MOS tube M0, the voltage of the node e is the ground voltage 0.

[0024] In addition, the voltage control unit includes a fourth MOS tube M4, a fifth MOS tube M5, a sixth MOS tube M6, a seventh MOS tube M7, an eighth MOS tube M8, a ninth MOS tube M9, a tenth MOS tube M10 and a voltage control switch, and the external power supply voltage AVD is respectively input to the source of the fourth MOS tube M4 and the fifth MOS tube M5, and the gates of the fourth MOS tube M4, the fifth MOS tube M5 and the eighth MOS tube M8 are connected together and connected to the gate of the switch MOS tube M0, and the drain of the fourth MOS tube M4 and the drain of the eighth MOS tube M8 are connected to the drain of the fourth MOS tube M4 and the drain of the eighth MOS tube M8. The drain and one end of the first capacitor C1 are connected together, the other end of the first capacitor C1 is connected to the drain of the sixth MOS tube M6, the drain of the fifth MOS tube M5 is connected to one end of the second capacitor C2, and the other end of the second capacitor C2 is connected to the source of the eighth MOS tube M8 and the drain of the seventh MOS tube M7; so that the power supply voltage AVD is charged to the upper plates (one end) of the first capacitor C1 and the second capacitor C2 through the fourth MOS tube M4 and the fifth MOS tube M5 respectively, until the voltage of the upper plates is the power supply voltage AVD. The first clock signal clkb is input to the gates of the sixth MOS tube M6 and the seventh MOS tube M7 respectively, and the sources of the sixth MOS tube M6 and the seventh MOS tube M7 are grounded, so that when the first clock signal clkb is at a high level, the sixth MOS tube M6 and the seventh MOS tube M7 are turned on, so that the lower plates (the other end) of the first capacitor C1 and the second capacitor C2 are grounded, and at the same time, it is ensured that the voltage of the upper plates of the first capacitor C1 and the second capacitor C2 is a stable power supply voltage AVD. The drain of the ninth MOS tube M9 is commonly connected to the drain of the sixth MOS tube M6 and the input end of the voltage control switch, the source of the ninth MOS tube M9 is connected to the source of the switch MOS tube M0, the gate of the ninth MOS tube M9 is commonly connected to a control end of the voltage control switch and the gate of the switch MOS tube M0, the drain of the tenth MOS tube M10 is connected to the drain of the fifth MOS tube M5, the source of the tenth MOS tube M10 is connected to the gate of the switch MOS tube M0, and the gate of the tenth MOS tube M10 is connected to the output end of the voltage control switch; the second clock signal clks is input to the other control end of the voltage control; wherein the voltage control switch is composed of two P-type MOS and N-type MOS tubes of the same size connected to each other in source and drain, when the second clock signal clks is at a high level, the voltage control switch is turned on, so that the node a is connected to the node f, otherwise, the voltage control switch is turned off, and the node a is disconnected from the node f, so as to adjust the voltage of the control node f.As a preferred embodiment of the present invention, the voltage control unit further includes an eleventh MOS tube M11, a drain of the eleventh MOS tube M11 is connected to the drain of the fifth MOS tube M5, a source of the eleventh MOS tube M11 is connected to the gate of the tenth MOS tube M10, a first clock signal clkb is input to the gate of the eleventh MOS tube M11, and when the first clock signal clkb is at a high level, the eleventh MOS tube M11 is turned on, thereby adding the voltage of the node d to the node f, pulling up the gate voltage of the tenth MOS tube M10, and turning off the tenth MOS tube M10 to prevent leakage.

[0025] Please refer to Figure 2 , describing the working process and working principle of the gate voltage bootstrap switch circuit for SAR ADC of the present invention:

[0026] When the first clock signal clkb is at a high level and the second clock signal clks is at a low level (wherein the high level is the external power supply voltage AVD and the low level is the ground voltage 0); at this time, the sixth MOS tube M6 and the seventh MOS tube M7 are turned on, and the voltages of the nodes a and c are at a low level; at the same time, the third MOS tube M3 is turned on, and the voltage of the node e is pulled down to the ground level, that is, at a low level, so that the fourth MOS tube M4 and the fifth MOS tube M5 are turned on, and the voltages of the nodes b and d are both at a high level; furthermore, the first clock signal clkb is at a high level, so that the first MOS tube M1 is turned on, and the voltage of the node g is pulled down to the ground level, that is, at a low level, that is, the substrate of the switch MOS tube M0 is connected to the ground at this time, ensuring that the switch MOS tube M0 is switched on during this time period. The substrate voltage of the switch MOS tube M0 must be lower than the voltage Vout of the output signal, which effectively prevents the leakage of the switch MOS tube M0; in addition, the first clock signal clkb is at a high level, so that the eleventh MOS tube M11 is turned on, thereby raising the gate voltage of the tenth MOS tube M10, so that the tenth MOS tube M10 is turned off to prevent leakage; all other MOS tubes are in a cut-off state, and at the same time, because the fourth MOS tube M4 and the fifth MOS tube M5 are turned on, the upper plates of the first capacitor C1 and the second capacitor C2 are charged, and the charging voltage is AVD, and because the sixth MOS tube M6 and the seventh MOS tube M7 are turned on, the lower plates of the first capacitor C1 and the second capacitor C2 are both ground voltage 0, which further ensures that the voltage of their upper plates is the power supply voltage AVD.

[0027] When the first clock signal clkb is at a low level and the second clock signal clks is at a high level, the voltage control switch is turned on, and the voltage of the node f is equal to the voltage of the node a and is at a low level (the voltage of the lower plate of the first capacitor C1), so the tenth MOS tube M10 is turned on, and at this time the voltage of the node e is pulled up (the upper plate of the second capacitor C2 is discharged to the node e through the tenth MOS tube M10), causing the eighth MOS tube M8, the ninth MOS tube M9, the second MOS tube M2 and the switch MOS tube M0 to be turned on. Because the ninth MOS tube M9 is turned on, the voltage of the node a is the external input signal voltage Vin, and because of the capacitor characteristics, the node b The voltage of node b is AVD+Vin. Because the eighth MOS tube M8 is turned on, the voltage of node b is equal to the voltage of node c. Because of the capacitance characteristics, the voltage of node d is AVD+(AVD+Vin)=2AVD+Vin. Because the tenth MOS tube M10 is turned on, the voltage of node d is equal to the voltage of node e. Therefore, the gate voltage of the switch MOS tube M0 is 2AVD+Vin. Therefore, the gate-source voltage Vgs of the switch MOS tube M0 is 2AVD. At this time, the second MOS tube M2 is turned on, so that the substrate voltage of the switch MOS tube M0 is also Vin, which is equal to its drain-source voltage, thereby preventing leakage.

[0028] In summary, the gate voltage bootstrap switch circuit for SAR ADC of the present invention is provided with a first capacitor and a second capacitor connected in parallel in the voltage control unit, and the upper plates of the first capacitor and the second capacitor can be charged to the power supply voltage AVD, and the first capacitor and the second capacitor are both connected to the gate of the switch MOS tube, so that the voltage of the gate of the switch MOS tube can be pulled to twice the power supply voltage, thereby reducing the resistance of the switch MOS tube M0 when it is turned on, and correspondingly improving the sampling rate of the SAR ADC; in addition, the substrate of the switch MOS tube M0 is connected to the drain of the first MOS tube M1, and the second MOS tube M2 is turned on while the first MOS tube M1 is turned off, so that the substrate voltage of the switch MOS tube M0 is also the voltage Vin of the external input signal, and is equal to the drain-source voltage of the switch MOS tube M0, thereby preventing the occurrence of leakage of the switch MOS tube M0.

[0029] The present invention has been described above in conjunction with the best embodiments, but the present invention is not limited to the embodiments disclosed above, but should cover various modifications and equivalent combinations based on the essence of the present invention.

Claims

1. A gate voltage bootstrap switch circuit for SAR ADC, comprising a voltage control unit and a switch tube unit, wherein the voltage control unit is connected to a power supply voltage and an external clock respectively, the external clock generates a first clock signal and a second clock signal with opposite phases, the voltage control unit applies the power supply voltage to the switch tube unit by receiving different external clock signals to control the voltage of the switch tube unit, an external signal is input to the switch tube unit, and when the switch tube unit is turned on under the voltage control of the voltage control unit, the external signal is output through the switch tube unit; characterized in that The voltage control unit includes a first capacitor and a second capacitor connected in parallel, one end of the first capacitor and the second capacitor are both connected to an external power supply, and the other end is both connected to the switch tube unit; the switch tube unit includes a switch MOS tube, a first MOS tube and a second MOS tube, the gate of the switch MOS tube is connected to the other end of the first capacitor and the second capacitor, when the first capacitor and the second capacitor are discharged, the gate voltage of the switch MOS tube increases to twice the power supply voltage, an external signal is input to the source of the switch MOS tube, the drain of the switch MOS tube forms an output end to output a signal, the substrate of the switch MOS tube is commonly connected to the drain of the first MOS tube and the source of the second MOS tube, the source of the first MOS tube is grounded, a first clock signal is input to the gate of the first MOS tube, the drain of the second MOS tube is connected to the source of the switch MOS tube, and its gate is connected to the gate of the switch MOS tube.

2. The gate voltage bootstrap switch circuit for SAR ADC according to claim 1, characterized in that: The switch tube unit further includes a third MOS tube, a source of the third MOS tube is connected to the gate of the switch MOS tube, a drain of the third MOS tube is grounded, and a first clock signal is input into the gate of the third MOS tube.

3. The gate voltage bootstrap switch circuit for SAR ADC according to claim 1, characterized in that: The voltage control unit includes a fourth MOS tube, a fifth MOS tube, a sixth MOS tube, a seventh MOS tube, an eighth MOS tube, a ninth MOS tube, a tenth MOS tube and a voltage control switch, the external power supply voltage is respectively input into the source of the fourth MOS tube and the fifth MOS tube, the gates of the fourth MOS tube, the fifth MOS tube and the eighth MOS tube are connected together and connected to the gate of the switch MOS tube, the drain of the fourth MOS tube, the drain of the eighth MOS tube and one end of the first capacitor are connected together, the other end of the first capacitor is connected to the drain of the sixth MOS tube, the drain of the fifth MOS tube is connected to one end of the second capacitor, the other end of the second capacitor is connected to the source of the eighth MOS tube, the drain of the seventh MOS tube The drains of the S tubes are connected together, the first clock signal is respectively input into the gates of the sixth MOS tube and the seventh MOS tube, and the sources of the sixth MOS tube and the seventh MOS tube are grounded; the drain of the ninth MOS tube is connected together with the drain of the sixth MOS tube and the input end of the voltage control switch, the source of the ninth MOS tube is connected to the source of the switch MOS tube, the gate of the ninth MOS tube is connected together with a control end of the voltage control switch and the gate of the switch MOS tube, the drain of the tenth MOS tube is connected to the drain of the fifth MOS tube, the source thereof is connected to the gate of the switch MOS tube, and the gate of the tenth MOS tube is connected to the output end of the voltage control switch; the second clock signal is input into the other control end of the voltage control.

4. The gate voltage bootstrap switch circuit for SAR ADC according to claim 3, characterized in that: The voltage control unit also includes an eleventh MOS tube, the drain of the eleventh MOS tube is connected to the drain of the fifth MOS tube, the source of the eleventh MOS tube is connected to the gate of the tenth MOS tube, and the first clock signal is input to the gate of the eleventh MOS tube.

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