A miniaturized Beidou III dual-frequency down-conversion board

Abstract

The invention discloses a miniaturized Beidou III dual-frequency down-conversion board, comprising a dual-frequency down-conversion module, wherein the dual-frequency down-conversion module is arranged between a low-noise amplifier and a whole mainboard of a receiver, and comprises a feeding circuit, an amplifying circuit, a power dividing circuit, a B3 filtering circuit, a B1c filtering circuit, a frequency conversion processing circuit, and a power conversion circuit. The invention completes the superheterodyne receiving function of Beidou III satellite navigation signals, and provides corresponding intermediate frequency digital signal output, thereby providing intermediate frequency information for Beidou III satellite positioning and navigation solution.

Description

Technical Field

[0001] The invention relates to the field of Beidou satellite navigation system, and in particular to a miniaturized Beidou III dual-frequency down-conversion board. Background Art

[0002] BeiDou Navigation Satellite System: BeiDou Navigation Satelite System, also known as BDS. It is a global satellite system independently developed by China. The BeiDou Navigation Satellite System consists of three parts: space segment, ground segment and user segment. It can provide high-precision and high-reliability positioning, navigation and timing services for all types of users around the world all day and all day, and has short message communication capabilities. It has initially acquired regional navigation, positioning and timing capabilities, with a positioning accuracy of 10 meters, a speed measurement accuracy of 0.2m / s, and a timing accuracy of 10ns.

[0003] BeiDou-3 satellite navigation system: On November 5, 2017, China's third-generation navigation satellite was successfully launched, marking the official start of China's construction of the BeiDou global satellite navigation system.

[0004] At present, the development of user receivers and other equipment at the user end of the Beidou III global satellite navigation system is in the exploratory stage, and the intermediate frequency point, sampling clock, sampling method, etc. are urgently needed to be optimized through engineering exploration. The present invention provides a dual-frequency receiving module to solve this problem. Summary of the invention

[0005] The technical problem to be solved by the present invention is to provide a miniaturized Beidou-3 dual-frequency down-conversion board to help the Beidou-3 global satellite navigation and positioning user receiver system to realize quantization, coding, positioning, speed measurement and other information solutions.

[0006] In order to solve the above technical problems, the technical solution adopted by the present invention is: a miniaturized Beidou III dual-frequency down-conversion board, including a dual-frequency down-conversion module, which is arranged between a low-noise amplifier and a main board of a receiver, and the dual-frequency down-conversion module is arranged with a semicircular stamp hole and fixedly arranged on the main board of the receiver, and the semicircular stamp holes are 54 in total, which are numbered as the 1st pin to the 54th pin respectively, and the 25th pin is a radio frequency input port, and the radio frequency input port receives the B1c frequency satellite navigation signal and the B3 frequency satellite navigation signal after the electromagnetic wave of the space navigation signal is processed by the active antenna low-noise amplification and filtering, and transmits them to the amplification circuit, and the amplification circuit synchronously amplifies the B1c frequency satellite navigation signal and the B3 frequency satellite navigation signal and transmits them to the power division circuit, and the power division circuit transmits the B1c frequency satellite navigation signal and the B3 frequency satellite navigation signal to the B3 filtering circuit respectively. and B1c filtering circuit, the output ends of the B3 filtering circuit and the B1c filtering circuit are connected to the frequency conversion processing circuit, the frequency conversion processing circuit down-converts the RF frequency of the B1c frequency point and the RF frequency of the B3 frequency point to the corresponding intermediate frequency frequency of the B1c frequency point and the intermediate frequency frequency of the B3 frequency point respectively, so as to realize the shifting of the spectrum, the frequency conversion processing circuit converts the intermediate frequency frequency of the B1c frequency point and the intermediate frequency frequency of the B3 frequency point into a digital intermediate frequency signal output, the 10MHz reference signal is input to the frequency conversion processing circuit, the frequency conversion processing circuit outputs an 80MHz sampling clock signal, one end of the feeding circuit is connected to the input end of the DC power supply VCC-5V, and the other end outputs DC power to feed the low-noise amplifier at the front end of the module, the input end of the DC power supply VCC-5V is also connected to the power conversion circuit, the power conversion circuit converts the DC power supply VCC-5V to the DC power supply VCC-3.3V output and provides them to the amplifier circuit and the frequency conversion processing circuit respectively.

[0007] A further improvement of the technical solution of the present invention is that: the feeding circuit includes a recoverable fuse R1, a choke coil inductor L1, a power filter capacitor C1, and a power filter capacitor C2. The input end of the DC power supply VCC-5V enters the first end connected to the recoverable fuse R1 through the 28th and 29th pins of the semicircular stamp hole. The second end of the recoverable fuse R1 is respectively connected to the first end of the power filter capacitor C1 and the power filter capacitor C2 in parallel and the first end of the choke coil inductor L1. The second end of the power filter capacitor C1 and the power filter capacitor C2 in parallel is grounded. The second end of the choke coil inductor L1 outputs DC power through the 25th pin of the semicircular stamp hole to feed the low-noise amplifier at the front end of the module.

[0008] A further improvement of the technical solution of the present invention is that: the amplification circuit includes a monolithic amplifier U3, and the low noise amplifier at the front end of the module processes the radio frequency navigation signal RF-IN and inputs it into the module through the 25th pin of the semicircular stamp hole and connects to the first end of the coupling capacitor C6, the second end of the coupling capacitor C6 is respectively connected to the first ends of the resistor R9, the resistor R3, and the resistor R5, the second end of the resistor R9 is grounded, the resistor R3, the resistor R5, and the resistor R4 form a π-type impedance matching network, the second end of the resistor R5 is respectively connected to the first end of the resistor R4 and the first end of the coupling capacitor C7, the second end of the resistor R3 and the second end of the resistor R4 are respectively grounded, and the second end of the coupling capacitor C7 is connected to the pin 4 of the monolithic amplifier U3, Pin 0, pin 2, pin 3, pin 5, pin 6, pin 7, and pin 8 of the monolithic amplifier U3 are grounded, pin 1 of the monolithic amplifier U3 is respectively connected to the first end of the inductor L2 and the first end of the coupling capacitor C8, the second end of the inductor L2 is respectively connected to the first ends of the inductor C3, the inductor C4, and the resistor R2, the second ends of the inductor C3 and the inductor C4 are respectively grounded, the second end of the resistor R2 is connected to the DC power supply VCC-3.3V, the second end of the coupling capacitor C8 is respectively connected to the first ends of the resistor R10, the resistor R7, and the resistor R6, the second end of the resistor R6 is connected to the first end of the resistor R8 and RF-IN-1, and the second ends of the resistor R10, the resistor R7, and the resistor R8 are respectively grounded.

[0009] A further improvement of the technical solution of the present invention is that: the power division circuit includes a power divider U2, RF-IN-1 is connected to pin 2 of the power divider U2, pin 1, pin 3, pin 4, pin 5, pin 6, pin 8, pin 10, pin 11, and pin 12 of the power divider U2 are grounded respectively, pin 9 of the power divider U2 is connected to the first end of the capacitor C5, the second end of the capacitor C5 is RF-B3-OUT, and pin 7 of the power divider U2 is connected to the first end of the capacitor C10, and the second end of the capacitor C10 is RF-B1c-OUT.

[0010] A further improvement of the technical solution of the present invention is that: the B3 filtering circuit includes a frequency point filter U8, RF-B3-OUT is respectively connected to the first end of resistor R26 and the first end of resistor R29, the second end of the resistor R26 is respectively connected to the first end of resistor R30 and pin 2 of the frequency point filter U8, the second end of the resistor R29 and the second end of the resistor R30 are respectively grounded, pin 1, pin 3, pin 4 and pin 6 of the frequency point filter U8 are respectively grounded, pin 5 of the frequency point filter U8 is respectively connected to the first end of resistor R27 and the first end of resistor R31, the second end of the resistor R27 is respectively connected to the first end of resistor R32 and the first end of capacitor C37, the second end of the resistor R31 and the second end of the resistor R32 are respectively grounded, and the second end of the capacitor C37 is RF-B3-OUT1.

[0011] A further improvement of the technical solution of the present invention is that: the B1c filtering circuit includes a dielectric filter U10, RF-B1c-OUT is respectively connected to the first end of the resistor R42 and the first end of the resistor R44, the second end of the resistor R42 is respectively connected to the first end of the resistor R45 and the pin 1 of the dielectric filter U10, the second end of the resistor R44 and the second end of the resistor R45 are respectively grounded, pins 3, 4, 5, 6 and 7 of the dielectric filter U10 are respectively grounded, pin 2 of the dielectric filter U10 is respectively connected to the first end of the resistor R43 and the first end of the resistor R46, the second end of the resistor R43 is respectively connected to the first end of the resistor R47 and the first end of the capacitor C43, the second end of the resistor R46 and the second end of the resistor R47 are respectively grounded, and the second end of the capacitor C43 is RF-B1c-OUT1.

[0012] A further improvement of the technical solution of the present invention is that: the power conversion circuit includes a power chip U4, and the external DC power supply VCC-5V of the dual-frequency down-conversion module enters through the 28th and 29th pins of the semicircular stamp holes and is respectively connected to the first end of the capacitor C12, the first end of the capacitor C13, and the pin 1 and pin 7 of the power chip U4. The pins 0, 4 and 6 of the power chip U4 are respectively grounded, and the pin 8 of the power chip U4 is connected to the first end of the resistor R11. The first end of the resistor R12 and the capacitor C11 after being connected in parallel is respectively connected to the pin 2 of the power chip U4 and the second end of the resistor R11. The second end of the resistor R12 and the capacitor C11 after being connected in parallel is grounded, and the pins 3 and 5 of the power chip U4 are chip output pins and are respectively connected to the first end of the power filter capacitor C14 and the DC power supply VCC-3.3V, and the second end of the power filter capacitor C14 is grounded.

[0013] A further improvement of the technical solution of the present invention is that: the frequency conversion processing circuit includes an integrated circuit U7, RF-B3-OUT1 is connected to the first end of the inductor L7, the second end of the inductor L7 is connected to the capacitor C36 and then to the pin 9 of the integrated circuit U7, RF-B1c-OUT1 is connected to the capacitor C44 and the inductor L10 in sequence and then to the pin 15 of the integrated circuit U7, the pin 2 of the integrated circuit U7 is respectively connected to the first end of the resistor R22 and the resistor R23, the second end of the resistor R23 is grounded, and the second end of the resistor R22 is connected to the power supply VCC-3.3 V-2202, the pin 5 of the integrated circuit U7 is respectively connected to the power supply VCC-3.3V-2202 and the grounded power supply filter capacitor C29, the pin 6 of the integrated circuit U7 is respectively connected to the resistor R24 ​​and the first end of the capacitor C32, the second end of the resistor R24 ​​is connected to the first end of the capacitor C30, the second end of the capacitor C32 is connected to the second end of the capacitor C30 and then to ground, the pin 7 of the integrated circuit U7 is respectively connected to the power supply VCC-3.3V-2202 and the grounded power supply filter capacitor C34, the pin 8 of the integrated circuit U7 is connected to the resistor R 25 is connected to ground, the pin 11 of the integrated circuit U7 is connected to the power supply VCC-3.3V-2202 and the grounded power supply filter capacitor C40, the pin 12 of the integrated circuit U7 is connected to the resistor R33 and then to ground, the pin 13 of the integrated circuit U7 is connected to the power supply VCC-3.3V-2202 and the grounded power supply filter capacitor C42, the pin 17 of the integrated circuit U7 is connected to the resistor R48 and then to the power supply VCC-3.3V-2202, the pin 18 of the integrated circuit U7 is connected to the power supply VCC-3.3V-2202 and the grounded The power filter capacitor C48 is connected to the ground, the pin 19 of the integrated circuit U7 is connected to the first end of the resistor R53 and the capacitor C45 respectively, the second end of the resistor R53 is connected to the first end of the capacitor C54, the second end of the capacitor C45 is connected to the second end of the capacitor C54 and then to the ground, the pin 20 of the integrated circuit U7 is connected to the capacitor C49 and then to the ground, the pin 22 and the pin 23 of the integrated circuit U7 are respectively connected to the power supply VCC-3.3V-2202 and the grounded power filter capacitor C50, and the pin 26 of the integrated circuit U7 is respectively connected to the power supply VCC-3.3V-2202.3V-2202 and a grounded power supply filter capacitor C46, ​​the pin 27 of the integrated circuit U7 is connected to the capacitor C47 and then to ground, the pin 29 of the integrated circuit U7 is connected to the resistor R49 and then to the B1c frequency point output intermediate frequency output terminal IF-B1c-D3 and output through the pin 44 of the semicircular stamp hole, the pin 30 of the integrated circuit U7 is connected to the resistor R50 and then to the B1c frequency point output intermediate frequency output terminal IF-B1c-D2 and output through the pin 45 of the semicircular stamp hole, the pin 31 of the integrated circuit U7 is connected to the resistor R51 and then to the B1c frequency point output intermediate frequency output terminal IF-B1c-D1 and output through the pin 46 of the semicircular stamp hole, the pin 32 of the integrated circuit U7 is connected to the resistor R52 and then to the Connect the B1c frequency output intermediate frequency output terminal IF-B1c-D0 and output through pin 47 of the semicircular stamp hole, the pin 35 of the integrated circuit U7 is connected to the resistor R39 and then connected to the B3 frequency output intermediate frequency output terminal IF-B3-D3 and output through pin 39 of the semicircular stamp hole, the pin 36 of the integrated circuit U7 is connected to the resistor R37 and then connected to the B3 frequency output intermediate frequency output terminal IF-B3-D2 and output through pin 40 of the semicircular stamp hole, the pin 37 of the integrated circuit U7 is connected to the resistor R36 and then connected to the B3 frequency output intermediate frequency output terminal IF-B3-D1 and output through pin 41 of the semicircular stamp hole, the pin 38 of the integrated circuit U7 is connected to the resistor R35 and then connected to the B3 frequency output intermediate frequency output The pin 47 of the integrated circuit U7 is respectively connected to the power supply VCC-3.3V-2202 and the grounded power supply filter capacitor C35, the pin 48 of the integrated circuit U7 is connected to the capacitor C33 and then connected to the B1c frequency analog digital signal output terminal IF-B1c-A, the pin 51 of the integrated circuit U7 is connected to the capacitor C31 and then connected to the B3 frequency analog digital signal output terminal IF-B3-A, the pin 54 of the integrated circuit U7 is respectively connected to the power supply VCC-3.3V-2202 and the grounded power supply filter capacitor C24, the pin 55 of the integrated circuit U7 is connected to the capacitor C23 and then grounded, and the pin 59 of the integrated circuit U7 is respectively connected to the power supply VCC-3.3V-2202 and the grounded power supply filter capacitor C24. Source VCC-3.3V-2202 and grounded power supply filter capacitor C22, pin 60 of the integrated circuit U7 is connected to resistor R21 and then connected to SPI control point SPI-CS, pin 61 of the integrated circuit U7 is connected to resistor R20 and then connected to SPI control point SPI-CLK, pin 62 of the integrated circuit U7 is connected to resistor R19 and then connected to SPI control point SPI-MOSI, pin 63 of the integrated circuit U7 is connected to resistor R18 and then connected to SPI control point SPI-MISO, pin 64 of the integrated circuit U7 is connected to capacitor C27 and then connected to 10MHz reference signal input port 10MHZ-IC-IN, and pin 65 of the integrated circuit U7 is respectively connected to power supply VCC-3.3V-2202 and grounded power supply filter capacitor C26, pin 67 of the integrated circuit U7 is respectively connected to the power supply VCC-3.3V-2202 and the grounded power supply filter capacitor C25, and pin 69 of the integrated circuit U7 is grounded;.

[0014] The frequency conversion processing circuit also includes a dual-frequency down-conversion module, wherein the internal DC power supply VCC-3.3V of the dual-frequency down-conversion module is respectively connected to the first ends of the magnetic bead L13, the capacitor C55 and the capacitor C56, the second end of the magnetic bead L13 is connected to the power supply VCC-3.3V-2202 of the integrated circuit U7, and the second ends of the capacitor C55 and the capacitor C56 are respectively grounded;

[0015] The frequency conversion processing circuit also includes an integrated circuit U7, the reference signal 10MHZ-IN is connected to the resistor R13 and then connected to the first ends of the inductor L3 and the capacitor C15 respectively, the second end of the inductor L3 is connected to the first ends of the inductor L4 and the capacitor C16 respectively, the second end of the inductor L4 is connected to the first end of the capacitor C17 and 10MHZ-IC-IN respectively, and the capacitors C15, C16 and C17 are grounded respectively;

[0016] The frequency conversion processing circuit also includes a NOT gate chip U5, an 80MHZ sampling clock signal is sequentially connected to a capacitor C20 and a resistor R15, and then respectively connected to the first end of a resistor R17, the first end of a resistor R14, and pins 1 and 2 of the NOT gate chip U5, a pin 3 of the NOT gate chip U5 is connected to the second end of the resistor R17 and then grounded, a second end of the resistor R14 is respectively connected to pin 5 of the NOT gate chip U5, a first end of a capacitor C18, a first end of a capacitor C19, and a first end of an inductor L5, a second end of the capacitor C18 and a second end of the capacitor C19 are respectively grounded, a second end of the inductor L5 is connected to a DC power supply VCC-3.3V, a pin 4 of the NOT gate chip U5 is sequentially connected to a capacitor C21 and a resistor R6, and then outputs 80MHZ-CLK-OUT, which is output to a baseband circuit at a later stage through the 37th pin of the semicircular stamp hole to provide an 80MHz sampling clock signal for it;

[0017] The frequency conversion processing circuit also includes an operational amplifier U9, and the B1c frequency analog intermediate frequency signal IF-B1c-OUT is output through the 6th pin of the semicircular stamp hole and connected to the first end of the capacitor C38 and the first end of the inductor L8 respectively, the second end of the capacitor C38 is grounded, the second end of the inductor L8 is connected to the resistor R28 and the capacitor C41 in sequence and then connected to the pin 1 of the operational amplifier U9, the pin 2 and the pin 4 of the operational amplifier U9 are grounded, the pin 5 of the operational amplifier U9 is connected to the first end of the resistor R38, the first end of the inductor L9 and the first end of the capacitor C39 respectively, the second end of the capacitor C39 is grounded, the second end of the inductor L9 is connected to the DC power supply VCC-3.3V, the B1c frequency analog intermediate frequency signal IF-B1c-A of the integrated circuit U7 is connected to the first end of the resistor R40 and the first end of the resistor R34 respectively, the second end of the resistor R40 is grounded, the pin 3 of the operational amplifier U9 is connected to the second end of the resistor R34, the second end of the resistor R38 and the first end of the resistor R41 respectively, and the second end of the resistor R41 is grounded;

[0018] The frequency conversion processing circuit also includes an operational amplifier U11. The B3 frequency analog intermediate frequency signal IF-B3-OUT is output through the 11th pin of the semicircular stamp hole and is respectively connected to the first end of the capacitor C51 and the first end of the inductor L11. The second end of the capacitor C51 is grounded. The second end of the inductor L11 is connected to the resistor R54 and the capacitor C53 in sequence and then connected to the pin 1 of the operational amplifier U11. The pins 2 and 4 of the operational amplifier U11 are grounded. The pin 5 of the operational amplifier U11 is respectively connected to the first end of the resistor R56 and the inductor L11. The first end of the inductor L12 and the first end of the capacitor C52 are connected, the second end of the capacitor C52 is grounded, the second end of the inductor L12 is connected to the DC power supply VCC-3.3V, the B3 frequency analog intermediate frequency signal IF-B3-A of the integrated circuit U7 is respectively connected to the first end of the resistor R57 and the first end of the resistor R55, the second end of the resistor R57 is grounded, the pin 3 of the operational amplifier U11 is respectively connected to the second end of the resistor R55, the second end of the resistor R56 and the first end of the resistor R58, the second end of the resistor R58 is grounded.

[0019] A further improvement of the technical solution of the present invention is that the frequency of the B3 frequency satellite navigation signal is 1268.52±10.23MHz, the intermediate frequency output from pin 39 to pin 42 is 15.48±10.23MHz, and the local oscillator frequency is 1284MHz; the frequency of the B1c frequency satellite navigation signal is 1575.42±16.368MHz, the intermediate frequency output from pin 44 to pin 47 is 20.58±16.368MHz, and the local oscillator frequency is 1596MHz.

[0020] Due to the adoption of the above technical solution, the technical progress achieved by the present invention is:

[0021] 1. The two frequency points B3 and B1c of the BeiDou-3 global satellite navigation system proposed in the present invention are down-converted to intermediate frequency bandpass signals, and a bandpass sampling method is adopted to realize analog-to-digital conversion. The bandpass sampling method has obvious advantages, such as reducing the sampling frequency, increasing the sampling rate, and effectively suppressing intermediate frequency harmonics.

[0022] 2. The present invention down-converts the B3 receiving radio frequency point 1268.52±10.23MHz in the BeiDou-3 global satellite navigation system to 15.48±10.23MHz. Down-converts the B1c receiving radio frequency point 1575.42±16.368MHz in the BeiDou-3 global satellite navigation system to 20.58±16.368MHz, and provides an 80MHz sampling clock for the digital baseband processing system;

[0023] 3. The dual-frequency down-conversion module of the present invention is small in size, with an overall size of 57mm×23mm×10mm. It adopts a surface mount structure and is welded with a semicircular stamp hole, which is conducive to the miniaturization and integrated design of the user's receiver.

[0024] 4. The present invention can feed the active antenna, which is beneficial to optimize the integration of the entire communication link;

[0025] 5. The module of the present invention has low power consumption, which is convenient for the user to realize low power consumption design of the whole receiver. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 It is a circuit principle block diagram of a dual-frequency down-conversion module of the present invention;

[0027] Figure 2 It is the appearance diagram of the dual-frequency down-conversion module of the present invention;

[0028] Figure 3 It is a principle block diagram of the feeding circuit of the dual-frequency down-conversion module of the present invention;

[0029] Figure 4 It is a schematic diagram of the amplifier circuit of the dual-frequency down-conversion module of the present invention;

[0030] Figure 5 It is a principle block diagram of the power division circuit of the dual-frequency down-conversion module of the present invention;

[0031] Figure 6 It is a schematic diagram of the filter circuit of the dual-frequency down-conversion module B3 of the present invention;

[0032] Figure 7 It is a schematic diagram of a filter circuit of a dual-frequency down-conversion module circuit B1c of the present invention;

[0033] Figure 8 It is a schematic diagram of a power conversion circuit of a dual-frequency down-conversion module of the present invention;

[0034] Fig. 9 It is a schematic diagram of a frequency conversion processing circuit of a dual-frequency down-conversion module of the present invention. DETAILED DESCRIPTION

[0035] The present invention is further described in detail below in conjunction with embodiments:

[0036] A miniaturized Beidou III dual-frequency down-conversion board includes a dual-frequency down-conversion module, which is arranged between a low-noise amplifier and a mainboard of a receiver. The dual-frequency down-conversion module is arranged with a semicircular stamp hole and is fixedly arranged on the mainboard of the receiver. There are 54 semicircular stamp holes, which are numbered as pin 1 to pin 54, respectively. The interface definition of each pin is as follows:

[0037]

[0038]

[0039] When welding, be sure to ensure that the module ground pin can be grounded over a large area, avoid short-circuiting the RF input port to the ground, and pay attention to electrostatic protection.

[0040] The 25th pin is the RF input port. Figure 2 As shown: the RF input port receives the B1c frequency satellite navigation signal and the B3 frequency satellite navigation signal after the electromagnetic wave of the space navigation signal is processed by the active antenna low noise amplification and filtering, and transmits them to the amplification circuit. The frequency of the B3 frequency satellite navigation signal is 1268.52±10.23MHz, the intermediate frequency output from the 39th pin to the 42nd pin is 15.48±10.23MHz, and the local oscillator frequency is 1284MHz; the frequency of the B1c frequency satellite navigation signal is 1575.42±16.368MHz, the intermediate frequency output from the 44th pin to the 47th pin is 20.58±16.368MHz, and the local oscillator frequency is 1596MHz. The input and output impedance matching of the dual-frequency down-conversion module are both 50 ohm standards, the overall frequency conversion link noise coefficient is less than 15dB, and the AGC range is greater than 35dB.

[0041] The amplifying circuit synchronously amplifies the B1c frequency satellite navigation signal and the B3 frequency satellite navigation signal of the navigation electromagnetic wave signal and transmits them to the power dividing circuit. The power dividing circuit transmits the B1c frequency satellite navigation signal and the B3 frequency satellite navigation signal to the B3 filtering circuit and the B1c filtering circuit respectively. The output ends of the B3 filtering circuit and the B1c filtering circuit are connected to the frequency conversion processing circuit. The frequency conversion processing circuit converts the radio frequency frequency of the B1c frequency point and the radio frequency frequency of the B3 frequency point down to the corresponding intermediate frequency frequency of the B1c frequency point and the intermediate frequency frequency of the B3 frequency point respectively, so as to realize the shifting of the spectrum. The processing circuit converts the intermediate frequency of the B1c frequency point and the intermediate frequency of the B3 frequency point into digital intermediate frequency signal output, and the 10MHz reference signal is input to the frequency conversion processing circuit, and the frequency conversion processing circuit outputs an 80MHz sampling clock signal. One end of the feeding circuit is connected to the input end of the DC power supply VCC-5V, and the other end outputs DC power to feed the low-noise amplifier at the front end of the module. The input end of the DC power supply VCC-5V is also connected to the power conversion circuit, and the power conversion circuit converts the DC power supply VCC-5V to the DC power supply VCC-3.3V output and provides it to the amplifier circuit and the frequency conversion processing circuit respectively.

[0042] like Figure 3 As shown: the feeding circuit includes a recoverable fuse R1, a choke coil inductor L1, a power filter capacitor C1, and a power filter capacitor C2. The input end of the DC power supply VCC-5V enters the first end of the recoverable fuse R1 through the 28th and 29th pins of the semicircular stamp hole. The second end of the recoverable fuse R1 is respectively connected to the first end of the power filter capacitor C1 and the power filter capacitor C2 in parallel and the first end of the choke coil inductor L1. The second end of the power filter capacitor C1 and the power filter capacitor C2 in parallel is grounded. The second end of the choke coil inductor L1 outputs DC power through the 25th pin of the semicircular stamp hole to feed the low noise amplifier at the front end of the module.

[0043] like Figure 4As shown: the amplification circuit includes a monolithic amplifier U3. After the low noise amplifier at the front end of the module processes the radio frequency navigation signal RF-IN, it is input into the module through the 25th pin of the semicircular stamp hole and connected to the first end of the coupling capacitor C6. The second end of the coupling capacitor C6 is respectively connected to the first ends of the resistors R9, R3 and R5. The second end of the resistor R9 is grounded. The resistors R3, R5 and R4 form a π-type impedance matching network. The second end of the resistor R5 is respectively connected to the first end of the resistor R4 and the first end of the coupling capacitor C7. The second ends of the resistor R3 and R4 are respectively grounded. The second end of the coupling capacitor C7 is connected to the pin 4 of the monolithic amplifier U3. Pin 0, pin 2, pin 3, pin 5, pin 6, pin 7 and pin 8 of the amplifier U3 are grounded, pin 1 of the monolithic amplifier U3 is respectively connected to the first end of the inductor L2 and the first end of the coupling capacitor C8, the second end of the inductor L2 is respectively connected to the first ends of the inductor C3, the inductor C4 and the resistor R2, the second ends of the inductor C3 and the inductor C4 are respectively grounded, the second end of the resistor R2 is connected to the DC power supply VCC-3.3V, the second end of the coupling capacitor C8 is respectively connected to the first ends of the resistor R10, the resistor R7 and the resistor R6, the second end of the resistor R6 is connected to the first end of the resistor R8 and RF-IN-1, and the second ends of the resistor R10, the resistor R7 and the resistor R8 are respectively grounded.

[0044] like Figure 5 As shown: the power division circuit includes a power divider U2, RF-IN-1 is connected to pin 2 of the power divider U2, pin 1, pin 3, pin 4, pin 5, pin 6, pin 8, pin 10, pin 11, and pin 12 of the power divider U2 are grounded respectively, pin 9 of the power divider U2 is connected to the first end of the capacitor C5, and the second end of the capacitor C5 is RF-B3-OUT, and pin 7 of the power divider U2 is connected to the first end of the capacitor C10, and the second end of the capacitor C10 is RF-B1c-OUT.

[0045] like Figure 6As shown: the B3 filtering circuit includes a frequency point filter U8, RF-B3-OUT is respectively connected to the first end of resistor R26 and the first end of resistor R29, the second end of the resistor R26 is respectively connected to the first end of resistor R30 and pin 2 of the frequency point filter U8, the second end of the resistor R29 and the second end of the resistor R30 are respectively grounded, pin 1, pin 3, pin 4 and pin 6 of the B3 frequency point filter U8 are respectively grounded, pin 5 of the frequency point filter U8 is respectively connected to the first end of resistor R27 and the first end of resistor R31, the second end of the resistor R27 is respectively connected to the first end of resistor R32 and the first end of capacitor C37, the second end of the resistor R31 and the second end of the resistor R32 are respectively grounded, and the second end of the capacitor C37 is RF-B3-OUT1.

[0046] like Figure 7 As shown: the B1c filtering circuit includes a dielectric filter U10, RF-B1c-OUT is respectively connected to the first end of the resistor R42 and the first end of the resistor R44, the second end of the resistor R42 is respectively connected to the first end of the resistor R45 and the pin 1 of the dielectric filter U10, the second end of the resistor R44 and the second end of the resistor R45 are respectively grounded, pins 3, 4, 5, 6 and 7 of the dielectric filter U10 are respectively grounded, pin 2 of the dielectric filter U10 is respectively connected to the first end of the resistor R43 and the first end of the resistor R46, the second end of the resistor R43 is respectively connected to the first end of the resistor R47 and the first end of the capacitor C43, the second end of the resistor R46 and the second end of the resistor R47 are respectively grounded, and the second end of the capacitor C43 is RF-B1c-OUT1.

[0047] like Figure 8 As shown: the power conversion circuit includes a power chip U4, the external DC power supply VCC-5V of the dual-frequency down-conversion module enters through the 28th and 29th pins of the semicircular stamp holes and is respectively connected to the first end of the capacitor C12, the first end of the capacitor C13, and the pin 1 and pin 7 of the power chip U4, the pin 0, pin 4 and pin 6 of the power chip U4 are respectively grounded, the pin 8 of the power chip U4 is connected to the first end of the resistor R11, the first end of the resistor R12 and the capacitor C11 after being connected in parallel is respectively connected to the pin 2 of the power chip U4 and the second end of the resistor R11, the second end of the resistor R12 and the capacitor C11 after being connected in parallel is grounded, the pin 3 and pin 5 of the power chip U4 are chip output pins and are respectively connected to the first end of the power filter capacitor C14 and the DC power supply VCC-3.3V, and the second end of the power filter capacitor C14 is grounded.

[0048] like Fig. 9As shown: the frequency conversion processing circuit includes an integrated circuit U7, RF-B3-OUT1 is connected to the first end of the inductor L7, the second end of the inductor L7 is connected to the capacitor C36 and then to the pin 9 of the integrated circuit U7, RF-B1c-OUT1 is connected to the capacitor C44 and the inductor L10 in sequence and then to the pin 15 of the integrated circuit U7, the pin 2 of the integrated circuit U7 is respectively connected to the first end of the resistor R22 and the resistor R23, the second end of the resistor R23 is grounded, the second end of the resistor R22 is connected to the power supply VCC-3.3V-2202, the integrated circuit Pin 5 of the integrated circuit U7 is respectively connected to the power supply VCC-3.3V-2202 and the grounded power supply filter capacitor C29, pin 6 of the integrated circuit U7 is respectively connected to the resistor R24 ​​and the first end of the capacitor C32, the second end of the resistor R24 ​​is connected to the first end of the capacitor C30, the second end of the capacitor C32 is connected to the second end of the capacitor C30 and then to the ground, pin 7 of the integrated circuit U7 is respectively connected to the power supply VCC-3.3V-2202 and the grounded power supply filter capacitor C34, pin 8 of the integrated circuit U7 is connected to the resistor R25 and then to the ground, Pin 11 of the integrated circuit U7 is respectively connected to the power supply VCC-3.3V-2202 and the grounded power supply filter capacitor C40, pin 12 of the integrated circuit U7 is connected to the resistor R33 and then to the ground, pin 13 of the integrated circuit U7 is respectively connected to the power supply VCC-3.3V-2202 and the grounded power supply filter capacitor C42, pin 17 of the integrated circuit U7 is connected to the resistor R48 and then to the power supply VCC-3.3V-2202, pin 18 of the integrated circuit U7 is respectively connected to the power supply VCC-3.3V-2202 and the grounded power supply filter capacitor C42. The power filter capacitor C48, the pin 19 of the integrated circuit U7 is respectively connected to the first end of the resistor R53 and the capacitor C45, the second end of the resistor R53 is connected to the first end of the capacitor C54, the second end of the capacitor C45 is connected to the second end of the capacitor C54 and then to ground, the pin 20 of the integrated circuit U7 is connected to the capacitor C49 and then to ground, the pins 22 and 23 of the integrated circuit U7 are respectively connected to the power supply VCC-3.3V-2202 and the grounded power filter capacitor C50, and the pin 26 of the integrated circuit U7 is respectively connected to the power supply VCC-3.3V-2202.3V-2202 and a grounded power supply filter capacitor C46, ​​the pin 27 of the integrated circuit U7 is connected to the capacitor C47 and then to ground, the pin 29 of the integrated circuit U7 is connected to the resistor R49 and then to the B1c frequency point output intermediate frequency output terminal IF-B1c-D3 and output through the pin 44 of the semicircular stamp hole, the pin 30 of the integrated circuit U7 is connected to the resistor R50 and then to the B1c frequency point output intermediate frequency output terminal IF-B1c-D2 and output through the pin 45 of the semicircular stamp hole, the pin 31 of the integrated circuit U7 is connected to the resistor R51 and then to the B1c frequency point output intermediate frequency output terminal IF-B1c-D1 and output through the pin 46 of the semicircular stamp hole, the pin 32 of the integrated circuit U7 is connected to the resistor R52 and then to the Connect the B1c frequency output intermediate frequency output terminal IF-B1c-D0 and output through pin 47 of the semicircular stamp hole, the pin 35 of the integrated circuit U7 is connected to the resistor R39 and then connected to the B3 frequency output intermediate frequency output terminal IF-B3-D3 and output through pin 39 of the semicircular stamp hole, the pin 36 of the integrated circuit U7 is connected to the resistor R37 and then connected to the B3 frequency output intermediate frequency output terminal IF-B3-D2 and output through pin 40 of the semicircular stamp hole, the pin 37 of the integrated circuit U7 is connected to the resistor R36 and then connected to the B3 frequency output intermediate frequency output terminal IF-B3-D1 and output through pin 41 of the semicircular stamp hole, the pin 38 of the integrated circuit U7 is connected to the resistor R35 and then connected to the B3 frequency output intermediate frequency output The pin 47 of the integrated circuit U7 is respectively connected to the power supply VCC-3.3V-2202 and the grounded power supply filter capacitor C35, the pin 48 of the integrated circuit U7 is connected to the capacitor C33 and then connected to the B1c frequency analog digital signal output terminal IF-B1c-A, the pin 51 of the integrated circuit U7 is connected to the capacitor C31 and then connected to the B3 frequency analog digital signal output terminal IF-B3-A, the pin 54 of the integrated circuit U7 is respectively connected to the power supply VCC-3.3V-2202 and the grounded power supply filter capacitor C24, the pin 55 of the integrated circuit U7 is connected to the capacitor C23 and then grounded, and the pin 59 of the integrated circuit U7 is respectively connected to the power supply VCC-3.3V-2202 and the grounded power supply filter capacitor C24. Source VCC-3.3V-2202 and grounded power supply filter capacitor C22, pin 60 of the integrated circuit U7 is connected to resistor R21 and then connected to SPI control point SPI-CS, pin 61 of the integrated circuit U7 is connected to resistor R20 and then connected to SPI control point SPI-CLK, pin 62 of the integrated circuit U7 is connected to resistor R19 and then connected to SPI control point SPI-MOSI, pin 63 of the integrated circuit U7 is connected to resistor R18 and then connected to SPI control point SPI-MISO, pin 64 of the integrated circuit U7 is connected to capacitor C27 and then connected to 10MHz reference signal input port 10MHZ-IC-IN, and pin 65 of the integrated circuit U7 is respectively connected to power supply VCC-3.3V-2202 and grounded power supply filter capacitor C26, pin 67 of the integrated circuit U7 is respectively connected to the power supply VCC-3.3V-2202 and the grounded power supply filter capacitor C25, and pin 69 of the integrated circuit U7 is grounded;.

[0049] The frequency conversion processing circuit also includes a dual-frequency down-conversion module, wherein the internal DC power supply VCC-3.3V of the dual-frequency down-conversion module is respectively connected to the first ends of the magnetic bead L13, the capacitor C55 and the capacitor C56, the second end of the magnetic bead L13 is connected to the power supply VCC-3.3V-2202 of the integrated circuit U7, and the second ends of the capacitor C55 and the capacitor C56 are respectively grounded;

[0050] The frequency conversion processing circuit also includes an integrated circuit U7, the reference signal 10MHZ-IN is connected to the resistor R13 and then connected to the first ends of the inductor L3 and the capacitor C15 respectively, the second end of the inductor L3 is connected to the first ends of the inductor L4 and the capacitor C16 respectively, the second end of the inductor L4 is connected to the first end of the capacitor C17 and 10MHZ-IC-IN respectively, and the capacitors C15, C16 and C17 are grounded respectively;

[0051] The frequency conversion processing circuit also includes a NOT gate chip U5, an 80MHZ sampling clock signal is sequentially connected to a capacitor C20 and a resistor R15, and then respectively connected to the first end of a resistor R17, the first end of a resistor R14, and pins 1 and 2 of the NOT gate chip U5, a pin 3 of the NOT gate chip U5 is connected to the second end of the resistor R17 and then grounded, a second end of the resistor R14 is respectively connected to pin 5 of the NOT gate chip U5, a first end of a capacitor C18, a first end of a capacitor C19, and a first end of an inductor L5, a second end of the capacitor C18 and a second end of the capacitor C19 are respectively grounded, a second end of the inductor L5 is connected to a DC power supply VCC-3.3V, a pin 4 of the NOT gate chip U5 is sequentially connected to a capacitor C21 and a resistor R6, and then outputs 80MHZ-CLK-OUT, which is output to a baseband circuit at a later stage through the 37th pin of the semicircular stamp hole to provide an 80MHz sampling clock signal for it;

[0052] The frequency conversion processing circuit also includes an operational amplifier U9, and the B1c frequency analog intermediate frequency signal IF-B1c-OUT is output through the 6th pin of the semicircular stamp hole and connected to the first end of the capacitor C38 and the first end of the inductor L8 respectively, the second end of the capacitor C38 is grounded, the second end of the inductor L8 is connected to the resistor R28 and the capacitor C41 in sequence and then connected to the pin 1 of the operational amplifier U9, the pin 2 and the pin 4 of the operational amplifier U9 are grounded, the pin 5 of the operational amplifier U9 is connected to the first end of the resistor R38, the first end of the inductor L9 and the first end of the capacitor C39 respectively, the second end of the capacitor C39 is grounded, the second end of the inductor L9 is connected to the DC power supply VCC-3.3V, the B1c frequency analog intermediate frequency signal IF-B1c-A of the integrated circuit U7 is connected to the first end of the resistor R40 and the first end of the resistor R34 respectively, the second end of the resistor R40 is grounded, the pin 3 of the operational amplifier U9 is connected to the second end of the resistor R34, the second end of the resistor R38 and the first end of the resistor R41 respectively, and the second end of the resistor R41 is grounded;

[0053] The frequency conversion processing circuit also includes an operational amplifier U11. The B3 frequency point analog intermediate frequency signal IF-B3-OUT is output through the 11th pin of the semicircular stamp hole and is respectively connected to the first end of the capacitor C51 and the first end of the inductor L11. The second end of the capacitor C51 is grounded. The second end of the inductor L11 is connected to the resistor R54 and the capacitor C53 in sequence and then connected to the pin 1 of the operational amplifier U11. The pins 2 and 4 of the operational amplifier U11 are grounded. The pins 5 and 6 of the operational amplifier U11 are respectively connected to the first ends of the resistors R56 and R57. The first end of the inductor L12 and the first end of the capacitor C52, the second end of the capacitor C52 is grounded, the second end of the inductor L12 is connected to the DC power supply VCC-3.3V, the B3 frequency analog intermediate frequency signal IF-B3-A of the integrated circuit is respectively connected to the first end of the resistor R57 and the first end of the resistor R55, the second end of the resistor R57 is grounded, the pin 3 of the operational amplifier U11 is respectively connected to the second end of the resistor R55, the second end of the resistor R56 and the first end of the resistor R58, the second end of the resistor R58 is grounded.

[0054] The present invention mainly realizes the frequency conversion part of the satellite navigation receiving link. When in use, the module area of ​​the present invention is digitally separated from the whole machine as much as possible to ensure good electromagnetic compatibility characteristics.

[0055] In summary, the present invention realizes the down-conversion function of the dual-frequency signal in the Beidou-3 navigation signal, outputs a bandpass signal, and can cooperate with the sampling clock to realize the navigation PVT solution, providing a good analog solution for the Beidou-3 navigation and positioning user terminal system.

Claims

1. A miniaturized Beidou III dual-frequency down-conversion board, characterized by: The invention comprises a dual-frequency down-conversion module, which is arranged between a low-noise amplifier and a mainboard of a receiver. The dual-frequency down-conversion module is arranged by a semicircular stamp hole and is fixedly arranged on the mainboard of the receiver. There are 54 semicircular stamp holes, which are numbered as the 1st to the 54th pins respectively. The 25th pin is a radio frequency input port. The radio frequency input port receives the B1c frequency satellite navigation signal and the B3 frequency satellite navigation signal after the electromagnetic wave of the space navigation signal is processed by the active antenna low-noise amplification and filtering, and transmits them to the amplification circuit. The amplification circuit synchronously amplifies the B1c frequency satellite navigation signal and the B3 frequency satellite navigation signal and transmits them to the power division circuit. The power division circuit transmits the B1c frequency satellite navigation signal and the B3 frequency satellite navigation signal to the B3 filtering circuit and the B1c filtering circuit respectively. The B3 filtering circuit and the B1c filtering circuit The output end of the filter circuit is connected to the frequency conversion processing circuit, which converts the RF frequency of the B1c frequency point and the RF frequency of the B3 frequency point to the corresponding intermediate frequency frequency of the B1c frequency point and the intermediate frequency frequency of the B3 frequency point respectively, so as to realize the shifting of the spectrum. The frequency conversion processing circuit converts the intermediate frequency frequency of the B1c frequency point and the intermediate frequency frequency of the B3 frequency point into a digital intermediate frequency signal output, and the 10MHz reference signal is input to the frequency conversion processing circuit. The frequency conversion processing circuit outputs an 80MHz sampling clock signal. One end of the feeding circuit is connected to the input end of the DC power supply VCC-5V, and the other end outputs DC power to feed the low-noise amplifier at the front end of the module. The input end of the DC power supply VCC-5V is also connected to the power conversion circuit, and the power conversion circuit converts the DC power supply VCC-5V to the DC power supply VCC-3.3V output and provides it to the amplifier circuit and the frequency conversion processing circuit respectively.

2. A miniaturized BeiDou III dual-frequency down-conversion board according to claim 1, characterized in that: The feeding circuit includes a recoverable fuse R1, a choke coil inductor L1, a power filter capacitor C1, and a power filter capacitor C2. The input end of the DC power supply VCC-5V enters the first end connected to the recoverable fuse R1 through the 28th and 29th pins of the semicircular stamp hole. The second end of the recoverable fuse R1 is respectively connected to the first end of the power filter capacitor C1 and the power filter capacitor C2 in parallel and the first end of the choke coil inductor L1. The second end of the power filter capacitor C1 and the power filter capacitor C2 in parallel is grounded. The second end of the choke coil inductor L1 outputs DC power through the 25th pin of the semicircular stamp hole to feed the low-noise amplifier at the front end of the module.

3. A miniaturized Beidou III dual-frequency down-conversion board according to claim 2, characterized in that: The amplification circuit includes a monolithic amplifier U3. After the low-noise amplifier at the front end of the module processes the radio frequency navigation signal RF-IN, it is input into the module through the 25th pin of the semicircular stamp hole and connected to the first end of the coupling capacitor C6. The second end of the coupling capacitor C6 is respectively connected to the first ends of the resistors R9, R3 and R5. The second end of the resistor R9 is grounded. The resistors R3, R5 and R4 form a π-type impedance matching network. The second end of the resistor R5 is respectively connected to the first end of the resistor R4 and the first end of the coupling capacitor C7. The second ends of the resistor R3 and R4 are respectively grounded. The second end of the coupling capacitor C7 is connected to the pin 4 of the monolithic amplifier U3. The monolithic amplifier U Pin 0, pin 2, pin 3, pin 5, pin 6, pin 7, and pin 8 of 3 are grounded, pin 1 of the monolithic amplifier U3 is respectively connected to the first end of the inductor L2 and the first end of the coupling capacitor C8, the second end of the inductor L2 is respectively connected to the first ends of the inductor C3, the inductor C4 and the resistor R2, the second ends of the inductor C3 and the inductor C4 are respectively grounded, the second end of the resistor R2 is connected to the DC power supply VCC-3.3V, the second end of the coupling capacitor C8 is respectively connected to the first ends of the resistor R10, the resistor R7 and the resistor R6, the second end of the resistor R6 is connected to the first end of the resistor R8 and RF-IN-1, and the second ends of the resistor R10, the resistor R7 and the resistor R8 are respectively grounded.

4. A miniaturized Beidou III dual-frequency down-conversion board according to claim 3, characterized in that: The power division circuit includes a power divider U2, RF-IN-1 is connected to pin 2 of the power divider U2, pin 1, pin 3, pin 4, pin 5, pin 6, pin 8, pin 10, pin 11, and pin 12 of the power divider U2 are grounded respectively, pin 9 of the power divider U2 is connected to the first end of capacitor C5, the second end of capacitor C5 is RF-B3-OUT, and pin 7 of the power divider U2 is connected to the first end of capacitor C10, and the second end of capacitor C10 is RF-B1c-OUT.

5. A miniaturized Beidou III dual-frequency down-conversion board according to claim 4, characterized in that: The B3 filtering circuit includes a frequency point filter U8, RF-B3-OUT is respectively connected to the first end of resistor R26 and the first end of resistor R29, the second end of the resistor R26 is respectively connected to the first end of resistor R30 and pin 2 of the frequency point filter U8, the second end of the resistor R29 and the second end of the resistor R30 are respectively grounded, pin 1, pin 3, pin 4 and pin 6 of the frequency point filter U8 are respectively grounded, pin 5 of the frequency point filter U8 is respectively connected to the first end of resistor R27 and the first end of resistor R31, the second end of the resistor R27 is respectively connected to the first end of resistor R32 and the first end of capacitor C37, the second end of the resistor R31 and the second end of the resistor R32 are respectively grounded, and the second end of the capacitor C37 is RF-B3-OUT1.

6. A miniaturized BeiDou III dual-frequency down-conversion board according to claim 5, characterized in that: The B1c filtering circuit includes a dielectric filter U10, RF-B1c-OUT is respectively connected to the first end of the resistor R42 and the first end of the resistor R44, the second end of the resistor R42 is respectively connected to the first end of the resistor R45 and the pin 1 of the dielectric filter U10, the second end of the resistor R44 and the second end of the resistor R45 are respectively grounded, pins 3, 4, 5, 6 and 7 of the dielectric filter U10 are respectively grounded, pin 2 of the dielectric filter U10 is respectively connected to the first end of the resistor R43 and the first end of the resistor R46, the second end of the resistor R43 is respectively connected to the first end of the resistor R47 and the first end of the capacitor C43, the second end of the resistor R46 and the second end of the resistor R47 are respectively grounded, and the second end of the capacitor C43 is RF-B1c-OUT1.

7. A miniaturized BeiDou III dual-frequency down-conversion board according to claim 6, characterized in that: The power conversion circuit includes a power chip U4. The external DC power supply VCC-5V of the dual-frequency down-conversion module enters through the 28th and 29th pins of the semicircular stamp holes and is respectively connected to the first end of the capacitor C12, the first end of the capacitor C13, and the pin 1 and pin 7 of the power chip U4. The pins 0, 4 and 6 of the power chip U4 are grounded respectively. The pin 8 of the power chip U4 is connected to the first end of the resistor R11. The first end of the resistor R12 and the capacitor C11 after being connected in parallel is respectively connected to the pin 2 of the power chip U4 and the second end of the resistor R11. The second end of the resistor R12 and the capacitor C11 after being connected in parallel is grounded. The pins 3 and 5 of the power chip U4 are chip output pins and are respectively connected to the first end of the power filter capacitor C14 and the DC power supply VCC-3.3V. The second end of the power filter capacitor C14 is grounded.

8. A miniaturized BeiDou III dual-frequency down-conversion board according to claim 7, characterized in that: The frequency conversion processing circuit includes an integrated circuit U7, RF-B3-OUT1 is connected to the first end of the inductor L7, the second end of the inductor L7 is connected to the capacitor C36 and then to the pin 9 of the integrated circuit U7, RF-B1c-OUT1 is connected to the capacitor C44 and the inductor L10 in sequence and then to the pin 15 of the integrated circuit U7, the pin 2 of the integrated circuit U7 is respectively connected to the first end of the resistor R22 and the resistor R23, the second end of the resistor R23 is grounded, the second end of the resistor R22 is connected to the power supply VCC-3.3V-2202, and the integrated circuit Pin 5 of the integrated circuit U7 is respectively connected to the power supply VCC-3.3V-2202 and the grounded power supply filter capacitor C29, pin 6 of the integrated circuit U7 is respectively connected to the first end of the resistor R24 ​​and the capacitor C32, the second end of the resistor R24 ​​is connected to the first end of the capacitor C30, the second end of the capacitor C32 is connected to the second end of the capacitor C30 and then to ground, pin 7 of the integrated circuit U7 is respectively connected to the power supply VCC-3.3V-2202 and the grounded power supply filter capacitor C34, pin 8 of the integrated circuit U7 is connected to the resistor R25 and then to ground, Pin 11 of the integrated circuit U7 is respectively connected to the power supply VCC-3.3V-2202 and the grounded power supply filter capacitor C40, the pin 12 of the integrated circuit U7 is connected to the resistor R33 and then to the ground, the pin 13 of the integrated circuit U7 is respectively connected to the power supply VCC-3.3V-2202 and the grounded power supply filter capacitor C42, the pin 17 of the integrated circuit U7 is connected to the resistor R48 and then to the power supply VCC-3.3V-2202, and the pin 18 of the integrated circuit U7 is respectively connected to the power supply VCC-3.3V-2202 and the grounded power supply The filter capacitor C48, the pin 19 of the integrated circuit U7 is respectively connected to the first end of the resistor R53 and the capacitor C45, the second end of the resistor R53 is connected to the first end of the capacitor C54, the second end of the capacitor C45 is connected to the second end of the capacitor C54 and then to ground, the pin 20 of the integrated circuit U7 is connected to the capacitor C49 and then to ground, the pins 22 and 23 of the integrated circuit U7 are respectively connected to the power supply VCC-3.3V-2202 and the grounded power filter capacitor C50, and the pin 26 of the integrated circuit U7 is respectively connected to the power supply VCC-3.3V-2202.3V-2202 and a grounded power supply filter capacitor C46, ​​the pin 27 of the integrated circuit U7 is connected to the capacitor C47 and then to ground, the pin 29 of the integrated circuit U7 is connected to the resistor R49 and then to the B1c frequency point output intermediate frequency output terminal IF-B1c-D3 and output through the pin 44 of the semicircular stamp hole, the pin 30 of the integrated circuit U7 is connected to the resistor R50 and then to the B1c frequency point output intermediate frequency output terminal IF-B1c-D2 and output through the pin 45 of the semicircular stamp hole, the pin 31 of the integrated circuit U7 is connected to the resistor R51 and then to the B1c frequency point output intermediate frequency output terminal IF-B1c-D1 and output through the pin 46 of the semicircular stamp hole, the pin 32 of the integrated circuit U7 is connected to the resistor R52 and then to the Connect the B1c frequency output intermediate frequency output terminal IF-B1c-D0 and output through pin 47 of the semicircular stamp hole, the pin 35 of the integrated circuit U7 is connected to the resistor R39 and then connected to the B3 frequency output intermediate frequency output terminal IF-B3-D3 and output through pin 39 of the semicircular stamp hole, the pin 36 of the integrated circuit U7 is connected to the resistor R37 and then connected to the B3 frequency output intermediate frequency output terminal IF-B3-D2 and output through pin 40 of the semicircular stamp hole, the pin 37 of the integrated circuit U7 is connected to the resistor R36 and then connected to the B3 frequency output intermediate frequency output terminal IF-B3-D1 and output through pin 41 of the semicircular stamp hole, the pin 38 of the integrated circuit U7 is connected to the resistor R35 and then connected to the B3 frequency output intermediate frequency output The pin 47 of the integrated circuit U7 is respectively connected to the power supply VCC-3.3V-2202 and the grounded power supply filter capacitor C35, the pin 48 of the integrated circuit U7 is connected to the capacitor C33 and then connected to the B1c frequency analog digital signal output terminal IF-B1c-A, the pin 51 of the integrated circuit U7 is connected to the capacitor C31 and then connected to the B3 frequency analog digital signal output terminal IF-B3-A, the pin 54 of the integrated circuit U7 is respectively connected to the power supply VCC-3.3V-2202 and the grounded power supply filter capacitor C24, the pin 55 of the integrated circuit U7 is connected to the capacitor C23 and then grounded, and the pin 59 of the integrated circuit U7 is respectively connected to the power supply VCC-3.3V-2202 and the grounded power supply filter capacitor C24. Source VCC-3.3V-2202 and grounded power supply filter capacitor C22, pin 60 of the integrated circuit U7 is connected to resistor R21 and then connected to SPI control point SPI-CS, pin 61 of the integrated circuit U7 is connected to resistor R20 and then connected to SPI control point SPI-CLK, pin 62 of the integrated circuit U7 is connected to resistor R19 and then connected to SPI control point SPI-MOSI, pin 63 of the integrated circuit U7 is connected to resistor R18 and then connected to SPI control point SPI-MISO, pin 64 of the integrated circuit U7 is connected to capacitor C27 and then connected to 10MHz reference signal input port 10MHZ-IC-IN, and pin 65 of the integrated circuit U7 is respectively connected to power supply VCC-3.3V-2202 and grounded power supply filter capacitor C26, pin 67 of the integrated circuit U7 is respectively connected to the power supply VCC-3.3V-2202 and the grounded power supply filter capacitor C25, and pin 69 of the integrated circuit U7 is grounded;. The frequency conversion processing circuit also includes a dual-frequency down-conversion module, wherein the internal DC power supply VCC-3.3V of the dual-frequency down-conversion module is respectively connected to the first ends of the magnetic bead L13, the capacitor C55 and the capacitor C56, the second end of the magnetic bead L13 is connected to the power supply VCC-3.3V-2202 of the integrated circuit U7, and the second ends of the capacitor C55 and the capacitor C56 are respectively grounded; The frequency conversion processing circuit also includes an integrated circuit U7, the reference signal 10MHZ-IN is connected to the resistor R13 and then connected to the first ends of the inductor L3 and the capacitor C15 respectively, the second end of the inductor L3 is connected to the first ends of the inductor L4 and the capacitor C16 respectively, the second end of the inductor L4 is connected to the first end of the capacitor C17 and 10MHZ-IC-IN respectively, and the capacitors C15, C16 and C17 are grounded respectively; The frequency conversion processing circuit also includes a NOT gate chip U5, an 80MHZ sampling clock signal is sequentially connected to a capacitor C20 and a resistor R15, and then respectively connected to the first end of a resistor R17, the first end of a resistor R14, and pins 1 and 2 of the NOT gate chip U5, a pin 3 of the NOT gate chip U5 is connected to the second end of the resistor R17 and then grounded, a second end of the resistor R14 is respectively connected to pin 5 of the NOT gate chip U5, a first end of a capacitor C18, a first end of a capacitor C19, and a first end of an inductor L5, a second end of the capacitor C18 and a second end of the capacitor C19 are respectively grounded, a second end of the inductor L5 is connected to a DC power supply VCC-3.3V, a pin 4 of the NOT gate chip U5 is sequentially connected to a capacitor C21 and a resistor R6, and then outputs 80MHZ-CLK-OUT, which is output to a baseband circuit at a later stage through the 37th pin of the semicircular stamp hole to provide an 80MHz sampling clock signal for it; The frequency conversion processing circuit also includes an operational amplifier U9, and the B1c frequency analog intermediate frequency signal IF-B1c-OUT is output through the 6th pin of the semicircular stamp hole and connected to the first end of the capacitor C38 and the first end of the inductor L8 respectively, the second end of the capacitor C38 is grounded, the second end of the inductor L8 is connected to the resistor R28 and the capacitor C41 in sequence and then connected to the pin 1 of the operational amplifier U9, the pin 2 and the pin 4 of the operational amplifier U9 are grounded, the pin 5 of the operational amplifier U9 is connected to the first end of the resistor R38, the first end of the inductor L9 and the first end of the capacitor C39 respectively, the second end of the capacitor C39 is grounded, the second end of the inductor L9 is connected to the DC power supply VCC-3.3V, the B1c frequency analog intermediate frequency signal IF-B1c-A of the integrated circuit U7 is connected to the first end of the resistor R40 and the first end of the resistor R34 respectively, the second end of the resistor R40 is grounded, the pin 3 of the operational amplifier U9 is connected to the second end of the resistor R34, the second end of the resistor R38 and the first end of the resistor R41 respectively, and the second end of the resistor R41 is grounded; The frequency conversion processing circuit also includes an operational amplifier U11. The B3 frequency analog intermediate frequency signal IF-B3-OUT is output through the 11th pin of the semicircular stamp hole and is respectively connected to the first end of the capacitor C51 and the first end of the inductor L11. The second end of the capacitor C51 is grounded. The second end of the inductor L11 is connected to the resistor R54 and the capacitor C53 in sequence and then connected to the pin 1 of the operational amplifier U11. The pins 2 and 4 of the operational amplifier U11 are grounded. The pin 5 of the operational amplifier U11 is respectively connected to the first end of the resistor R56 and the inductor L11. The first end of the inductor L12 and the first end of the capacitor C52 are connected, the second end of the capacitor C52 is grounded, the second end of the inductor L12 is connected to the DC power supply VCC-3.3V, the B3 frequency analog intermediate frequency signal IF-B3-A of the integrated circuit U7 is respectively connected to the first end of the resistor R57 and the first end of the resistor R55, the second end of the resistor R57 is grounded, the pin 3 of the operational amplifier U11 is respectively connected to the second end of the resistor R55, the second end of the resistor R56 and the first end of the resistor R58, the second end of the resistor R58 is grounded.

9. A miniaturized BeiDou III dual-frequency down-conversion board according to claim 1, characterized in that: The frequency of the B3 frequency satellite navigation signal is 1268.52±10.23MHz, the intermediate frequency output from pin 39 to pin 42 is 15.48±10.23MHz, and the local oscillator frequency is 1284MHz; the frequency of the B1c frequency satellite navigation signal is 1575.42±16.368MHz, the intermediate frequency output from pin 44 to pin 47 is 20.58±16.368MHz, and the local oscillator frequency is 1596MHz.

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